LM158A MDR [TI]
Space-grade, dual, 32-V, 700-kHz operational amplifier | Y | 0 | -55 to 125;
| 型号： | LM158A MDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Space-grade, dual, 32-V, 700-kHz operational amplifier | Y | 0 | -55 to 125 放大器 运算放大器 放大器电路 |
| 文件： | 总30页 (文件大小：962K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM158QML
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SNOSAP3F –JULY 2005–REVISED MARCH 2013
LM158QML Low Power Dual Operational Amplifiers
Check for Samples: LM158QML
ADVANTAGES
1
FEATURES
•
•
•
Two Internally Compensated Op Amps
Eliminates Need for Dual Supplies
Allows Direct Sensing Near Gnd and VO also
Goes to Gnd
Compatible with all Forms of Logic
Power Drain Suitable for Battery Operation
2
•
Available with Radiation Specification
–
–
High Dose Rate 100 krad(Si)
ELDRS Free 100 krad(Si)
•
Internally Frequency Compensated for Unity
Gain
•
•
•
•
Large DC Voltage Gain: 100 dB
Wide Bandwidth (Unity Gain): 1 MH
z(Temperature Compensated)
DESCRIPTION
The LM158 series consists of two independent, high
gain, internally frequency compensated operational
amplifiers which were designed specifically to operate
from a single power supply over a wide range of
voltages. Operation from split power supplies is also
possible and the low power supply current drain is
independent of the magnitude of the power supply
voltage.
•
Wide Power Supply Range:
–
–
Single Supply: 3V to 32V
Or Dual Supplies: ±1.5V to ±16V
•
Very Low Supply Current Drain (500 μA) −
Essentially Independent of Supply Voltage
•
•
Low Input Offset Voltage: 2 mV
Application areas include transducer amplifiers, dc
gain blocks and all the conventional op amp circuits
which now can be more easily implemented in single
power supply systems. For example, the LM158
series can be directly operated off of the standard
+5V power supply voltage which is used in digital
systems and will easily provide the required interface
electronics without requiring the additional ±15V
power supplies.
Input Common-mode Voltage Range Includes
Ground
•
•
Differential Input Voltage Range Equal to the
Power Supply Voltage
Large Output Voltage Swing: 0V to V+ − 1.5V
UNIQUE CHARACTERISTICS
•
In the Linear Mode the Input Common-Mode
Voltage Range Includes Ground and the Output
Voltage can also Swing to Ground, even though
Operated from only a Single Power Supply
Voltage.
•
•
The Unity Gain Cross Frequency is Temperature
Compensated.
The Input Bias Current is also Temperature
Compensated.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM158QML
SNOSAP3F –JULY 2005–REVISED MARCH 2013
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Connection Diagrams
Figure 1. TO-99 Package
See Package Number LMC0008C
Top View
Top View
OUT A
-IN A
+IN A
GND
N/C
1
2
3
4
5
10
9
V+
OUT B
-IN B
+IN B
N/C
8
7
6
Figure 2. CDIP Package
See Package Number NAB0008A
Figure 3. 10 Lead CLGA Package
See Package Number NAC0010A
Schematic Diagram
(Each Amplifier)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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SNOSAP3F –JULY 2005–REVISED MARCH 2013
Absolute Maximum Ratings(1)
Supply Voltage, V+
32VDC
32VDC
Differential Input Voltage
Input Voltage
Power Dissipation(2)
−0.3VDC to +32VDC
830 mW
Output Short-Circuit to GND(3)
(One Amplifier)
Continuous
V+ ≤ 15VDC and TA = 25°C
Maximum Junction Temperature (TJmax
Input Current (VI < −0.3V)(4)
)
150°C
50 mA
Operating Temperature Range
Storage Temperature Range
−55°C ≤ TA ≤ +125°C
−65°C ≤ TA ≤ +150°C
300°C
Lead Temperature (Soldering, 10
seconds)
TO-99
CDIP
260°C
CLGA
260°C
Thermal
Resistance
θJA
TO-99 (Still Air)
TO-99 (500LF/Min Air Flow)
CDIP (Still Air)
CDIP (500LF/Min Air Flow)
CLGA (Still Air)
CLGA (500LF/Min Air Flow)
TO-99
155°C/W
80°C/W
132°C/W
81°C/W
195°C/W
131°C/W
42°C/W
θJC
CDIP
23°C/W
CLGA
33°C/W
Package Weight
ESD Tolerance(5)
TO-99
CDIP
1,000mg
1,100mg
220mg
CLGA
250V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
(3) Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 40 mA independent of the magnitude of V+. At values of supply voltage in excess of +15V,
continuous short-circuits can exceed the power dissipation ratings and cause eventual destruction. Destructive dissipation can result
from simultaneous shorts on all amplifiers.
(4) This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of
the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is
also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the op amps to go to
the V+voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and
normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than −0.3V (at 25°C).
(5) Human body model, 1.5 kΩ in series with 100 pF.
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Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Temp °C
+25
1
2
Static tests at
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
+25
5
+125
-55
6
7
+25
8A
8B
9
+125
-55
+25
10
11
12
13
14
+125
-55
+25
+125
-55
4
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SNOSAP3F –JULY 2005–REVISED MARCH 2013
LM158 Electrical Characteristics SMD 5962–8771001 DC Parameters
The following conditions apply, unless otherwise specified. All voltages referenced to device ground.
Sub-
groups
Parameter
Test Conditions
Notes
Min Max
Units
ICC
Power Supply Current
+VCC = 5V, RL = 100K,
VO = 1.4V
1.2
mA
1, 2, 3
+VCC = 30V, RL = 100K,
VO = 1.4V
3.0
mA
mA
V
1
4.0
2, 3
VOH
Output Voltage High
Output Voltage Low
+VCC = 30V, RL = 2KΩ
+VCC = 30V, RL = 10KΩ
+VCC = 30V, RL = 10KΩ
+VCC = 30V, ISink = 1µA
+VCC = 5V, RL = 10KΩ
26
27
20
20
20
12
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
V
VOL
mV
mV
mV
µA
ISink
Output Sink Current
+VCC = 15V, VO = 200mV,
+VI = 0V, -VI = +65mV
+VCC = 15V, VO = 2V,
+VI = 0V, -VI = +65mV
10
5.0
-20
-10
-60
mA
mA
mA
mA
mA
mV
mV
mV
1
2, 3
1
ISource
Output Source Current
+VCC = 15V, VO = 2V,
+VI = 0V, -VI = -65mV
2, 3
1
IOS
VIO
Short Circuit Current
Input Offset Voltage
+VCC = 5V, VO = 0V
+VCC = 30V, VCM = 0V,
RS = 50Ω, VO = 1.4V
-5.0
-7.0
-5.0
5.0
7.0
5.0
1
2, 3
1
+VCC = 30V, VCM = 28.5V,
RS = 50Ω, VO = 1.4V
+VCC = 30V, VCM = 28V,
-7.0
7.0
mV
2, 3
RS = 50Ω, VO = 1.4V
+VCC = 5V, VCM = 0V,
RS = 50Ω, VO = 1.4V
-5.0
-7.0
70
5.0
7.0
mV
mV
dB
1
2, 3
1
CMRR
±IIB
Common Mode Rejection Ratio
Input BIas Current
+VCC = 30V, RS = 50Ω
VI = 0V to 28.5V,
+VCC = 5V, VCM = 0V
+VCC = 5V, VCM = 0V
See(1)
See(1)
-150 -1.0
-300 -1.0
nA
nA
nA
nA
dB
1
2, 3
1
IIO
Input Offset Current
-30
30
-100 100
65
2, 3
1
PSRR
VCM
Power Supply Rejection Ratio
Common Mode Voltage Range
+VCC = 5V to 30V,
VCM = 0V
(3)
+VCC = 30V
See(2)
See(2)
,
,
28.5
V
V
1
2, 3
1, 2, 3
4
(3)
28.0
VDiff
AVS
Differential Input Voltage
Large Signal Gain
See(4)
32
V
+VCC = 15V, RL = 2KΩ,
VO = 1V to 11V
50
25
V/mV
V/mV
5, 6
(1) The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the input lines.
(2) The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3V (at 25°C). The
upper end of the common-mode voltage range is V+ −1.5V (at 25°C), but either or both inputs can go to +32V without damage,
independent of the magnitude of V+.
(3) Specified by input offset voltage.
(4) Specified parameter not tested.
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LM158A Electrical Characteristics SMD 5962–8771002, High Dose Rate DC Parameters
The following conditions apply, unless otherwise specified. All voltages referenced to device ground.
Sub-
groups
Parameter
Test Conditions
Notes
Min Max
Units
ICC
Power Supply Current
+VCC = 5V, RL = 100K,
VO = 1.4V
1.2
mA
1, 2, 3
+VCC = 30V, RL = 100K,
VO = 1.4V
3.0
4.0
mA
mA
V
1
2, 3
1, 2, 3
1, 2, 3
1
VOH
Output Voltage High
Output Voltage Low
+VCC = 30V, RL = 2KΩ
+VCC = 30V, RL = 10KΩ
+VCC = 30V, RL = 10KΩ
26
27
V
VOL
40
mV
mV
mV
mV
mV
mV
µA
100
40
2, 3
1
+VCC = 30V, ISink = 1µA
100
40
2, 3
1
+VCC = 5V, RL = 10KΩ
100
12
2, 3
1
ISink
Output Sink Current
+VCC = 15V, VO = 200mV,
+VI = 0V, -VI = +65mV
+VCC = 15V, VO = 2V,
+VI = 0V, -VI = +65mV
10
5.0
-20
-10
-60
mA
mA
mA
mA
mA
mV
mV
mV
1
2, 3
1
ISource
Output Source Current
+VCC = 15V, VO = 2V,
+VI = 0V, -VI = -65mV
2, 3
1
IOS
VIO
Short Circuit Current
Input Offset Voltage
+VCC = 5V, VO = 0V
+VCC = 30V, VCM = 0V,
RS = 50Ω, VO = 1.4V
-2.0
-4.0
-2.0
2.0
4.0
2.0
1
2, 3
1
+VCC = 30V, VCM = 28.5V,
RS = 50Ω, VO = 1.4V
+VCC = 30V, VCM = 28V,
-4.0
4.0
mV
2, 3
RS = 50Ω, VO = 1.4V
+VCC = 5V, VCM = 0V,
RS = 50Ω, VO = 1.4V
-2.0
-4.0
70
2.0
4.0
mV
mV
dB
1
2, 3
1
CMRR
±IIB
Common Mode Rejection Ratio
Input BIas Current
+VCC = 30V, RS = 50Ω
VI = 0V to 28.5V,
+VCC = 5V, VCM = 0V
+VCC = 5V, VCM = 0V
See(1)
See(1)
-50
-1.0
nA
nA
nA
nA
dB
1
2, 3
1
-100 -1.0
IIO
Input Offset Current
-10
-30
65
10
30
2, 3
1
PSRR
VCM
Power Supply Rejection Ratio
Common Mode Voltage Range
+VCC = 5V to 30V,
VCM = 0V
+VCC = 30V
See(2) (3)
See(2) (3)
28.5
28.0
32
V
V
1
2, 3
1, 2, 3
4
(4)
VDiff
AVS
Differential Input Voltage
Large Signal Gain
See
V
+VCC = 15V, RL = 2KΩ,
VO = 1V to 11V
50
25
V/mV
V/mV
5, 6
(1) The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the input lines.
(2) The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3V (at 25°C). The
upper end of the common-mode voltage range is V+ −1.5V (at 25°C), but either or both inputs can go to +32V without damage,
independent of the magnitude of V+.
(3) Specified by input offset voltage.
(4) Specified parameter not tested.
6
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SMD 5962–8771002, High Dose Rate
DC Drift Parameters
The following conditions apply, unless otherwise specified. All voltages referenced to device ground.
Delta calculations are performed on QMLV devices at Group B, Subgroup 5 only.
Sub-
groups
Parameter
Test Conditions
Notes
Min Max
Units
VIO
Input Offset Voltage
+VCC = 30V, VCM = 0V,
RS = 50Ω, VO = 1.4V
-0.5
-0.5
-0.5
-10
0.5
0.5
0.5
10
mV
1
1
1
1
+VCC = 30V, VCM = 28.5V,
RS = 50Ω, VO = 1.4V
mV
mV
nA
+VCC = 5V, VCM = 0V,
RS = 50Ω, VO = 1.4V
±IIB
Input Bias Current
+VCC = 5V, VCM = 0V
See(1)
(1) The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the input lines.
SMD 5962–8771002, High Dose Rate SMD 5962–8771002, High Dose Rate
100K Post Radiation Limits @ +25°C(1)
DC Parameters
The following conditions apply, unless otherwise specified. All voltages referenced to device ground.
Parameter
Test Conditions
Notes
See(1)
See(1)
See(1)
Min Max
Units
mV
Sub -
groups
VIO
Input Offset Voltage
+VCC = 30V, VCM = 0V,
RS = 50Ω, VO = 1.4V
-4.0
-4.0
-4.0
-60
4.0
4.0
4.0
1
1
1
+VCC = 30V, VCM = 28.5V,
RS = 50Ω, VO = 1.4V
mV
+VCC = 5V, VCM = 0V,
RS = 50Ω, VO = 1.4V
mV
±IIB
ICC
Input Bias Current
+VCC = 5V, VCM = 0V
See(1)(2)
See(1)
-1.0
1.5
nA
1
1
Power Supply Current
+VCC = 5V, RL = 100K,
VO = 1.4V
mA
(1) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate
sensitivity. Radiation end point limits for the noted parameters are specified only for the conditions as specified in MIL-STD-883, per
Test Method 1019, Condition A.
(2) The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the input lines.
LM158A Electrical Characteristics SMD 5962–8771003 ELDRS Free Only
DC Parameters
The following conditions apply, unless otherwise specified. All voltages referenced to device ground.
Sub-
groups
Parameter
Test Conditions
Notes
Min Max
Units
ICC
Power Supply Current
+VCC = 5V, RL = 100K,
VO = 1.4V
1.2
mA
1, 2, 3
+VCC = 30V, RL = 100K,
VO = 1.4V
3.0
4.0
mA
1,
2, 3
1, 2, 3
1, 2, 3
1
VOH
Output Voltage High
Output Voltage Low
+VCC = 30V, RL = 2KΩ
+VCC = 30V, RL = 10KΩ
+VCC = 30V, RL = 10KΩ
26
V
27
V
VOL
40
mV
mV
mV
mV
mV
mV
100
40
2, 3
1
+VCC = 30V, ISink = 1µA
100
40
2, 3
1
+VCC = 5V, RL = 10KΩ
100
2, 3
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LM158A Electrical Characteristics SMD 5962–8771003 ELDRS Free Only
DC Parameters (continued)
The following conditions apply, unless otherwise specified. All voltages referenced to device ground.
Sub-
groups
Parameter
Test Conditions
Notes
Min Max
Units
ISink
Output Sink Current
+VCC = 15V, VO = 200mV,
+VI = 0V, -VI = +65mV
12
µA
1
+VCC = 15V, VO = 2V,
+VI = 0V, -VI = +65mV
10
5.0
-20
-10
-60
mA
mA
mA
mA
mA
mV
mV
mV
1
2, 3
1
ISource
Output Source Current
+VCC = 15V, VO = 2V,
+VI = 0V, -VI = -65mV
2, 3
1
IOS
VIO
Short Circuit Current
Input Offset Voltage
+VCC = 5V, VO = 0V
+VCC = 30V, VCM = 0V,
RS = 50Ω, VO = 1.4V
-2.0
-4.0
-2.0
2.0
4.0
2.0
1
2, 3
1
+VCC = 30V, VCM = 28.5V,
RS = 50Ω, VO = 1.4V
+VCC = 30V, VCM = 28V,
-4.0
4.0
mV
2, 3
RS = 50Ω, VO = 1.4V
+VCC = 5V, VCM = 0V,
RS = 50Ω, VO = 1.4V
-2.0
-4.0
70
2.0
4.0
mV
mV
dB
1
2, 3
1
CMRR
±IIB
Common Mode Rejection Ratio
Input BIas Current
+VCC = 30V, RS = 50Ω
VI = 0V to 28.5V,
+VCC = 5V, VCM = 0V
+VCC = 5V, VCM = 0V
See(1)
See(1)
-50
-1.0
nA
nA
nA
nA
dB
1
2, 3
1
-100 -1.0
IIO
Input Offset Current
-10
-30
65
10
30
2, 3
1
PSRR
VCM
Power Supply Rejection Ratio
Common Mode Voltage Range
+VCC = 5V to 30V,
VCM = 0V
(3)
+VCC = 30V
See(2)
See(2)
,
,
28.5
28.0
32
V
V
1
2, 3
1, 2, 3
4
(3)
VDiff
AVS
Differential Input Voltage
Large Signal Gain
See(4)
V
+VCC = 15V, RL = 2KΩ,
VO = 1V to 11V
50
25
V/mV
V/mV
5, 6
(1) The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the input lines.
(2) The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3V (at 25°C). The
upper end of the common-mode voltage range is V+ −1.5V (at 25°C), but either or both inputs can go to +32V without damage,
independent of the magnitude of V+.
(3) Specified by input offset voltage.
(4) Specified parameter not tested.
SMD 5962–8771003 ELDRS Free Only
DC Drift Parameters
The following conditions apply, unless otherwise specified. All voltages referenced to device ground.
Delta calculations are performed on QMLV devices at Group B, Subgroup 5 only.
Sub-
groups
Parameter
Test Conditions
Notes
Min Max
Units
VIO
Input Offset Voltage
+VCC = 30V, VCM = 0V,
RS = 50Ω, VO = 1.4V
-0.5
-0.5
-0.5
0.5
0.5
0.5
mV
1
+VCC = 30V, VCM = 28.5V,
RS = 50Ω, VO = 1.4V
mV
mV
1
1
+VCC = 5V, VCM = 0V,
RS = 50Ω, VO = 1.4V
8
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SMD 5962–8771003 ELDRS Free Only
DC Drift Parameters (continued)
The following conditions apply, unless otherwise specified. All voltages referenced to device ground.
Delta calculations are performed on QMLV devices at Group B, Subgroup 5 only.
Sub-
groups
Parameter
Test Conditions
+VCC = 5V, VCM = 0V
Notes
Min Max
-10 10
Units
±IIB
Input Bias Current
See(1)
nA
1
(1) The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the input lines.
SMD 5962–8771003 ELDRS Free Only
100K Post Radiation Limits @ +25°C(1)
DC Parameters
The following conditions apply, unless otherwise specified. All voltages referenced to device ground.
Parameter
Test Conditions
Notes
Min Max
Units
mV
mV
mV
nA
Sub -
groups
VIO
Input Offset Voltage
+VCC = 30V, VCM = 0V,
RS = 50Ω, VO = 1.4V
See(1)
-4.0
-4.0
-4.0
-60
4.0
4.0
4.0
-1.0
1
1
1
1
+VCC = 30V, VCM = 28.5V,
RS = 50Ω, VO = 1.4V
See(1)
+VCC = 5V, VCM = 0V,
RS = 50Ω, VO = 1.4V
See(1)
±IIB
Input Bias Current
+VCC = 5V, VCM = 0V
See(1)(2)
(1) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post
Radiation Limits Table. These parts may be sensitive in a high dose environment. Low dose rate testing has been performed on a
wafer-by-wafer basis, per Test Method 1019, Condition D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS).
(2) The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the input lines.
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Typical Performance Characteristics
Input Voltage Range
Input Current
Figure 4.
Figure 5.
Supply Current
Voltage Gain
Figure 6.
Figure 7.
Open Loop Frequency Response
Common-Mode Rejection Ratio
Figure 8.
Figure 9.
10
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SNOSAP3F –JULY 2005–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Voltage Follower Pulse Response
Voltage Follower Pulse Response (Small Signal)
Figure 10.
Figure 11.
Large Signal Frequency Response
Output Characteristics Current Sourcing
Figure 12.
Figure 13.
Output Characteristics Current Sinking
Current Limiting
Figure 14.
Figure 15.
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APPLICATION HINTS
The LM158 series are op amps which operate with only a single power supply voltage, have true-differential
inputs, and remain in the linear mode with an input common-mode voltage of 0 VDC. These amplifiers operate
over a wide range of power supply voltage with little change in performance characteristics. At 25°C amplifier
operation is possible down to a minimum supply voltage of 2.3 VDC
.
Precautions should be taken to insure that the power supply for the integrated circuit never becomes reversed in
polarity or that the unit is not inadvertently installed backwards in a test socket as an unlimited current surge
through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a
destroyed unit.
Large differential input voltages can be easily accommodated and, as input differential voltage protection diodes
are not needed, no large input currents result from large differential input voltages. The differential input voltage
may be larger than V+ without damaging the device. Protection should be provided to prevent the input voltages
from going negative more than −0.3 VDC (at 25°C). An input clamp diode with a resistor to the IC input terminal
can be used.
To reduce the power supply current drain, the amplifiers have a class A output stage for small signal levels which
converts to class B in a large signal mode. This allows the amplifiers to both source and sink large output
currents. Therefore both NPN and PNP external current boost transistors can be used to extend the power
capability of the basic amplifiers. The output voltage needs to raise approximately 1 diode drop above ground to
bias the on-chip vertical PNP transistor for output current sinking applications.
For ac applications, where the load is capacitively coupled to the output of the amplifier, a resistor should be
used, from the output of the amplifier to ground to increase the class A bias current and prevent crossover
distortion. Where the load is directly coupled, as in dc applications, there is no crossover distortion.
Capacitive loads which are applied directly to the output of the amplifier reduce the loop stability margin. Values
of 50 pF can be accommodated using the worst-case non-inverting unity gain connection. Large closed loop
gains or resistive isolation should be used if larger load capacitance must be driven by the amplifier.
The bias network of the LM158 establishes a drain current which is independent of the magnitude of the power
supply voltage over the range of 3 VDC to 30 VDC
.
Output short circuits either to ground or to the positive power supply should be of short time duration. Units can
be destroyed, not as a result of the short circuit current causing metal fusing, but rather due to the large increase
in IC chip dissipation which will cause eventual failure due to excessive junction temperatures. Putting direct
short-circuits on more than one amplifier at a time will increase the total IC power dissipation to destructive
levels, if not properly protected with external dissipation limiting resistors in series with the output leads of the
amplifiers. The larger value of output source current which is available at 25°C provides a larger output current
capability at elevated temperatures (see Typical Performance Characteristics) than a standard IC op amp.
The circuits presented in the section on typical applications emphasize operation on only a single power supply
voltage. If complementary power supplies are available, all of the standard op amp circuits can be used. In
general, introducing a pseudo-ground (a bias voltage reference of V+/2) will allow operation above and below this
value in single power supply systems. Many application circuits are shown which take advantage of the wide
input common-mode voltage range which includes ground. In most cases, input biasing is not required and input
voltages which range to ground can easily be accommodated.
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SNOSAP3F –JULY 2005–REVISED MARCH 2013
Typical Single-Supply Applications
(V+ = 5.0 VDC
)
*R not needed due to temperature independent IIN
Figure 16. Non-Inverting DC Gain (0V Output)
VO = 0 VDC for VIN = 0 VDC
AV = 10
Where: VO = V1 + V2 −V3 − V4
(V1 + V2) ≥ (V3 + V4) to keep VO > 0 VDC
Figure 17. DC Summing Amplifier
(VIN'S ≥ 0 VDC and VO ≥ 0 VDC
Figure 18. Power Amplifier
)
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fo = 1 kHz
Q = 50
Av = 100 (40 dB)
Figure 19. “BI-QUAD” RC Active Bandpass Filter
Figure 20. Fixed Current Sources
Figure 21. Lamp Driver
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SNOSAP3F –JULY 2005–REVISED MARCH 2013
*(Increase R1 for IL small)
L ≤ V+ −2V
V
Figure 22. LED Driver
Figure 23. Current Monitor
VO = VIN
Figure 24. Driving TTL
Figure 25. Voltage Follower
Figure 26. Pulse Generator
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Figure 27. Squarewave Oscillator
Figure 28. Pulse Generator
HIGH ZIN
LOW ZOUT
Figure 29. Low Drift Peak Detector
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SNOSAP3F –JULY 2005–REVISED MARCH 2013
IO = 1 amp/volt VIN
(Increase RE for IO small)
Figure 30. High Compliance Current Sink
Figure 31. Comparator with Hysteresis
*WIDE CONTROL VOLTAGE RANGE: 0 VDC ≤ VC ≤ 2 (V+ −1.5V DC
)
Figure 32. Voltage Controlled Oscillator (VCO)
Figure 33. AC Coupled Inverting Amplifier
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Figure 34. Ground Referencing a Differential Input Signal
Av = 11 (As Shown)
Figure 35. AC Coupled Non-Inverting Amplifier
fo = 1 kHz
Q = 1
AV = 2
Figure 36. DC Coupled Low-Pass RC Active Filter
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SNOSAP3F –JULY 2005–REVISED MARCH 2013
fo = 1 kHz
Q = 25
Figure 37. Bandpass Active Filter
Figure 38. High Input Z, DC Differential Amplifier
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Figure 39. Photo Voltaic-Cell Amplifier
Figure 40. Bridge Current Amplifier
Figure 41. High Input Z Adjustable-Gain
DC Instrumentation Amplifier
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SNOSAP3F –JULY 2005–REVISED MARCH 2013
Figure 42. Using Symmetrical Amplifiers to
Reduce Input Current (General Concept)
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REVISION HISTORY
Changes from Revision E (March 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-8771002GA
ACTIVE
TO-99
LMC
8
20
TBD
Call TI
Call TI
-55 to 125
LM158AH-SMD
5962-8771002GA Q A
CO
5962-8771002GA Q >
T
5962-8771002QXA
5962R8771002VGA
ACTIVE
ACTIVE
CFP
NAC
LMC
10
54
20
TBD
Call TI
Call TI
-55 to 125
LM158AWG
/883 Q
5962-87710
(02QXA ACO ~ 02QYA
ACO)
(02QXA >T ~
02QYA >T)
TO-99
8
TBD
Call TI
Call TI
-55 to 125
LM158AHRQMLV
5962R8771002VGA Q
ACO
5962R8771002VGA Q
>T
5962R8771002VPA
5962R8771002VXA
ACTIVE
ACTIVE
CDIP
CFP
NAB
NAC
8
40
54
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
LM158AJRQMLV
5962R87710
02VPA Q ACO
02VPA Q >T
10
LM158AWG
RQMLV Q
5962R87710
02VXA ACO
02VXA >T
5962R8771003VGA
ACTIVE
TO-99
LMC
8
20
TBD
Call TI
Call TI
-55 to 125
LM158AHRLQMLV
5962R8771003VGA Q
ACO
5962R8771003VGA Q
>T
5962R8771003VPA
5962R8771003VXA
ACTIVE
ACTIVE
CDIP
CFP
NAB
NAC
8
40
54
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
LM158AJRLQV
5962R87710
03VPA Q ACO
03VPA Q >T
10
LM158AWG
RLQMLV Q
5962R87710
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
03VXA ACO
03VXA >T
LM158A MDE
PREVIEW
ACTIVE
DIESALE
TO-99
Y
0
8
Green (RoHS
& no Sb/Br)
Call TI
Call TI
Level-1-NA-UNLIM
Call TI
25 Only
LM158AH-SMD
LMC
20
TBD
-55 to 125
LM158AH-SMD
5962-8771002GA Q A
CO
5962-8771002GA Q >
T
LM158AH/883
ACTIVE
ACTIVE
TO-99
TO-99
LMC
LMC
8
8
20
20
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
LM158AH/883 Q ACO
LM158AH/883 Q >T
LM158AHRLQMLV
LM158AHRLQMLV
5962R8771003VGA Q
ACO
5962R8771003VGA Q
>T
LM158AHRQMLV
ACTIVE
TO-99
LMC
8
20
TBD
Call TI
Call TI
-55 to 125
LM158AHRQMLV
5962R8771002VGA Q
ACO
5962R8771002VGA Q
>T
LM158AJ/883
LM158AJRLQMLV
LM158AJRQMLV
LM158AWG/883
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CDIP
CDIP
CFP
NAB
NAB
NAB
NAC
8
8
40
40
40
54
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
-55 to 125
-55 to 125
LM158AJ/883
5962-87710
02PA Q ACO
02PA Q >T
LM158AJRLQV
5962R87710
03VPA Q ACO
03VPA Q >T
8
LM158AJRQMLV
5962R87710
02VPA Q ACO
02VPA Q >T
10
LM158AWG
/883 Q
5962-87710
(02QXA ACO ~ 02QYA
ACO)
(02QXA >T ~
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
02QYA >T)
LM158AWGRLQMLV
LM158AWGRQMLV
LM158H/883
ACTIVE
CFP
CFP
NAC
10
10
8
54
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-55 to 125
LM158AWG
RLQMLV Q
5962R87710
03VXA ACO
03VXA >T
ACTIVE
ACTIVE
NAC
LMC
54
20
-55 to 125
-55 to 125
LM158AWG
RQMLV Q
5962R87710
02VXA ACO
02VXA >T
TO-99
LM158H/883 Q ACO
LM158H/883 Q >T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM158QML, LM158QML-SP :
Military: LM158QML
•
Space: LM158QML-SP
•
NOTE: Qualified Version Definitions:
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 4
MECHANICAL DATA
NAB0008A
J08A (Rev M)
www.ti.com
MECHANICAL DATA
NAC0010A
WG10A (Rev H)
www.ti.com
IMPORTANT NOTICE
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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