LM1770TMFX/NOPB [TI]
具有无需外部补偿组件的低电压 SOT23 同步降压控制器 | DBV | 5 | -40 to 125;
| 型号： | LM1770TMFX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有无需外部补偿组件的低电压 SOT23 同步降压控制器 | DBV | 5 | -40 to 125 控制器 开关 光电二极管 输出元件 |
| 文件： | 总25页 (文件大小：554K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM1770
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SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013
LM1770 Low-Voltage SOT-23 Synchronous Buck Controller With No External
Compensation
Check for Samples: LM1770
1
FEATURES
DESCRIPTION
The LM1770 is an efficient synchronous buck
switching controller in a tiny SOT-23 package. The
constant on-time control scheme provides a simple
design free of compensation components, allowing
minimal component count and board space. It also
incorporates a unique input feed-forward to maintain
2
•
Input Voltage Range of 2.8V to 5.5V
0.8V Reference Voltage
•
•
•
•
•
•
•
No Compensation Required
Constant Frequency Across Input Range
Low Quiescent Current of 400µA
Internal Soft-start
a
constant frequency independent of the input
voltage. The LM1770 is optimized for a low voltage
input range of 2.8V to 5.5V and can provide an
adjustable output as low as 0.8V. Driving an external
high side PFET and low side NFET it can provide
efficiencies as high as 95%.
Short Circuit Protection
5-Pin SOT-23 Package
APPLICATIONS
Three versions of the LM1770 are available
depending on the switching frequency desired for the
application. Nominal switching frequencies are in the
range of 100kHz to 1000kHz.
•
Simple To Design, High Efficiency Step Down
Switching Regulators
•
•
•
•
•
Set-Top Boxes
Cable Modems
Printers
Digital Video Recorders
Servers
Typical Application Circuit
V
IN
V
IN
HG
LG
FB
V
OUT
LM1770
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM1770
SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013
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Connection Diagram
V
1
5 FB
4 HG
IN
GND 2
LG 3
Figure 1. 5-Pin SOT-23 (Top View)
See DBV Package
Pin Functions
Table 1. Pin Descriptions
Pin #
Name
VIN
Function
1
2
3
4
5
Input supply
Ground
GND
LG
NFET Gate Drive
PFET Gate Drive
Feedback Pin
HG
FB
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1) (2)
Absolute Maximum Ratings
VIN
-0.3V to 6V
−65°C to 150°C
150°C
Storage Temperature Range
Junction Temperature
Lead Temperature (soldering, 10sec)
ESD Rating
260°C
2.5kV
(1) Absolute Maximum Ratings indicate limits beyond which damage may occur to the device. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical
Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(1)
Operating Ratings
VIN to GND
2.8V to 5.5V
Junction Temperature Range (TJ)
−40°C to +125°C
(1) Absolute Maximum Ratings indicate limits beyond which damage may occur to the device. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical
Characteristics.
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(1)
Electrical Characteristics
Specifications with standard typeface are for TJ = 25°C, and those in bold face type apply over the full Junction Temperature
Range (−40°C to +125°C). Minimum and Maximum limits are specified through test, design or statistical correlation. Typical
values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. Unless
otherwise specified VIN = 3.3V.
Symbol
Parameter
Feedback pin voltage
Conditions
VIN = 3.3V
Min
Typ
0.80
0.79
-5
Max
0.818
0.808
Unit
VFB
0.782
0.772
V
VIN = 5.0V
ΔVFB / ΔVIN
Line Regulation
VIN = 2.8V to 5.5V
VFB = 0.9V
mV/V
µA
IQ
Operating Quiescent current
Switch On-Time
400
0.5
1.0
2.0
150
135
120
70
600
0.6
TON
LM1770S - (500ns)
LM1770T - (1000ns)
LM1770U - (2000ns)
LM1770S - (500ns)
LM1770T - (1000ns)
LM1770U - (2000ns)
0.4
0.8
1.6
µs
1.2
2.4
TOFF_MIN
Minimum Off-Time
250
225
220
ns
TD
IFB
Gate Drive Dead-Time
ns
nA
V
Feedback pin bias current
Under-voltage lock out
VFB = 0.9V
50
VUVLO
VUVLO_HYS
VSC_TH
VIN Rising Edge
2.6
30
2.8
Under-voltage lock out hysteresis
mV
V
Feedback pin Short Circuit Latch
Threshold
0.5
0.55
0.65
RDS(ON) 1
RDS(ON) 2
RDS(ON) 3
RDS(ON) 4
HG FET driver pull-up On resistance
IHG = 20 mA
5
9
9
5
Ω
Ω
Ω
Ω
HG FET driver pull-down On resistance IHG = 20 mA
LG FET driver pull-up On resistance
LG FET driver pull-down On resistance
ILG = 20 mA
ILG = 20 mA
(1) Absolute Maximum Ratings indicate limits beyond which damage may occur to the device. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical
Characteristics.
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Typical Performance Characteristics
TON vs Temperature (LM1770S)
Quiescent Current vs Temperature
0.54
0.53
0.52
0.51
0.50
0.49
0.48
0.47
500
450
400
350
300
250
200
150
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 2.
Figure 3.
TOFF vs Temperature
Feedback Voltage vs Temperature
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.802
0.801
0.800
0.799
0.798
0.797
0.796
0.795
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 4.
Figure 5.
Deadtime vs Temperature
Short Circuit Threshold vs Temperature
80.0
77.5
75.0
72.5
70.0
67.5
65.0
62.5
0.58
0.57
0.56
0.55
0.54
0.53
0.52
0.51
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
UVLO Threshold vs Temperature
TON vs VIN (LM1770S)
2.75
700
600
500
400
300
200
100
0
2.73
2.71
2.69
2.67
2.65
2.63
2.61
-50 -25
0
25
50
75 100 125
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TEMPERATURE (°C)
V
IN
(V)
Figure 8.
Figure 9.
TON vs Temperature (LM1770T)
TON vs VIN (LM1770T)
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
1400
1200
1000
800
600
400
200
0
-50 -25
0
25
50
75 100 125
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TEMPERATURE (°C)
V
IN
(V)
Figure 10.
Figure 11.
TON vs Temperature (LM1770U)
TON vs VIN (LM1770U)
2.08
2.06
2.04
2.02
2.00
1.98
1.96
1.94
3500
3000
2500
2000
1500
1000
500
0
-50 -25
0
25
50
75 100 125
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TEMPERATURE (°C)
V
IN
(V)
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
Efficiency vs IOUT
(VIN = 5V, VOUT = 3.3V)
Efficiency vs IOUT
(VIN = 5V, VOUT = 2.5V)
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50
0.00 0.75 1.50 2.25 3.00 3.75 4.50 5.25
I
(A)
OUT
I
(A)
OUT
Figure 14.
Figure 15.
Efficiency vs IOUT
(VIN = 5V, VOUT = 1V)
Efficiency vs IOUT
(VIN = 3.3V, VOUT = 0.8V)
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50
I
(A)
I
OUT
(A)
OUT
Figure 16.
Figure 17.
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BLOCK DIAGRAM
LM1770
V
IN
ON TIMER
Vin
UVLO
SD
OFF TIMER
Q
High Side
Driver
Q
HG
0.8V
Level Shift
and
Shoot
REGULATION
COMPARATOR
R
S
Q
Q
FB
Through
Protection
Low Side
Driver
LG
SD
UVLO
0.55V
R
S
Q
Q
/Soft Start
SHORT
CIRCUIT
PROTECTION
GND
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APPLICATION INFORMATION
THEORY OF APPLICATION
The LM1770 synchronous buck switcher has a control scheme that is referred to as constant on-time control.
This topology relies on a fixed switch on-time to regulate the output voltage. This on-time is internally set by
EEPROM and is available with three different set-points to allow for different frequency options. The LM1770
automatically adjusts the on-time during operation inversely with the input voltage (VIN) to maintain a constant
frequency. Therefore the switching frequency during continuous conduction mode is independent of the inductor
and capacitor size unlike hysteretic switchers.
At the beginning of the cycle the LM1770 turns on the high side PFET for a fixed duration. This on-time is
predetermined (internally set by EEPROM and adjusted by VIN) and the switch will not turn off until the timer has
completed its period. The PFET will then turn off for a minimum pre-determined time period. This minimum TOFF
of 150ns is internally set and cannot be adjusted. This is to prevent false triggering from occurring on the
comparator due to noise from the SW node transition. After the minimum TOFF period has expired, the PFET will
remain off until the comparator trip-point has been reached. Upon passing this trip-point (set at 0.8V at the
feedback pin), the PFET will turn back on and the process will repeat, thus regulating the output.
The NFET control is complementary to the PFET control with the exception of a short dead-time to prevent shoot
through from occurring.
DEVICE OPERATION
Timing Opinion
Three versions of the LM1770 are available each with a predetermined TON set internally by EEPROM. This TON
setting will determine the switching frequency for the application. Derivation and calculation of the switching
frequency’s dependence on VIN and TON can be seen in the following section.
In a PWM buck switcher the following equations can be manipulated to obtain the switching frequency.
Equation 1 shows the standard duty-cycle equation given by the volts-seconds balance on the inductor with the
following equations defining standard relationships:
VOUT
D =
VIN
(1)
(2)
TON = D x TP
1
fSW
TP =
(3)
(4)
Using this equation and solving for duty-cycle:
D = fSW x TON
Frequency can now be expressed as:
VOUT
F =
VIN x TON
(5)
Or simply written as:
VOUT
fSW
=
a
(6)
(7)
where,
α = VIN x TON
To maintain a set frequency in an application, α is always held constant by varying TON inversely with VIN. The
three versions of the LM1770 are identified by the on times at a VIN of 3.3V for consistency. For clarification see
Table 2:
Table 2. LM1770 "ON" Times Identification
Product ID
LM1770S
LM1770T
TON @ 3.3V
0.5µs
α (V µs)
1.65
1.0µs
3.3
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Table 2. LM1770 "ON" Times Identification (continued)
Product ID
TON @ 3.3V
α (V µs)
LM1770U
2.0µs
6.6
The variation of TON versus VIN can also be expressed graphically. These graphs can be found in the Typical
Performance Characteristics section.
With α being a constant regardless of the version of the LM1770 used, Equation 6 shows that the only
dependent variable remaining is VOUT. Since VOUT will be a constant in any application, the frequency will also
remain constant. The switching frequency at which the application runs depends upon the VOUT desired and the
LM1770 version chosen. For any VOUT, three frequency options (LM1770 versions) can be selected. This can be
seen in Table 3. The recommended frequency range of operation is 100kHz to 1000kHz.
Table 3. LM1770 VOUT Frequency Option
VOUT
Timing Options
500ns
485
1000ns
242
2000ns
121
0.8
1
606
303
152
1.2
1.5
1.8
2.5
3.3
727
364
182
909
455
227
1091
1515
2000
545
273
758
379
1000
500
SHORT-CIRCUIT PROTECTION
The LM1770 has an internal short circuit comparator that constantly monitors the feedback node (except during
soft-start). If the feedback voltage drops below 0.55V (equivalent to the output voltage dropping below 68% of
nominal), the comparator will trip causing the part to latch off. The LM1770 will not resume switching until the
input voltage is taken below the UVLO threshold and then brought back into its normal operating range. The
purpose of this function is to prevent a severe short circuit from causing damage to the application. Due to the
fast transient response of the LM1770 a severe short on the output causing the feedback to drop would only
occur if the load applied had an effective resistance that approaches the PMOS RDS(ON)
.
SOFT-START
To limit in-rush current and allow for a controlled startup the LM1770 incorporates an internal soft-start scheme.
Every time the input voltage rises through the UVLO threshold the LM1770 goes through an adaptive soft-start
that limits the on-time and expands the minimum off-time. In addition the part will only activate the PMOS
allowing a discontinuous mode of operation enabling a pre-biased startup. The time spent in soft-start will
depend on the load applied to the output, but is usually close to a set time that is dependent on the timing option.
The approximate soft-start time can be seen in Table 4 for each timing option.
Table 4. Soft-Start Time Approximations
Product ID
LM1770S
LM1770T
LM1770U
Timing
0.5µs
1.0µs
2.0µs
TSS
1ms
1.2ms
1.8ms
It should be noted that as soon as soft-start terminates the short-circuit protection is enabled. This means that if
the output voltage does not reach at least 68% of its final value the part will latch off. Therefore, if the input
supply is extremely slow rising such that at the end of soft-start the input voltage is still near the UVLO threshold,
a timing option should be chosen to ensure that maximum duty-cycle permits the output to meet the minimum
condition. As a general recommendation it is advisable to use the 2000ns option (LM1770U) in conditions where
the output voltage is 2.5V or greater to avoid false latch offs when there is concern regarding the input supply
slew rate.
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JITTER
The LM1770 utilizes a constant on-time control scheme that relies on the output voltage ripple to provide a
consistent switching frequency. Under certain conditions, excessive noise can couple onto the feedback pin
causing the switch node to appear to have a slight amount of jitter. This is not indicative of an unstable design.
The output voltage will still regulate to the exact same value. Careful component selection and layout should
minimize any external influence.
In addition to any external noise that can add to the jitter seen on the switch node, the LM1770 will always have
a slight amount of switch jitter. This is because the LM1770 makes a small alteration in the reference voltage
every 128 cycles to improve its accuracy and long term performance. This has the effect of causing a change in
the switching frequency at that instant. When viewed on an oscilloscope this can be seen as a jitter in the switch
node. The change in feedback voltage or output voltage, however, is almost indistinguishable.
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DESIGN GUIDE
The following section walks the designer through the steps necessary to select the external components to build
a fully functional power supply. As with any DC-DC converter numerous trade-offs are possible to optimize the
design for efficiency, size or performance. These will be taken into account and highlighted throughout this
discussion.
The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with
the FETs and parasitic resistances it can be approximated by:
VOUT
D =
VIN
(8)
A more accurate calculation for duty-cycle can be used that takes into account the voltage drops across the
FETs. Equation 9 can be used to determine the slight load dependency on switch frequency if needed. Otherwise
the simplified equation works well for component calculation.
VOUT + VDS_NMOS
D =
VIN + VDS_NMOS + VDS_PMOS
(9)
FREQUENCY SELECTION
The LM1770 is available with three preset timing options that select the on-time and hence determine the
switching frequency of the application. Increasing the switching frequency has the effect of reducing the inductor
size needed for the application while requiring a slight trade-off in efficiency. Table 5 shows the same frequency
table as shown previously in Table 3, with the exception that the recommended timing option for each VOUT is
highlighted. It is not recommended to use a high switching frequency with VOUT equal to or greater than 2.5V due
to the maximum duty-cycle limitations of the device coupled with the internal startup.
Table 5. LM1770 Recommended VOUT Frequency Option
VOUT
Timing Options
500ns
485
606
727
909
-
1000ns
242
303
364
455
545
-
2000ns
0.8
1
-
-
1.2
1.5
1.8
2.5
3.3
-
227
273
379
500
-
-
-
INDUCTOR SELECTION
The inductor selection is an iterative process likely requiring several passes before settling on a final value. The
reason for this is because it influences the amount of ripple seen at the output, a critical component to ensure
general stability of an adaptive on-time circuit. For the first pass at inductor selection the value can be obtained
by targeting a maximum peak-to-peak ripple current equal to 30% of the maximum load current. The inductor
current ripple (ΔIL) can be calculated by:
(VIN œ VOUT) x D
DIL =
L x fSW
(10)
Therefore, L can be initially set to the following by applying the 30% rule:
(VIN œ VOUT) x D
L =
0.3 x fSW x IOUT
(11)
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The other features of the inductor that can be selected besides inductance value are saturation current and core
material. Because the LM1770 does not have a current limit, it is recommended to have a saturation current
higher than the maximum output current to handle any ripple or momentary over-current events. The core
material also influences the saturation characteristics as ferrite materials have a hard saturation curve and care
should be taken such that they never saturate during normal use. A shielded inductor or low profile unshielded
inductor is recommended to reduce EMI. This also helps prevent any spurious noise from picking up on the
feedback node resulting in unexpected tripping of the feedback comparator.
OUTPUT CAPACITOR
One of the most important components to select with the LM1770 is the output capacitor. This is because its size
and ESR have a direct effect on the stability of the loop. A constant on-time control scheme works by sensing the
output voltage ripple and switching the FETs appropriately. The output voltage ripple on a buck converter can be
approximated by stating that the AC inductor ripple flows entirely into the output capacitor and is created by the
ESR of the capacitor. This can be expressed in the following equation:
ΔVOUT = ΔIL x RESR
(12)
To ensure stability, two constraints need to be met. The first is that there is sufficient ESR to create enough
voltage ripple at the feedback pin. The recommendation is to have at least 10mV of ripple seen at the feedback
pin. This can be calculated by multiplying the output voltage ripple by the gain seen through the feedback
resistors. This gain, H, can be calculated below:
VFB
0.8V
=
H =
VOUT
VOUT
(13)
If the output voltage is fairly high, causing significant attenuation through the feedback resistors, a feed-forward
capacitor can be used. This is actually recommended for most circuits as it improves performance. See the
Feed-Forward Capacitor section for more details.
The second criteria is to ensure that there is sufficient ripple at the output that is in-phase with the switch. The
problem exists that there is actually ripple caused by the capacitor charging and discharging, not only the ESR
ripple. Since these are effectively out of phase, problems can exist. To avoid this issue it is recommended that
the ratio of the two ripples (β) is always greater than 5. To calculate the minimum ESR value needed, the
following equation can be used.
b x tP
8 x C
RESR
í
(14)
In general the best capacitors to use are chemistries that have a known and consistent ESR across the entire
operating temperature range. Tantalum capacitors or similar chemistries such as Niobium Oxide perform well
along with certain families of Aluminum Electrolytics. Small value POSCAPs and SP CAPs also work as they
have sufficient ESR. When used in conjunction with a low value inductor it is possible to have an extremely
stable design. The only capacitors that require modification to the circuit are ceramic capacitors. Ceramic
capacitors cause problems meeting both criteria because they have low ESR and low capacitance. Therefore, if
they are to be used, an external ESR resistor (RSNS) should be added. This can be seen below in the following
circuit.
V
IN
C
IN
V
IN
Q
HG
LG
FB
1
L
R
1
SNS
V
OUT
LM1770
C
OUT
Q
2
C
FF
R
FB1
GND
R
FB2
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This circuit uses an additional resistor in series with the inductor to add ripple at the output. It is placed in this
location and used in combination with the feed-forward capacitor (CFF) to provide ripple to the feedback pin,
without adding ripple or a DC offset to the output. The benefit of using a ceramic capacitor is still obtained with
this technique. Because the addition of the resistor results in power loss, this circuit implementation is only
recommended for low currents (2A and below). The power loss and rating of the resistor should be taken into
account when selecting this component.
This circuit implementation utilizing the feed-forward capacitor begins to experience limitations when the output
voltage is small. Previously the circuit relied on the CFF for all the ripple at the feedback node by assuming that
the resistor divider was negligible. As VOUT decreases this can not be assumed. The resistor divider contributes a
larger amount of ripple which is problematic as it is also out of phase. Therefore the resistor location should be
changed to be in series with the output capacitor. This can be viewed as adding an effective ESR to the output
capacitor.
V
IN
C
IN
V
IN
Q
HG
LG
FB
1
L
1
V
OUT
LM1770
Q
2
RSNS
R
R
FB1
C
OUT
GND
FB2
FEED-FORWARD CAPACITOR
The feed-forward capacitor is used across the top feedback resistor to provide a lower impedance path for the
high frequency ripple without degrading the DC accuracy. Typically the value for this capacitor should be small
enough to prevent load transient errors because of the discharging time, but large enough to prevent attenuation
of the ripple voltage. In general a small ceramic capacitor in the range of 1nF to 10nF is sufficient.
If CFF is used then it can be assumed that the ripple voltage seen at the feedback pin is the same as the ripple
voltage at the output. The attenuation factor H no longer needs to be used. However, in these conditions, it is
recommended to have a minimum of 20mV ripple at the feedback pin. The use of a CFF capacitor is
recommended as it improves the regulation and stability of the design. However, its benefit is diminished as VOUT
starts approaching VREF , therefore it is not needed in this situation.
INPUT CAPACITOR
The dominating factor that usually sets an input capacitors’ size is the current handling ability. This is usually
determined by the package size and ESR of the capacitor. If these two criteria are met then there usually should
be enough capacitance to prevent impedance interactions with the source. In general it is recommended to use a
ceramic capacitor for the input as they provide a low impedance and small footprint. One important note is to use
a good dielectric for the ceramic capacitor such as X5R or X7R. These provide better over temperature
performance and also minimize the DC voltage derating that occurs on Y5V capacitors. To calculate the input
capacitor RMS current, the equation below can be used:
«
2
DIL
∆
≈
≈
ICIN_RMS = IOUT
D
1 - D +
∆
«
2
12 x IOUT
(15)
which can be approximated by,
ICIN_RMS = IOUT
x
D(1 - D)
(16)
13
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MOSFET Selection
The two FETs used in the LM1770 requires attention to selection of parameters to ensure optimal performance of
the power supply. The high side FET should be a PFET and the low side an NFET. These can be integrated in
one package or as two separate packages. The criteria that matter in selection are listed below:
VDS VOLTAGE RATING
The first selection criteria is to select FETs that have sufficient VDS voltage ratings to handle the maximum
voltage seen at the input plus any transient spikes that can occur from parasitic ringing. In general most FETs
available for this application will have ratings from 8V to 20V. If a larger voltage rating is used then the
performance will most likely be degraded because of higher gate capacitance.
RDSON
The RDS(ON) specification is important as it determines several attributes of the FET and the overall power supply.
The first is that it sets the maximum current of the FET for a given package. A lower RDS(ON) will permit a higher
allowable current and reduce conduction losses, however, it will increase the gate capacitance and the switching
losses.
GATE DRIVE
The next step is to ensure that the FETs are capable of switching at the low Vin supplies used by the LM1770.
The FET should have the Rdson specified at either 1.8V or 2.5V to ensure that it can switch effectively as soon
as the LM1770 starts up.
GATE CHARGE
Because the LM1770 utilizes a fixed dead-time scheme to prevent cross conduction, the FET transitions must
occur in this time. The rise and fall time of the FETs gate can be influenced by several factors including the gate
capacitance. Therefore the total gate charge of both FETs should be limited to less than 20nC at 4.5V VGS. The
lower the number the faster the FETs should switch and the better the efficiency.
RISE / FALL TIMES
A better indication of the actual switching times of the FETs can be found in their Electrical Characteristics table.
The rise and fall time should be specified and selected to be at a minimum. This helps improve efficiency and
ensuring that shoot through does not occur.
GATE CHARGE RATIO
Another consideration in selecting the FETs is to pay attention to the Qgd / Qgs ratio. The reason for this is that
proper selection can prevent spurious turn on. If we look at the NFET for example, when the FET is turning off,
the gate signal will pull to ground. Conversely the PFET will be turning on, causing the SW node to rise towards
VIN. The gate to drain capacitance of the NFET couples the SW node to the gate and will cause it to rise. If this
voltage is excessive, then it could weakly turn on the low side FET causing an efficiency loss. However, this
coupling is mitigated by having a large gate to source capacitance of the FET, which helps to hold the gate
voltage down. Ideally, a very low Qgd / Qgs would be ideal, but in practice it is common to find the number
around 1. As a general rule, the lower the ratio, the better.
If the above selection criteria have been met it is useful to generate a figure of merit to allow comparison
between the FETs. One such method is to multiply the RDS(ON) of the FET by the total gate charge. This allows
an easy comparison of the different FETs available. Once again, the lower the product, the better.
FEEDBACK RESISTORS
The feedback resistors are used to scale the output voltage to the internal reference value such that the loop can
be regulated. The feedback resistors should not be made arbitrarily large as this creates a high impedance node
at the feedback pin that is more susceptible to noise. A combined value of 50kΩ for the two resistors is
adequate. To calculate the resistor values use the equation below. Typically the low side resistor is initially set to
a pre-determined value such as 10 kΩ.
14
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SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013
«
∆
≈
≈
∆
«
VOUT
VFB
- 1
RFB1 = RFB2
(17)
VFB is the internal reference voltage that can be found in the Electrical Characteristics table or approximated by
0.8V.
The output voltage value can be set in a precise manner by taking into account the fact that the reference
voltage is regulating the bottom of the output ripple as opposed to the average value. This relationship is shown
in the figure below.
V
OUT_ACTUAL
DV
OUT
V
OUT_SET
It can be seen that the average output voltage (VOUT_ACTUAL) is higher than the output voltage (VOUT_SET)
that was calculated by the earlier equation by exactly half the output voltage ripple. The output voltage that is
targeted for regulation may then be appended according to the voltage ripple. This can be seen below:
VOUT_ACTUAL= VOUT_SET + ½ΔVOUT = VOUT_SET + ½ΔIL x RESR
(18)
Efficiency Calculations
One of the most important parameters to calculate during the design stage is the expected efficiency of the
system. This can help determine optimal FET selection and can be used to calculate expected temperature rise
of the individual components. The individual losses of each component are broken down and the equations are
listed below:
QUIESCENT CURRENT
The quiescent current consumed by the LM1770 is one of the major sources of loss within the controller.
However, from a system standpoint this is usually less than 0.5% of the overall efficiency. Therefore, it could
easily be omitted but is shown for completeness:
PIQ = VIN x IQ
(19)
CONDUCTION LOSS
There are three losses associated with the external FETs. From the DC standpoint there is the I-squared R loss,
caused by the on resistance of the FET. This can be modeled for the PMOS by:
2
PP_COND = D x RDSON_PMOS x IOUT
(20)
(21)
and the NMOS by:
2
PN_COND = (1 - D) x RDSON_NMOS x IOUT
SWITCHING LOSS
The next loss is the switching loss that is caused by the need to charge and discharge the gate capacitance of
the FETs every cycle. This can be approximated by:
PP_SWITCH = VIN x Qg_PMOS x fSW
(22)
for the PMOS, and the same approach can be adapted for the NMOS:
PN_SWITCH = VIN x Qg_NMOS x fSW
(23)
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TRANSITIONAL LOSS
The last FET power loss is the transitional loss. This is caused by switching the PMOS while it is conducting
current. This approach only models the PMOS transition, the NMOS loss is considered negligible because it has
minimal drain to source voltage when it switches due to the conduction of the body diode. Therefore the
transitional loss of the PMOS can be modeled by:
PP_TRANSITIONAL = 0.5 x VIN x IOUT x fSW x (tr + tf)
(24)
tr and tf are the rise and fall times of the FET and can be found in their corresponding datasheet. Typically these
numbers are simulated using a 6Ω drive, which corresponds well to the LM1770. Given this, no adjustment is
needed.
DCR LOSS
The last source of power loss in the system that needs to be calculated is the loss associated with the inductor
resistance (DCR) which can be calculated by
2
PDCR = RDCR x IOUT
(25)
EFFICIENCY
The efficiency, η, can then be calculated by summing all the power losses and then using the equation below:
POUT
h =
POUT + PLOSSES
(26)
Thermals
By breaking down the individual power loss in each component it makes it easy to determine the temperature
rise of each component. Generally the expected temperature rise of the LM1770 is extremely low as it is not in
the power path. Therefore the only two items of concern are the PMOS and the NMOS. The power loss in the
PMOS is the sum of the conduction loss and transitional loss, while the NMOS only has conduction loss. It is
assumed that any loss associated with the body diode conduction during the dead-time is negligible.
For completeness of design it is important to watch out for the temperature rise of the inductor. Assuming the
inductor is kept out of saturation the predominant loss will be the DC copper resistance. At higher frequencies,
depending on the core material, the core loss could approach or exceed the DCR losses. Consult with the
inductor manufacturer for appropriate temp curves based on current.
Layout
The LM1770, like all switching regulators, requires careful attention to layout to ensure optimal performance. The
following steps should be taken to aid in the layout. For more information refer to Application Note AN-1299
SNVA074.
1. Ensure that the ground connections of the input capacitor, output capacitor and NMOS are as close as
possible. Ideally these should all be grounded together in close proximity on the component side of the
board.
2. Keep the switch node small to minimize EMI without degrading thermal cooling of the FETs.
3. Locate the feedback resistors close to the IC and keep the feedback trace as short as possible. Do not run
any feedback traces near the switch node.
4. Keep the gate traces short and keep them away from the switch node as much as possible.
5. If a small bypass capacitor is used on VIN (0.1µF) place it as close to the pin, with the ground connection as
close to the chip ground as possible.
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SNVS403C –SEPTEMBER 2005–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 16
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM1770SMF/NOPB
LM1770TMF/NOPB
LM1770TMFX/NOPB
LM1770UMF/NOPB
LM1770UMFX/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
1000 RoHS & Green
1000 RoHS & Green
3000 RoHS & Green
1000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
SKJB
SKKB
SKKB
SKLB
SKLB
SN
SN
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM1770SMF/NOPB
LM1770TMF/NOPB
LM1770TMFX/NOPB
LM1770UMF/NOPB
LM1770UMFX/NOPB
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
1000
1000
3000
1000
3000
178.0
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM1770SMF/NOPB
LM1770TMF/NOPB
LM1770TMFX/NOPB
LM1770UMF/NOPB
LM1770UMFX/NOPB
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
1000
1000
3000
1000
3000
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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