LM20146MH/NOPB [TI]
6A，可调节频率同步降压稳压器 | PWP | 16 | -40 to 125;
| 型号： | LM20146MH/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 6A，可调节频率同步降压稳压器 | PWP | 16 | -40 to 125 开关 光电二极管 稳压器 |
| 文件： | 总33页 (文件大小：997K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM20146
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SNVS563C –FEBRUARY 2008–REVISED APRIL 2013
LM20146 6A, Adjustable Frequency Synchronous Buck Regulator
Check for Samples: LM20146
1
FEATURES
DESCRIPTION
The LM20146 is a full featured adjustable frequency
synchronous buck regulator capable of delivering up
to 6A of continuous output current. The current mode
control loop can be compensated to be stable with
virtually any type of output capacitor. For most cases,
compensating the device only requires two external
components, providing maximum flexibility and ease
of use. The device is optimized to work over the input
voltage range of 2.95V to 5.5V making it suitable for
a wide variety of low voltage systems.
2
•
•
Input Voltage Range 2.95V to 5.5V
Accurate Current Limit Minimizes Inductor
Size
•
•
97% Peak Efficiency
Adjustable Switching Frequency (250 kHz to
750 kHz)
•
•
•
•
•
•
•
•
16mΩ and 20mΩ Integrated FET Switches
Starts up into Pre-biased Loads
Output Voltage Tracking
The device features internal over voltage protection
(OVP) and over current protection (OCP) circuits for
increased system reliability. A precision enable pin
and integrated UVLO allows the turn-on of the device
to be tightly controlled and sequenced. Start-up
inrush currents are limited by both an internally fixed
and externally adjustable Soft-Start circuit. Fault
detection and supply sequencing are possible with
the integrated power good circuit.
Peak Current Mode Control
Adjustable Output Voltage Down to 0.8V
Adjustable Soft-Start with External Capacitor
Precision Enable Pin with Hysteresis
Integrated OVP, UVLO, Power Good and
Thermal Shutdown
•
16-Pin HTSSOP Exposed Pad Package
The LM20146 is designed to work well in multi-rail
power supply architectures. The output voltage of the
device can be configured to track a higher voltage rail
using the SS/TRK pin. If the output of the LM20146 is
pre-biased at startup it will not pull the ouput low.
APPLICATIONS
•
•
•
Simple to Design, High Efficiency Point of
Load Regulation from a 5V or 3.3V Bus
High Performance DSPs, FPGAs, ASICs and
Microprocessors
The frequency of this device can be adjusted from
250 kHz to 750 kHz by connecting an external
resistor from the RT pin to ground.
Broadband, Networking and Optical
Communications Infrastructure
The LM20146 is offered in a 16-pin HTSSOP
package with an exposed pad that can be soldered to
the PCB, eliminating the need for bulky heatsinks.
Typical Application Circuit
L
LM20146
V
SW
FB
PVIN
OUT
V
IN
R
R
FB1
EN
C
IN
R
F
C
OUT
AVIN
RT
FB2
PGOOD
VCC
C
F
R
T
COMP
C
VCC
SS/TRK
AGND
R
C1
PGND
C
SS
C
C1
(optional)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
LM20146
SNVS563C –FEBRUARY 2008–REVISED APRIL 2013
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Connection Diagram
RT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SS/TRK
FB
AGND
AVIN
VCC
EN
PGOOD
COMP
NC
EP
PVIN
PVIN
SW
PGND
PGND
SW
Figure 1. Top View
16-Pin HTSSOP
See PWP Package
PIN DESCRIPTIONS
Pin #
Name
Description
1
SS/TRK
Soft-Start or Tracking control input. An internal 5 µA current source charges an external capacitor to set the
Soft-Start ramp rate. If driven by a external source less than 800 mV, this pin overrides the internal reference
that sets the output voltage. If left open, an internal 1ms Soft-Start ramp is activated.
2
3
FB
Feedback input to the error amplifier from the regulated output. This pin is connected to the inverting input of
the internal transconductance error amplifier. An 800 mV reference connected to the non-inverting input of the
error amplifier sets the closed loop regulation voltage at the FB pin.
PGOOD
Power good output signal. Open drain output indicating the output voltage is regulating within tolerance. A
pull-up resistor of 10 kΩ to 100 kΩ is recommend for most applications.
4
5
COMP
NC
External compensation pin. Connect a resistor and capacitor to this pin to compensate the device.
Connect this pin to GND to ensure proper operation
6,7
PVIN
Input voltage to the power switches inside the device. These pins should be connected together at the device.
A low ESR capacitor should be placed near these pins to stabilize the input voltage.
8,9
10,11
12
SW
PGND
EN
Switch pin. The PWM output of the internal power switches.
Power ground pin for the internal power switches.
Precision enable input for the device. An external voltage divider can be used to set the device turn-on
threshold. If not used the EN pin should be connected to PVIN.
13
14
15
16
EP
VCC
AVIN
Internal 2.7V sub-regulator. This pin should be bypassed with a 1 µF ceramic capacitor.
Analog input supply that generates the internal bias. Must be connected to PVIN through a low pass RC filter.
Quiet analog ground for the internal bias circuitry.
AGND
RT
Frequency adjust pin. Connecting a resistor on this pin to ground will set the oscillator frequency.
Exposed Pad
Exposed metal pad on the underside of the package with a weak electrical connection to ground. It is
recommended to connect this pad to the PC board ground plane in order to improve heat dissipation.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings(1)(2)
Voltages from the indicated pins to GND
AVIN, PVIN, EN, PGOOD, SS/TRK, COMP, FB, RT
Storage Temperature
-0.3V to +6V
-65°C to 150°C
150°C
Junction Temperature
Power Dissipation(3)
2.6W
Lead Temperature (Soldering, 10 sec)
Minimum ESD Rating(4)
260°C
±2kV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junctions-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using: PD_MAX = (TJ_MAX – TA)/θJA. The maximum power dissipations of 2.6W is determined using TA = 25°C, θJA = 25°C/W, and TJ_MAX
= 125°C. The θJA specification of 25°C/W listed in the electrical characteristics table is measured with the part surface mounted to a 2" x
2" FR4 4 layer board. See Figure 36 for more detailed θJA information.
(4) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor to each pin.
Operating Ratings
PVIN, AVIN to GND
2.95V to 5.5V
Junction Temperature
−40°C to + 125°C
Electrical Characteristics
Unless otherwise stated, the following conditions apply: AVIN = PVIN = VIN = 5V. Limits in standard type are for TJ = 25°C
only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits
are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at
TJ = 25°C, and are provided for reference purposes only.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
VFB
Feedback pin voltage
VIN = 2.95V to 5.5V
0.788
0.8
0.81
2
V
ΔVOUT/ΔIOUT
ICL
Load Regulation
IOUT = 100 mA to 6A
VIN = 3.3V
0.08
8.5
20
%/A
A
Switch Current Limit Threshold
High-Side Switch On Resistance
Low-Side Switch On Resistance
Operating Quiescent Current
Shutdown Quiescent current
VIN Under Voltage Lockout
VIN Under Voltage Lockout Hysteresis
VCC Voltage
7.35
2.45
9.35
27
RDS_ON
RDS_ON
IQ
ISW = 3.5A
mΩ
mΩ
mA
µA
V
ISW = 3.5A
16
23
Non-switching, VFB = VCOMP
VEN = 0V
3.5
75
6
ISD
180
2.95
100
2.95
7
VUVLO
VUVLO_HYS
VVCC
Rising VIN
2.7
45
Falling VIN
mV
V
IVCC = 0 µA
2.45
2
2.7
4.5
3
ISS
Soft-Start Pin Source Current
SS/TRK Accuracy, VSS - VFB
VSS/TRK = 0V
VSS/TRK = 0.4V
µA
mV
VTRACK
-10
15
Oscillator
FOSCH
FOSCL
Oscillator Frequency
Oscillator Frequency
Maximum Duty Cycle
Minimum On Time
RT = 49.9 kΩ
RT = 249 kΩ
ILOAD = 0A
675
225
750
260
85
825
290
kHz
kHz
%
DCMAX
TON_TIME
TCL_BLANK
100
80
ns
Current Sense Blanking Time
After Rising VSW
ns
Error Amplifier and Modulator
IFB
Feedback pin bias current
VFB = 0.8V
1
100
nA
µA
µA
ICOMP_SRC
ICOMP_SNK
COMP Output Source Current
COMP Output Sink Current
VFB = 0.6V, VCOMP = 0.5V
VFB = 1.0V, VCOMP = 0.6V
80
80
100
100
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Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: AVIN = PVIN = VIN = 5V. Limits in standard type are for TJ = 25°C
only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits
are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at
TJ = 25°C, and are provided for reference purposes only.
Symbol
Gm
Parameter
Conditions
Min
450
Typ Max
Unit
Error Amplifier Transconductance
Error Amplifier Voltage Gain
ICOMP = ± 50 µA
510
600 µmho
AVOL
2000
V/V
Power Good
VOVP
Over Voltage Protection Rising Threshold
Over Voltage Protection Hysteresis
PGOOD Rising Threshold
With respect to VFB
With respect to VFB
105
92
108
2
111
3
%
%
VOVP_HYS
VPGTH
94
2
96
3
%
VPGHYS
TPGOOD
IOL
PGOOD Falling Hysteresis
%
PGOOD deglitch time
16
1
µs
mA
nA
PGOOD Low Sink Current
VPGOOD = 0.4V
VPGOOD = 5V
0.6
IOH
PGOOD High Leakage Current
5
100
Enable
VIH_EN
EN Pin turn-on Threshold
EN Pin Hysteresis
VEN Rising
1.08
1.18 1.28
V
VEN_HYS
Thermal Shutdown
TSD
66
mV
Thermal Shutdown
160
10
°C
°C
TSD_HYS
Thermal Shutdown Hysteresis
Thermal Resistance
θJA Junction to Ambient
See(1)
25
°C/W
(1) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junctions-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using: PD_MAX = (TJ_MAX – TA)/θJA. The maximum power dissipations of 2.6W is determined using TA = 25°C, θJA = 25°C/W, and TJ_MAX
= 125°C. The θJA specification of 25°C/W listed in the electrical characteristics table is measured with the part surface mounted to a 2" x
2" FR4 4 layer board. See Figure 36 for more detailed θJA information.
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Typical Performance Characteristics
Unless otherwise specified: CIN = COUT = 100µF, L = 1.0µH (TDK SPM6530T-1R0M120), VIN = 5V, VOUT = 1.2V, RLOAD
1.2Ω, fSW = 500 kHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others.
=
Efficiency
vs.
Load Current (VIN = 5V)
Efficiency
vs.
Load Current (VIN = 3.3V)
VOUT = 3.3V
VOUT = 2.5V
VOUT = 2.5V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.2V
L=SPM6530T-1R0M120
L=SPM6530T-1R0M120
Figure 2.
Figure 3.
High-Side FET Resistance
vs.
Low-Side FET Resistance
vs.
Temperature (TJ)
Temperature (TJ)
Figure 4.
Figure 5.
Error Amplifier Gain
vs.
Frequency
Line Regulation
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
Unless otherwise specified: CIN = COUT = 100µF, L = 1.0µH (TDK SPM6530T-1R0M120), VIN = 5V, VOUT = 1.2V, RLOAD
=
1.2Ω, fSW = 500 kHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others.
Feedback Pin Voltage
vs.
Temperature (TJ)
Load Regulation
Figure 8.
Figure 9.
Switching Frequency
vs.
Temperature (TJ)
Switching Frequency
vs.
RT
Figure 10.
Figure 11.
Quiescent Current
vs.
VIN (Not Switching)
Shutdown Current
vs.
Temperature (TJ)
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
Unless otherwise specified: CIN = COUT = 100µF, L = 1.0µH (TDK SPM6530T-1R0M120), VIN = 5V, VOUT = 1.2V, RLOAD
1.2Ω, fSW = 500 kHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others.
=
Enable Threshold
vs.
Temperature (TJ)
UVLO Threshold
vs.
Temperature (TJ)
Figure 14.
Figure 15.
Peak Current Limit
vs.
Temperature (TJ)
Peak Current Limit
vs.
VOUT
Figure 16.
Figure 17.
Peak Current Limit
vs.
VIN
Load Transient Response
VOUT (100 mV/DIV)
IOUT (2A/DIV)
IOUT (600 mA to 6A)
TIME (100 és/DIV)
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
Unless otherwise specified: CIN = COUT = 100µF, L = 1.0µH (TDK SPM6530T-1R0M120), VIN = 5V, VOUT = 1.2V, RLOAD
=
1.2Ω, fSW = 500 kHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others.
Line Transient Response
Start-Up (Soft-Start)
VOUT (50 mV/DIV)
RLOAD = 1.2Ö
VEN (5V/DIV)
VIN (1V/DIV)
VOUT (500 mV/DIV)
CSS/TRK = 68 nF
CSS/TRK = 33 nF
CSS/TRK = None
VIN (3V to 5V)
TIME (100 és/DIV)
TIME (2 ms/DIV)
Figure 20.
Figure 21.
Start-Up (Tracking)
Power Down
VEN (1V/DIV)
RLOAD = 1.2Ö
RLOAD = 1.2Ö
RFB1 = 0Ö
VSS/TRK (500 mV/DIV)
VOUT (500 mV/DIV)
VOUT (500 mV/DIV)
TIME (200 és/DIV)
TIME (4 ms/DIV)
Figure 22.
Figure 23.
Short Circuit Input Current
PGOOD
vs.
IPGOOD
vs.
VIN
Figure 24.
Figure 25.
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Block Diagram
+2.7V
REGULATOR
VCC
AVIN
UVLO
+
-
2.7V
SLOPE COMP
PVIN
COMP
2.7V
CURRENT SENSE
+
5 mA
(50 ms)
DISCHARGE
SS/TRK
FB
ERROR AMP
m
g
= 510 mmho
DISCHARGE
+
-
CURRENT
LIMIT
+
+
-
8.5
PVIN
VREF
+
-
800 mV
+
-
PWM COMPARATOR
OVERVOLTAGE
DIODE
EMULATION
+
-
864 mV
+
-
PG-L
CONTROL
LOGIC
SW
UNDERVOLTAGE
752 mV
+
-
PVIN
THERMAL
PROTECTION
+
-
1.18V
EN
PGND
PG-L
OSCILLATOR
PGOOD
RT
AGND
Figure 26.
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OPERATION DESCRIPTION
General
The LM20146 switching regulator features all of the functions necessary to implement an efficient low voltage
buck regulator using a minimum number of external components. This easy to use regulator features two
integrated switches and is capable of supplying up to 6A of continuous output current. The regulator utilizes peak
current mode control with nonlinear slope compensation to optimize stability and transient response over the
entire output voltage range. Peak current mode control also provides inherent line feed-forward, cycle-by-cycle
current limiting and easy loop compensation. The switching frequency can be varied from 250 kHz to 750 kHz.
The device can operate at high switching frequency allowing use of a small inductor while still achieving high
efficiency. The precision internal voltage reference allows the output to be set as low as 0.8V. Fault protection
features include: current limiting, thermal shutdown, over voltage protection, and shutdown capability. The device
is available in the HTSSOP package featuring an exposed pad to aid thermal dissipation. The LM20146 can be
used in numerous applications to efficiently step-down from a 5V or 3.3V bus. The typical application circuit for
the LM20146 is shown in Figure 29 in the design guide.
Precision Enable
The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal.
This pin is a precision analog input that enables the device when the voltage exceeds 1.18V (typical). The EN pin
has 66 mV of hysteresis and will disable the output when the enable voltage falls below 1.11V (typical). If the EN
pin is not used, it should be connected to VIN. Since the enable pin has a precise turn-on threshold it can be
used along with an external resistor divider network from VIN to configure the device to turn-on at a precise input
voltage. The precision enable circuitry will remain active even when the device is disabled.
Peak current Mode Control
In most cases, the peak current mode control architecture used in the LM20146 only requires two external
components to achieve a stable design. The compensation can be selected to accommodate any output
capacitor type or value. The external compensation also allows the user to set the crossover frequency and
optimize the transient performance of the device.
For duty cycles above 50% all current mode control buck converters require the addition of an artificial ramp to
avoid sub-harmonic oscillation. This artificial linear ramp is commonly referred to as slope compensation. What
makes the LM20146 unique is the amount of slope compensation will change depending on the output voltage.
When operating at high output voltages the device will have more slope compensation than when operating at
lower output voltages. This is accomplished in the LM20146 by using a non-linear parabolic ramp for the slope
compensation. The parabolic slope compensation of the LM20146 is much better than the traditional linear slope
compensation because it optimizes the stability of the device over the entire output voltage range.
Current Limit
The precise current limit of the LM20146 is set at the factory to be within 10% over the entire operating
temperature range. This enables the device to operate with smaller inductors that have lower saturation currents.
When the peak inductor current reaches the current limit threshold, an over current event is triggered and the
internal high-side FET turns off and the low-side FET turns on allowing the inductor current to ramp down until
the next switching cycle. For each sequential over-current event, the reference voltage is decremented and PWM
pulses are skipped resulting in a current limit that does not aggressively fold back for brief over-current events,
while at the same time providing frequency and voltage foldback protection during hard short circuit conditions.
Soft-Start and Voltage Tracking
The SS/TRK pin is a dual function pin that can be used to set the start up time or track an external voltage
source. The start up or Soft-Start time can be adjusted by connecting a capacitor from the SS/TRK pin to ground.
The Soft-Start feature allows the regulator output to gradually reach the steady state operating point, thus
reducing stresses on the input supply and controlling start up current. If no Soft-Start capacitor is used the device
defaults to the internal Soft-Start circuitry resulting in a start up time of approximately 1 ms. For applications that
require a monotonic start up or utilize the PGOOD pin, an external Soft-Start capacitor is recommended. The
SS/TRK pin can also be set to track an external voltage source. The tracking behavior can be adjusted by two
external resistors connected to the SS/TRK pin as shown in Figure 34. in the design guide.
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Pre-Bias Start up Capability
The LM20146 is in a pre-biased state when the device starts up with an output voltage greater than zero. This
often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these
applications the output can be pre-biased through parasitic conduction paths from one supply rail to another.
Even though the LM20146 is a synchronous converter it will not pull the output low when a prebias condition
exists. During start up the LM20146 will not sink current until the Soft-Start voltage exceeds the voltage on the
FB pin. Since the device can not sink current it protects the load from damage that might otherwise occur if
current is conducted through the parasitic paths of the load.
Power Good and Over Voltage Fault Handling
The LM20146 has built in under and over voltage comparators that control the power switches. Whenever there
is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turn-
on the low-side FET, and pull the PGOOD pin low. The low-side FET will remain on until either the FB voltage
falls back into regulation or the zero cross detection is triggered which in turn tri-states the FETs. If the output
reaches the UVP threshold the part will continue switching and the PGOOD pin will be asserted and go low.
Typical values for the PGOOD resistor are on the order of 100 kΩ or less. To avoid false tripping during transient
glitches the PGOOD pin has 16 µs of built in deglitch time to both rising and falling edges. The powergood
behavior for fault conditions is illustrated in Figure 27.
CURRENT LIMIT
I
L
Soft Start Time
V
2.7V
0.8V
SS
V
FB FOLDBACK
V
OVP
}
V
OVPHYS
0.8V
0.0V
V
V
UVP
FB
V
}
PGHYS
V
ENABLE
T
PGOOD
V
PGOOD
F
SW FOLDBACK
V
SWITCH
OVP-
LOW SIDE ON
UVP
PRE-BIASED
STARTUP CONDITION
DISABLE
CURRENT LIMIT
Figure 27. Powergood Behavior
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UVLO
The LM20146 has a built-in under-voltage lockout protection circuit that keeps the device from switching until the
input voltage reaches 2.7V (typical). The UVLO threshold has 45 mV of hysteresis that keeps the device from
responding to power-on glitches during start up. If desired the turn-on point of the supply can be changed by
using the precision enable pin and a resistor divider network connected to VIN as shown in Figure 33. in the
design guide.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When activated, typically at 160°C, the LM20146 tri-states the power FETs
and resets soft start. After the junction cools to approximately 150°C, the part starts up using the normal start up
routine. This feature is provided to prevent catastrophic failures from accidental device overheating.
Light Load Operation
The LM20146 offers increased efficiency when operating at light loads. Whenever the load current is reduced to
a point where the peak to peak inductor ripple current is greater than two times the load current, the part will
enter the diode emulation mode preventing significant negative inductor current. The point at which this occurs is
the critical conduction boundary and can be calculated by the following equation:
(VIN œ VOUT) x D
IBOUNDARY
=
2 x L x fSW
(1)
Several diagrams are shown in Figure 28 illustrating continuous conduction mode (CCM), discontinuous
conduction mode, and the boundary condition.
It can be seen that in diode emulation mode, whenever the inductor current reaches zero the SW node will
become high impedance. Ringing will occur on this pin as a result of the LC tank circuit formed by the inductor
and the parasitic capacitance at the node. If this ringing is of concern an additional RC snubber circuit can be
added from the switch node to ground.
At very light loads, usually below 100 mA, several pulses may be skipped in between switching cycles, effectively
reducing the switching frequency and further improving light-load efficiency.
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Continuous Conduction Mode (CCM)
V
IN
Time (s)
Continuous Conduction Mode (CCM)
I
AVERAGE
Time (s)
DCM - CCM Boundary
I
AVERAGE
Time (s)
Discontinuous Conduction Mode (DCM)
V
IN
Time (s)
Discontinuous Conduction Mode (DCM)
I
Peak
Time (s)
Figure 28. Modes of Operation for LM20146
Design Guide
This section walks the designer through the steps necessary to select the external components to build a fully
functional power supply. As with any DC-DC converter numerous trade-offs are possible to optimize the design
for efficiency, size, or performance. These will be taken into account and highlighted throughout this discussion.
To facilitate component selection discussions the circuit shown in Figure 29 below may be used as a reference.
Unless otherwise indicated all formulas assume units of Amps (A) for current, Farads (F) for capacitance,
Henries (H) for inductance and Volts (V) for voltage.
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L
LM20146
PVIN
V
IN
SW
FB
V
OUT
R
FB1
EN
R
C
F
C
IN
C
OUT
AVIN
V
IN
R
FB2
F
R
PG
RT
PGOOD
VCC
V
PG
RT
COMP
R
SS/TRK
PGND GND
C1
C
VCC
C
SS
C
C1
Figure 29. Typical Application Circuit
The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with
the FETs and parasitic resistances it can be approximated by:
VOUT
D =
VIN
(2)
Inductor Selection (L)
The inductor value is determined based on the operating frequency, load current, ripple current, and duty cycle.
The inductor selected should have a saturation current rating greater than the peak current limit of the device.
Keep in mind the specified current limit does not account for delay of the current limit comparator, therefore the
current limit in the application may be higher than the specified value. To optimize the performance and prevent
the device from entering current limit at maximum load, the inductance is typically selected such that the ripple
current, ΔiL, is less than 30% of the rated output current. Figure 30, shown below illustrates the switch and
inductor ripple current waveforms. Once the input voltage, output voltage, operating frequency, and desired ripple
current are known, the minimum value for the inductor can be calculated by the formula shown below:
(VIN - VOUT) x D
LMIN
=
DiL x f
SW
(3)
V
SW
V
IN
Time
I
L
I
= I
OUT
DI
L
L AVG
Time
Figure 30. Switch and Inductor Current Waveforms
If needed, slightly smaller value inductors can be used, however, the peak inductor current, IOUT + ΔiL/2, should
be kept below the peak current limit of the device. In general, the inductor ripple current, ΔiL, should be greater
than 10% of the rated output current to provide adequate current sense information for the current mode control
loop. If the ripple current in the inductor is too low, the control loop will not have sufficient current sense
information and can be prone to instability.
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Output Capacitor Selection (COUT
)
The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load
conditions. A wide range of output capacitors may be used with the LM20146 that provide excellent performance.
The best performance is typically obtained using ceramic, SP, or OSCON type chemistries. Typical trade-offs are
that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes,
while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading
conditions.
When selecting the value for the output capacitor the two performance characteristics to consider are the output
voltage ripple and transient response. The output voltage ripple can be approximated by using the formula shown
below.
1
DVOUT = DiL x
RESR
+
8 x fSW x COUT
where
•
•
•
•
ΔVOUT (V) is the amount of peak to peak voltage ripple at the power supply output
RESR (Ω) is the series resistance of the output capacitor
fSW(Hz) is the switching frequency
COUT (F) is the output capacitance used in the design
(4)
The amount of output ripple that can be tolerated is application specific; however a general recommendation is to
keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes
preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor
the value of the capacitance can drop significantly with applied voltage. The output capacitor selection will also
affect the output voltage droop during a load transient. The peak droop on the output voltage during a load
transient is dependent on many factors; however, an approximation of the transient droop ignoring loop
bandwidth can be obtained using the following equation.
2
L x DIOUTSTEP
VDROOP = DIOUTSTEP x RESR
+
COUT x (VIN - VOUT
)
where
•
•
•
•
•
•
•
COUT (F) is the minimum required output capacitance
L (H) is the value of the inductor
VDROOP (V) is the output voltage drop ignoring loop bandwidth considerations
ΔIOUTSTEP (A) is the load step change
RESR (Ω) is the output capacitor ESR
VIN (V) is the input voltage
VOUT (V) is the set regulator output voltage
(5)
Both the tolerance and voltage coefficient of the capacitor needs to be examined when designing for a specific
output ripple or transient drop target.
Input Capacitor Selection (CIN)
Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the
switch current during the on-time. In general it is recommended to use a ceramic capacitor for the input as they
provide both a low impedance and small footprint. One important note is to use a good dielectric for the ceramic
capacitor such as X5R or X7R. These provide better over temperature performance and also minimize the DC
voltage derating that occurs on Y5V capacitors. For most applications, a 22 µF, X5R, 6.3V input capacitor is
sufficient; however, additional capacitance may be required if the connection to the input supply is far from the
PVIN pins. The input capacitor should be placed as close as possible PVIN and PGND pins of the device.
Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good
approximation for the required ripple current rating is given by the relationship:
IIN-RMS = IOUT D(1 - D)
(6)
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As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty
cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output
current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance
capacitors to provide the best input filtering for the device.
Setting the output Voltage (RFB1, RFB2
)
The resistors RFB1 and RFB2 are selected to set the output voltage for the device. Table 1, shown below, provides
suggestions for RFB1 and RFB2 for common output voltages.
Table 1. Suggested Values for RFB1 and RFB2
RFB1(kΩ)
short
4.99
RFB2(kΩ)
open
10
VOUT
0.8
1.2
1.5
1.8
2.5
3.3
8.87
10.2
12.7
10.2
21.5
10.2
31.6
10.2
If different output voltages are required, RFB2 should be selected to be between 4.99 kΩ to 49.9 kΩ and RFB1 can
be calculated using the equation below.
VOUT
x RFB2
- 1
RFB1
=
0.8
(7)
Adjusting the Operating Frequency (RT)
The operating frequency of the LM20146 can be adjusted by connecting a resistor from the RT pin to ground.
The equation shown below can be used to calculate the value of RT for a given operating frequency.
78000
- 55
RT =
fSW
where
•
•
fSW is the switching frequency in kHz
RT is the frequency adjust resistor in kΩ
(8)
Please refer to the curve Oscillator Frequency verses RT in the Typical Performance Characteristics section If the
RT resistor is omitted the device will not operate.
Loop Compensation (RC1, CC1
)
The purpose of loop compensation is to meet static and dynamic performance requirements while maintaining
adequate stability. Optimal loop compensation depends on the output capacitor, inductor, load, and the device
itself. Table 2 below gives values for the compensation network that will result in a stable system when using a
100 µF, 6.3V ceramic X5R output capacitor and 1 µH inductor.
Table 2. Recommended Compensation for
COUT = 100 µF, L = 1.5 µH & fSW = 500 kHz
VIN
VOUT
3.30
2.50
1.80
1.50
1.20
0.80
2.50
1.80
CC1 (nF)
2.2
RC1 (kΩ)
15.4
13.3
10.7
9.31
7.87
4.42
8.45
7.5
5.00
5.00
5.00
5.00
5.00
5.00
3.30
3.30
2.2
2.2
2.2
2.2
2.7
2.7
2.7
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Table 2. Recommended Compensation for
COUT = 100 µF, L = 1.5 µH & fSW = 500 kHz (continued)
VIN
VOUT
1.50
1.20
0.80
CC1 (nF)
2.7
RC1 (kΩ)
6.81
3.30
3.30
3.30
2.7
5.9
2.7
4.32
If the desired solution differs from the table above the loop transfer function should be analyzed to optimize the
loop compensation. The overall loop transfer function is the product of the power stage and the feedback network
transfer functions. For stability purposes, the objective is to have a loop gain slope that is -20db/decade from a
very low frequency to beyond the crossover frequency. Figure 31, shown below, shows the transfer functions for
power stage, feedback/compensation network, and the resulting closed loop system for the LM20146.
Output Filter Pole, f
P(FIL)
A
M
0 dB
Output Filter Zero, f
Z(FIL)
Complex Double Pole, f
P(MOD)
Error Amp Pole, f
P1(EA)
A
EA
Optional Error Amp
Pole, f
P2(EA)
0 dB
Error Amp Zero, f
Z(EA)
A
EA
+ A
M
Error Amp Pole, f
P(EA)
0 dB
Complex Double Pole, f
P(MOD)
f
f
/2
C
SW
FREQUENCY (Hz)
Figure 31. LM20146 Loop Compensation
The power stage transfer function is dictated by the modulator, output LC filter, and load; while the feedback
transfer function is set by the feedback resistor ratio, error amp gain, and external compensation network.
To achieve a -20dB/decade slope, the error amplifier zero, located at fZ(EA), should positioned to cancel the
output filter pole (fP(FIL)). An additional error amp pole, located at fP2(EA), can be added to cancel the output filter
zero at fZ(FIL). Cancellation of the output filter zero is recommended if larger value, non-ceramic output capacitors
are used.
Compensation of the LM20146 is achieved by adding an RC network as shown in Figure 32 below.
LM20146
COMP
R
C1
C
C2
(optional)
C
C1
Figure 32. Compensation Network for LM20146
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A good starting value for CC1 for most applications is 3.3 nF. Once the value of CC1 is chosen the value of RC
should be calculated using the equation below to cancel the output filter pole (FP(FIL)) as shown in Figure 31.
-1
D x fSW
CC1
IOUT
1-D
1
x
+
+
-
RC1
=
48750*VIN
2 x fSW x L
COUT
VOUT fSW x L
(9)
A higher crossover frequency can be obtained, usually at the expense of phase margin, by lowering the value of
CC1 and recalculating the value of RC1. Likewise, increasing CC1 and recalculating RC1 will provide additional
phase margin at a lower crossover frequency. As with any attempt to compensate the LM20146 the stability of
the system should be verified for desired transient droop and settling time.
If the output filter zero, FZ(FIL) approaches the crossover frequency (FC), an additional capacitor (CC2) should be
placed at the COMP pin to ground. This capacitor adds a pole to cancel the output filter zero assuring the
crossover frequency will occur before the double pole at fSW/2 degrades the phase margin. The output filter zero
is set by the output capacitor value and ESR as shown in the equation below.
1
fZ(FIL)
=
2 x p x COUT x RESR
(10)
If needed, the value for CC2 should be calculated using the equation shown below.
COUT x RESR
CC2
=
RC1
where
•
•
RESR is the output capacitor series resistance
RC1 is the calculated compensation resistance
(11)
AVIN Filtering Components (CF and RF)
To prevent high frequency noise spikes from disturbing the sensitive analog circuitry connected to the AVIN and
AGND pins, a high frequency RC filter is required between PVIN and AVIN. These components are shown in
Figure 29. as CF and RF. The required value for RF is 1Ω. CF must be used. Recommended value of CF is 1.0
µF. The filter capacitor, CF should be placed as close to the IC as possible with a direct connection from AVIN to
AGND. A good quality X5R or X7R ceramic capacitor should be used for CF.
Sub-Regulator Bypass Capacitor (CVCC
)
The capacitor at the VCC pin provides noise filtering and stability for the internal sub-regulator. The
recommended value of CVCC should be no smaller than 1 µF and no greater than 10 µF. The capacitor should be
a good quality ceramic X5R or X7R capacitor. In general, a 1 µF ceramic capacitor is recommended for most
applications.
Setting the Start up Time (CSS
)
The addition of a capacitor connected from the SS pin to ground sets the time at which the output voltage will
reach the final regulated value. Larger values for CSS will result in longer start up times. Table 3, shown below
provides a list of soft start capacitors and the corresponding typical start up times.
Table 3. Start Up Times for Different Soft-Start Capacitors
Start Up Time (ms)
CSS (nF)
none
33
1
5
10
15
20
68
100
120
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If different start up times are needed the equation shown below can be used to calculate the start up time.
0.8V x CSS
tSS
=
ISS
(12)
As shown above, the start up time is influenced by the value of the Soft-Start capacitor CSS(F) and the 5 µA Soft-
Start pin current ISS(A).
While the Soft-Start capacitor can be sized to meet many start up requirements, there are limitations to its size.
The Soft-Start time can never be faster than 1ms due to the internal default 1 ms start up time. When the device
is enabled there is an approximate time interval of 50 µs when the Soft-Start capacitor will be discharged just
prior to the Soft-Start ramp. If the enable pin is rapidly pulsed or the Soft-Start capacitor is large there may not be
enough time for CSS to completely discharge resulting in start up times less than predicted. To aid in the
discharging of the Soft-Start capacitor during long disable periods an external 1 MΩ resistor from SS/TRK to
ground can be used without greatly affecting the start-up time.
Using Precision Enable and Power Good
The precision enable (EN) and power good (PGOOD) pins of the LM20146 can be used to address many
sequencing requirements. The turn-on of the LM20146 can be controlled with the precision enable pin by using
two external resistors as shown in Figure 33.
External
Power Supply
V
OUT1
LM20146
R
A
R
B
V
OUT2
EN
Figure 33. Sequencing LM20146 with Precision Enable
The value for resistor RB can be selected by the user to control the current through the divider. Typically this
resistor will be selected to be between 10 kΩ and 1 MΩ. Once the value for RB is chosen the resistor RA can be
solved using the equation below to set the desired turn-on voltage.
VTO
VIH_EN
x R
- 1
RA =
B
(13)
When designing for a specific turn-on threshold (VTO) the tolerance on the input supply, enable threshold
(VIH_EN), and external resistors needs to be considered to insure proper turn-on of the device.
The LM20146 features an open drain power good (PGOOD) pin to sequence external supplies or loads and to
provide fault detection. This pin requires an external resistor (RPG) to pull PGOOD high while when the output is
within the PGOOD tolerance window. Typical values for this resistor range from 10 kΩ to 100 kΩ.
Tracking an External Supply
By using a properly chosen resistor divider network connected to the SS/TRK pin, as shown in Figure 34, the
output of the LM20146 can be configured to track an external voltage source to obtain a simultaneous or
ratiometric start up.
External
Power Supply
V
OUT1
LM20146
R1
R2
EN
V
OUT2
SS/TRK
Figure 34. Tracking an External Supply
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Since the Soft-Start charging current ISS is always present on the SS/TRK pin, the size of R2 should be less than
10 kΩ to minimize the errors in the tracking output. Once a value for R2 is selected the value for R1 can be
calculated using appropriate equation in Figure 35, to give the desired start up. Figure 35 shows two common
start up sequences; the top waveform shows a simultaneous start up while the waveform at the bottom illustrates
a ratiometric start up.
SIMULTANEOUS START UP
V
V
OUT1
OUT2
≈
’
V
OUT2
0.8V
∆
∆
÷
x
÷
-1
R1=
V
R2
«
◊
V
EN
< 0.8 x V
OUT2
OUT1
TIME
RATIOMETRIC START UP
V
OUT1
(
)
-1
x
R2
V
R1=
OUT1
V
OUT2
V
EN
TIME
Figure 35. Common Start Up Sequences
A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these
systems the higher voltage, VOUT1, usually powers the I/O, and the lower voltage, VOUT2, powers the core. A
simultaneous start up provides a more robust power up for these applications since it avoids turning on any
parasitic conduction paths that may exist between the core and the I/O pins of the processor.
The second most common power on behavior is known as a ratiometric start up. This start up is preferred in
applications where both supplies need to be at the final value at the same time.
Similar to the Soft-Start function, the fastest start up possible is 1ms regardless of the rise time of the tracking
voltage. When using the track feature the final voltage seen by the SS/TRACK pin should exceed 1V to provide
sufficient overdrive and transient immunity.
Thermal Considerations
The thermal characteristics of the LM20146 are specified using the parameter θJA, which relates the junction
temperature to the ambient temperature. Although the value of θJA is dependant on many variables, it still can be
used to approximate the operating junction temperature of the device.
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To obtain an estimate of the device junction temperature, one may use the following relationship:
TJ = PDθJA + TA
(14)
and
PD = PIN x (1 - Efficiency) - 1.1 x IOUT2 x DCR
where
•
•
•
•
•
•
TJ is the junction temperature in °C
PIN is the input power in Watts (PIN = VIN x IIN)
θJA is the junction to ambient thermal resistance for the LM20146
TA is the ambient temperature in °C
IOUT is the output load current
DCR is the inductor series resistance
(15)
It is important to always keep the operating junction temperature (TJ) below 125°C for reliable operation. If the
junction temperature exceeds 160°C the device will cycle in and out of thermal shutdown. If thermal shutdown
occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device.
Figure 36, shown below, provides a better approximation of the θJA for a given PCB copper area on a 4 layer
board. The PCB heatsink area consists of 2oz. copper located on the bottom layer of the PCB directly under the
HTSSOP exposed pad. The bottom copper area is connected to the HTSSOP exposed pad by means of a 4 x 4
array of 12 mil thermal vias.
No Air Flow
200 LFPM
500 LPFM
Figure 36. Thermal Resistance vs PCB Area
PCB Layout Considerations
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched
rapidly. The first loop starts from the input capacitor, to the regulator VIN pin, to the regulator SW pin, to the
inductor then out to the output capacitor and load. The second loop starts from the output capacitor ground, to
the regulator PGND pins, to the inductor and then out to the load (see Figure 37). To minimize both loop areas
the input capacitor should be placed as close as possible to the PVIN pin. Grounding for both the input and
output capacitor should consist of a small localized top side plane that connects to PGND and the die attach pad
(DAP). The inductor should be placed as close as possible to the SW pin and output capacitor.
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2. Minimize the copper area of the switch node. Since the LM20146 has the SW pins on opposite sides of the
package it is recommended to via these pins down to the bottom or internal layer with 2 to 4 vias on each SW
pin. The SW pins should be directly connected with a trace that runs across the bottom of the package. To
minimize IR losses this trace should be no smaller that 50 mils wide, but no larger than 100 mils wide to keep the
copper area to a minimum. In general the SW pins should not be connected on the top layer since it could block
the ground return path for the power ground. The inductor should be placed as close as possible to one of the
SW pins to further minimize the copper area of the switch node.
3. Have a single point ground for all device analog grounds located under the DAP. The ground connections for
the compensation, feedback, and Soft-Start components should be connected together then routed to the AGND
pin of the device. The AGND pin should connect to PGND under the DAP. This prevents any switched or load
currents from flowing in the analog ground plane. If not properly handled poor grounding can result in degraded
load regulation or erratic switching behavior.
4. Minimize trace length to the FB pin. Since the feedback node can be high impedance the trace from the output
resistor divider to FB pin should be as short as possible. This is most important when high value resistors are
used to set the output voltage. The feedback trace should be routed away from the SW pin and inductor to avoid
contaminating the feedback signal with switch noise.
5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or
output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure
feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the
best output accuracy.
6. Provide adequate device heatsinking. Use as many vias as is possible to connect the DAP to the power plane
heatsink. For best results use a 4x4 via array with a minimum via diameter of 12 mils. See the Thermal
Considerations section to insure enough copper heatsinking area is used to keep the junction temperature below
125°C.
LM20146
L
SW
PVIN
V
OUT
C
IN
C
OUT
PGND
LOOP1
LOOP2
Figure 37. Schematic of LM20146 Highlighting Layout Sensitive Nodes
Typical Application Circuits
This section provides several application solutions with a bill of materials. All bill of materials reference the below
figure. The compensation for these solutions were optimized to work over a wide range of input and output
voltages; if a faster transient response is needed reduce the value of CC1 and calculate the new value for RC1 as
outlined in the design guide.
L
LM20146
V
OUT
SW
FB
V
IN
PVIN
EN
R
R
FB1
R
F
C
C
OUT
IN
AVIN
RT
FB2
C
F
PGOOD
R
T
VCC
COMP
C
VCC
R
C1
SS/TRK
PGND AGND
C
SS
C
C
C1
C2
(optional)
Figure 38.
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Bill of Materials (VIN = 5V, VOUT = 3.3V, FSW = 500kHz, IOUTMAX = 6A)
Designator
U1
Description
Synchronous Buck Regulator
100µF, 1210, X5R, 6.3V
100µF, 1210, X5R, 6.3V
1µH, 7.8 mΩ
Part Number
LM20146
Manufacturer
Texas Instruments
TDK
Qty
1
CIN
C3225X5R0J107M
C3225X5R0J107M
SPM6530T-1R0M120
CRCW06031R0J-e3
GRM188R71C104KA01
GRM188R60J105KA01
CRCW06031432F-e3
GRM1885C1H102JA01
VJ0603Y333KXXA
CRCW06031003F-e3
CRCW06033162F-e3
CRCW06031022F-e3
1
COUT
L
TDK
1
TDK
1
RF
1Ω, 0603
Vishay-Dale
Murata
1
CF
100nF, 0603, X7R, 16V
1µF, 0603, X5R, 6.3V
14.3 kΩ, 0603
1
CVCC
RC1
Murata
1
Vishay-Dale
Murata
1
CC1
1nF, 0603, COG, 50V
33nF, 0603, X7R, 25V
100kΩ, 0603
1
CSS
RT
Vishay-Vitramon
Vishay-Dale
Vishay-Dale
Vishay-Dale
1
1
RFB1
RFB2
31.6kΩ, 0603
1
10.2kΩ, 0603
1
Bill of Materials (VIN = 3.3V to 5V, VOUT = 1.2V, FSW =750kHz, IOUTMAX = 6A)
Designator
U1
Description
Synchronous Buck Regulator
100µF, 1210, X5R, 6.3V
100µF, 1210, X5R, 6.3V
0.68µH, 5.39 mΩ
Part Number
LM20146
Manufacturer
Texas Instruments
TDK
Qty
1
CIN
C3225X5R0J107M
C3225X5R0J107M
SPM6530T-R68M140
CRCW06031R0J-e3
GRM188R71C104KA01
GRM188R60J105KA01
CRCW06034532F-e3
VJ0603Y182KXXA
VJ0603Y333KXXA
CRCW06034872F-e3
CRCW06034991F-e3
CRCW06031002F-e3
1
COUT
L
TDK
1
TDK
1
RF
1Ω, 0603
Vishay-Dale
Murata
1
CF
100nF, 0603, X7R, 16V
1µF, 0603, X5R, 6.3V
4.53kΩ, 0603
1
CVCC
RC1
Murata
1
Vishay-Dale
Vishay-Vitramon
Vishay-Vitramon
Vishay-Dale
Vishay-Dale
Vishay-Dale
1
CC1
1.8nF, 0603, X7R, 25V
33nF, 0603, X7R, 25V
48.7kΩ, 0603
1
CSS
RT
1
1
RFB1
RFB2
4.99kΩ, 0603
1
10kΩ, 0603
1
Copyright © 2008–2013, Texas Instruments Incorporated
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23
Product Folder Links: LM20146
LM20146
SNVS563C –FEBRUARY 2008–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 23
24
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM20146
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM20146MH/NOPB
LM20146MHE/NOPB
LM20146MHX/NOPB
ACTIVE
HTSSOP
HTSSOP
HTSSOP
PWP
16
16
16
92
RoHS & Green
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
L20146
MH
ACTIVE
ACTIVE
PWP
250
SN
SN
L20146
MH
PWP
2500 RoHS & Green
L20146
MH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM20146MHE/NOPB
LM20146MHX/NOPB
HTSSOP PWP
HTSSOP PWP
16
16
250
178.0
330.0
12.4
12.4
6.95
6.95
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM20146MHE/NOPB
LM20146MHX/NOPB
HTSSOP
HTSSOP
PWP
PWP
16
16
250
210.0
367.0
185.0
367.0
35.0
35.0
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
PWP HTSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM20146MH/NOPB
16
92
495
8
2514.6
4.06
Pack Materials-Page 3
PACKAGE OUTLINE
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
0.19
4.5
4.3
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
4X 0.166 MAX
NOTE 5
2X 1.34 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
3.3
2.7
17
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
3.3
2.7
4214868/A 02/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3.3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
17
SYMM
(3.3)
(5)
NOTE 9
14X (0.65)
8
9
(
0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4214868/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3.3)
17
SYMM
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.69 X 3.69
3.3 X 3.3 (SHOWN)
3.01 X 3.01
0.125
0.15
0.175
2.79 X 2.79
4214868/A 02/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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