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LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

LM25122-Q1 具有多相功能的宽输入同步升压控制器

1 特性

2 应用

1

•

符合 AEC-Q100 1 级标准（T_A= –40°C 至

125°C）

•

12V、24V 和 48V 电源系统

汽车启停

•

最高输入电压：42V

音频电源

最低输入电压：3V（启动时为 4.5V）

输出电压最高可达 50V

旁路 (V_OUT= V_IN) 运行

精度为 ±1.0% 的 1.2V 基准

自由运行和同步开关频率最高可达 600 kHz

峰值电流模式控制

高电流升压电源

3 说明

LM25122 是一款支持多相位的同步升压控制器，面向

高效同步升压稳压器应用。此控制方法基于峰值电流

模式控制。电流模式控制可提供内部线路前馈、逐周期

电流限制和简化的环路补偿。

稳健耐用的 3A 集成栅极驱动器

自适应死区时间控制

开关频率最高可通过编程设定为 600kHz。通过两个支

持自适应死区时间控制的稳健耐用 N 通道金属氧化物

半导体场效应晶体管 (MOSFET) 栅极驱动器来实现更

高效率。一个用户可选二极管仿真模式还可实现断续模

式运行，以提高轻负载时的效率。

可选二极管仿真模式

可编程逐周期电流限制

断续模式过载保护

可编程线路欠压闭锁 (UVLO)

可编程软启动

一个内部电荷泵可针对高侧同步开关实现 100% 占空

比（旁路运行）。一个 180º 相移时钟输出可实现简单

多相位交叉配置。其他功能包括：热关断、频率同

步、断续模式电流限制和可调线路欠压锁定。

热关断保护

低关断静态电流：9μA

可编程斜率补偿

可编程跳周模式减少待机功耗

允许使用外部 VCC 电源

电感器分布式直流电阻 (DCR) 电流感应功能

多相位功能

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

LM25122-Q1

HTSSOP (20)

6.50mm x 4.40mm

耐热增强型 20 引脚散热薄型小外形尺寸封装

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

(HTSSOP)

简化的应用示意图

V

OUT

IN

+

VCC

CSN

BST

SW

LO

HO

COMP

FB

CSP

VIN

UVLO

SLOPE

RES

SS

SYNCIN/RT

SYNCOUT

MODE

PGND

AGND

OPT

LM25122

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVSAF0

LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

www.ti.com.cn

7.3 Feature Description................................................. 13

7.4 Device Functional Modes........................................ 20

Application and Implementation ........................ 23

8.1 Application Information............................................ 23

8.2 Typical Application .................................................. 32

Power Supply Recommendations...................... 40

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Typical Characteristics.............................................. 9

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7.2 Functional Block Diagram ....................................... 12

8

9

10 Layout................................................................... 40

10.1 Layout Guidelines ................................................. 40

10.2 Layout Example .................................................... 40

11 器件和文档支持 ..................................................... 41

11.1 社区资源................................................................ 41

11.2 商标....................................................................... 41

11.3 静电放电警告......................................................... 41

11.4 Glossary................................................................ 41

12 机械、封装和可订购信息....................................... 41

7

4 修订历史记录

Changes from Original (December 2015) to Revision A

Page

•

产品预览至量产数据版本 ....................................................................................................................................................... 1

2

LM25122-Q1

www.ti.com.cn

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

5 Pin Configuration and Functions

PWP Package

20-Pin HTSSOP With Exposed Pad

Top View

SYNCOUT

OPT

1

2

3

4

5

6

7

8

20

19

18

17

16

15

14

13

12

11

BST

HO

CSN

SW

CSP

VCC

VIN

LO

EP

UVLO

PGND

RES

SS

SYNCIN/RT

AGND

MODE

SLOPE

COMP

9

10

FB

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

AGND

9

G

Analog ground connection. Return for the internal voltage reference and analog circuits.

High-side driver supply for bootstrap gate drive. Connect to the cathode of the external bootstrap

diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-

side N-channel MOSFET gate and should be placed as close to controller as possible. An internal

BST charge pump will supply 200-µA current into bootstrap capacitor for bypass operation.

BST

20

P

Output of the internal error amplifier. The loop compensation network should be connected between

this pin and the FB pin.

COMP

CSN

11

3

O

I

Inverting input of current sense amplifier. Connect to the negative-side of the current sense resistor.

Non-inverting input of current sense amplifier. Connect to the positive-side of the current sense

resistor.

CSP

4

I

Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin

sets the output voltage level. The regulation threshold at the FB pin is 1.2 V. The controller is

configured as slave mode if the FB pin voltage is above 2.7 V at initial power-on.

FB

10

I

High-side N-channel MOSFET gate drive output. Connect to the gate of the high-side synchronous

N-channel MOSFET switch through a short, low inductance path.

HO

LO

19

16

O

Low-side N-channel MOSFET gate drive output. Connect to the gate of the low-side N-channel

MOSFET switch through a short, low inductance path.

Switching mode selection pin. 700-kΩ pullup and 100-kΩ pulldown resistor internal hold MODE pin

to 0.15 V as a default. By adding external pullup or pulldown resistor, MODE pin voltage can be

programmed. When MODE pin voltage is greater than 1.2 V diode emulation mode threshold,

forced PWM mode is enabled, allowing current to flow in either direction through the high-side N-

channel MOSFET switch. When MODE pin voltage is less than 1.2 V, the controller works in diode

emulation mode. Skip cycle comparator is activated as a default. If MODE pin is grounded, the

controller still operates in diode emulation mode, but the skip cycle comparator will not be triggered

in normal operation, this enables pulse skipping operation at light load.

MODE

13

I

Clock synchronization selection pin. This pin also enables/disables SYNCOUT related with

master/slave configuration. The OPT pin should not be left floating.

OPT

2

I

Power ground connection pin for low-side N-channel MOSFET gate driver. Connect directly to the

source terminal of the low-side N-channel MOSFET switch.

PGND

15

G

The restart timer pin for an external capacitor that configures hiccup mode off-time and restart delay

during over load conditions. Connect directly to the AGND when hiccup mode operation is not

required.

RES

14

O

(1) G = Ground, I = Input, O = Output, P = Power

3

LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

www.ti.com.cn

Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

SLOPE

12

I

Slope compensation is programmed by a single resistor between SLOPE and the AGND.

Soft-start programming pin. An external capacitor and an internal 10-μA current source set the ramp

rate of the internal error amplifier reference during soft-start.

SS

7

Switching node of the boost regulator. Connect to the bootstrap capacitor, the source terminal of the

high-side N-channel MOSFET switch and the drain terminal of the low-side N-channel MOSFET

switch through short, low inductance paths.

SW

18

I/O

The internal oscillator frequency is programmed by a single resistor between RT and the AGND.

The internal oscillator can be synchronized to an external clock by applying a positive pulse signal

into this SYNCIN pin. The recommended maximum internal oscillator frequency in master

configuration is 1.2 MHz which leads to 600 kHz maximum switching frequency.

SYNCIN/RT

SYNCOUT

8

1

I

Clock output pin. SYNCOUT provides 180º shifted clock output for an interleaved operation.

SYNCOUT pin can be left floating when it is not used. See Slave Mode and SYNCOUT section.

O

Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the

shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4 V and below

1.2 V, the regulator is in standby mode with the VCC regulator operational and no switching at the

HO and LO outputs. If the UVLO pin voltage is above 1.2 V, the startup sequence begins. A 10-μA

current source at UVLO pin is enabled when UVLO exceeds 1.2 V and flows through the external

UVLO resistors to provide hysteresis. The UVLO pin should not be left floating.

UVLO

6

I

VCC bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to

controller as possible.

VCC

VIN

EP

17

5

P/O/I

P/I

Supply voltage input source for the VCC regulator. Connect to input capacitor and source power

supply connection with short, low impedance paths.

Exposed pad of the package. No internal electrical connections. Should be soldered to the large

ground plane to reduce thermal resistance.

EP

N/A

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

MIN

–0.3

–5.0

–0.3

–40

MAX

UNIT

V

Input

VIN, CSP, CSN

BST to SW, FB, MODE, UVLO, OPT, VCC⁽²⁾

50

15

V

SW

60

V

BST

75

V

SS, SLOPE, SYNCIN/RT

CSP to CSN, PGND

HO to SW

7

V

0.3

V

BST to SW+0.3

V

Output⁽³⁾

LO

VCC+0.3

7

V

COMP, RES, SYNCOUT

Junction Temperature

Storage temperature

V

Thermal

T_stg

150

ºC

°C

–55

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Unless

otherwise specified, all voltages are referenced to AGND pin.

(2) See Application Information when input supply voltage is less than the VCC voltage.

(3) All output pins are not specified to have an external voltage applied.

4

LM25122-Q1

www.ti.com.cn

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

Corner pins (1, 10, 11,

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per AEC

Q100-011

and 20)

Other pins

±1000

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

Input supply voltage⁽²⁾

VIN

4.5

42

14

V

Low-side driver bias voltage

High-side driver bias voltage

VCC

BST to SW

3.8

3

Current sense common mode CSP, CSN

range⁽²⁾

42

Switch node voltage

Junction temperature

SW

T_J

50

V

–40

125

ºC

(1) Recommended Operating Conditions are conditions under which operation of the device is intended to be functional, but does not

guarantee specific performance limits.

(2) Minimum VIN operating voltage is always 4.5 V. The minimum input power supply voltage can be 3.0 V after start-up, assuming VIN

voltage is supplied from an available external source.

6.4 Thermal Information

LM25122-Q1

PWP

(HTSSOP)

20 PINS

36.0

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

ºC/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

20.1

16.8

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JB

16.7

ψ_JCbot

1.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

5

LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

www.ti.com.cn

6.5 Electrical Characteristics

Unless otherwise specified, these specifications apply for –40°C ≤ T_J≤ +125°C, V_VIN= 12 V, V_VCC= 8.3 V, R_T= 20 kΩ, no

load on LO and HO. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIN SUPPLY

I_SHUTDOWNVIN shutdown current

I_BIASVIN operating current (exclude

the current into RT resistor)

V_UVLO= 0 V

9

4

17

5

µA

V_UVLO= 2 V, non-switching

mA

VCC REGULATOR

V_CC(REG)VCC regulation

No load

6.9

50

7.6

8.3

0.25

0.5

V

V_VIN= 4.5 V, no external load

V_VIN= 4.5 V, I_VCC= 25 mA

V_VCC= 0 V

VCC dropout (VIN to VCC)

0.28

62

V

VCC sourcing current limit

mA

V

V_VCC= 8.3 V

3.5

4.5

4.0

5

8

VCC operating current (exclude

the current into RT resistor)

I_VCC

V_VCC= 12 V

VCC rising, V_VIN= 4.5 V

VCC falling, V_VIN= 4.5 V

3.9

4.1

3.7

VCC undervoltage threshold

VCC undervoltage hysteresis

V

0.385

V

UNDERVOLTAGE LOCKOUT

UVLO threshold

UVLO rising

V_UVLO= 1.4 V

UVLO rising

1.17

7

1.20

10

1.23

13

V

µA

V

UVLO hysteresis current

UVLO standby enable threshold

UVLO standby enable hysteresis

0.3

0.4

0.1

0.5

0.125

V

MODE

Diode emulation mode threshold MODE rising

Diode emulation mode hysteresis

Default MODE voltage

1.20

145

1.24

0.1

1.28

170

V

155

mV

V

COMP rising, measured at COMP

1.290

1.245

40

Default skip cycle threshold

Skip cycle hysteresis

COMP falling, measured at COMP

Measured at COMP

V

mV

ERROR AMPLIFIER

V_REFFB reference voltage

Measured at FB, V_FB= V_COMP

V_FB= V_REF

1.188

1.200

5

1.212

0.25

V

nA

V

FB input bias current

I_SOURCE= 2 mA, V_VCC= 4.5 V

I_SOURCE= 2 mA, V_VCC= 12 V

I_SINK= 2 mA

2.75

3.40

V_OH

COMP output high voltage

V

V_OL

A_OL

f_BW

COMP output low voltage

DC gain

V

80

3

dB

MHz

V

Unity gain bandwidth

Slave mode threshold

FB rising

2.7

3.4

500

2.9

OSCILLATOR

f_SW1

Switching frequency 1

R_T= 20 kΩ

400

450

1.2

2.5

2.0

kHz

V

RT output voltage

RT sync rising threshold

RT sync falling threshold

Minimum sync pulse width

RT rising

RT falling

V

1.6

V

100

ns

SYNCOUT

OPT

SYNCOUT high-state voltage

SYNCOUT low-state voltage

I_SYNCOUT= –1 mA

I_SYNCOUT= 1 mA

3.3

4.3

V

0.15

0.25

6

LM25122-Q1

www.ti.com.cn

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

Electrical Characteristics (continued)

Unless otherwise specified, these specifications apply for –40°C ≤ T_J≤ +125°C, V_VIN= 12 V, V_VCC= 8.3 V, R_T= 20 kΩ, no

load on LO and HO. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Synchronization selection

threshold

OPT rising

2.0

3.0

4.0

V

SLOPE COMPENSATION

SLOPE output voltage

1.17

1.20

1.23

V

R_SLOPE= 20 kΩ, f_SW= 100 kHz, 50%

duty cycle, T_J= –40ºC to +125ºC

1.375

1.650

1.925

V_SLOPE

Slope compensation amplitude

R_SLOPE= 20 kΩ, f_SW= 100 kHz, 50% duty

cycle, T_J= 25ºC

1.400

7.5

1.650

1.900

12

V

SOFT-START

I_SS-SOURCESS current source

V_SS= 0 V

10

13

µA

SS discharge switch R_DS-ON

PWM COMPARATOR

Ω

V_VCC= 5.5 V

330

560

150

300

1.10

400

750

ns

V

t_LO-OFF

Forced LO off-time

V_VCC= 4.5 V

R_SLOPE= 20 kΩ

R_SLOPE= 200 kΩ

T_J= –40ºC to +125ºC

T_J= 25ºC

t_ON-MIN

Minimum LO on-time

0.95

1.00

1.25

1.20

COMP to PWM voltage drop

V

CURRENT SENSE / CYCLE-BY-CYCLE CURRENT LIMIT

CSP to CSN, T_J= –40ºC to +125ºC

65.5

67.0

75.0

7

87.5

86.0

mV

V/V

µA

Cycle-by-cycle current limit

threshold

V_CS-TH1

CSP to CSN, T_J= 25ºC

CSP to CSN, rising

CSP to CSN, falling

V_CS-ZCDZero cross detection threshold

Current sense amplifier gain

0.5

6

12

10

12

11

1

I_CSP

I_CSN

CSP input bias current

CSN input bias current

Bias current matching

CS to LO delay

µA

I_CSP- I_CSN

–1.75

1.15

3.75

1.25

µA

Current sense / current limit delay

150

ns

HICCUP MODE RESTART

V_RES

Restart threshold

RES rising

1.20

4.2

V

V_HCP-

UPPER

Hiccup counter upper threshold

RES rising,

V_VIN= V_VCC= 4.5 V

3.6

2.15

1.85

V

RES falling

V_HCP-

LOWER

Hiccup counter lower threshold

RES current source1

RES falling,

V_VIN= V_VCC= 4.5 V

I_RES-

SOURCE1

Fault-state charging current

20

30

5

40

µA

I_RES-SINK1RES current sink1

Normal-state discharging current

I_RES-

SOURCE2

RES current source2

Hiccup mode off-time charging current

10

I_RES-SINK2RES current sink2

Hiccup cycle

Hiccup mode off-time discharging current

5

8

µA

Cycles

Ω

RES discharge switch R_DS-ON

40

Ratio of hiccup mode off-time to

restart delay time

122

HO GATE DRIVER

7

LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

www.ti.com.cn

Electrical Characteristics (continued)

Unless otherwise specified, these specifications apply for –40°C ≤ T_J≤ +125°C, V_VIN= 12 V, V_VCC= 8.3 V, R_T= 20 kΩ, no

load on LO and HO. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

HO high-state voltage drop

HO low-state voltage drop

HO rise time (10% to 90%)

HO fall time (90% to 10%)

TEST CONDITIONS

I_HO= –100 mA, V_OHH= V_BST–V_HO

I_HO= 100 mA, V_OLH= V_HO–V_SW

C_LOAD= 4700 pF, V_BST= 12 V

V_HO= 0 V, V_SW= 0 V, V_BST= 4.5 V

V_HO= 0 V, V_SW= 0 V, V_BST= 7.6 V

V_HO= V_BST= 4.5 V

MIN

TYP

0.15

0.1

25

MAX

0.24

0.18

UNIT

V

V_OHH

V_OLH

V

ns

A

20

0.8

1.9

3.2

I_OHH

Peak HO source current

Peak HO sink current

A

I_OLH

I_BST

V_HO= V_BST= 7.6 V

A

BST charge pump sourcing

current

V_VIN= V_SW= 9.0 V , V_BST- V_SW= 5.0 V

100

5.3

200

6.2

8.5

µA

V

B_STto SW, I_BST= –70 μA,

V_VIN= V_SW= 9.0 V

6.75

9

BST charge pump regulation

B_STto SW, I_BST= –70 μA,

V_VIN= V_SW= 12 V

7

V

BST to SW undervoltage

BST DC bias current

2.0

3.0

30

3.5

45

V

V_BST- V_SW= 12 V, V_SW= 0 V

µA

LO GATE DRIVER

V_OHL

V_OLL

LO high-state voltage drop

I_LO= –100 mA, V_OHL= V_VCC–V_LO

I_LO= 100 mA, V_OLL= V_LO

C_LOAD= 4700 pF

0.15

0.1

25

0.25

0.17

V

LO low-state voltage drop

LO rise time (10% to 90%)

LO fall time (90% to 10%)

ns

A

C_LOAD= 4700 pF

20

V_LO= 0 V, V_VCC= 4.5 V

V_LO= 0 V

0.8

2.0

1.8

3.2

I_OHL

Peak LO source current

Peak LO sink current

A

V_LO= V_VCC= 4.5 V

V_LO= V_VCC

A

I_OLL

A

SWITCHING CHARACTERISTICS

t_DLH

t_DHL

LO fall to HO rise delay

HO fall to LO rise delay

No load, 50% to 50%

50

60

80

115

105

ns

THERMAL

T_SD

Thermal shutdown

Temperature rising

165

25

ºC

Thermal shutdown hysteresis

8

LM25122-Q1

www.ti.com.cn

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

6.6 Typical Characteristics

5.00

6.00

5.00

4.00

3.00

2.00

1.00

0.00

4.00

3.00

SINK

2.00

1.00

0.00

SOURCE

4

5

6

7

8

9

10

11

12

13

14

4

5

6

7

8

9

10

11

12

13

14

C001

V_BST- V_SW[V]

V_VCC[V]

V_VIN= 12 V

V_SW= 0 V

V_VIN= 12 V

Figure 1. HO Peak Current vs V_BST- V_SW

Figure 2. LO Peak Current vs V_VCC

100.00

90.00

80.00

70.00

60.00

50.00

40.00

30.00

20.00

10.00

0.00

100

95

90

85

80

75

70

65

60

55

50

t_DHL

t_DLH

4

5

6

7

8

9

10

11

12

-50

-25

0

25

50

75

100

125

150

C001

V_VCC[V]

C001

Temperature [°C]

V_VIN= 12 V

V_SW= 12 V C_LOAD= 2600pF

1 V to 1 V

Figure 3. Dead Time vs V_VCC

Figure 4. Dead Time vs Temperature

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

20

15

10

5

t_DHL

t_DLH

0.0

0

10

20

30

40

50

60

-50

-25

0

25

50

75

100

125

150

C001

V_SW[V]

C001

Temperature [°C]

V_VIN= 12 V

V_VCC= 7.6 V C_LOAD= 2600pF

1 V to 1 V

Figure 5. Dead Time vs V_SW

Figure 6. I_SHUTDOWNvs Temperature

9

LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

www.ti.com.cn

Typical Characteristics (continued)

8

6

4

2

0

8

No load

6

4

2

0

No load

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14

0

10

20

30

40

50

60

70

80

C001

V_VIN[V]

I_VCC[mA]

Figure 8. V_VCCvs V_VIN

Figure 7. V_VCCvs I_VCC

15

10

5

40

30

20

10

0

180

A_CL=101, COMP unload

I_CSP

135

90

45

0

PHASE

I_CSN

GAIN

0

-10

-45

-50

-25

0

25

50

75

100

125

150

1000

10000

100000

1000000

10000000

C002

FREQUENCY [Hz]

C001

Temperature [°C]

Figure 9. Error Amp Gain and Phase

vs Frequency

Figure 10. I_CSP, I_CSNvs Temperature

15.0

300

280

260

240

220

200

180

160

140

120

100

I_BST= -70uA

V_VIN=V_SW=9V

10.0

5.0

0.0

4

9

14

19

-50

-25

0

25

50

75

100

125

150

C001

V_SW[V]

Temperature [°C]

Figure 11. V_BST-SWvs V_SW

Figure 12. I_BSTvs Temperature

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www.ti.com.cn

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

Typical Characteristics (continued)

80

90

85

80

75

70

65

60

V_VIN=V_CSP

75

70

4

5

6

7

8

9

10

11

12

-50

-25

0

25

50

75

100

125

150

C001

V_VIN[V]

Temperature [°C]

Figure 13. V_CS-TH1vs V_VIN

Figure 14. V_CS-TH1vs Temperature

12.00

11.00

10.00

9.00

8.00

7.00

6.00

5.00

4.00

3.00

2.00

1.00

V_SW= 12V

V_SW= 9V

V_VIN= V_SW

I_BST= -70uA

0.00

-50

-25

0

25

50

75

100

125

150

C001

Temperature [°C]

Figure 15. V_BST-SWvs Temperature

11

LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

www.ti.com.cn

7 Detailed Description

7.1 Overview

The LM25122 wide input range synchronous boost controller features all of the functions necessary to implement

a highly efficient synchronous boost regulator. The regulator control method is based upon peak current mode

control. Peak current mode control provides inherent line feed-forward and ease of loop compensation. This

highly integrated controller provides strong high-side and low-side N-channel MOSFET drivers with adaptive

dead-time control. The switching frequency is user programmable up to 600 kHz set by a single resistor or

synchronized to an external clock. The LM25122’s 180º shifted clock output enables easy multi-phase

configuration.

The control mode of high-side synchronous switch can be configured as either forced PWM (FPWM) or diode

emulation mode. Fault protection features include cycle-by-cycle current limiting, hiccup mode over load

protection, thermal shutdown and remote shutdown capability by pulling down the UVLO pin. The UVLO input

enables the controller when the input voltage reaches a user selected threshold, and provides a tiny 9 μA

shutdown quiescent current when pulled low. The device is available in 20-pin HTSSOP package featuring an

exposed pad to aid in thermal dissipation.

7.2 Functional Block Diagram

V

IN

R

S

L

IN

C

IN

CSP

CSN

VIN

10uA

LM25122

1.2V

R

UV2

STANDBY

-

+

VCC

A=10

VIN

UVLO

0.4V/0.3V

VCC

Regulator

CS

AMP

R

UV1

-

+

SHUTDOWN

C

VCC

SLOPE

BST Charge Pump

D

BST

R

SLOPE

Generator

6 ì 10⁹

V_SENSE1

V_SLOPE

=

BST

ì

R_SLOPE

f_SW

V

OUT

C

Q

H

HF

V_SENSE2

1.2 V

C

BST

-

+

COMP

FB

HO

SW

+

-

LEVEL SHIFT

DIODE EMULATION

750mV

+

-

C

R

ZCD threshold

COMP

C

OUT

-

ERR

AMP

C/L

Comparator

+

VCC

1.2V

Q

L

LO

ADAPTIVE

TIMER

PWM

Comparator

CLK

PWM

C

SS

S

R

Q

10uA

1.2V

SS

Skip Cycle

R

FB2

FB1

Comparator

30uA

10uA

700k

40mV

20mV

Hysteresis

-

RESTART

TIMER

+

-

MODE

+

R

CLK

1.2V

+

-

Diode

Emulation

Clock Generator

/SYNC Detector

100k

f_CLK/ 2

or

f_CLK

RES

5uA

C

RES

Diode

Emulation

Comparator

SYNCIN/RT

AGND PGND

SYNCOUT

OPT

R

T

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LM25122-Q1

www.ti.com.cn

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

7.3 Feature Description

7.3.1 Undervoltage Lockout (UVLO)

The LM25122 features a dual level UVLO circuit. When the UVLO pin voltage is less than the 0.4-V UVLO

standby enable threshold, the LM25122 is in the shutdown mode with all functions disabled. The shutdown

comparator provides 0.1 V of hysteresis to avoid chatter during transition. If the UVLO pin voltage is greater than

0.4 V and below 1.2 V during power up, the controller is in standby mode with the VCC regulator operational and

no switching at the HO and LO outputs. This feature allows the UVLO pin to be used as a remote shutdown

function by pulling the UVLO pin down below the UVLO standby enable threshold with an external open collector

or open drain device.

V

IN

UVLO Hysteresis

Current

UVLO

Threshold

R

UV2

UVLO

-

+

STANDBY

UVLO Standby

Enable Threshold

R

UV1

-

SHUTDOWN

STANDBY

+

Figure 16. UVLO Remote Standby and Shutdown Control

If the UVLO pin voltage is above the 1.2-V UVLO threshold and VCC voltage exceeds the VCC UV threshold, a

startup sequence begins. UVLO hysteresis is accomplished with an internal 10-μA current source that is

switched on or off into the impedance of the UVLO setpoint divider. When the UVLO pin voltage exceeds 1.2 V,

the current source is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls

below the 1.2-V UVLO threshold, the current source is disabled causing the voltage at the UVLO pin to quickly

fall. In addition to the UVLO hysteresis current source, a 5-μs deglitch filter on both rising and falling edge of

UVLO toggling helps preventing chatter upon power up or down.

An external UVLO setpoint voltage divider from the supply voltage to AGND is used to set the minimum input

operating voltage of the regulator. The divider must be designed such that the voltage at the UVLO pin is greater

than 1.2 V when the input voltage is in the desired operating range. The maximum voltage rating of the UVLO

pin is 15 V. If necessary, the UVLO pin can be clamped with an external zener diode. The UVLO pin should not

be left floating. The values of R_UV1and R_UV2can be determined from Equation 1 and Equation 2.

V_HYS

R_UV2

=

W

» ÿ

⁄

10ꢀA

1.2V ìR_UV2

-1.2V

(1)

R_UV1

=

W

» ÿ

⁄

V

IN(STARTUP)

(2)

where

•

V_HYSis the desired UVLO hysteresis

V_IN(STARTUP)is the desired startup voltage of the regulator during turn-on.

Typical shutdown voltage during turn-off can be calculated as follows:

= V_IN(STARTUP)- V_HYS[V]

V

IN(SHUTDOWN)

(3)

7.3.2 High Voltage VCC Regulator

The LM25122 contains an internal high voltage regulator that provides typical 7.6 V VCC bias supply for the

controller and N-channel MOSFET drivers. The input of VCC regulator, VIN, can be connected to an input

voltage source as high as 42 V. The VCC regulator turns on when the UVLO pin voltage is greater than 0.4 V.

When the input voltage is below the VCC setpoint level, the VCC output tracks VIN with a small dropout voltage.

The output of the VCC regulator is current limited at 50 mA minimum.

13

LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

www.ti.com.cn

Feature Description (continued)

Upon power-up, the VCC regulator sources current into the capacitor connected to the VCC pin. The

recommended capacitance range for the VCC capacitor is 1.0 μF to 47 μF and is recommended to be at least 10

times greater than C_BSTvalue. When operating with a VIN voltage less than 6 V, the value of VCC capacitor

should be 4.7 µF or greater.

The internal power dissipation of the LM25122 device can be reduced by supplying VCC from an external supply.

If an external VCC bias supply exists and the voltage is greater than 9 V and below 14.5 V. The external VCC

bias supply can be applied to the VCC pin directly through a diode, as shown in Figure 17.

External VCC Supply

VCC

C

LM25122

VCC

Figure 17. External Bias Supply when 9 V<V_EXT<14.5 V

Shown in Figure 18 is a method to derive the VCC bias voltage with an additional winding on the boost inductor.

This circuit must be designed to raise the VCC voltage above VCC regulation voltage to shut off the internal VCC

regulator.

VCC

+

nìV_IN

+

nìV_OUT

+

nì(V_OUT-V_IN

)

1 : n

V

IN

V

OUT

+

Figure 18. External Bias Supply using Transformer

The VCC regulator series pass transistor includes a diode between VCC and VIN that should not be fully forward

biased in normal operation, as shown in Figure 19. If the voltage of the external VCC bias supply is greater than

the VIN pin voltage, an external blocking diode is required from the input power supply to the VIN pin to prevent

the external bias supply from passing current to the input supply through VCC. The need for the blocking diode

should be evaluated for all applications when the VCC is supplied by the external bias supply. Especially, when

the input power supply voltage is less than 4.5 V, the external VCC supply should be provided and the external

blocking diode is required.

V

IN

VIN

LM25122

External VCC Supply

VCC

Figure 19. VIN Configuration when V_VIN< V_VCC

14

LM25122-Q1

www.ti.com.cn

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

Feature Description (continued)

7.3.3 Oscillator

The LM25122 switching frequency is programmable by a single external resistor connected between the RT pin

and the AGND pin. The resistor should be located very close to the device and connected directly to the RT pin

and AGND pin. To set a desired switching frequency (f_SW), the resistor value can be calculated from Equation 4.

9ì10⁹

f_SW

R_T=

W

» ÿ

⁄

(4)

7.3.4 Slope Compensation

For duty cycles greater than 50%, peak current mode regulators are subject to sub-harmonic oscillation. Sub-

harmonic oscillation is normally characterized by observing alternating wide and narrow duty cycles. This sub-

harmonic oscillation can be eliminated by a technique, which adds an artificial ramp, known as slope

compensation, to the sensed inductor current.

Additional slope

Sensed Inductor Current

I

ì

10

=

ì

R

S

LIN

t

ON

Figure 20. Slope Compensation

The amount of slope compensation is programmable by a single resistor connected between the SLOPE pin and

the AGND pin. The amount of slope compensation can be calculated as follows:

6x10⁹

V_SLOPE

=

xD [V]

f_SWx R_SLOPE

where

V

IN

D = 1-

V_OUT

•

(5)

(6)

R_SLOPEvalue can be determined from the following equation at minimum input voltage:

L_INì 6ì10⁹

R_SLOPE

=

W

» ÿ

⁄

»

ÿ

ìR_Sì10

K ì V_OUT- V

IN(MIN)

⁄

where

•

K=0.82~1 as a default

From the previous equation, K can be calculated over the input range as follows:

L_INì 6ì10⁹

V ìR_Sì10ìR_SLOPE

≈

’

K = 1+

ìD^'

∆

÷

◊

∆

«

IN

where

V

'

IN

D =

V_OUT

•

(7)

In any case, K should be greater than at least 0.5. At higher switching frequency over 500 kHz, K factor is

recommended to be greater than or equal to 1 because the minimum on-time affects the amount of slope

compensation due to internal delays.

15

LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

www.ti.com.cn

Feature Description (continued)

The sum of sensed inductor current and slope compensation should be less than COMP output high voltage

(V_OH) for proper startup with load and proper current limit operation. This limits the minimum value of R_SLOPEto

be:

5.7ì10⁹

V

≈

’

÷

◊

IN MIN

(

)

∆

R_SLOPE

>

ì 1.2 -

W

» ÿ

⁄

∆

÷

f_SW

V_OUT

«

•

This equation can be used in most cases

8ì10⁹

f_SW

R_SLOPE

>

W

» ÿ

⁄

•

This conservative selection should be considered when V_IN(MIN)< 5.5 V

The SLOPE pin cannot be left floating.

7.3.5 Error Amplifier

The internal high-gain error amplifier generates an error signal proportional to the difference between the FB pin

voltage and the internal precision 1.2-V reference. The output of the error amplifier is connected to the COMP pin

allowing the user to provide a Type 2 loop compensation network.

R_COMP, C_COMPand C_HFconfigure the error amplifier gain and phase characteristics to achieve a stable voltage

loop. This network creates a pole at DC, a mid-band zero (f_{Z_EA}) for phase boost, and a high frequency pole

(f_{P_EA}). The minimum recommended value of R_COMPis 2 kΩ. See the Feedback Compensation section.

1

f_{Z_EA}

=

Hz

» ÿ

⁄

2pìR_COMPìC_COMP

(9)

1

f_{P_EA}

=

Hz

» ÿ

⁄

≈

∆

«

’

÷

◊

C_COMPìC_HF

C_COMP+ C_HF

2pìR_COMP

ì

(10)

7.3.6 PWM Comparator

The PWM comparator compares the sum of sensed inductor current and slope compensation ramp to the

voltage at the COMP pin through a 1.2-V internal COMP to PWM voltage drop, and terminates the present cycle

when the sum of sensed inductor current and slope compensation ramp is greater than V_COMP–1.2 V.

I

LIN

R

S

CSP

CSN

A=10

CS

AMP

R

SLOPE

Generator

V

OUT

REF

R

FB2

+

-

+

-

FB

-

PWM

Comparator

Error

Amplifier

1.2 V

R

C

COMP

R

FB1

C

(optional)

HF

Type 2 Compensation Components

Figure 21. Feedback Configuration and PWM Comparator

16

LM25122-Q1

www.ti.com.cn

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

Feature Description (continued)

7.3.7 Soft-Start

The soft-start feature helps the regulator to gradually reach the steady state operating point, thus reducing

startup stresses and surges. The LM25122 regulates the FB pin to the SS pin voltage or the internal 1.2-V

reference, whichever is lower. The internal 10-μA soft-start current source gradually increases the voltage on an

external soft-start capacitor connected to the SS pin. This results in a gradual rise of the output voltage starting

from the input voltage level to the target output voltage. Soft-start time (t_SS) varies by the input supply voltage, is

calculated from Equation 11.

≈

’

÷

◊

C_SSì1.2V

10ꢀA

V

IN

t_SS

=

ì 1-

sec

» ÿ

∆

⁄

V_OUT

«

(11)

When the UVLO pin voltage is greater than the 1.2-V UVLO threshold and VCC voltage exceeds the VCC UV

threshold, an internal 10-μA soft-start current source turns on. At the beginning of this soft-start sequence, V_SS

should be allowed to fall down below 25 mV by the internal SS pulldown switch. The SS pin can be pulled down

by external switch to stop switching, but pulling up to enable switching is not allowed. The startup delay (see

Figure 22) should be long enough for high-side boot capacitor to be fully charged up by internal BST charge

pump.

The value of C_SSshould be large enough to charge the output capacitor during soft-start time.

10ꢀA ì V_OUTC_OUT

C_SS

>

ì

F

» ÿ

⁄

1.2V

I_OUT

(12)

Standby

Shut down

0.4V

1.2V

UVLO

VCC

VCC UV threshold

Startup delay

10µA

1.2V

current

source

SS

LO

HO-SW

V

IN

t

SS

VOUT

Figure 22. Startup Sequence

17

LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

www.ti.com.cn

Feature Description (continued)

7.3.8 HO and LO Drivers

The LM25122 contains strong N-channel MOSFET gate drivers and an associated high-side level shifter to drive

the external N-channel MOSFET switches. The high-side gate driver works in conjunction with an external boot

diode D_BST, and bootstrap capacitor C_BST. During the on-time of the low-side N-channel MOSFET driver, the SW

pin voltage is approximately 0 V and the C_BSTis charged from VCC through the D_BST. A 0.1-μF or larger ceramic

capacitor, connected with short traces between the BST and SW pin, is recommended.

The LO and HO outputs are controlled with an adaptive dead-time methodology which insures that both outputs

are never enabled at the same time. When the controller commands LO to be enabled, the adaptive dead-time

logic first disables HO and waits for HO-SW voltage to drop. LO is then enabled after a small delay (HO Fall to

LO Rise Delay). Similarly, the HO turn-on is delayed until the LO voltage has discharged. HO is then enabled

after a small delay (LO Fall to HO Rise Delay). This technique insures adequate dead-time for any size N-

channel MOSFET device, especially when VCC is supplied by a higher external voltage source. Be careful when

adding series gate resistors, as this may decrease the effective dead-time.

Care should be exercised in selecting the N-channel MOSFET devices threshold voltage, especially if the VIN

voltage range is below the VCC regulation level or a bypass operation is required. If the bypass operation is

required, especially when output voltage is less than 12 V, a logic level device should be selected for the high-

side N-channel MOSFET. During startup at low input voltages, the low-side N-channel MOSFET switch’s gate

plateau voltage should be sufficient to completely enhance the N-channel MOSFET device. If the low-side N-

channel MOSFET drive voltage is lower than the low-side N-channel MOSFET device gate plateau voltage

during startup, the regulator may not start up properly and it may stick at the maximum duty cycle in a high

power dissipation state. This condition can be avoided by selecting a lower threshold N-channel MOSFET switch

or by increasing V_IN(STARTUP)with the UVLO pin voltage programming.

7.3.9 Bypass Operation (V_OUT= V_IN)

The LM25122 allows 100% duty cycle operation for the high-side synchronous switch when the input supply

voltage is equal to or greater than the target output voltage. An internal 200 μA BST charge pump maintains

sufficient high-side driver supply voltage to keep the high-side N-channel MOSFET switch on without the power

stage switching. The internal BST charge pump is enabled when the UVLO pin voltage is greater than 1.2 V and

the VCC voltage exceeds the VCC UV threshold. The BST charge pump generates 5.3-V minimum BST to SW

voltage when SW voltage is greater than 9 V. This requires minimum 9 V boost output voltage for proper bypass

operation. The leakage current of the boot diode should be always less than the BST charge pump sourcing

current to maintain a sufficient driver supply voltage at both low and high temperatures. Forced PWM mode is

the recommended PWM configuration when bypass operation is required.

7.3.10 Cycle-by-Cycle Current Limit

The LM25122 features a peak cycle-by-cycle current limit function. If the CSP to CSN voltage exceeds the 75-

mV cycle-by-cycle current limit threshold, the current limit comparator immediately terminates the LO output.

For the case where the inductor current may overshoot, such as inductor saturation, the current limit comparator

skips pulses until the current has decayed below the current limit threshold. Peak inductor current in current limit

can be calculated as follows:

75mV

I_PEAK(CL)

=

A

» ÿ

⁄

R_S

(13)

7.3.11 Clock Synchronization

The SYNCIN/RT pin can be used to synchronize the internal oscillator to an external clock. A positive going

synchronization clock at the RT pin must exceed the RT sync rising threshold and negative going

synchronization clock at RT pin must exceed the RT sync falling threshold to trip the internal synchronization

pulse detector.

18

LM25122-Q1

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

Feature Description (continued)

In Master1 mode, two types of configurations are allowed for clock synchronization. With the configuration in

Figure 23, the frequency of the external synchronization pulse is recommended to be within +40% and –20% of

the internal oscillator frequency programmed by the RT resistor. For example, 900-kHz external synchronization

clock and 20-kΩ RT resistor are required for 450-kHz switching in master1 mode. The internal oscillator can be

synchronized by AC coupling a positive edge into the RT pin. A 5-V amplitude pulse signal coupled through 100-

pF capacitor is a good starting point. The RT resistor is always required with AC coupling capacitor with the

Figure 23 configuration, whether the oscillator is free running or externally synchronized.

Care should be taken to guarantee that the RT pin voltage does not go below –0.3 V at the falling edge of the

external pulse. This may limit the duty cycle of external synchronization pulse. There is approximately 400-ns

delay from the rising edge of the external pulse to the rising edge of LO.

f_SYNC

SYNCIN/RT

C

SYNC

R

T

LM25122

Figure 23. Oscillator Synchronization Through AC Coupling in Master1 Mode

With the configuration in Figure 24, the internal oscillator can be synchronized by connecting the external

synchronization clock into the RT pin through RT resistor with free of the duty cycle limit. The output stage of the

external clock source should be a low impedance totem-pole structure. Default logic state of f_SYNCshould be low.

f_SYNC

SYNCIN/RT

R

T

LM25122

Figure 24. Oscillator Synchronization Through a Resistor in Master1 Mode

In master2 and slave modes, this external synchronization clock should be directly connected to the RT pin and

always provided continuously. The internal oscillator frequency can be either of two times faster than switching

frequency or the same as the switching frequency by configuring the combination of FB and OPT pins (see

Table 1).

7.3.12 Maximum Duty Cycle

When operating with a high PWM duty cycle, the low-side N-channel MOSFET device is forced off each cycle.

This forced LO off-time limits the maximum duty cycle of the controller. When designing a boost regulator with

high switching frequency and high duty cycle requirements, a check should be made of the required maximum

duty cycle. The minimum input supply voltage which can achieve the target output voltage is estimated from

Equation 14.

V

= f_SWì V_OUTì(750ns + margin) [V]

IN(MIN)

(14)

In normal operation, about 100 ns of margin is recommended.

7.3.13 Thermal Protection

Internal thermal shutdown circuitry is provided to protect the controller in the event the maximum junction

temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low-power shutdown

mode, disabling the output drivers, disconnection switch and the VCC regulator. This feature is designed to

prevent overheating and destroying the device.

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7.4 Device Functional Modes

7.4.1 MODE Control (Forced PWM Mode and Diode Emulation Mode)

A fully synchronous boost regulator implemented with a high-side switch rather than a diode has the capability to

sink current from the output in certain conditions such as light load, overvoltage or load transient. The LM25122

can be configured to operate in either forced PWM mode or diode emulation mode.

In forced PWM mode (FPWM), reverse current flow in high-side N-channel MOSFET switch is allowed and the

inductor current conducts continuously at light or no load conditions. The benefit of the forced PWM mode is fast

light load to heavy load transient response and constant frequency operation at light or no load conditions. To

enable forced PWM mode, connect the MODE pin to VCC or tie to a voltage greater than 1.2 V. In FPWM mode,

reverse current flow is not limited.

In diode emulation mode, current flow in the high-side switch is only permitted in one direction (source to drain).

Turn-on of the high-side switch is allowed if CSP to CSN voltage is greater than 7 mV rising threshold of zero

current detection during low-side switch on-time. If CSP to CSN voltage is less than 6 mV falling threshold of

zero current detection during high-side switch on-time, reverse current flow from output to input through the high-

side N-channel MOSFET switch is prevented and discontinuous conduction mode of operation is enabled by

latching off the high-side N-channel MOSFET switch for the remainder of the PWM cycle. A benefit of the diode

emulation is lower power loss at light load conditions.

1.2 V

COMP

+

-

40mV

Hysteresis

SkipCycle

1.2V

-

+

700k

20mV

Default

150mV

Skip Cycle

Comparator

+

-

MODE

1.2V

Diode

Emulation

100k

+

-

Figure 25. MODE Selection

During startup the LM25122 forces diode emulation, for startup into a pre-biased load, while the SS pin voltage is

less than 1.2 V. Forced diode emulation is terminated by a pulse from PWM comparator when SS is greater than

1.2 V. If there are no LO pulses during the soft-start period, a 350-ns one-shot LO pulse is forced at the end of

soft-start to help charge the boot strap capacitor. Due to the internal current sense delay, configuring the

LM25122 for diode emulation mode should be carefully evaluated if the inductor current ripple ratio is high and

when operating at very high switching frequency. The transient performance during full load to no load in FPWM

mode should also be verified.

7.4.2 MODE Control (Skip Cycle Mode and Pulse Skipping Mode)

Light load efficiency of the regulator typically drops as the losses associated with switching and bias currents of

the converter become a significant percentage of the total power delivered to the load. In order to increase the

light load efficiency the LM25122 provides two types of light load operation in diode emulation mode.

The skip cycle mode integrated into the LM25122 controller reduces switching losses and improves efficiency at

light load condition by reducing the average switching frequency. Skip cycle operation is achieved by the skip

cycle comparator. When a light load condition occurs, the COMP pin voltage naturally decreases, reducing the

peak current delivered by the regulator. During COMP voltage falling, the skip cycle threshold is defined as

V_MODE–20 mV and during COMP voltage rising, it is defined as V_MODE+20 mV. There is 40mV of internal

hysteresis in the skip cycle comparator.

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LM25122-Q1

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

Device Functional Modes (continued)

When the voltage at PWM comparator input falls below V_MODE–20 mV, both HO and LO outputs are disabled.

The controller continues to skip switching cycles until the voltage at PWM comparator input increases to V_MODE

+20 mV, demanding more inductor current. The number of cycles skipped depends upon the load and the

response time of the frequency compensation network. The internal hysteresis of skip cycle comparator helps to

produce a long skip cycle interval followed by a short burst of pulses. An internal 700 kΩ pullup and 100 kΩ

pulldown resistor sets the MODE pin to 0.15 V as a default. Since the peak current limit threshold is set to 750

mV, the default skip threshold corresponds to approximately 17% of the peak level. In practice the skip level will

be lower due to the added slope compensation. By adding an external pullup resistor to SLOPE or VCC pin or

adding an external pulldown resistor to the ground, the skip cycle threshold can be programmed. Because the

skip cycle comparator monitors the PWM comparator input which is proportional to the COMP voltage, skip cycle

operation is not recommended when the bypass operation is required.

Conventional pulse skipping operation can be achieved by connecting the MODE pin to ground. The negative 20-

mV offset at the positive input of skip cycle comparator ensures the skip cycle comparator will not trigger in

normal operation. At light or no load conditions, the LM25122 skips LO pulses if the pulse width required by the

regulator is less than the minimum LO on-time of the device. Pulse skipping appears as a random behavior as

the error amplifier struggles to find an average pulse width for LO in order to maintain regulation at light or no

load conditions.

7.4.3 Hiccup Mode Over-Load Protection

If cycle-by-cycle current limit is reached during any cycle, a 30-μA current is sourced into the RES capacitor for

the remainder of the clock cycle. If the RES capacitor voltage exceeds the 1.2-V restart threshold, a hiccup mode

over load protection sequence is initiated; The SS capacitor is discharged to GND, both LO and HO outputs are

disabled, the voltage on the RES capacitor is ramped up and down between 2-V hiccup counter lower threshold

and 4-V hiccup counter upper threshold eight times by 10-μA charge and 5-μA discharge currents. After the

eighth cycles, the SS capacitor is released and charged by the 10-μA soft-start current again. If a 3-V zener

diode is connected in parallel with the RES capacitor, the regulator enters into the hiccup mode off mode and

then never restarts until UVLO shutdown is cycled. Connect RES pin directly to the AGND when the hiccup

mode operation is not used.

I_RES= 10µA

I_RES= -5µA

4V

2.0V

1.2V

Count to Eight

I_RES= 30µA

RES

Restart Delay t_RD

Hiccup Mode Off-time t_RES

SS

HO

LO

Figure 26. Hiccup Mode Over-Load Protection

7.4.4 Slave Mode and SYNCOUT

The LM25122 is designed to easily implement dual (or higher) phase boost converters by configuring one

controller as a master and all others as slaves. Slave mode is activated by connecting the FB pin to the VCC pin.

The FB pin is sampled during initial power-on and if a slave configuration is detected, the state is latched. In the

slave mode, the error amplifier is disabled and has a high impedance output, 10 μA hiccup mode off-time

charging current and 5-μA hiccup mode off-time discharging current are disabled, 5-μA normal-state RES

discharging current and 10-μA soft-start charging current are disabled, 30 μA fault-state RES charging current is

changed to 35 μA. 10-μA UVLO hysteresis current source works the same as master mode. Also, in slave mode,

the internal oscillator is disabled, and an external synchronization clock is required.

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Device Functional Modes (continued)

The SYNCOUT function provides a 180º phase shifted clock output, enabling easy dual-phase interleaved

configuration. By directly connecting master1 SYNCOUT to slave1 SYNCIN, the switching frequency of slave

controller is synchronized to the master controller with 180º phase shift. In master mode, if OPT pin is tied to

GND, an internal oscillator clock divided by two with 50% duty cycle is provided to achieve an 180º phase-shifted

operation in two phase interleaved configuration. Switching frequency of master controller is half of the external

clock frequency with this configuration. If the OPT pin voltage is higher than 2.7-V OPT threshold or the pin is

tied to VCC, SYNCOUT is disabled and the switching frequency of master controller becomes the same as the

external clock frequency. An external synchronization clock should be always provided and directly connected to

SYNCIN for master2, slave1 and slave2 configurations. See Interleaved Boost Configuration section for detailed

information.

Table 1. LM25122 Multiphase Configuration

MULTIPHASE

CONFIGURATION

ERROR

AMPLIFIER

FB

OPT

SWITCHING FREQUENCY

SYNCOUT

Master1

Slave1

Master2

Slave2

Feedback

VCC

GND

VCC

Enable

Disable

Enable

Disable

f_SYNC/2, Free running with RT resistor

f_SYNC,No free running

f_SYNC/2, f_SW–180º

Disable

Feedback

VCC

f_SYNC,No free running

Disable

f_SYNC/2, No free running

f_SYNC/2, f_SW–180º

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM25122 device is a step-up dc-dc converter. The device is typically used to convert a lower dc voltage to a

higher dc voltage. Use the following design procedure to select component values for the LM25122 device.

Alternately, use the WEBENCH^®software to generate a complete design. The WEBENCH software uses an

iterative design procedure and accesses a comprehensive database of components when generating a design.

This section presents a simplified discussion of the design process.

8.1.1 Feedback Compensation

The open loop response of a boost regulator is defined as the product of modulator transfer function and

feedback transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator

gain and feedback gain. The modulator transfer function of a current mode boost regulator including a power

stage transfer function with an embedded current loop can be simplified as one pole, one zero and one Right

Half Plane (RHP) zero system.

Modulator transfer function is defined as follows:

≈

’ ≈

’

s

1+

ì 1-

∆

«

÷ ∆

◊ «

÷

◊

Ù

&

V_OUT(s)

Z _ESR

Z _RHP

= A_Mì

Ù

≈

’

V_COMP(s)

s

1+

∆

«

÷

◊

&

P _LF

where

D^'

2

R_LOAD

A_M(ModulatorDCgain) =

ì

R_{S_EQ}ì A_S

•

2

&_{P _LF}(Load pole) =

R_LOADìC_OUT

1

&

_{Z _ESR}(ESR zero) =

R_ESRìC_OUT

' 2

R_LOADì(D )

&

_{Z _RHP}(RHP zero) =

L_{IN_EQ}

•

L

R

S

IN

L

=

, R

=

S_EQ

IN_EQ

•

n

n is the number of the phase.

(15)

If the ESR of C_OUT(R_ESR) is small enough and the RHP zero frequency is far away from the target crossover

frequency, the modulator transfer function can be further simplified to one pole system and the voltage loop can

be closed with only two loop compensation components, R_COMPand C_COMP, leaving a single pole response at the

crossover frequency. A single pole response at the crossover frequency yields a very stable loop with 90 degrees

of phase margin.

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LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

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Application Information (continued)

The feedback transfer function includes the feedback resistor divider and loop compensation of the error

amplifier. R_COMP, C_COMPand optional C_HFconfigure the error amplifier gain and phase characteristics, create a

pole at origin, a low frequency zero and a high frequency pole.

Feedback transfer function is defined as follows:

s

1+

Ù

&

V_COMP

Z _EA

-

= A_FBì

Ù

≈

∆

«

’

V_OUT

s

sì 1+

∆

÷

◊

&

P_EA

where

1

A_FB(Feedback DC gain) =

R_FB2ì C

+ C_HF

(

)

COMP

•

1

&

_{Z _EA}(Low frequency zero) =

R_COMPì C_COMP

1

&_{P _EA}(High frequency pole) =

R_COMPìC_HF

(16)

The pole at the origin minimizes the output steady state error. The low frequency zero should be placed to cancel

the load pole of the modulator. The high frequency pole can be used to cancel the zero created by the output

capacitor ESR or to decrease noise susceptibility of the error amplifier. By placing the low frequency zero an

order of magnitude less than the crossover frequency, the maximum amount of phase boost can be achieved at

the crossover frequency. The high frequency pole should be placed beyond the crossover frequency since the

addition of C_HFadds a pole in the feedback transfer function.

The crossover frequency (open loop bandwidth) is usually selected between one twentieth and one fifth of the

f_SW. In a simplified formula, the estimated crossover frequency can be defined as:

R_COMP

f_CROSS

=

ìD' [Hz]

pìR_{S_EQ}ìR_FB2ì A_SìC_OUT

where

V

'

IN

D =

V_OUT

•

(17)

For higher crossover frequency, R_COMPcan be increased, while proportionally decreasing C_COMP. Conversely,

decreasing R_COMPwhile proportionally increasing C_COMP, results in lower bandwidth while keeping the same zero

frequency in the feedback transfer function.

The modulator transfer function can be measured by a network analyzer and the feedback transfer function can

be configured for the desired open loop transfer function. If the network analyzer is not available, step load

transient tests can be performed to verify acceptable performance. The step load goal is minimum

overshoot/undershoot with a damped response.

8.1.2 Sub-Harmonic Oscillation

Peak current mode regulator can exhibit unstable behavior when operating above 50% duty cycle. This behavior

is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the SW pin.

Sub-harmonic oscillation can be prevented by adding an additional slope voltage ramp (slope compensation) on

top of the sensed inductor current. By choosing K ≥ 0.82~1.0, the sub-harmonic oscillation will be eliminated

even with wide varying input voltage.

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LM25122-Q1

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

Application Information (continued)

In time-domain analysis, the steady-state inductor current starting from an initial point returns to the same point.

When the amplitude of an end cycle current error (dI₁) caused by an initial perturbation (dI₀) is less than the

amplitude of dI₀or dI₁/dI₀> –1, the perturbation naturally disappears after a few cycles. When dl₁/dl₀< –1, the

initial perturbation no longer disappear, it results in sub-harmonic oscillation in steady-state.

Steady-State

Inductor Current

dI₀

t_ON

dI₁

Inductor Current with

Initial Perturbation

Figure 27. Effect of Initial Perturbation when dl₁/dl₀< -1

dI₁/dI₀can be calculated as:

dI₁

1

= 1-

dI₀

K

(18)

The relationship between dI₁/dI₀and K factor is illustrated graphically in the following.

Figure 28. dl₁/dl₀vs K Factor

The absolute minimum value of K is 0.5. When K < 0.5, the amplitude of dl₁is greater than the amplitude of dl₀

and any initial perturbation results in sub-harmonic oscillation. If K=1, any initial perturbation will be removed in

one switching cycle. This is known as one-cycle damping. When –1 < dl₁/dl₀< 0, any initial perturbation will be

under-damped. Any perturbation will be over-damped when 0 < dl₁/dl₀< 1.

In the frequency-domain, Q, the quality factor of sampling gain term in modulator transfer function, is used to

predict the tendency for sub-harmonic oscillation, which is defined as:

1

Q =

p K - 0.5

(

)

(19)

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LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

www.ti.com.cn

Application Information (continued)

The relationship between Q and K factor is illustrated in Figure 29.

Figure 29. Sampling Gain Q vs K Factor

The recommended absolute minimum value of K is 0.5. High gain peaking when K is less than 0.5 results sub-

harmonic oscillation at f_SW/2. A higher value of K factor may introduce additional phase shift near the crossover

frequency, but has the benefit of reducing noise susceptibility in current loop. The maximum allowable value of K

factor can be calculated by the maximum crossover frequency equation in frequency analysis formulas in

Table 2.

Table 2. Boost Regulator Frequency Analysis

SIMPLIFIED FORMULA

COMPREHENSIVE FORMULA⁽¹⁾

≈

’

≈

∆

«

’

≈

’

≈

’

s

1+

ì 1-

∆

«

÷

◊

∆

÷

◊

∆

«

÷

◊

∆

÷

◊

1+

ì 1-

∆

«

Ù

w_{Z _ESR}

w_{Z _RHP}

&

V_OUT

s

V_OUT(s)

MODULATOR TRANSER

FUNCTION

(

)

Z_ESR

Z_RHP

= A_M

ì

= A_M

ì

Ù

≈

’

≈

’

≈

’

≈

’

V_COMP

s

V_COMP(s)

(

s

s²

s

1+

ì 1+

+

∆

«

÷

◊

∆

÷

◊

∆

÷

◊

1+

∆

«

÷

◊

2

∆

«

∆

«

&

P_HF

w_{P _LF}

&

n

P_LF

p _ESR

R_LOAD

R_{S _EQ}ì A_S

D'

(2)

A_M

=

ì

Modulator DC gain

2

R_LOADì(D')²

(2)

RHP zero

&

=

Z _RHP

L_{IN_EQ}

1

&

=

&

=

ESR zero

Z _ESR

R_ESRìC_OUT

R_ESR1ìC_OUT1

1

&

=

ESR pole

Not considered

P _ESR

R_ESR1ì C_OUT1/ /C_OUT2

(

)

2

&

=

Dominant load pole

P _LF

R_LOADìC_OUT

f_SW

&

=

P _HF

K - 0.5

Sampled gain inductor pole

Not considered

or

&

= Qì&_n

P _HF

(1) Comprehensive equation includes an inductor pole and a gain peaking at f_SW/2, which is caused by sampling effect of the current mode

control. Also, it assumes that a ceramic capacitor C_OUT2(No ESR) is connected in parallel with C_OUT1. R_ESR1represents ESR of C_OUT1

.

V_OUT

I_OUTof each phase ìn

, and C_OUT= C_OUTof each phase x n, where n =

L_IN

n

R_S

n

R_LOAD

=

L_{IN_EQ}

=

R_{S _EQ}=

(2) With multiphase configuration,

number of phases.

,

26

LM25122-Q1

www.ti.com.cn

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

Application Information (continued)

Table 2. Boost Regulator Frequency Analysis (continued)

SIMPLIFIED FORMULA

COMPREHENSIVE FORMULA⁽¹⁾

1

Q =

Quality factor

Not considered

p K - 0.5

(

)

&

SW

&

=

= pì f_SW

n

2

Sub-harmonic double pole

Not considered

or

f_SW

2

f_n

=

L_INì 6ì10⁹

_INìR_Sì10ìR_SLOPE

≈

’

÷ìD^'

K factor

K = 1

K = ∆1+

∆

÷

V

«

◊

s

1+

Ù

&

V_COMP(s)

Z _EA

FEEDBACK TRANSFER

FUNCTION

-

= A_FBì

Ù

≈

∆

«

’

V_OUT(s)

s

sì 1+

∆

÷

◊

&

P _EA

1

A_FB

=

Feedback DC gain

Mid-band Gain

R_FB2ì(C_COMP+ C_HF

)

R_COMP

A_{FB _MID}

=

R_FB2

1

&

=

Low frequency zero

High frequency pole

Z _EA

R_COMPìC_COMP

1

&

=

&

=

P _EA

R_COMPì C

/ /C_COMP

R_COMPìC_HF

(

)

CHF

≈

’

≈

∆

«

’

≈

’

≈

’

s

1+

ì 1-

∆

«

÷

◊

∆

÷

◊

1+

∆1+

÷ì∆1-

÷

◊

1+

∆

÷ ∆

&

Z _RHP

&

Z _EA

Z_ESR

Z_RHP

Z _ESR

Z_EA

«

◊ «

T

s

( )

= A_Mì A_FB

ì

T s = A_Mì A_FB

ì

OPEN LOOP RESPONSE

(

)

s

s²

≈

’

≈

’

≈

’

≈

’

≈

’

≈

’

s

sì 1+

1+

ì

1+

ì ∆1+

+

÷

◊

∆

÷

◊

∆

«

÷

◊

∆

«

÷

◊

1+

sì 1+

∆

«

÷

◊

∆

÷

◊

2

∆

«

∆

«

&

∆

«

&

P_HF

&

P _EA

P _LF

p _ESR

n

P_LF

P_EA

(3)

R_COMP

Crossover frequency

f_CROSS

=

ìD^'

Use graphic tool

(Open loop band width)

pìR_{S_EQ}ìR_FB2ì A_SìC_OUT

f_SW

1+ 4ìQ²-1

≈

∆

«

’

◊

f_{CROSS_MAX}

=

ì

÷

4ìQ

&

f_SW

Maximum cross over

frequency⁽⁴⁾

or

&

Z_RHP

f_{CROSS_MAX}

=

or

whichever is smaller

5

2ì pì 4

Z _RHP

2ì pì 4

, whichever is smaller

R_LOADìC_OUT

4ìR_COMP

V

IN

&

Z_RHP

C_COMP

=

D' =

f_CROSS

<

&

= &_{P _LF}

&

= &_{Z _ESR}

V_OUT

Z _EA

P _EA

2ì pì10

(3) Assuming

,

, and

.

(4) The frequency at which 45º phase shift occurs in modulator phase characteristics.

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LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

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8.1.3 Interleaved Boost Configuration

Interleaved operation offers many advantages in single output, high current applications such as higher

efficiency, lower component stresses and reduced input and output ripple. For dual phase interleaved operation,

the output power path is split reducing the input current in each phase by one-half. Ripple currents in the input

and output capacitors are reduced significantly since each channel operates 180 degrees out of phase from the

other. Shown in Figure 30 is a normalized (I_RMS/I_OUT) output capacitor ripple current vs duty cycle for both a

single phase and dual phase boost converter, where I_RMSis the output current ripple RMS.

Figure 30. Normalized Output Capacitor RMS Ripple Current

To configure for dual phase interleaved operation, one device should be configured as a master and the other

device should be configured in slave mode by connecting FB to VCC. Also COMP, UVLO, RES, SS and

SYNCOUT on the master side should be connected to COMP, UVLO, RES, SS and SYNCIN on slave side

respectively. The compensation network is connected between master FB and the common COMP connection.

The output capacitors of the two power stages are connected together at the common output.

V

SUPPLY

V

OUT

+

CSN VCC BST

SW

LO

CSP

VIN

HO

UVLO

SLOPE

RES

SS

OPT

SYNCIN/RT

FB

SYNCOUT

COMP

V

MASTER

SUPPLY

CSN VCC BST

CSP

SW

LO

VIN

HO

COMP

SLOPE

SYNCIN/RT

SS

OPT

FB

VCC

RES

UVLO

SLAVE

Figure 31. Dual Phase Interleaved Boost Configuration

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

Shown in Figure 32 is a dual phase timing diagram. The 180° phase shift is realized by connecting SYNCOUT on

the master side to the SYNCIN on the slave side.

f_SYNC

Free running when no

SYNCIN(MASTER)

external synchronization.

GND

C

SYNC

Master

Internal

Optional f_SYNC

(5V_PP

SYNCIN/RT

SYNCOUT

CLK(MASTER)

)

OPT=GND

R

T

SW(MASTER)

Duty cycle of f_SYNC

Should be controlled

for RT not to go below GND

Slave

SYNCOUT(MASTER)

SYNCIN(SLAVE)

(50%Duty-cycle)

SYNCIN/RT

OPT=GND

Internal

CLK(SLAVE)

SW(SLAVE)

Figure 32. Dual Phase Configuration and Timing Diagram

Each channel is synchronized by an individual external clock in Figure 33. The SYNCOUT pin is used in

Figure 34 requiring only one external clock source. A 50% duty cycle of external synchronization pulse should be

always provided with this daisy chain configuration.

Current sharing between phases is achieved by sharing one error amplifier output of the master controller with

the 3 slave controllers. Resistor sensing is a preferred method of current sensing to accurately balance the

phase currents.

f_SYNCshould be always provided

(5V_PP

)

Master

SYNCIN/RT

f_SYNC1

OPT=VCC

f_SYNC1

SYNCIN_MASTER

Slave1

SYNCIN/RT

f_SYNC2

SYNCIN_SLAVE1

f_SYNC2

OPT=GND

f_SYNC3

SYNCIN_SLAVE2

Slave2

SYNCIN/RT

f_SYNC3

OPT=GND

f_SYNC4

SYNCIN_SLAVE3

Slave3

SYNCIN/RT

f_SYNC4

OPT=GND

Figure 33. 4-Phase Timing Diagram Individual Clock

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LM25122-Q1

ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

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Master

f_SYNCshould be always provided

SYNCIN

SYNCOUT

(5VPP)

R

T

OPT=GND

f_SYNC

D

QZ

Q

f_SYNC

Slave1

SYNCIN_MASTER

SYNCIN

OPT=GND

SYNCIN_SLAVE1

Slave2

SYNCIN

SYNCOUT

R

T

SYNCIN_SLAVE2

SYNCIN_SLAVE3

OPT=VCC

Slave3

SYNCIN

OPT=GND

Figure 34. 4-Phase Timing Diagram Daisy Chain

8.1.4 DCR Sensing

For the applications requiring lowest cost with minimum conduction loss, Inductor DC resistance (DCR) is used

to sense the inductor current rather than using a sense resistor. Shown in Figure 35 is a DCR sensing

configuration using two DCR sensing resistors and one capacitor.

V

OUT

L

IN

R

DCR

V

IN

+

R

CSN

C

DCR

SW

HO LO

CSN

CSP

LM25122

Figure 35. DCR Sensing

R_CSNand C_DCRselection should meet Equation 20 since this indirect current sensing method requires a time

constant matching. C_DCRis usually selected to be in the range of 0.1 µF to 2.2 µF.

L_IN

= C_DCRì R_CSN

R_DCR

(20)

Smaller value of R_CSNminimizes the voltage drop caused by CSN bias current, but increases the dynamic power

dissipation of R_CSN. The DC voltage drop of R_CSNcan be compensated by selecting the same value of R_CSP, but

the gain of current amplifier, which is typically 10, is affected by adding R_CSP. The gain of current amplifier with

the DCR sensing network can be determined as:

A_{CS_DCR}= 12.5 kW / (1.25 kW +R_CSP

)

(21)

Due to the reduced accuracy of DCR sensing, FPWM mode operation is recommended when DCR sensing is

used.

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

8.1.5 Output Overvoltage Protection

Output overvoltage protection can be achieved by adding a simple external circuit. The output overvoltage

protection circuit shown in Figure 36 shuts down the LM25122 when the output voltage exceeds the overvoltage

threshold set by the zener diode.

V

OUT

LM25122

UVLO

Figure 36. Output Overvoltage Protection

8.1.6 SEPIC Converter Simplified Schematic

V

OUT

SUPPLY

+

LO

HO

FB

LM25122

CSN

CSP

COMP

VIN

RES

SS

SYNCOUT

OPT

PGND

AGND

UVLO

SLOPE

SYNCIN/RT

MODE VCC BST SW

Figure 37. Sepic Converter Simplified Schematic

8.1.7 Non-Isolated Synchronous Flyback Converter Simplified Schematic

9V ~ 36V

V

OUT

V

SUPPLY

12V

744851101

COUPLED

INDUCTOR

+

LO

LM25122 ^HO

CSN

CSP

FB

COMP

VIN

RES

SYNCOUT

SS

OPT

PGND

AGND

UVLO

SLOPE

SYNCIN/RT

MODE VCC BST SW

Figure 38. Non-Isolated Synchronous Flyback Converter Simplified Schematic

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8.2 Typical Application

Figure 39. Single Phase Example Schematic

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

Typical Application (continued)

8.2.1 Design Requirements

DESIGN PARAMETERS

VALUE

24 V

Output Voltage (V_OUT

)

Full Load Current (I_OUT

)

4.5 A

108 W

9 V

Output Power

Minimum Input Voltage (V_IN(MIN)

Typical Input Voltage (V_IN(TYP)

Maximum Input Voltage (V_IN(MAX)

)

12 V

)

20 V

Switching Frequency (f_SW

)

250 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Timing Resistor R_T

Generally, higher frequency applications are smaller but have higher losses. Operation at 250 kHz is selected for

this example as a reasonable compromise between small size and high-efficiency. The value of R_Tfor 250 kHz

switching frequency is calculated as follows:

9ì10⁹

f_SW

9ì10⁹

250 kHz

R_T

=

= 36.0 kW

(22)

A standard value of 36.5 kΩ is chosen for R_T.

8.2.2.2 UVLO Divider R_UV2, R_UV1

The desired startup voltage and the hysteresis are set by the voltage divider R_UV2, R_UV1. The UVLO shutdown

voltage should be high enough to enhance the low-side N-channel MOSFET switch fully. For this design, the

startup voltage is set to 8.7 V which is 0.3 V below V_IN(MIN). V_HYSis set to 0.5 V. This results 8.2 V of

V_IN(SHUTDOWN). The values of R_UV2, R_UV1are calculated as follows:

V_HYS

0.5 V

R_UV2

=

= 50 kW

I_HYS

10 mA

(23)

(24)

1.2V ìR_UV2

-1.2V

1.2V ì50 kW

8.7V -1.2V

R_UV1

=

= 8 kW

V

IN(STARTUP)

A standard value of 49.9 kΩ is selected for R_UV2. R_UV1is selected to be a standard value of 8.06 kΩ.

8.2.2.3 Input Inductor L_IN

The inductor ripple current is typically set between 20% and 40% of the full load current, known as a good

compromise between core loss and copper loss of the inductor. Higher ripple current allows for a smaller inductor

size, but places more of a burden on the output capacitor to smooth the ripple voltage on the output. For this

example, a ripple ratio (RR) of 0.25, 25% of the input current was chosen. Knowing the switching frequency and

the typical output voltage, the inductor value can be calculated as follows:

≈

’

÷

◊

V

IN

1

12V

108W

1

12V

24V

≈

’

IN

L_IN

=

ì

ì 1-

=

ì

ì 1-

= 10.7 ꢀH

∆

÷

◊

I ìRR f_SW

V_OUT

250 kHz

«

IN

«

ì0.25

12V

(25)

The closest standard value of 10 μH was chosen for L_IN.

The saturation current rating of inductor should be greater than the peak inductor current, which is calculated at

the minimum input voltage and full load. 8.7 V startup voltage is used conservatively.

≈

’

÷

◊

V

IN

1

24Vì 4.5A

1

8.7V

≈

’

IN

I_PEAK= I

+

ì

ì 1-

=

+

ì

ì 1-

= 13.5 A

∆

IN

∆

÷

◊

2 L_INìf_SW

V_OUT

8.7V

2 10 ꢀHì250 kHz

24V

«

(26)

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

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8.2.2.4 Current Sense Resistor R_S

The maximum peak input current capability should be 20~50% higher than the required peak current at low input

voltage and full load, accounting for tolerances. For this example, 40% is margin is chosen.

V_CS-TH1

75 mV

R_S

=

= 3.97 mW

I_PEAK(CL)13.5 A ì1.4

(27)

(28)

A closest standard value of 4 mΩ is selected for R_S. The maximum power loss of R_Sis calculated as follows.

= I²R = (13.5 A ì1.4)²ì 4 mW = 1.43 W

P

LOSS(RS)

8.2.2.5 Current Sense Filter R_CSFP, R_CSFN, C_CS

The current sense filter is optional. 100 pF of C_CSand 100 Ω of R_CSFP, R_CSFNare normal recommendations.

Because CSP and CSN pins are high impedance, C_CSshould be placed physically as close to the device.

V

IN

R

S

+

CSN

CSP

C

LM25122

CS

Figure 40. Current Sense Filter

8.2.2.6 Slope Compensation Resistor R_SLOPE

The K value is selected to be 1 at the minimum input voltage. R_SLOPEshould be carefully selected so that the

sum of sensed inductor current and slope compensation is less than COMP output high voltage.

8ì10⁹

f_SW

8ì10⁹

250 kHz

R_SLOPE

>

=

= 32 kW

(29)

(30)

L_INì6ì10⁹

10 ꢀHì6ì10⁹

R_SLOPE

=

= 100 kW

1ì24V -9V ì4mWì10

»

ÿ

(

)

Kì V_OUT- V

ìR_Sì10

IN(MIN)

⁄

A closest standard value of 100 kΩ is selected for R_SLOPE

.

8.2.2.7 Output Capacitor C_OUT

The output capacitors smooth the output voltage ripple and provide a source of charge during transient loading

conditions. Also the output capacitors reduce the output voltage overshoot when the load is disconnected

suddenly.

Ripple current rating of output capacitor should be carefully selected. In boost regulator, the output is supplied by

discontinuous current and the ripple current requirement is usually high. In practice, the ripple current

requirement can be dramatically reduced by placing high quality ceramic capacitors earlier than the bulk

aluminum capacitors as close to the power switches.

The output voltage ripple is dominated by ESR of the output capacitors. Paralleling output capacitor is a good

choice to minimize effective ESR and split the output ripple current into capacitors.

In this example, three 330 µF aluminum capacitors are used to share the output ripple current and source the

required charge. The maximum output ripple current can be simply calculated at the minimum input voltage as

follows:

I_OUT

4.5A

9V

I_{RIPPLE_MAX(COUT)}

=

= 6A

V

IN(MIN)

2ì

24V

V_OUT

(31)

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

Assuming 60 mΩ of ESR per an output capacitor, the output voltage ripple at the minimum input voltage is

calculated as follows:

≈

’

÷

◊

I_OUT

≈

∆

«

’

÷

◊

1

4.5A

9V

60mW

1

V_{RIPPLE_MAX(COUT)}

=

ì R

+

=

ì

+

= 0.252V

∆

ESR

V

4ìC_OUTì f_SW

3

4ì3ì330 ꢀFì250 kHz

IN(MIN)

«

24V

V_OUT

(32)

In practice, four 10 µF ceramic capacitors are additionally placed earlier than the bulk aluminum capacitors to

reduce the output voltage ripple and split the output ripple current.

Due to the inherent path from input to output, unlimited inrush current can flow when the input voltage rises

quickly and charges the output capacitor. The slew rate of input voltage rising should be controlled by a hot-swap

or by starting the input power supply softly for the inrush current not to damage the inductor, sense resistor or

high-side N-channel MOSFET switch.

8.2.2.8 Input Capacitor C_IN

The input capacitors smooth the input voltage ripple. Assuming high quality ceramic capacitors are used for the

input capacitors, the maximum input voltage ripple which happens when the input voltage is half of the output

voltage can be calculated as follows:

V_OUT

24V

V_{RIPPLE_MAX(CIN)}

=

= 0.09V

32ì10 ꢀHì 4ì3.3 ꢀFì 250 kHz²

32ìL_INìC_INì f_SW₂

(33)

The value of input capacitor is also a function of source impedance, the impedance of source power supply. The

more input capacitor will be required to prevent a chatter condition upon power up if the impedance of source

power supply is not enough low.

8.2.2.9 VIN Filter R_VIN, C_VIN

An R-C filter (R_VIN, C_VIN) on VIN pin is optional. It is not required if C_INcapacitors are high quality ceramic

capacitors and placed physically close to the device. The filter helps to prevent faults caused by high frequency

switching noise injection into the VIN pin. A 0.47 μF ceramic capacitor is used this example. 3 Ω of R_VINand 0.47

µF of C_VINare normal recommendations. A larger filter with 2.2 µ~4.7 µF C_VINis recommended when the input

voltage is lower than 8 V or the required duty cycle is close to the maximum duty cycle limit.

V

IN

VIN

R

VIN

LM25122

C

VIN

Figure 41. VIN Filter

8.2.2.10 Bootstrap Capacitor C_BSTand Boost Diode D_BST

The bootstrap capacitor between the BST and SW pin supplies the gate current to charge the high-side N-

channel MOSFET device gate during each cycle’s turn-on and also supplies recovery charge for the bootstrap

diode. These current peaks can be several amperes. The recommended value of the bootstrap capacitor is 0.1

μF. C_BSTshould be a good quality, low ESR, ceramic capacitor located at the pins of the device to minimize

potentially damaging voltage transients caused by trace inductance. The minimum value for the bootstrap

capacitor is calculated as follows:

Q_G

C_BST

=

F

» ÿ

⁄

ûV_BST

(34)

Where Q_Gis the high-side N-channel MOSFET gate charge and ΔV_BSTis the tolerable voltage droop on C_BST

,

which is typically less than 5% of VCC or 0.15 V, conservatively. In this example, the value of the BST capacitor

(C_BST) is 0.1 µF.

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

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The voltage rating of D_BSTshould be greater than the peak SW node voltage plus 16 V. A low leakage diode is

mandatory for the bypass operation. The leakage current of D_BSTshould be low enough for the BST charge

pump to maintain a sufficient high-side driver supply voltage at high temperature. A low leakage diode also

prevents the possibility of excessive VCC voltage during shutdown, in high output voltage applications. If the

leakage is excessive, a zener VCC clamp or bleed resistor may be required. High-side driver supply voltage

should be greater than the high-side N-channel MOSFET switch’s gate plateau at the minimum input voltage.

8.2.2.11 VCC Capacitor C_VCC

The primary purpose of the VCC capacitor is to supply the peak transient currents of the LO driver and bootstrap

diode as well as provide stability for the VCC regulator. These peak currents can be several amperes. The value

of C_VCCshould be at least 10 times greater than the value of C_BST, and should be a good quality, low ESR,

ceramic capacitor. C_VCCshould be placed close to the pins of the IC to minimize potentially damaging voltage

transients caused by trace inductance. A value of 4.7 µF was selected for this design example.

8.2.2.12 Output Voltage Divider R_FB1, R_FB2

R_FB1and R_FB2set the output voltage level. The ratio of these resistors is calculated as follows:

R_FB2

R_FB1

V_OUT

1.2V

=

-1

(35)

The ratio between R_COMPand R_FB2determines the mid-band gain, A_{FB_MID}. A larger value for R_FB2may require a

corresponding larger value for R_COMP. R_FB2should be large enough to keep the total divider power dissipation

small. 49.9 kΩ in series with 825 Ω was chosen for high-side feedback resistors in this example, which results in

a R_FB1value of 2.67 kΩ for 24 V output.

8.2.2.13 Soft-Start Capacitor C_SS

The soft-start time (t_SS) is the time for the output voltage to reach the target voltage from the input voltage. The

soft-start time is not only proportional with the soft-start capacitor, but also depends on the input voltage. With

0.1 µF of C_SS, the soft-start time is calculated as follows:

V

≈

∆

«

’

C_SSì1.2V

0.1ꢀFì1.2V

10 ꢀA

20V

24V

≈

’

IN(MAX)

t_SS(MIN)

=

ì 1-

=

ì 1-

= 2 msec

∆

÷

∆

÷

◊

I_SS

V_OUT

«

◊

(36)

(37)

V

≈

∆

«

’

C_SSì1.2V

0.1 ꢀFì1.2V

10 ꢀA

9V

≈

’

IN(MIN)

t_SS(MAX)

=

ì 1-

=

ì 1-

= 7.5 msec

∆

÷

∆

÷

◊

I_SS

V_OUT

24V

«

◊

8.2.2.14 Restart Capacitor C_RES

The restart capacitor determines restart delay time t_RDand hiccup mode off time t_RES(see Figure 26). t_RDshould

be greater than t_SS(MAX). The minimum required value of C_REScan be calculated at the low input voltage as

follows:

I_RESì t_SS(MAX)

30 ꢀA ì7.5 msec

C_RES(MIN)

=

= 0.19 mF

V_RES

1.2V

(38)

A standard value of 0.47 µF is selected for C_RES

.

8.2.2.15 Low-Side Power Switch Q_L

Selection of the power N-channel MOSFET devices by breaking down the losses is one way to compare the

relative efficiencies of different devices. Losses in the low-side N-channel MOSFET device can be separated into

conduction loss and switching loss.

Low-side conduction loss is approximately calculated as follows:

2

≈

’ ≈

’

÷

◊

V

I_OUTì V_OUT

IN

P_COND(LS)= DìI ìR_{DS_ON(LS)}ì1.3 = 1-

ì

ìR_{DS_ON(LS)}ì1.3[W]

IN²

∆

«

÷ ∆

V_OUT

V

IN

◊ «

(39)

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

Where, D is the duty cycle and the factor of 1.3 accounts for the increase in the N-channel MOSFET device on-

resistance due to heating. Alternatively, the factor of 1.3 can be eliminated and the high temperature on-

resistance of the N-channel MOSFET device can be estimated using the R_DS(ON)vs temperature curves in the N-

channel MOSFET datasheet.

Switching loss occurs during the brief transition period as the low-side N-channel MOSFET device turns on and

off. During the transition period both current and voltage are present in the channel of the N-channel MOSFET

device. The low-side switching loss is approximately calculated as follows:

P_SW(LS)= 0.5ì V_OUTìI ì(t_R+ t_F)ì f_SW[W]

IN

(40)

t_Rand t_Fare the rise and fall times of the low-side N-channel MOSFET device. The rise and fall times are usually

mentioned in the N-channel MOSFET datasheet or can be empirically observed with an oscilloscope.

An additional Schottky diode can be placed in parallel with the low-side N-channel MOSFET switch, with short

connections to the source and drain in order to minimize negative voltage spikes at the SW node.

8.2.2.16 High-Side Power Switch Q_Hand Additional Parallel Schottky Diode

Losses in the high-side N-channel MOSFET device can be separated into conduction loss, dead-time loss and

reverse recovery loss. Switching loss is calculated for the low-side N-channel MOSFET device only. Switching

loss in the high-side N-channel MOSFET device is negligible because the body diode of the high-side N-channel

MOSFET device turns on before and after the high-side N-channel MOSFET device switches.

High-side conduction loss is approximately calculated as follows:

2

≈

∆

«

’ ≈

’

÷

◊

V

I_OUTì V_OUT

IN

P_COND(HS)= (1-D)ìI ìR_{DS_ON(HS)}ì1.3 =

ì

ìR_{DS_ON(HS)}ì1.3[W]

IN²

÷ ∆

V_OUT

V

IN

◊ «

(41)

Dead-time loss is approximately calculated as follows:

= V x I x (t + t ) x f [W]

P

DT(HS)

D

IN

DLH

DHL

SW

where

•

V_Dis the forward voltage drop of the high-side NMOS body diode.

(42)

Reverse recovery characteristics of the high-side N-channel MOSFET switch strongly affect efficiency, especially

when the output voltage is high. Small reverse recovery charge helps to increase the efficiency while also

minimizes switching noise.

Reverse recovery loss is approximately calculated as follows:

P_RR(HS)= V_OUTìQ_RRì f_SW[W]

(43)

where

•

Q_RRis the reverse recovery charge of the high-side N-channel MOSFET body diode.

(44)

An additional Schottky diode can be placed in parallel with the high-side switch to improve efficiency. Usually, the

power rating of this parallel Schottky diode can be less than the high-side switch’s because the diode conducts

only during dead-times. The power rating of the parallel diode should be equivalent or higher than high-side

switch’s if bypass operation is required, hiccup mode operation is required or any load exists before switching.

8.2.2.17 Snubber Components

A resistor-capacitor snubber network across the high-side N-channel MOSFET device reduces ringing and

spikes at the switching node. Excessive ringing and spikes can cause erratic operation and can couple noise to

the output voltage. Selecting the values for the snubber is best accomplished through empirical methods. First,

make sure the lead lengths for the snubber connections are very short. Start with a resistor value between 5 and

50 Ω. Increasing the value of the snubber capacitor results more damping, but this also results higher snubber

losses. Select a minimum value for the snubber capacitor that provides adequate damping of the spikes on the

switch waveform at heavy load. A snubber may not be necessary with an optimized layout.

8.2.2.18 Loop Compensation Components C_COMP, R_COMP, C_HF

R_COMP, C_COMPand C_HFconfigure the error amplifier gain and phase characteristics to produce a stable voltage

loop. For a quick start, follow the following 4 steps:

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

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1. Select f_CROSS

Select the cross over frequency (f_CROSS) at one fourth of the RHP zero or one tenth of the switching

frequency whichever is lower.

f_SW

= 25 kHz

10

(45)

V_OUT

V

IN

2

ì(

)

R_LOADì(D')²

4ì 2pìL_{IN_EQ}

I_OUT

V_OUT

f_{Z _RHP}

=

= 5.3 kHz

4

4ì 2pìL_{IN_EQ}

(46)

5.3 kHz of the crossover frequency is selected between two. RHP zero at minimum input voltage should be

considered if the input voltage range is wide.

2. Determine required R_COMP

Knowing f_CROSS, R_COMPis calculated as follows:

V_OUT

R_COMP= f_CROSSì pìR_SìR_FB2ì10ìC_OUT

ì

= 68.5 kW

V

IN

(47)

A standard value of 68.1 kΩ is selected for R_COMP

3. Determine C_COMPto cancel load pole. Place error amplifier zero at the twice of load pole frequency. Knowing

R_COMP, C_COMPis calculated as follows:

R_LOADxC_OUT

C_COMP

=

= 20.2nF

4xR_COMP

(48)

(49)

A standard value of 22 nF is selected for C_COMP

4. Determine C_HFto cancel ESR zero.

Knowing R_COMP, R_ESRand C_COMP, C_HFis calculated as follows:

R_ESRìC_OUTì C_COMP

R_COMPì C_COMP- R_ESRì C_OUT

C_HF

=

= 307 pF

A standard value of 330 pF is selected for C_HF

.

8.2.3 Application Curves

C1: F_SYNC, C2:

SW

V_SUPPLY= 12 V,

F_SYNC= 500 kHz

C1:SW

V_SUPPLY= 12 V,

I_LOAD= 0A

Figure 42. Clock Synchronization

Figure 43. Forced PWM

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

C1:SW

V_SUPPLY= 12 V,

I_LOAD= 0A

C1:SW

V_SUPPLY= 12 V,

I_LOAD= 0A

Figure 44. Pulse Skip

Figure 45. Skip Cycle

C1:SW

V_SUPPLY= 12 V,

I_LOAD= 0A

C1: V_SUPPLY, C2: Inductor current, C3:

V_OUT, C4: SS

V_SUPPLY= 12 V,

I_LOAD= 0A

Figure 46. Loop Response

Figure 47. Start-Up

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

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9 Power Supply Recommendations

LM25122 is a power management device. The power supply for the device is any DC voltage source within the

specified input range.

10 Layout

10.1 Layout Guidelines

In a boost regulator, the primary switching loop consists of the output capacitor and N-channel MOSFET power

switches. Minimizing the area of this loop reduces the stray inductance and minimizes noise. Especially, placing

high quality ceramic output capacitors as close to this loop earlier than bulk aluminum output capacitors

minimizes output voltage ripple and ripple current of the aluminum capacitors.

In order to prevent a dv/dt induced turn-on of high-side switch, HO and SW should be connected to the gate and

source of the high-side synchronous N-channel MOSFET switch through short and low inductance paths. In

FPWM mode, the dv/dt induced turn-on can occur on the low-side switch. LO and PGND should be connected to

the gate and source of the low-side N-channel MOSFET, through short and low inductance paths. All of the

power ground connections should be connected to a single point. Also, all of the noise sensitive low power

ground connections should be connected together near the AGND pin and a single connection should be made

to the single point PGND. CSP and CSN are high impedance pins and noise sensitive. CSP and CSN traces

should be routed together with kelvin connections to the current sense resistor as short as possible. If needed,

place 100 pF ceramic filter capacitor as close to the device. MODE pin is also high impedance and noise

sensitive. If an external pullup or pulldown resistor is used at MODE pin, the resistor should be placed as close

the device. VCC, VIN and BST capacitor must be as physically close as possible to the device.

The LM25122 has an exposed thermal pad to aid power dissipation. Adding several vias under the exposed pad

helps conduct heat away from the device. The junction to ambient thermal resistance varies with application. The

most significant variables are the area of copper in the PC board, the number of vias under the exposed pad and

the amount of forced air cooling. The integrity of the solder connection from the device exposed pad to the PC

board is critical. Excessive voids greatly decrease the thermal dissipation capacity. The highest power dissipating

components are the two power switches. Selecting N-channel MOSFET switches with exposed pads aids the

power dissipation of these devices.

10.2 Layout Example

Inductor

Controller

Place controller as

close to the switches

Q_L

R

SENSE

Q_H

C

OUT

C

IN

OUT

VOUT

VIN

GND GND

Figure 48. Power Path Layout

40

LM25122-Q1

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ZHCSEL4A –DECEMBER 2015–REVISED DECEMBER 2015

11 器件和文档支持

11.1 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.2 商标

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

41

重要声明

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都遵循在订单确认时所提供的TI 销售条款与条件。

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应用

www.ti.com.cn/telecom

数字音频

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www.ti.com.cn/dataconverters

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DLP® 产品

DSP - 数字信号处理器

时钟和计时器

接口

www.ti.com.cn/computer

www.ti.com/consumer-apps

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www.ti.com.cn/dsp

工业应用

医疗电子

安防应用

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逻辑

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德州仪器在线技术支持社区

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IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE MATERIALS INFORMATION

www.ti.com

18-Feb-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM25122QPWPRQ1

LM25122QPWPTQ1

HTSSOP PWP

20

2500

250

330.0

178.0

16.4

6.95

7.1

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

18-Feb-2016

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM25122QPWPRQ1

LM25122QPWPTQ1

HTSSOP

PWP

20

2500

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

MECHANICAL DATA

PWP0020A

MXA20A (Rev C)

www.ti.com

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

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所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

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TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	LM25122QPWPTQ1
厂家：	TEXAS INSTRUMENTS
描述：	符合 AEC-Q100 标准的具有多相功能的 3V 至 42V 宽输入电压同步升压控制器 \| PWP \| 20 \| -40 to 125 控制器
文件：	总48页 (文件大小：2738K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM25122QPWPTQ1 [TI]

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