LM26400YMHX/NOPB [TI]
LM26400Y Dual 2-A, 500-kHz Wide Input Range Buck Regulator;
| 型号： | LM26400YMHX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LM26400Y Dual 2-A, 500-kHz Wide Input Range Buck Regulator |
| 文件： | 总33页 (文件大小：4735K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
LM26400Y Dual 2-A, 500-kHz Wide Input Range Buck Regulator
1 Features
3 Description
The LM26400Y device is a monolithic, two-output
fixed-frequency PWM step-down DC-DC regulator, in
a 16-pin WSON or thermally-enhanced HTSSOP
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Voltage Range of 3 V to 20 V
Dual 2-A Output
Output Voltage Down to 0.6 V
Internal Compensation
package. With
a minimum number of external
components and internal loop compensation, the
LM26400Y is easy to use.
500-kHz PWM Frequency
Separate Enable Pins
The ability to drive 2-A loads with an internal 175-mΩ
NMOS switch using state-of-the-art 0.5-µm BiCMOS
technology results in a high-power density design.
The world class control circuitry allows for an ON-
time as low as 40 ns, thus supporting high-frequency
conversion over the entire input range of 3 V to 20 V
and down to an output voltage of only 0.6 V. The
LM26400Y utilizes peak current-mode control and
internal compensation to provide high-performance
regulation over a wide range of line and load
conditions. Switching frequency is internally set to
500 kHz, optimal for a broad range of applications in
terms of size versus thermal tradeoffs.
Separate Soft-Start Pins
Frequency Foldback Protection
175-mΩ NMOS Switch
Integrated Bootstrap Diodes
Overcurrent Protection
HTSSOP and WSON Packages
Thermal Shutdown
2 Applications
•
•
•
•
•
•
•
DTV-LCD
Given a nonsynchronous architecture, efficiencies
above 90% are easy to achieve. External shutdown is
included, enabling separate turnon and turnoff of the
Set-Top Boxes
XDSL
two
channels.
Additional
features
include
Automotive
programmable soft-start circuitry to reduce inrush
current, pulse-by-pulse current limit and frequency
foldback, integrated bootstrap structure, and thermal
shutdown.
Computing Peripherals
Industrial Controls
Points-of-Load
Device Information(1)
PART NUMBER
PACKAGE
WSON (16)
HTSSOP (16)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
4.40 mm × 5.00 mm
LM26400Y
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Applications ............................................... 15
Power Supply Recommendations...................... 19
9.1 Low Input Voltage Considerations .......................... 19
9.2 Programming Output Voltage ................................. 19
9
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 24
10.3 Thermal Considerations........................................ 24
11 Device and Documentation Support ................. 26
11.1 Device Support...................................................... 26
11.2 Community Resources.......................................... 26
11.3 Trademarks........................................................... 26
11.4 Electrostatic Discharge Caution............................ 26
11.5 Glossary................................................................ 26
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 18
2
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: LM26400Y
LM26400Y
www.ti.com
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP With PowerPAD IC Package
Top View
NHQ Package
16-Pin WSON
Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Input supply for generating the internal bias used by the entire IC and for generating the
internal bootstrap bias. Needs to be locally bypassed.
AVIN
4
PWR
Supply rail for the gate drive of Channel 1's NMOS switch. A bootstrap capacitor should be
placed between the BST1 and SW1 pins.
BST1
BST2
EN1
EN2
FB1
16
O
Supply rail for the gate drive of Channel 2's NMOS switch. A bootstrap capacitor should be
placed between the BST2 and SW2 pins.
9
O
Enable control input for Channel 1. Logic high enables operation. Do not allow this pin to
float or be greater than VIN + 0.3 V.
3
I
Enable control input for Channel 2. Logic high enables operation. Do not allow this pin to
float or be greater than VIN + 0.3 V.
6
I
Feedback pin of Channel 1. Connect FB1 to an external voltage divider to set the output
voltage of Channel 1.
1
I
Feedback pin of Channel 2. Connect FB2 to an external voltage divider to set the output
voltage of Channel 2.
FB2
8
I
Signal and Power ground pin. Kelvin connect the lower resistor of the feedback voltage
divider to this pin for good load regulation.
GND
PVIN
SS1
5
PWR
Input voltage of the power supply. Directly connected to the drain of the internal NMOS
switch. Tie these pins together and connect to a local bypass capacitor.
11, 12, 13,14
PWR
Soft start pin of Channel 1. Connect a capacitor between this pin and ground to program the
start up speed.
2
7
I
I
Soft start pin of Channel 2. Connect a capacitor between this pin and ground to program the
start up speed.
SS2
SW2
SW1
10
15
O
O
Switch node of Channel 2. Connects to the inductor, catch diode, and bootstrap capacitor.
Switch node of Channel 1. Connects to the inductor, catch diode, and bootstrap capacitor.
Die Attach
Pad
Must be connected to system ground for low thermal impedance and low grounding
inductance.
DAP
—
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LM26400Y
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
(1)(2)
See
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
22
22
26
6
UNIT
V
AVIN, PVIN
SWx Voltage
V
BSTx Voltage
V
BSTx to SW Voltage
FBx Voltage
ENx Voltage(3)
V
3
V
22
3
V
SSx Voltage
V
Junction Temperature
Storage Temperature, Tstg
150
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) EN1 and EN2 pins should never be higher than VIN + 0.3 V.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. Test method is per JESD-22-A114.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
20
UNIT
V
VIN
Junction Temperature
–40
125
°C
6.4 Thermal Information
LM26400Y
THERMAL METRIC(1)
PWP (HTSSOP)
NHQ (WSON)
16 PINS
27.8
UNIT
16 PINS
39.4
24.5
18
RθJA
RθJC(top) Junction-to-case (top) thermal resistance
Junction-to-ambient thermal resistance(2)(3)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
27.2
RθJB
ψJT
Junction-to-board thermal resistance
9.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.7
0.3
ψJB
17.8
2.1
10.1
RθJC(bot) Junction-to-case (bottom) thermal resistance
2.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Value is highly board-dependent. For comparison of package thermal performance only. Not recommended for prediction of junction
temperature in real applications. See Thermal Considerations for more information.
(3) A standard board refers to a four-layer PCB with the size 4.5”x3”x0.063”. Top and bottom copper is 2 oz. Internal plane copper is 1 oz.
For details refer to JESD51-7 standard. Mount package on a standard board and test per JESD51-7 standard.
4
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: LM26400Y
LM26400Y
www.ti.com
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
6.5 Electrical Characteristics
Unless otherwise stated, the following conditions apply: AVIN = PVIN = VIN = 5 V. Limits are for TJ = 25°C. Minimum and
maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
0.591
0.585
TYP
MAX
0.611
0.617
UNIT
TJ = 25°C
0.6
Feedback Loop Closed
Feedback Loop V Closed
TJ = 0°C to 85°C
TJ = 25°C
VFB
Voltages at FB1 and FB2 Pins
V
0.6
TJ = –40°C to 125°C
Line Regulation of FB1 and FB2 Voltages,
ΔVFB_Line
Expressed as PPM Change Per Volt of VIN VIN = 3 V to 20 V
Variation
66
ppm/V
nA
Current in FB1 and FB2 Pins
VFB = 0.6 V
TJ = 25°C
0.4
IFB
TJ = –40°C to 125°C
TJ = 25°C
250
2.9
2.7
2.3
VIN Rising From 0 V
Undervoltage Lockout Threshold
TJ = –40°C to 125°C
TJ = 25°C
VUVLO
V
VIN Falling From 3.3 V
TJ = –40°C to 125°C
2
0.2
UVLO Hysteresis
TJ = 25°C
0.36
0.52
96%
VUVLO_HYS
V
TJ = –40°C to 125°C
TJ = 25°C
0.55
0.65
FSW
Switching Frequency
MHz
TJ = –40°C to 125°C
TJ = 25°C
0.39
90%
DMAX
DMIN
Maximum Duty Cycle
Minimum Duty Cycle
TJ = –40°C to 125°C
2%
TJ = 25°C
175
HTSSOP, 2-A Drain Current
WSON, 2-A Drain Current
TJ = –40°C to 125°C
TJ = 25°C
320
350
4.5
RDS(ON)
ON-Resistance of Internal Power MOSFET
mΩ
194
3
TJ = –40°C to 125°C
Peak Current Limit of Internal MOSFET
Shutdown Current of AVIN Pin
TJ = 25°C
ICL
ISD
IQ
A
TJ = –40°C to 125°C
EN1 = EN2 = 0 V
2.5
2.5
2
nA
Quiescent Current of AVIN Pin (both
channels are enabled but not switching)
EN1 = EN2 = 5 V, FB1 = FB2 = 0.7 V,
TJ = –40°C to 125°C
4
mA
VEN_IH
VEN_IL
IEN
Input Logic High of EN1 and EN2 Pins
Input Logic Low of EN1 and EN2 Pins
EN1 and EN2 Currents (sink or source)
TJ = –40°C to 125°C
TJ = –40°C to 125°C
V
V
0.4
5
1
nA
Switch Leakage Current Measured at SW1
and SW2 Pins
ISW_LEAK
EN1 = EN2 = SWx = 0
µA
Phase Shift Between SW1 and SW2 Rising
Edges
ΔΦ
Feedback Loop Closed. Continuous Conduction Mode.
170
11
180
16
19
deg
SSx Pin Current
TJ = 25°C
ISS
µA
TJ = –40°C to 125°C
21
3
ΔISS
Difference Between SS1 and SS2 Currents TJ = –40°C to 125°C
µA
V
FB1 and FB2 Frequency Foldback
Threshold
VFB_F
0.35
TSD
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Junction temperature rises.
165
15
°C
°C
TSD_HYS
Junction temperature falls from above TSD.
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LM26400Y
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
www.ti.com
6.6 Typical Characteristics
Unless otherwise specified or thermal-shutdown related, TA = 25°C for efficiency curves, loop gain plots and waveforms, and
TJ = 25°C for all others.
VOUT = 5 V
VOUT = 3.3 V
Figure 1. Efficiency
Figure 2. Efficiency
VOUT = 2.5 V
VOUT = 1.2 V
Figure 3. Efficiency
Figure 4. Efficiency
Figure 5. AVIN Shutdown Current vs Temperature
Figure 6. VIN Shutdown Current vs VIN
6
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: LM26400Y
LM26400Y
www.ti.com
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
Typical Characteristics (continued)
Unless otherwise specified or thermal-shutdown related, TA = 25°C for efficiency curves, loop gain plots and waveforms, and
TJ = 25°C for all others.
Figure 7. Switching Frequency vs Temperature
Figure 8. Feedback Voltage vs Temperature
Figure 9. Feedback Voltage vs VIN
Figure 10. Frequency Foldback
Figure 11. SS-Pin Current vs Temperature
Figure 12. FET RDS_ON vs Temperature
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LM26400Y
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
www.ti.com
Typical Characteristics (continued)
Unless otherwise specified or thermal-shutdown related, TA = 25°C for efficiency curves, loop gain plots and waveforms, and
TJ = 25°C for all others.
Figure 13. Switch Current Limit vs Temperature
Figure 14. Loop Gain, CCM
Figure 16. Loop Gain, CCM
Figure 15. Loop Gain, DCM
Figure 18. Line Transient Response
Figure 17. Loop Gain, DCM
8
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: LM26400Y
LM26400Y
www.ti.com
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
Typical Characteristics (continued)
Unless otherwise specified or thermal-shutdown related, TA = 25°C for efficiency curves, loop gain plots and waveforms, and
TJ = 25°C for all others.
Figure 19. Shutdown
Figure 20. Thermal Shutdown
Figure 21. Recovery from Thermal Shutdown
Figure 22. Short-Circuit Triggering
Figure 23. Short-Circuit Release
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LM26400Y
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
www.ti.com
7 Detailed Description
7.1 Overview
The LM26400Y device is a dual PWM peak-current mode buck regulator with two integrated power MOSFET
switches. The part is designed to be easy to use. The two regulators are mostly identical and share the same
input voltage and the same reference voltage (0.6 V). The two PWM clocks are of the same frequency but 180°
out of phase. The two channels can have different soft-start ramp slopes and can be turned on and off
independently.
Loop compensation is built in. The feedback loop design is optimized for ceramic output capacitors.
Since the power switches are built in, the achievable output current level also has to do with thermal environment
of the specific application. The LM26400Y enters thermal shutdown when the junction temperature exceeds
approximately 165°C.
7.2 Functional Block Diagram
SHARED CONTROL
9ꢁ1
9ꢁ2
!ëLꢁ
9ꢁ1_buf
ëref_[5h
ëref
uvlo
Ç{5
Üë[h
/omparator
Lnternal
wegulator
Lnternal
wegulator
weference
9ꢁ2_buf
/[Y1
/[Y2
ëbst
ëddi
Çꢄermal
{ꢄutdoꢅn
ꢂain
h{/
ëbst
ꢀëLꢁ
{witching ꢀegulator 1
+
L-sense
amp
-
Ç{5
.ootstrap
5iode
9ꢁ_buf
.{Ç
{í
/urrent
[imit
5river
[ogic
Lref
{lave
h{/
hë
/omparator
weset
ꢀulse
/[Y
110% ëref
ꢀíꢂ
/omparator
0ꢃ32ë
Lsense
Dm
!mplifier
Creqꢃ Coldback
/omparator
C.
{{
-
+
ëddi
+
ëref
Lnternal
/ompensation
+
+
/orrective wamp
Dꢁ5
7.3 Feature Description
7.3.1 Overcurrent Protection
The instantaneous switch current is limited to a typical of 3 Amperes. Any time the switch current reaches that
value, the switch will be turned off immediately. This will result in a smaller duty cycle than normal, which will
cause the output voltage to dip. The output voltage will continue drooping until the load draws a current that is
equal to the peak-limited inductor current. As the output voltage droops, the FB pin voltage will also droop
proportionally. When the FB voltage dips below 0.35 V or so, the PWM frequency will start to decrease. The
lower the FB voltage the lower the PWM frequency. See Figure 10.
10
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: LM26400Y
LM26400Y
www.ti.com
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
Feature Description (continued)
The frequency foldback helps two things. One is to prevent the switch current from running away as a result of
the finite minimum ON-time (40 ns or so for the LM26400Y) and the small duty cycle caused by lowered output
voltage due to the current limit. The other is it also helps reduce thermal stress both in the IC and the external
diode.
The current limit threshold of the LM26400Y remains constant over all duty cycles.
One thing to pay attention to is that recovery from an overcurrent condition does not go through a soft-start
process. This is because the reference voltage at the noninverting input of the error amplifier always sits at 0.6 V
during the overcurrent protection. So if the overcurrent condition is suddenly removed, the regulator will bring the
FB voltage back to 0.6 V as quickly as possible. This may cause an overshoot in the output voltage. Generally,
the larger the inductor or the lower the output capacitance the more the overshoot, and vice versa. If the amount
of such overshoot exceeds the allowed limit for a system, add a CFF capacitor in parallel with the upper feedback
resistor to eliminate the overshoot. See Load Step Response for more details on CFF.
When one channel gets into overcurrent protection mode, the operation of the other channel will not be affected.
7.3.2 Loop Stability
To the first order approximation, the LM26400Y has a VFB-to-Inductor Current transfer admittance (that is, ratio of
inductor current to FB pin voltage, in frequency domain) close to the plot in Figure 24. The transfer admittance
has a DC value of 104 dBS (dBS stands for decibel Siemens. The equivalent of 0 dBS is 1 Siemens.). There is a
pole at 1 Hz and a zero at approximately 8 kHz. The plateau after the 8 kHz zero is about 27 dBS. There are
also high frequency poles that are not shown in the figure. They include a double pole at 1.2 MHz or so, and
another double pole at half the switching frequency. Depending on factors such as inductor ripple size and duty
cycle, the double pole at half the switching frequency may become two separate poles near half the switching
frequency.
Figure 24. VFB-to-Inductor Current Transfer Admittance
An easy strategy to build a stable loop with reasonable phase margin is to try to cross over from 20 kHz to 100
kHz, assuming the output capacitor is ceramic. When using pure ceramic capacitors at the output, simply use the
following equation to find out the crossover frequency.
where
•
•
22S (22 Siemens) is the equivalent of the 27 dBS transfer admittance
r is the ratio of 0.6 V to the output voltage
(1)
Use the same equation to find out the needed output capacitance for a given crossover frequency. Phase margin
is typically between 50° and 60°. The above equation is only good for a crossover from 20 kHz to 100 kHz. A
crossover frequency outside this range may result in lower phase margin and less accurate prediction by the
above equation.
Example: VOUT = 2.5 V, COUT = 36 µF, find out the crossover frequency.
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LM26400Y
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
www.ti.com
Feature Description (continued)
Assume the crossover is from 20 kHz to 100 kHz. Then:
(2)
The above analysis serves as a starting point. It is a good practice to always verify loop gain on bench.
7.3.3 Load Step Response
In general, the excursion in output voltage caused by a load step can be reduced by increasing the output
capacitance. Besides that, increasing the small-signal loop bandwidth also helps. This can be achieved by
adding a 27 nF or so capacitor (CFF) in parallel with the upper feedback resistor (assuming the lower feedback
resistor is 5.9 kΩ). See Figure 25 for an illustration.
Figure 25. Adding a CFF Capacitor
The responses to a load step from 0.2 A to 2 A with and without a CFF are shown in Figure 26. The higher loop
bandwidth as a result of CFF reduces the total output excursion by about 80 mV.
Figure 26. CFF Improves Load Step Response
Use the following equation to calculate the new loop bandwidth:
(3)
Again, the assumption is the crossover is from 20 kHz to 100 kHz.
In an extreme case where the load goes to less than 100 mA during a large load step, output voltage may exhibit
extra undershoot. This usually happens when the load toggles high at the time VOUT just ramps down to its
regulation level from an overshoot. Figure 27 shows such a case where the load toggles between 1.7 A and only
50 mA.
12
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: LM26400Y
LM26400Y
www.ti.com
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
Feature Description (continued)
Figure 27. Extreme Load Step
In the example, the load first goes down to 50 mA quickly (0.9 A/µs), causing a 90-µs no-switching period, and
then quickly goes up to 1.7 A when VOUT1 just hits its regulation level (1.2 V), resulting in a large dip of 440 mV in
the output voltage.
If it is known in a system design that the load can go down to less than 100 mA during a load step, and that the
load can toggle high any time after it toggles low, take the following measures to minimize the potential extra
undershoot. First is to add the Cff mentioned above. Second is to increase the output capacitance.
For example, to meet a ±10% VOUT excursion requirement for a 100 mA to 2-A load step, approximately 200 µF
output capacitance is needed for a 1.2-V output, and about 44 µF is needed for a 5-V output.
7.4 Device Functional Modes
7.4.1 Start-Up and Shutdown
During a soft start, the ramp of the output voltage is proportional to the ramp of the SS pin. When the EN pin is
pulled high, an internal 16-µA current source starts to charge the corresponding SS pin. The capacitance
between the SS pin and ground determines how fast the SS voltage ramps up. The noninverting input of the
transconductance error amplifier, that is, the moving reference during soft start, will be the lower of SS voltage
and the 0.6-V reference (VREF). So before SS reaches 0.6V, the reference to the error amplifier will be the SS
voltage. When SS exceeds 0.6 V, the noninverting input of the transconductance amplifier will be a constant 0.6
V and that will be the time soft start ends. The SS voltage will continue to ramp all the way up to the internal 2.7-
V supply voltage before leveling off.
To calculate the needed SS capacitance for a given soft-start duration, use Equation 4.
where
•
•
•
ISS is SS pin charging current, typically 16 µA
VREF is the internal reference voltage, typically 0.6 V
tSS is the desired soft-start duration
(4)
For example, if 1 ms is the desired soft-start time, then the nominal SS capacitance should be 25 nF. Apply
tolerances if necessary. Use the VFB entry in Electrical Characteristics for the VREF tolerance.
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LM26400Y
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
www.ti.com
Device Functional Modes (continued)
Inductor current during soft start can be calculated by Equation 5.
where
•
•
•
VOUT is the target output voltage
IOUT is the load current during start-up
COUT is the output capacitance
(5)
For example, if the output capacitor is 10 µF, output voltage is 2.5 V, soft-start capacitor is 10 nF and there is no
load, then the average inductor current during soft start will be 62.5 mA.
When EN pin is pulled below 0.4 V or so, the 16-µA current source will stop charging the SS pin. The SS pin will
be discharged through a 330-Ω internal FET to ground. During this time, the internal power switch will remain
turned off while the output is discharged by the load.
If EN is again pulled high before SS and output voltage are completely discharged, soft-start will begin with a
non-zero reference and the level of the soft-start reference will be the lower of SS voltage and 0.6 V.
When the output is prebiased, the LM26400Y can usually start up successfully if there is at least a 2-V difference
between the input voltage and the prebias. An output prebias condition refers to the case when the output is
sitting at a non-zero voltage at the beginning of a start-up. The key to a successful start-up under such a
situation is enough initial voltage across the bootstrap capacitor. When an output prebias condition is anticipated,
the power supply designer should check the start-up behavior under the highest potential prebias.
A prebias condition caused by a glitch in the enable signal after start-up or by an input brownout condition
normally is not an issue because the bootstrap capacitor holds its charge much longer than the output
capacitors.
Due to the frequency foldback mechanism, the switching frequency during start-up will be lower than the normal
value before VFB reaches 0.35 V or so. See Figure 10.
It is generally okay to connect the EN pin to VIN to simplify the system design. However, if the VIN ramp is slow
and the load current is relatively high during soft start, the VOUT ramp may have a notch in it and a slight
overshoot at the end of startup. This is due to the reduced load current handling capability of the LM26400Y for
VIN lower than 5 V. If this kind of behavior is a problem for the system designer, there are two solutions. One is to
control the EN pin with a logic signal and do not pull the EN high until VIN is above 5 V or so. Make sure the logic
signal is never higher than VIN by 0.3 V. The other is to use an external 5-V bootstrap bias if it is ready before VIN
hits 2.7 V or so. See Low Input Voltage Considerations for more information.
14
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: LM26400Y
LM26400Y
www.ti.com
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM26400Y device will operate with input voltage from 3 V to 20 V and provide two regulated output voltages.
The device is optimized for high-efficiency operation with minimum number of external components.
8.2 Typical Applications
8.2.1 LM26400Y Design Example 1
8.2.1.1 Design Requirements
The device must be able to operate at any voltage within the recommended operating range. The load current
must be defined in order to properly size the inductor, input, and output capacitors .The inductor must be able to
handle full expected load current as well as the peak current generated load transients and start-up.
8.2.1.2 Detailed Design Procedure
The best capacitors for use with the LM26400Y are multi-layer ceramic capacitors. They have the lowest ESR
(equivalent series resistance) and highest resonance frequency which makes them optimum for use with high
frequency switching converters. When selecting a ceramic capacitor, only X5R and X7R dielectric types should
be used. Other types such as Z5U and Y5F have such severe loss of capacitance due to effects of temperature
variation and applied voltage, they may provide as little as 20% of rated capacitance in many typical applications.
Always consult capacitor manufacturer’s data curves before selecting a capacitor. High-quality ceramic
capacitors can be obtained from Taiyo-Yuden, AVX, and Murata.
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LM26400Y
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
www.ti.com
Typical Applications (continued)
Table 1. Bill of Materials (Circuit 1, VIN = 12 V±10%, Output1 = 1.2 V/2 A, Output2 = 2.5 V/2 A)
PART
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
L1
DESCRIPTION
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Diode, Schottky
Diode, Schottky
Inductor
PART VALUES
10 µF, 16 V, X5R
0.22 µF, 16 V, X5R
0.1 µF, 6.3 V, X5R
0.1 µF, 6.3 V, X5R
100 µF, 6.3 V, X5R
47 µF, 6.3 V, X5R
0.012 µF, 6.3 V, X5R
0.012 µF, 6.3 V, X5R
0.027 µF, 6.3 V, X5R
0.027 µF, 6.3 V, X5R
2 A, 30 V
PHYSICAL SIZE
1210
PART NUMBER
MANUFACTURER
Murata
GRM32DR61C106KA01
EMK107BJ224KA-T
C1005X5R0J104K
0603
Taiyo Yuden
TDK
0402
0402
C1005X5R0J104K
TDK
1210
GRM32ER60J107ME20L
GRM32ER60J476ME20L
C0402C123K9PACTU
C0402C123K9PACTU
C0402C273K9PACTU
C0402C273K9PACTU
MBRS230LT3G
Murata
1210
Murata
0402
Kemet
0402
Kemet
0402
Kemet
0402
Kemet
SMB
ON Semiconductor
ON Semiconductor
Sumida
2 A, 30 V
SMB
MBRS230LT3G
5 µH, 2.2 A
7 × 7 × 2.8 mm3
7 × 7 × 4 mm3
0402
CDRH6D26NP-5R0NC
CDRH6D38NP-8R7NC
CRCW040210R0FK
CRCW04025K90FK
CRCW04025K90FK
CRCW040218K7FK
CRCW04025K90FK
LM26400YMH
L2
Inductor
8.7 µH, 2.2 A
Sumida
R1
R2
R3
R4
R5
U1
Resistor
10 Ω, 1%
Vishay
Resistor
5.9 kΩ, 1%
0402
Vishay
Resistor
5.9 kΩ, 1%
0402
Vishay
Resistor
18.7 kΩ, 1%
0402
Vishay
Resistor
5.9 kΩ, 1%
0402
Vishay
Regulator
Dual 2-A Buck
HTSSOP-16
Texas Instruments
Table 2. Bill of Materials (Circuit 1, VIN = 7 V to 20 V, Output1 = 3.3 V/2 A, Output2 = 5 V/2 A)
PART
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
L1
DESCRIPTION
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Diode, Schottky
Diode, Schottky
Inductor
PART VALUES
10 µF, 25 V, X5R
0.22 µF, 25 V, X5R
0.1 µF, 6.3 V, X5R
0.1 µF, 6.3 V, X5R
47 µF, 6.3 V, X5R
33 µF, 6.3 V, X5R
0.012 µF, 6.3 V, X5R
0.012 µF, 6.3 V, X5R
0.027 µF, 6.3 V, X5R
0.027 µF, 6.3 V, X5R
2 A, 30 V
PHYSICAL SIZE
1812
PART NUMBER
MANUFACTURER
Murata
GRM43DR61E106KA12
TMK107BJ224KA-T
C1005X5R0J104K
0603
Taiyo Yuden
TDK
0402
0402
C1005X5R0J104K
TDK
1210
GRM32ER60J476ME20
GRM32DR60J336ME19
C0402C123K9PACTU
C0402C123K9PACTU
C0402C273K9PACTU
C0402C273K9PACTU
MBRS230LT3G
Murata
1210
Murata
0402
Kemet
0402
Kemet
0402
Kemet
0402
Kemet
SMB
ON Semiconductor
ON Semiconductor
Sumida
2 A, 30 V
SMB
MBRS230LT3G
10 µH, 3 A
8.3 × 8.3 × 4 mm3 CDRH8D38NP-100NC
8.3 × 8.3 × 4 mm3 CDRH8D43/HP-150NC
L2
Inductor
15 µH, 3 A
Sumida
R1
R2
R3
R4
R5
U1
Resistor
10 Ω, 1%
0402
CRCW040210R0FK
CRCW040226K7FK
CRCW04025K90FK
CRCW040218K7FK
CRCW04025K90FK
LM26400YMH
Vishay
Resistor
26.7 kΩ, 1%
0402
Vishay
Resistor
5.9 kΩ, 1%
0402
Vishay
Resistor
43.2 kΩ, 1%
0402
Vishay
Resistor
5.9 kΩ, 1%
0402
Vishay
Regulator
Dual 2-A Buck
HTSSOP-16
Texas Instruments
16
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: LM26400Y
LM26400Y
www.ti.com
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
8.2.1.3 Application Curves
Figure 28. Load Step Response
Figure 29. Load Step Response
Figure 30. Start-Up (No Load)
Figure 31. Start-Up (No Load)
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: LM26400Y
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
www.ti.com
8.2.2 LM26400Y Design Example 2
Table 3. Bill of Materials (Circuit 2, VIN = 3 V to 5 V, Output1 = 1.2 V/2 A, Output2 = 1.8 V/2 A)
PART
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
L1
DESCRIPTION
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Diode, Schottky
Diode, Schottky
Inductor
PART VALUES
PHYSICAL SIZE
1206
PART NUMBER
MANUFACTURER
Murata
10 µF, 6.3 V, X5R
0.22 µF, 6.3 V, X5R
0.1 µF, 6.3 V, X5R
0.1 µF, 6.3 V, X5R
100 µF, 6.3 V, X5R
100 µF, 6.3 V, X5R
GRM319R60J106KE19
JMK105BJ224KV-F
C1005X5R0J104K
0402
Taiyo Yuden
TDK
0402
0402
C1005X5R0J104K
TDK
1210
GRM32ER60J107ME20L
GRM32ER60J107ME20L
C0402C123K9PACTU
C0402C123K9PACTU
C0402C273K9PACTU
C0402C273K9PACTU
MBRS230LT3G
Murata
1210
Murata
0.012 µF, 6.3 V, X5R 0402
0.012 µF, 6.3 V, X5R 0402
0.027 µF, 6.3 V, X5R 0402
0.027 µF, 6.3 V, X5R 0402
Kemet
Kemet
Kemet
Kemet
2 A, 30 V
SMB
ON Semiconductor
ON Semiconductor
Sumida
2 A, 30 V
SMB
MBRS230LT3G
5 µH, 2.2 A
5 µH, 2.2 A
10 Ω, 1%
7 × 7 × 2.8 mm3
7 × 7 × 2.8 mm3
0402
CDRH6D26NP-5R0NC
CDRH6D26NP-5R0NC
CRCW040210R0FK
CRCW04025K90FK
CRCW04025K90FK
CRCW040211K8FK
CRCW04025K90FK
LM26400YMH
L2
Inductor
Sumida
R1
R2
R3
R4
R5
U1
Resistor
Vishay
Resistor
5.9 kΩ, 1%
5.9 kΩ, 1%
11.8 kΩ, 1%
5.90 kΩ, 1%
Dual 2-A Buck
0402
Vishay
Resistor
0402
Vishay
Resistor
0402
Vishay
Resistor
0402
Vishay
Regulator
HTSSOP-16
Texas Instruments
18
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: LM26400Y
LM26400Y
www.ti.com
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
9 Power Supply Recommendations
9.1 Low Input Voltage Considerations
When VIN is from 3 V to 5 V, TI recommends that an external bootstrap bias voltage and a Schottky diode be
used to handle load currents up to 2 A. See Figure 32 for an illustration.
Figure 32. External Bootstrap for Low VIN
The recommended voltage for the external bias is 5 V. Due to the absolute maximum rating of VBST - VSW, the
external 5-V bias should not be higher than 6 V.
9.2 Programming Output Voltage
First make sure the required maximum duty cycle in steady state is less than 80% so that the regulator will not
lose regulation. The datasheet lower limit for maximum duty cycle is about 90% over temperature (see Electrical
Characteristics for the accurate value). The maximum duty cycle in steady state happens at low line and full load.
The output voltage is programmed through the feedback resistors R1 and R2, as illustrated in Figure 33.
Figure 33. Programming Output Voltage
TI recommends that the lower feedback resistor R2 always be 5.9 kΩ. This simplifies the selection of the CFF
value (for an explanation of CFF, see Load Step Response). The 5.9 kΩ is also a suitable R2 value in
applications that need to increase the output voltage on the fly by paralleling another resistor with R2. Because
the FB pin is 0.6 V during normal operation, the current through the feedback resistors is normally 0.6 V / 5.9 kΩ
= 0.1 mA and the power dissipation in R2 is 0.6 V × 0.6 V / 5.9 kΩ = 61 µW - low enough for 0402 size or
smaller resistors.
Use Equation 6 to determine the upper feedback resistor R1.
(6)
To determine the maximum allowed resistor tolerance, use Equation 7:
where
•
•
TOL is the set point accuracy of the regulator
Φ is the tolerance of VFB
(7)
19
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LM26400Y
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
www.ti.com
Programming Output Voltage (continued)
Example:
VOUT = 1.2 V, with a set-point accuracy of ±3.5%.
(8)
(9)
Choose 1% resistors. R2 = 5.90 kΩ.
10 Layout
10.1 Layout Guidelines
There are mainly two considerations for PCB layout - thermal and electrical. For thermal details, see Thermal
Considerations. Electrical wise, follow the rules below as much as possible. In general, the LM26400Y is a quite
robust part in terms of insensitivity to different layout patterns or even abuses.
•
•
•
•
•
•
•
•
•
Keep the input ceramic capacitor(s) as close to the PVIN pins as possible.
Use internal ground planes when available.
The SW pins are high current carrying pins so traces connected to them should be short and fat.
Keep feedback resistors close to the FB pins.
Keep the AVIN RC filter close to the AVIN pin.
Keep the voltage feedback traces away from the switch nodes.
Use six or more vias next to the ground pad of the catch diode.
Use at least four vias next to the ground pad of output capacitors.
Use at least four vias next to each pad of the input capacitors.
For low EMI emission, try not to assign large areas of copper to the noisy switch nodes as a heat sinking
method. Instead, assign a lot of copper to the output nodes.
10.1.1 Thermal Shutdown
Whenever the junction temperature of the LM26400Y exceeds 165°C, the MOSFET switch will be kept off until
the temperature drops below 150°C, at which point the regulator will go through a hard start to quickly raise the
output voltage back to normal. Since it is a hard start, there will be an overshoot at the output. See Figure 20.
10.1.2 Power Loss Estimation
The total power loss in the LM26400Y comprises of three parts: the power FET conduction loss, the power FET
switching loss, and the IC's housekeeping power loss. Use Equation 10 to estimate the conduction loss.
where
•
•
TJ is the junction temperature or the target junction temperature if the former is unknown
RDS is the ON resistance of the internal FET at room temperature
(10)
(11)
Use 180 mΩ for RDS if the actual value is unknown.
Use Equation 11 to estimate the switching loss.
Another loss in the IC is the housekeeping loss. The loss is the power dissipated by circuitry in the IC other than
the power FETs. The equation is:
(12)
The 15 mW is gate drive loss. Do the calculation for both channels and find out the total power loss in the IC.
20
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: LM26400Y
LM26400Y
www.ti.com
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
Layout Guidelines (continued)
(13)
The power loss calculation can help estimate the overall power supply efficiency.
Example:
VIN = 12 V, VOUT1 = 1.2 V, IOUT1 = 2 A, VOUT2 = 2.5 V, IOUT2 = 2 A. Target junction temperature is 90°C.
So conduction loss in Channel 1 is:
(14)
(15)
Conduction loss in Channel 2 is:
Switching loss in either channel is:
(16)
(17)
Housekeeping loss is:
Finally the total power loss in the LM26400Y is:
(18)
10.1.3 Inductor Selection
TI recommends an inductance value that gives a peak-to-peak ripple current of 0.4 A to 0.8 A. Too large of a
ripple current can reduce the maximum achievable DC load current because the peak current of the switch is
limited to a typical of 3 A. Too small of a ripple current can cause the regulator to oscillate due to the lack of
inductor current ramp signal, especially under high input voltages. Use Equation 19 to determine inductance:
where
•
VIN_MAX is the maximum input voltage of the application.
(19)
The rated current of the inductor should be higher than the maximum DC load current. Generally speaking, the
lower the DC resistance of the inductor winding, the higher the overall regulator efficiency.
Ferrite core inductors are recommended for less AC loss and less fringing magnetic flux. The drawback of ferrite
core inductors is their quick saturation characteristic. Once the inductor gets saturated, its current can spike up
very quickly if the switch is not turned off immediately. The current limit circuit has a propagation delay and so is
oftentimes not fast enough to stop the saturated inductor from going above the current limit. This has the
potential to damage the internal switch. So to prevent a ferrite core inductor from getting into saturation, the
inductor saturation current rating should be higher than the switch current limit ICL. The LM26400Y is quite robust
in handling short pulses of current that is a few amps above the current limit. When a compromise has to be
made, pick an inductor with a saturation current just above the lower limit of the ICL. Be sure to validate the short-
circuit protection over the intended temperature range.
To prevent the inductor from saturating over the entire –40°C to 125°C range, pick one with a saturation current
higher than the upper limit of ICL in Electrical Characteristics.
Inductor saturation current is usually lower when hot. So consult the inductor vendor if the saturation current
rating is only specified at room temperature.
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: LM26400Y
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
www.ti.com
Layout Guidelines (continued)
Soft saturation inductors such as the iron powder types can also be used. Such inductors do not saturate
suddenly and therefore are safer when there is a severe overload or even shorted output. Their physical sizes
are usually smaller than the Ferrite core inductors. The downside is their fringing flux and higher power
dissipation due to relatively high AC loss, especially at high frequencies.
Example:
VOUT = 1.2 V; VIN = 9 V to 14 V; IOUT = 2 A maximum; Peak-to-peak Ripple Current ΔI = 0.6 A.
(20)
Choose a 5-µH or so ferrite core inductor that has a saturation current around 3 A at room temperature. For
example, Sumida's CDRH6D26NP-5R0NC.
If the maximum load current is significantly lower than 2 A, pick an inductor with the same saturation rating as a
2-A design but with a lowered DC current rating. That should result in a smaller inductor. There are not many
choices, though. Another possibility is to use a soft saturation type inductor, whose size will be dominated by the
DC current rating.
10.1.4 Output Capacitor Selection
Output capacitors in a buck regulator handles the AC current from the inductor and so have little ripple RMS
current and their power dissipation is not a concern. The concern usually revolves around loop stability and
capacitance retention.
The LM26400Y's internal loop compensation was designed around ceramic output capacitors. From a stability
point of view, the lower the output voltage, the more capacitance is needed.
Below is a quick summary of temperature characteristics of some commonly used ceramic capacitors. So an
X7R ceramic capacitor means its capacitance can vary ±15% over the temperature range of –55°C to 125°C.
Table 4. Capacitance Variation Over Temperature (Class II Dielectric Ceramic Capacitors)
LOW TEMPERATURE
X: –55°C
HIGH TEMPERATURE
5: +85°C
CAPACITANCE CHANGE RANGE
R: ±15%
Y: –30°C
6: +105°C
S: ±22%
Z: +10°C
7: +125°C
U: +22%, –56%
V: +22%, –82%
8: +150°C
Besides the variation of capacitance over temperature, the actual capacitance of ceramic capacitors also vary,
sometimes significantly, with applied DC voltage. Figure 34 illustrates such a characteristic of several ceramic
capacitors of various physical sizes from Murata. Unless the DC voltage across the capacitor is going to be small
relative to its rated value, going to too small a physical size will have the penalty of losing significant capacitance
during circuit operation.
Figure 34. Capacitance vs Applied DC Voltage
22
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: LM26400Y
LM26400Y
www.ti.com
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
The amount of output capacitance directly contributes to the output voltage ripple magnitude. A quick way to
estimate the output voltage ripple is to multiply the inductor peak-to-peak ripple current by the impedance of the
output capacitors. For example, if the inductor ripple current is 0.6 A peak-to-peak, and the output capacitance is
44 µF, then the output voltage ripple should be close to 0.6 A × (6.28 × 500 kHz × 44 µF)-1 = 4.3 mV. Sometimes
when a large ceramic capacitor is used, the switching frequency may be higher than the capacitor's self
resonance frequency. In that case, find out the true impedance at the switching frequency and then multiply that
value by the ripple current to get the ripple voltage.
The amount of output capacitance also impacts the stability of the feedback loop. Refer to Loop Stability for
guidelines.
10.1.5 Input Capacitor Selection
The input capacitors provide the AC current needed by the nearby power switch so that current provided by the
upstream power supply does not carry a lot of AC content, generating less EMI. To the buck regulator in
question, the input capacitor also prevents the drain voltage of the FET switch from dipping when the FET is
turned on, therefore providing a healthy line rail for the LM26400Y to work with. Since typically most of the AC
current is provided by the local input capacitors, the power loss in those capacitors can be a concern. In the case
of the LM26400Y regulator, since the two channels operate 180° out of phase, the AC stress in the input
capacitors is less than if they operated in phase. The measure for the AC stress is called input ripple RMS
current. It is strongly recommended that at least one 4.7-µF ceramic capacitor be placed next to the PVIN pins.
Bulk capacitors such as electrolytic capacitors or OSCON capacitors can be added to help stabilize the local line
voltage, especially during large load transient events. As for the ceramic capacitors, use X7R , X6S, or X5R
types. They maintain most of their capacitance over a wide temperature range. Try to avoid sizes smaller than
0805. Otherwise significant drop in capacitance may be caused by the DC bias voltage. See Output Capacitor
Selection section for more information. The DC voltage rating of the ceramic capacitor should be higher than the
highest input voltage.
Capacitor temperature is a major concern in board designs. While using a 4.7-µF or higher MLCC as the input
capacitor is a good starting point, it is a good idea to check the temperature in the real thermal environment to
make sure the capacitors are not over heated. Capacitor vendors may provide curves of ripple RMS current
versus temperature rise, based on a designated thermal impedance. In reality, the thermal impedance may be
very different. So it is always a good idea to check the capacitor temperature on the board.
Because the duty cycles of the two channels may overlap, calculation of the input ripple RMS current is a little
tedious. Use Equation 21:
where
•
•
•
•
•
•
I1 is Channel 1's maximum output current
I2 is Channel 2's maximum output current
d1 is the non-overlapping portion of Channel 1's duty cycle, D1
d2 is the non-overlapping portion of Channel 2's duty cycle, D2
d3 is the overlapping portion of the two duty cycles
Iav is the average input current, Iav= I1 × D1 + I2 × D2
(21)
To quickly determine the values of d1, d2, and d3, refer to the decision tree in Figure 35. To determine the duty
cycle of each channel, use D = VOUT/VIN for a quick result or use the following equation for a more accurate
result.
where
•
•
RDC is the winding resistance of the inductor
RDS is the ON-resistance of the MOSFET switch.
(22)
Example:
VIN = 5 V, VOUT1 = 3.3 V, IOUT1 = 2 A, VOUT2 = 1.2 V, IOUT2 = 1.5 A, RDS = 170 mΩ, RDC = 30 mΩ. (IOUT1 is the
same as I1 in the input ripple RMS current equation, IOUT2 is the same as I2).
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: LM26400Y
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
www.ti.com
First, find out the duty cycles. Plug the numbers into the duty cycle equation and we get D1 = 0.75, and D2 =
0.33. Next, follow the decision tree in Figure 35 to find out the values of d1, d2, and d3. In this case, d1 = 0.5, d2
= D2 + 0.5 – D1 = 0.08, and d3 = D1 – 0.5 = 0.25. Iav = IOUT1 × D1 + IOUT2 × D2 = 1.995 A. Plug all the numbers
into the input ripple RMS current equation and the result is Iirrm = 0.77 A.
Figure 35. Determining d1, d2, and d3
10.1.6 Catch Diode Selection
The catch diode should be at least 2-A rated. The most stressful operation for the diode is usually when the
output is shorted under high line. Always pick a Schottky diode for its lower forward drop and higher efficiency.
The reverse voltage rating of the diode should be at least 25% higher than the highest input voltage. The diode
junction temperature is a main concern here. Always validate the diode's junction temperature in the intended
thermal environment to make sure its thermally derated maximum current is not exceeded. There are a few 2-A,
30-V surface mount Schottky diodes available in the market. Diodes have a negative temperature coefficient, so
do not put two diodes in parallel to achieve a lower temperature rise. Current will be hogged by one of the diodes
instead of shared by the two. Use a larger package for that purpose.
10.2 Layout Example
Figure 36. PCB Layout Example
10.3 Thermal Considerations
Due to the low thermal impedance from junction to the die-attach pad (or DAP, exposed metal at the bottom of
the package), thermal performance heavily depends on PCB copper arrangement. The minimum requirement is
to have a top-layer thermal pad that is exactly the same size as the DAP. There should be at least nine 8-mil
thermal vias in the pad. The thermal vias should be connected to internal ground planes (if available) and to a
ground plane on the bottom layer that is as large as allowed.
24
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: LM26400Y
LM26400Y
www.ti.com
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
Thermal Considerations (continued)
In boards that have internal ground planes, extending the top-layer thermal pad outside the body of the package
to form a "dogbone" shape offers little performance improvement. However, for two-layer boards, the dogbone
shape on the top layer will provide significant help.
Predicting on paper with reasonable accuracy the junction temperature of the LM26400Y in a real-world
application is still an art. Major factors that contribute to the junction temperature but not directly associated with
the thermal performance of the LM26400Y itself include air speed, air temperature, nearby heating elements and
arrangement of PCB copper connected to the DAP of the LM26400Y. The RθJA value published in the datasheet
is based on a standard board design in a single heating element mode and measured in a standard environment.
The real application is usually completely different from those conditions. So the actual RθJA will be significantly
different from the datasheet number. The best approach is still to assign as much copper area as allowed to the
DAP and prototype the design.
When prototyping the design, it is necessary to know the junction temperature of the LM26400Y to assess the
thermal margin. The best way to measure the LM26400Y's junction temperature when the board is working in its
usual mode is to measure the package-top temperature using an infrared thermal imaging camera. Look for the
highest temperature reading across the case-top. Add two degrees to the measurement result and the number
should be a pretty good estimate of the junction temperature. Due to the high temperature gradient across the
case-top, the use of a thermal couple is generally not recommended. If a thermal couple has to be used, try to
locate the hottest spot on the case-top first and then secure the thermal couple at exactly the same location. The
thermal couple needs to be a light-gauge type (such as 40-gauge). Apply a small blob of thermal compound to
the contact point and then secure the thermal couple on the case-top using thermally non-conductive glue.
If the maximum allowed junction temperature is exceeded, load current has to be lowered to bring the
temperature back in specification. Or better thermal management such as more air flow needs to be provided.
As a summary, here is a list of important items to consider:
•
•
Use multi-layer PC boards with internal ground planes.
Use nine or more thermal vias to connect the top-layer thermal pad to internal ground planes and ground
copper on the bottom layer.
•
•
•
•
Generate as large a ground plane as allowable on outer layers, especially near the package.
Use 2-oz. copper whenever possible.
Try to spread out heat generating components.
The inductors and diodes are heat generating components and should be connected to power or ground
planes using many vias.
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: LM26400Y
LM26400Y
SNVS457D –FEBRUARY 2007–REVISED OCTOBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: LM26400Y
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
PACKAGING INFORMATION
Orderable Device
LM26400YMH/NOPB
LM26400YMHX/NOPB
LM26400YSD/NOPB
LM26400YSDE/NOPB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
HTSSOP
HTSSOP
WSON
PWP
16
16
16
16
92
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
L26400
YMH
ACTIVE
ACTIVE
ACTIVE
PWP
NHQ
NHQ
2500
1000
250
Green (RoHS
& no Sb/Br)
-40 to 125
L26400
YMH
Green (RoHS
& no Sb/Br)
L26400Y
WSON
Green (RoHS
& no Sb/Br)
L26400Y
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM26400YMHX/NOPB HTSSOP PWP
16
16
16
2500
1000
250
330.0
178.0
178.0
12.4
12.4
12.4
6.95
5.3
5.6
5.3
5.3
1.6
1.3
1.3
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
LM26400YSD/NOPB
LM26400YSDE/NOPB
WSON
WSON
NHQ
NHQ
5.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM26400YMHX/NOPB
LM26400YSD/NOPB
LM26400YSDE/NOPB
HTSSOP
WSON
PWP
NHQ
NHQ
16
16
16
2500
1000
250
367.0
210.0
210.0
367.0
185.0
185.0
35.0
35.0
35.0
WSON
Pack Materials-Page 2
MECHANICAL DATA
PWP0016A
MXA16A (Rev A)
www.ti.com
MECHANICAL DATA
NHQ0016A
SDA16A (Rev A)
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
相关型号：
LM2640MTC-ADJ/NOPB
IC DUAL SWITCHING CONTROLLER, 230 kHz SWITCHING FREQ-MAX, PDSO28, TSSOP-28, Switching Regulator or Controller
NSC
©2020 ICPDF网 联系我们和版权申明