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LM26420, LM26420-Q0, LM26420-Q1

SNVS579J –FEBRUARY 2009–REVISED SEPTEMBER 2015

LM26420/LM26420-Q0/Q1 Dual 2-A Automotive-Qualified, High-Efficiency Synchronous

DC-DC Converter

1 Features

3 Description

The LM26420 regulator is

a monolithic, high-

1

•

Input Voltage Range of 3 V to 5.5 V

Output Voltage Range of 0.8 V to 4.5 V

2-A Output Current per Regulator

efficiency dual PWM step-down DC-DC converter.

This device has the ability to drive two 2-A loads with

an internal 75-mΩ PMOS top switch and an internal

50-mΩ NMOS bottom switch using state-of-the-art

BICMOS technology results in the best power density

available. The world-class control circuitry allow on

times as low as 30 ns, thus supporting exceptionally

high-frequency conversion over the entire 3-V to 5.5-

V input operating range down to the minimum output

voltage of 0.8 V.

High Switching Frequency: 2.2 MHz (LM26420X)

0.55 MHz (LM26420Y)

•

0.8 V, 1.5% Internal Voltage Reference

Internal Soft-start

Independent Power Good and Precision Enable

for Each Output

•

Current Mode, PWM Operation

Thermal Shutdown

Although the operating frequency is high, efficiencies

up to 93% are easy to achieve. External shutdown is

included, featuring an ultra-low standby current. The

LM26420 utilizes current-mode control and internal

compensation to provide high performance regulation

over a wide range of operating conditions.

Overvoltage Protection

Start-up into Pre-biased Output Loads

Regulators are 180° Out of Phase

LM26420-Q0: AEC-Q100 Grade 0 (Q0) Qualified

(T_J= –40°C to 150°C)

LM26420-Q1: AEC-Q100 Grade 1 (Q1) Qualified

(T_J= –40°C to 125°C)

Device Information⁽¹⁾

PART NUMBER

PACKAGE

HTSSOP (20)

WQFN (16)

BODY SIZE (NOM)

6.50 mm x 4.40 mm

4.00 mm x 4.00 mm

LM26420

•

Compliant with CISPR25 Class 5 Conducted

Emissions

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

2 Applications

space

•

Local 5 V to Vcore of FPGAs

Core Power in HDDs and Set-Top Boxes

USB Powered Devices

Powering Core and I/O Voltages for CPUs and

ASICs

•

Automotive Camera, Infotainment, and Clusters

space

LM26420 Dual Buck DC-DC Converter

LM26420 Efficiency (Up to 93%)

V_IN

3V to 5.5V

VIN

PG

EN

PG

EN

2

1

Buck 1

V_OUT1

Buck 2

V_OUT2

1

2.5V/2A

1.2V/2A

SW

FB

SW

FB

2

1

GND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM26420, LM26420-Q0, LM26420-Q1

SNVS579J –FEBRUARY 2009–REVISED SEPTEMBER 2015

www.ti.com

Table of Contents

1

2

3

4

5

6

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings (LM26420X/Y) .................................... 5

6.3 ESD Ratings (Automotive-LM26420-Q0/Q1) ............ 5

6.4 Recommended Operating Conditions....................... 5

6.5 Thermal Information.................................................. 5

6.6 Electrical Characteristics Per Buck........................... 6

6.7 Typical Characteristics.............................................. 7

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 LM26420 Functional Block Diagram....................... 14

7.3 Feature Description................................................. 14

7.4 Device Functional Modes........................................ 15

8

Application and Implementation ........................ 16

8.1 Application Information............................................ 16

8.2 Typical Applications ............................................... 19

Power Supply Recommendations...................... 30

9

10 Layout................................................................... 31

10.1 Layout Guidelines ................................................. 31

10.2 Layout Example .................................................... 32

10.3 Thermal Considerations........................................ 32

11 Device and Documentation Support ................. 35

11.1 Device Support...................................................... 35

11.2 Documentation Support ........................................ 35

11.3 Related Links ........................................................ 35

11.4 Community Resources.......................................... 35

11.5 Trademarks........................................................... 35

11.6 Electrostatic Discharge Caution............................ 35

11.7 Glossary................................................................ 35

7

12 Mechanical, Packaging, and Orderable

Information ........................................................... 36

4 Revision History

Changes from Revision I (June 2015) to Revision J

Page

•

fixed error in WQFN Pin Functions - shifted "Description" column down one row and added back description for

VIND₁pin................................................................................................................................................................................ 3

•

Changed reference from "Typical Applications" to "Table 1". ............................................................................................. 21

Deleted definition for R_DS(not part of equation 15) ............................................................................................................. 22

Changes from Revision H (August 2014) to Revision I

Page

•

Changed "Frequency" to "Efficiency" in title; add new Feature bullet re: CISPR25............................................................... 1

Added new Application .......................................................................................................................................................... 1

Changed moved Storage temperature to Absolute Maximum Ratings table ......................................................................... 5

Changed figure 36 caption .................................................................................................................................................. 13

Added part number to caption wording ................................................................................................................................ 14

Added application note ........................................................................................................................................................ 16

Changed title of Thermal Guidelines to Thermal Considerations and moved the section to the correct location................ 32

Added Related Documentation and Community Resources subsections............................................................................ 35

Changes from Revision G (July 2014) to Revision H

Page

•

Changed percent sign to suffix .............................................................................................................................................. 6

Changes from Revision F (March 2013) to Revision G

Page

•

Added automotive Grade 0..................................................................................................................................................... 1

Changed formatting to match new TI datasheet guidelines; added Device Information and Handling Ratings tables,

Layout, and Device and Documentation Support sections; reformatted Functional Description to Detailed

Description and Applications to Applications and Implementation sections........................................................................... 1

•

Changed to new equation..................................................................................................................................................... 33

2

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SNVS579J –FEBRUARY 2009–REVISED SEPTEMBER 2015

5 Pin Configuration and Functions

RUM Package

16-Pin WQFN

Top View

PWP Package

20-Pin HTSSOP

Top View

15

14 13

12

11

19

18 17

16

3

2

4

1

20

16

15

14

13

5

6

7

8

DAP

10

11

9

12

3

7

8

9

10

1

2

4

6

5

Pin Functions: 16-Pin WQFN

TYPE

DESCRIPTION

NUMBER

NAME

VIND₁

SW₁

1,2

3

P

G

A

G

Power input supply for Buck 1.

Output switch for Buck 1. Connect to the inductor.

Power ground pin for Buck 1.

4

PGND₁

FB₁

5

Feedback pin for Buck 1. Connect to external resistor divider to set output voltage.

6

PG₁

Power Good Indicator for Buck 1. Pin is connected through a resistor to an external supply

(open drain output).

7

PG₂

G

Power Good Indicator for Buck 2. Pin is connected through a resistor to an external supply

(open drain output).

8

FB₂

PGND₂

SW₂

A

G

P

A

Feedback pin for Buck 2. Connect to external resistor divider to set output voltage.

Power ground pin for Buck 2.

9

10

Output switch for Buck 2. Connect to the inductor.

Power Input supply for Buck 2.

11, 12

13

VIND₂

EN₂

Enable control input. Logic high enable operation for Buck 2. Do not allow this pin to float or

be greater than V_IN+ 0.3 V.

14

AGND

G

Signal ground pin. Place the bottom resistor of the feedback network as close as possible to

pin.

15

16

VINC

EN₁

A

Input supply for control circuitry.

Enable control input. Logic high enable operation for Buck 1. Do not allow this pin to float or

be greater than V_IN+ 0.3 V.

DAP

Die Attach Pad

—

Connect to system ground for low thermal impedance and as a primary electrical GND

connection.

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SNVS579J –FEBRUARY 2009–REVISED SEPTEMBER 2015

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Pin Functions 20-Pin HTSSOP

TYPE

DESCRIPTION

NUMBER

NAME

VINC

EN₁

1

2

A

Input supply for control circuitry.

Enable control input. Logic high enable operation for Buck 1. Do not allow this pin to float or

be greater than V_IN+ 0.3 V.

3, 4

5

VIND₁

SW₁

A

P

G

A

G

Power Input supply for Buck 1.

Output switch for Buck 1. Connect to the inductor.

Power ground pin for Buck 1.

6,7

8

PGND₁

FB₁

Feedback pin for Buck 1. Connect to external resistor divider to set output voltage.

9

PG₁

Power Good Indicator for Buck 1. Pin is connected through a resistor to an external supply

(open drain output).

10, 11, DAP

12

Die Attach Pad

PG₂

—

G

Connect to system ground for low thermal impedance, but it cannot be used as a primary

GND connection.

Power Good Indicator for Buck 2. Pin is connected through a resistor to an external supply

(open drain output).

13

FB₂

PGND₂

SW₂

A

G

P

A

Feedback pin for Buck 2. Connect to external resistor divider to set output voltage.

Power ground pin for Buck 2.

14, 15

16

Output switch for Buck 2. Connect to the inductor.

Power Input supply for Buck 2.

17, 18

19

VIND₂

EN₂

Enable control input. Logic high enable operation for Buck 2. Do not allow this pin to float or

be greater than V_IN+ 0.3 V.

20

AGND

G

Signal ground pin. Place the bottom resistor of the feedback network as close as possible to

pin.

4

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SNVS579J –FEBRUARY 2009–REVISED SEPTEMBER 2015

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

7

UNIT

VIN

Input voltages

FB

3

V

EN

SW

7

Output voltages

7

V

Infrared or convection reflow (15 sec) Soldering Information

Storage temperature T_stg

220

150

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings (LM26420X/Y)

VALUE

±2000

±750

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings (Automotive-LM26420-Q0/Q1)

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

±2000

±750

Other pins

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per AEC Q100-

011

Corner pins 1, 10, 11, and

20

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

3

NOM

MAX

5.5

UNIT

V_IN

V

Junction temperature (Q1)

Junction temperature (Q0)

–40

125

150

°C

6.5 Thermal Information

LM26420

THERMAL METRIC⁽¹⁾

PWP (HTSSOP) RUM (WQFN)

UNIT

20 PINS

35

16 PINS

40

R_θJA

R_θJC

Junction-to-ambient thermal resistance

Junction-to-case thermal resistance

°C/W

3.9

6.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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SNVS579J –FEBRUARY 2009–REVISED SEPTEMBER 2015

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6.6 Electrical Characteristics Per Buck

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

0.8

MAX

UNIT

V

V_FB

Feedback Voltage

0.788

0.812

ΔV_FB/V_IN

I_B

Feedback Voltage Line Regulation

Feedback Input Bias Current

V_IN= 3 V to 5.5 V

0.05

0.4

%/V

nA

V

100

2.9

V_INRising

V_INFalling

2.628

2.3

Undervoltage Lockout

UVLO Hysteresis

UVLO

2

V

330

2.2

mV

LM26420-X

1.85

0.4

2.65

0.7

F_SW

Switching Frequency

MHz

kHz

LM26420-Y

0.55

300

150

91.5%

98%

75

LM26420-X

F_FB

Frequency Fold-back

LM26420-Y

LM26420-X

86%

90%

D_MAX

Maximum Duty Cycle

TOP Switch On Resistance

LM26420-Y

WQFN-16 Package

HTSSOP-20 Package

WQFN-16 Package

TSSOP-20 Package

V_IN= 3.3 V

135

100

80

R_{DSON_TOP}

mΩ

70

55

R_{DSON_BOT}

BOTTOM Switch On Resistance

TOP Switch Current Limit

45

I_{CL_TOP}

I_{CL_BOT}

2.4

0.4

3.3

A

BOTTOM Switch Reverse Current

Limit

V_IN= 3.3 V

0.75

ΔΦ

Phase Shift Between SW₁and SW₂

Enable Threshold Voltage

Enable Threshold Hysteresis

Switch Leakage

160

180

1.04

0.15

-0.7

5

200

°

0.97

1.12

V_{EN_TH}

V

I_{SW_TOP}

I_EN

µA

nA

Enable Pin Current

Sink/Source

V_PG-TH-U

Upper Power Good Threshold

Upper Power Good Hysteresis

Lower Power Good Threshold

Lower Power Good Hysteresis

FB Pin Voltage Rising

848

656

925

40

1,008

791

mV

V_PG-TH-L

FB Pin Voltage Rising

710

40

VINC Quiescent Current (non-

switching) with both outputs on

LM26420X/Y V_FB= 0.9 V

LM26420X/Y V_FB= 0.7 V

3.3

5.0

6.2

mA

µA

I_QVINC

VINC Quiescent Current (switching)

with both outputs on

4.7

VINC Quiescent Current (shutdown)

All Options V_EN= 0 V

0.05

0.9

VIND Quiescent Current (non-

switching)

LM26420X/Y V_FB= 0.9 V

1.5

LM26420X V_FB= 0.7 V

LM26420Q0X V_FB= 0.7 V

LM26420Y V_FB= 0.7 V

All Options V_EN= 0 V

11

15

18

mA

I_QVIND

VIND Quiescent Current (switching)

3.7

0.1

165

7.5

VIND Quiescent Current (shutdown)

Thermal Shutdown Temperature

µA

°C

T_SD

6

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SNVS579J –FEBRUARY 2009–REVISED SEPTEMBER 2015

6.7 Typical Characteristics

All curves taken at V_IN= 5 V with configuration in typical application circuits shown in Application and Implementation section

of this datasheet. T_J= 25°C, unless otherwise specified.

Figure 1. Efficiency vs Load "X"

Figure 2. Efficiency Vs Load "Y"

Figure 4. Efficiency Vs Load "Y"

Figure 3. Efficiency Vs Load - "X"

Figure 5. Efficiency Vs Load "X"

Figure 6. Efficiency vs Load "Y"

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Typical Characteristics (continued)

All curves taken at V_IN= 5 V with configuration in typical application circuits shown in Application and Implementation section

of this datasheet. T_J= 25°C, unless otherwise specified.

Figure 7. Efficiency vs Load "X"

Figure 8. Efficiency vs Load "Y"

Figure 9. Efficiency vs Load "X"

Figure 10. Efficiency vs Load "Y"

1.808

1.807

1.806

1.805

1.804

1.805

1.804

1.803

1.802

1.801

1.803

1.802

1.801

0.0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0

LOAD (A)

V_IN= 5 V

V_OUT= 1.8 V

V_IN= 3 V

V_OUT= 1.8 V

Figure 11. Load Regulation (All Options)

Figure 12. Load Regulation (All Options)

8

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SNVS579J –FEBRUARY 2009–REVISED SEPTEMBER 2015

Typical Characteristics (continued)

All curves taken at V_IN= 5 V with configuration in typical application circuits shown in Application and Implementation section

of this datasheet. T_J= 25°C, unless otherwise specified.

1.798

1.797

1.796

1.795

1.794

1.793

1.792

1.808

1.807

1.806

1.805

1.804

1.803

1.802

3.0

3.5

4.0

4.5

5.0

5.5

3.0

3.5

4.0

4.5

5.0

5.5

INPUT VOLTAGE (V)

V_OUT= 1.8 V

I_OUT= 1000 mA

V_OUT= 1.8 V

I_OUT= 1000 mA

Figure 13. Line Regulation - "X"

Figure 14. Line Regulation - "Y"

Figure 16. Oscillator Frequency vs Temperature - "Y"

Figure 15. Oscillator Frequency vs Temperature - "X"

110

80

100

90

70

60

50

40

30

80

70

60

50

-50 -25

0

25

50

75 100 125

-50 -25

0

25

50

75 100 125

TEMPERATURE (°C)

Figure 17. R_DSONTop Vs Temperature (WQFN-16 Package)

Figure 18. R_DSONBottom Vs Temperature

(WQFN-16 Package)

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Typical Characteristics (continued)

All curves taken at V_IN= 5 V with configuration in typical application circuits shown in Application and Implementation section

of this datasheet. T_J= 25°C, unless otherwise specified.

110

80

70

60

50

100

90

80

40

30

20

70

60

50

-50 -25

0

25

50

75 100 125

-50 -25

0

25

50

75 100 125

TEMPERATURE (°C)

Figure 20. R_DSONBottom Vs Temperature

(TSSOP-20 Package)

Figure 19. R_DSONTop Vs Temperature (TSSOP-20 Package)

11.6

3.9

X Version

Y Version

11.4

11.2

3.8

3.7

3.6

3.5

3.4

11.0

10.8

10.6

-50 -25

0

25

50

75 100 125

-50 -25

0

25

50

75 100 125

TEMPERATURE (°C)

Figure 21. I_Q(Quiescent Current Switching) - "X"

Figure 22. I_Q(Quiescent Current Switching) - "Y"

3.50

3.45

3.40

3.35

3.30

3.25

3.20

3.15

3.10

-50 -25

0

25

50

75 100 125

TEMPERATURE (°C)

V_IN= 5 V & 3.3 V

Figure 24. Current Limit Vs Temperature

Figure 23. V_FBVs Temperature

10

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Typical Characteristics (continued)

All curves taken at V_IN= 5 V with configuration in typical application circuits shown in Application and Implementation section

of this datasheet. T_J= 25°C, unless otherwise specified.

0.78

0.77

0.76

0.75

0.74

0.73

0.72

0.71

0.70

-50 -25

0

25

50

75 100 125

TEMPERATURE (°C)

Figure 26. Short Circuit Waveforms

Figure 25. Reverse Current Limit Vs Temperature

12.50

0.8002

0.8000

0.7998

0.7996

0.7994

0.7992

0.7990

12.00

11.50

11.00

10.50

10.00

IQ SWITCHING - VIND (mA)

FEEDBACK VOLTAGE (V)

0

50

TEMPERATURE (öC)

100

150

0

50

100

150

±50

TEMPERATURE (|C)

C002

C004

Figure 27. I_Q(Quiescent Current) vs Temperature

(Q0 Grade)

Figure 28. V_FBvs Temperature (Q0 Grade)

3.400

0.740

3.350

3.300

3.250

3.200

3.150

3.100

3.050

3.000

0.735

0.730

0.725

0.720

0.715

0.710

0.705

CURRENT LIMIT (A)

REVERSE CURRENT LIMIT (A)

-50

0

50

TEMPERATURE (öꢀ

100

150

-50

0

50

100

150

TEMPERATURE (|C)

C005

C006

Figure 29. Current Limit vs Temperature (Q0 Grade)

Figure 30. Reverse Current Limit vs Temperature (Q0 Grade)

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Typical Characteristics (continued)

All curves taken at V_IN= 5 V with configuration in typical application circuits shown in Application and Implementation section

of this datasheet. T_J= 25°C, unless otherwise specified.

110.0

105.0

100.0

95.0

90.0

85.0

80.0

75.0

70.0

65.0

60.0

65.0

60.0

55.0

50.0

45.0

40.0

35.0

TSSOP - TOP FET - RDSON (mꢀꢀ

TSSOP - BOTTOM FET - RDSON (mꢀꢀ

-50

0

50

100

150

-50

0

50

100

150

TEMPERATURE (|C)

C007

C008

Figure 31. R_DSONTop vs Temperature (Q0 Grade)

Figure 32. R_DSONBottom vs Temperature (Q0 Grade)

2.110

2.105

2.100

2.095

2.090

2.085

OSCILLATOR FREQUENCY (MHz)

-50.0

0.0

50.0

100.0

150.0

TEMPERATURE (|C)

C009

Figure 33. Oscillator Frequency vs Temperature (Q0 Grade)

12

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SNVS579J –FEBRUARY 2009–REVISED SEPTEMBER 2015

7 Detailed Description

7.1 Overview

The LM26420 is a constant frequency dual PWM buck synchronous regulator device that can supply two loads at

up to 2 A each. The regulator has a preset switching frequency of either 2.2 MHz or 550 kHz. This high

frequency allows the LM26420 to operate with small surface mount capacitors and inductors, resulting in a DC-

DC converter that requires a minimum amount of board space. The LM26420 is internally compensated, so it is

simple to use and requires few external components. The LM26420 uses current-mode control to regulate the

output voltage. The following operating description of the LM26420 will refer to the LM26420 Functional Block

Diagram, which depicts the functional blocks for one of the two channels, and to the waveforms in Figure 34. The

LM26420 supplies a regulated output voltage by switching the internal PMOS and NMOS switches at constant

frequency and variable duty cycle. A switching cycle begins at the falling edge of the reset pulse generated by

the internal clock. When this pulse goes low, the output control logic turns on the internal PMOS control switch

(TOP Switch). During this on-time, the SW pin voltage (V_SW) swings up to approximately V_IN, and the inductor

current (I_L) increases with a linear slope. I_Lis measured by the current sense amplifier, which generates an

output proportional to the switch current. The sense signal is summed with the regulator’s corrective ramp and

compared to the error amplifier’s output, which is proportional to the difference between the feedback voltage

and V_REF. When the PWM comparator output goes high, the TOP Switch turns off and the NMOS switch

(BOTTOM Switch) turns on after a short delay, which is controlled by the Dead-Time-Control Logic, until the next

switching cycle begins. During the top switch off-time, inductor current discharges through the BOTTOM Switch,

which forces the SW pin to swing to ground. The regulator loop adjusts the duty cycle (D) to maintain a constant

output voltage.

V

SW

D = T /T

ON SW

V

IN

SW

Voltage

T

OFF

ON

0

t

T

SW

I

L

I

PK

Inductor

Current

0

t

Figure 34. LM26420 Basic Operation of the PWM Comparator

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7.2 LM26420 Functional Block Diagram

VIN

EN

OVP

I

LIMIT

SHDN

ENABLE and

UVLO

Thermal

SHDN

x

+

-

VREF 1.15

+

-

I

SENSE

-

+

Control

Logic

RAMP

Artificial

Clock

2.2 MHz/550 kHz

I

SENSE

S

R

Q

ꢀ

P-FET

N-FET

ꢀ

Dead-

Time-

Control

Logic

+

-

DRIVERS

SW

FB

-

+

Internal-

Comp

Q

R

V

=0.8 V

REF

+

-

S

Internal - LDO

SOFT-START

I

REVERSE-LIMIT

P_good

880 mV

720 mV

+

-

+

-

GND

7.3 Feature Description

7.3.1 Soft-Start

This function forces V_OUTto increase at a controlled rate during start-up in a controlled fashion, which helps

reduce inrush current and eliminate overshoot on V_OUT. During soft-start, the error amplifier’s reference voltage

ramps from 0 V to its nominal value of 0.8 V in approximately 600 µs. If the converter is turned on into a pre-

biased load, then the feedback will begin ramping from the pre-bias voltage but at the same rate as if it had

started from 0 V. The two outputs start up ratiometrically if enabled at the same time, see Figure 35 below.

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Feature Description (continued)

RATIOMETRIC START UP

V

OUT1

V

OUT2

V

EN1,2

TIME

Figure 35. LM26420 Soft-Start

7.3.2 Power Good

The LM26420 features an open drain power good (PG) pin to sequence external supplies or loads and to provide

fault detection. This pin requires an external resistor (R_PG) to pull PG high when the output is within the PG

tolerance window. Typical values for this resistor range from 10 kΩ to 100 kΩ.

7.3.3 Precision Enable

The LM26420 features independent precision enables that allow the converter to be controlled by an external

signal. This feature allows the device to be sequenced either by a external control signal or the output of another

converter in conjunction with a resistor divider network. It can also be set to turn on at a specific input voltage

when used in conjunction with a resistor divider network connected to the input voltage. The device is enabled

when the EN pin exceeds 1.04 V and has a 150-mV hysteresis.

7.4 Device Functional Modes

7.4.1 Output Overvoltage Protection

The overvoltage comparator compares the FB pin voltage to a voltage that is approximately 15% greater than the

internal reference V_REF. Once the FB pin voltage goes 15% above the internal reference, the internal PMOS

switch is turned off, which allows the output voltage to decrease toward regulation.

7.4.2 Undervoltage Lockout

Undervoltage lockout (UVLO) prevents the LM26420 from operating until the input voltage exceeds 2.628 V

(typical). The UVLO threshold has approximately 330 mV of hysteresis, so the part will operate until V_INdrops

below 2.3 V (typical). Hysteresis prevents the part from turning off during power up if V_INis non-monotonic.

7.4.3 Current Limit

The LM26420 uses cycle-by-cycle current limiting to protect the output switch. During each switching cycle, a

current limit comparator detects if the output switch current exceeds 3.3 A (typical), and turns off the switch until

the next switching cycle begins.

7.4.4 Thermal Shutdown

Thermal shutdown limits total power dissipation by turning off the output switch when the device junction

temperature exceeds 165°C. After thermal shutdown occurs, the output switch does not turn on until the junction

temperature drops to approximately 150°C.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Programming Output Voltage

The output voltage is set using the following equation where R2 is connected between the FB pin and GND, and

R1 is connected between V_OUTand the FB pin. A good value for R2 is 10 kΩ. When designing a unity gain

converter (V_OUT= 0.8 V), R1 should be between 0 Ω and 100 Ω, and R2 should be on the order of 5 kΩ to 50

kΩ. 10 kΩ is the suggested value where R1 is the top feedback resistor and R2 is the bottom feedback resistor.

V_OUT

x R2

- 1

R1 =

V_REF

(1)

(2)

V_REF= 0.80V

L

OUT

LM26420

V

OUT

SW

VIND

C

OUT

VINC

EN

R1

R2

FB

AGND

PGND

Figure 36. Programming V_OUT

To determine the maximum allowed resistor tolerance, use Equation 3:

1

V_FB

V =

1 ꢀ

V_OUT

TOL ꢀꢁI

1 + 2x

where

•

TOL is the set point accuracy of the regulator, is the tolerance of V_FB

.

(3)

Example:

V_OUT= 2.5 V, with a set point accuracy of ±3.5%.

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Application Information (continued)

1

0.8V

2.5V

3.5% ꢀ 1.5%

1 ꢀ

V =

= 1.4%

1 + 2x

(4)

Choose 1% resistors. If R2 = 10 kΩ, then R1 is 21.25 kΩ.

8.1.2 VINC Filtering Components

Additional filtering is required between VINC and AGND in order to prevent high frequency noise on VIN from

disturbing the sensitive circuitry connected to VINC. A small RC filter can be used on the VINC pin as shown in

Figure 37.

V

IN

LM26420

VIND

VINC

1,2

SW

FB

R

F

EN

C

IN

C

F

AGND

PGND

Figure 37. RC Filter On VINC

In general, R_Fis typically between 1 Ω and 10 Ω so that the steady state voltage drop across the resistor due to

the VINC bias current does not affect the UVLO level. C_Fcan range from 0.22 µF to 1 µF in X7R or X5R

dielectric, where the RC time constant should be at least 2 µs. C_Fshould be placed as close as possible to the

device with a direct connection from VINC and AGND.

8.1.3 Using Precision Enable and Power Good

The LM26420 device's precision enable and power good pins address many of the sequencing requirements

required in today's challenging applications. Each output can be controlled independently and have independent

power good. This allows for a multitude of ways to control each output. Typically, the enables to each output are

tied together to the input voltage and the outputs will ratiometrically ramp up when the input voltage reaches

above UVLO rising threshold. There may be instances where it is desired that the second output (V_OUT2) does

not turn on until the first output (V_OUT1) has reached 90% of the desired set-point. This is easily achieved with an

external resistor divider attached from V_OUT1to EN₂, see Figure 38.

Figure 38. V_OUT1Controlling V_OUT2with Resistor Divider

If it is not desired to have a resistor divider to control V_OUT2with V_OUT1, then the PG₁can be connected to the

EN₂pin to control V_OUT2, see Figure 39. R_PG1is a pullup resistor on the range of 10 kΩ to 100 kΩ, 50 kΩ is the

suggested value. This will turn on V_OUT2when V_OUT1is approximately 90% of the programmed output.

NOTE

This will also turn off V_OUT2when V_OUT1is outside the ±10% of the programmed output.

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Application Information (continued)

Figure 39. PG₁Controlling V_OUT2

Another example might be that the output is not to be turned on until the input voltage reaches 90% of desired

voltage set-point. This verifies that the input supply is stable before turning on the output. Select R_EN1and R_EN2

such that the voltage at the EN pin is greater than 1.12 V when reaching the 90% desired set-point.

Figure 40. V_OUTControlling V_IN

The power good feature of the LM26420 is designed with hysteresis in order to ensure no false power good flags

are asserted during large transient. Once power good is asserted high, it will not be pulled low until the output

voltage exceeds ±14% of the setpoint for a during of approximately 7.5 µs (typical), see Figure 41.

V_OUT

+14%

+10%

-10%

-14%

~7.5 Ps

t

V_PG

t

Figure 41. Power Good Hysteresis Operation

8.1.4 Overcurrent Protection

When the switch current reaches the current limit value, it is turned off immediately. This effectively reduces the

duty cycle and therefore the output voltage dips and continues to droop until the output load matches the peak

current limit inductor current. As the FB voltage drops below 480 mV the operating frequency begins to decrease

until it hits full on frequency fold-back which is set to approximately 150 kHz for the Y version and 300 kHz for

the X version. Frequency fold back helps reduce the thermal stress in the device by reducing the switching

losses and to prevent runaway of the inductor current when the output is shorted to ground.

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Application Information (continued)

It is important to note that when recovering from a over-current condition the converter does not go through the

soft-start process. There may be an overshoot due to the sudden removal of the overcurrent fault. The reference

voltage at the non-inverting input of the error amplifier always sits at 0.8 V during the overcurrent condition,

therefore when the fault is removed the converter bring the FB voltage back to 0.8 V as quickly as possible. The

overshoot depend on whether there is a load on the output after the removal of the overcurrent fault, the size of

the inductor, and the amount of capacitance on the output. The smaller the inductor and the larger the

capacitance on the output the smaller the overshoot.

NOTE

Overcurrent protection for each output is independent.

8.2 Typical Applications

8.2.1 LM26420X 2.2-MHz, 0.8-V Typical High-Efficiency Application Circuit

Vin

3V to 5.5V

C

R

7

C

5

C

4

3

R

5

R

6

VIN

1

VIN

c

VIN

2

PG

EN

SW

FB

1

2

LM26420

EN

1

V_OUT2

0.8V/2A

V_OUT1

1.8V/2A

L

2

1

SW

1

R

1

2

FB

1

C₁

C

1

C

6

PGND , PGND ,

1

2

AGND, DAP

R

3

R

4

Figure 42. LM26420X (2.2 MHz): V_IN= 5 V, V_OUT1= 1.8 V at 2 A and V_OUT2= 0.8 V at 2 A

8.2.1.1 Design Requirements

Example requirements for typical synchronous DC-DC converter applications:

Table 1. Design Parameters

DESIGN PARAMETER

V_OUT

VALUE

Output voltage

V_IN(minimum)

V_IN(maximum)

I_OUT(maximum)

ƒ_SW

Maximum input voltage

Minimum input voltage

Maximum output current

Switching frequency

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8.2.1.2 Detailed Design Procedure

Table 2. Bill Of Materials

PART ID

U1

PART VALUE

MANUFACTURER

PART NUMBER

2 A Buck Regulator

15 µF, 6.3 V, 1206, X5R

33 µF, 6.3 V, 1206, X5R

22 µF, 6.3 V, 1206, X5R

0.47 µF, 10 V, 0805, X7R

1.0 µH, 7.9 A

TI

LM26420X

C3216X5R0J156M

C3216X5R0J336M

C3216X5R0J226M

VJ0805Y474KXQCW1BC

RLF7030T-1R0M6R4

LPS4414-701ML

C3, C4

C1

TDK

C2, C6

C5

TDK

Vishay

TDK

L1

L2

0.7 µH, 3.7 A

Coilcraft

Vishay

R3, R4

R5, R6

R1

10.0 kΩ, 0603, 1%

49.9 kΩ, 0603, 1%

12.7 kΩ, 0603, 1%

4.99 Ω, 0603, 1%

CRCW060310K0F

CRCW060649K9F

CRCW060312K7F

CRCW06034R99F

R7, R2

8.2.1.2.1 Inductor Selection

The Duty Cycle (D) can be approximated as the ratio of output voltage (V_OUT) to input voltage (V_IN):

V_OUT

D =

V_IN

(5)

The voltage drop across the internal NMOS (SW_BOT) and PMOS (SW_TOP) must be included to calculate a

more accurate duty cycle. Calculate D by using the following formulas:

V_OUT+ V_{SW_BOT}

D =

V_IN+ V_{SW_BOT}± V_{SW_TOP}

(6)

V_{SW_TOP}and V_{SW_BOT}can be approximated by:

V_{SW_TOP}= I_OUTx R_{DSON_TOP}

V_{SW_BOT}= I_OUTx R_{DSON_BOT}

(7)

(8)

The inductor value determines the output ripple voltage. Smaller inductor values decrease the size of the

inductor, but increase the output ripple voltage. An increase in the inductor value will decrease the output ripple

current.

One must ensure that the minimum current limit (2.4 A) is not exceeded, so the peak current in the inductor must

be calculated. The peak current (I_LPK) in the inductor is calculated by:

I_LPK= I_OUT+ Δi_L

(9)

'i

L

I

OUT

V

OUT

V

- V

OUT

IN

L

t

DT

T

S

Figure 43. Inductor Current

V_IN- V_OUT

L

2'i_L

=

DT_S

(10)

(11)

In general,

Δi_L= 0.1 × (I_OUT) → 0.2 × (I_OUT

)

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If Δi_L= 20% of 2 A, the peak current in the inductor will be 2.4 A. The minimum ensured current limit over all

operating conditions is 2.4 A. One can either reduce Δi_L, or make the engineering judgment that zero margin will

be safe enough. The typical current limit is 3.3 A.

The LM26420 operates at frequencies allowing the use of ceramic output capacitors without compromising

transient response. Ceramic capacitors allow higher inductor ripple without significantly increasing output ripple

voltage. See Output Capacitor section for more details on calculating output voltage ripple. Now that the ripple

current is determined, the inductance is calculated by:

DT_S

2'i_L

x (V_IN- V_OUT

)

L =

(12)

Where

1

f_S

T_S=

(13)

When selecting an inductor, make sure that it is capable of supporting the peak output current without saturating.

Inductor saturation will result in a sudden reduction in inductance and prevent the regulator from operating

correctly. The peak current of the inductor is used to specify the maximum output current of the inductor and

saturation is not a concern due to the exceptionally small delay of the internal current limit signal. Ferrite based

inductors are preferred to minimize core losses when operating with the frequencies used by the LM26420. This

presents little restriction since the variety of ferrite-based inductors is huge. Lastly, inductors with lower series

resistance (R_DCR) will provide better operating efficiency. For recommended inductors see Table 2.

8.2.1.2.2 Input Capacitor Selection

The input capacitors provide the AC current needed by the nearby power switch so that current provided by the

upstream power supply does not carry a lot of AC content, generating less EMI. To the buck regulator in

question, the input capacitor also prevents the drain voltage of the FET switch from dipping when the FET is

turned on, therefore providing a healthy line rail for the LM26420 to work with. Since typically most of the AC

current is provided by the local input capacitors, the power loss in those capacitors can be a concern. In the case

of the LM26420 regulator, since the two channels operate 180° out of phase, the AC stress in the input

capacitors is less than if they operated in phase. The measure for the AC stress is called input ripple RMS

current. It is strongly recommended that at least one 10µF ceramic capacitor be placed next to each of the VIND

pins. Bulk capacitors such as electrolytic capacitors or OSCON capacitors can be added to help stabilize the

local line voltage, especially during large load transient events. As for the ceramic capacitors, use X7R or X5R

types. They maintain most of their capacitance over a wide temperature range. Try to avoid sizes smaller than

0805. Otherwise significant drop in capacitance may be caused by the DC bias voltage. See Output Capacitor

section for more information. The DC voltage rating of the ceramic capacitor should be higher than the highest

input voltage.

Capacitor temperature is a major concern in board designs. While using a 10-µF or higher MLCC as the input

capacitor is a good starting point, it is a good idea to check the temperature in the real thermal environment to

make sure the capacitors are not over-heated. Capacitor vendors may provide curves of ripple RMS current vs.

temperature rise, based on a designated thermal impedance. In reality, the thermal impedance may be very

different. So it is always a good idea to check the capacitor temperature on the board.

Since the duty cycles of the two channels may overlap, calculation of the input ripple RMS current is a little

tedious. Use the following equation.

I

=

(I₁- I_av)²d1+(I₂- I_av)²d2 +(I₁+I₂- I_av)²d3

irrms

where

•

I₁is Channel 1's maximum output current.

I₂is Channel 2's maximum output current.

d1 is the non-overlapping portion of Channel 1's duty cycle D₁.

d2 is the non-overlapping portion of Channel 2's duty cycle D₂.

d3 is the overlapping portion of the two duty cycles.

I_avis the average input current.

(14)

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I_av= I₁× D₁+ I₂× D₂. To quickly determine the values of d1, d2 and d3, refer to the decision tree in Figure 44. To

determine the duty cycle of each channel, use D = V_OUT/V_INfor a quick result or use the following equation for a

more accurate result.

V_OUT+ V_{SW_BOT}+ I_OUTx R_DC

D =

V_IN+ V_{SW_BOT}- V_{SW_TOP}

where

•

R_DCis the winding resistance of the inductor.

(15)

Example:

V_IN= 5 V, V_OUT1= 3.3 V, I_OUT1= 2 A, V_OUT2= 1.2 V, I_OUT2= 1.5 A, R_DS= 170 mΩ, R_DC= 30 mΩ. (I_OUT1is the

same as I₁in the input ripple RMS current equation, I_OUT2is the same as I₂).

First, find out the duty cycles. Plug the numbers into the duty cycle equation and we get D1 = 0.75, and D2 =

0.33. Next, follow the decision tree in Figure 44 to find out the values of d1, d2 and d3. In this case, d1 = 0.5, d2

= D2 + 0.5 – D1 = 0.08, and d3 = D1 – 0.5 = 0.25. I_av= I_OUT1× D1 + I_OUT2x D2 = 1.995 A. Plug all the numbers

into the input ripple RMS current equation and the result is I_IR(rms)= 0.77 A.

Figure 44. Determining D1, D2, And D3

8.2.1.2.3 Output Capacitor

The output capacitor is selected based upon the desired output ripple and transient response. The initial current

of a load transient is provided mainly by the output capacitor. The output ripple of the converter is approximately:

1

R_ESR

+

'V_OUT= 'I_L

8 x F_SWx C_OUT

(16)

When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the

output ripple will be approximately sinusoidal and 90° phase shifted from the switching action. Given the

availability and quality of MLCCs and the expected output voltage of designs using the LM26420, there is really

no need to review any other capacitor technologies. Another benefit of ceramic capacitors is their ability to

bypass high frequency noise. A certain amount of switching edge noise will couple through parasitic

capacitances in the inductor to the output. A ceramic capacitor will bypass this noise while a tantalum will not.

Since the output capacitor is one of the two external components that control the stability of the regulator control

loop, most applications will require a minimum of 22 µF of output capacitance. Capacitance often, but not always,

can be increased significantly with little detriment to the regulator stability. Like the input capacitor, recommended

multilayer ceramic capacitors are X7R or X5R types.

8.2.1.2.4 Calculating Efficiency, and Junction Temperature

The complete LM26420 DC-DC converter efficiency can be estimated in the following manner.

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P_OUT

K =

P_IN

(17)

(18)

Or

P_OUT

P_OUT+ P_LOSS

K =

Calculations for determining the most significant power losses are shown below. Other losses totaling less than

2% are not discussed.

Power loss (P_LOSS) is the sum of two basic types of losses in the converter: switching and conduction.

Conduction losses usually dominate at higher output loads, whereas switching losses remain relatively fixed and

dominate at lower output loads. The first step in determining the losses is to calculate the duty cycle (D):

V_OUT+ V_{SW_BOT}

D =

V_IN+ V_{SW_BOT}± V_{SW_TOP}

(19)

V_{SW_TOP}is the voltage drop across the internal PFET when it is on, and is equal to:

V_{SW_TOP}= I_OUT× R_{DSON_TOP}

(20)

V_{SW_BOT}is the voltage drop across the internal NFET when it is on, and is equal to:

V_{SW_BOT}= I_OUT× R_{DSON_BOT}

(21)

(22)

If the voltage drop across the inductor (V_DCR) is accounted for, the equation becomes:

V_OUT+ V_{SW_BOT}+ V_DCR

D =

V_IN+ V_{SW_BOT}+ V_DCR± V_{SW_TOP}

Another significant external power loss is the conduction loss in the output inductor. The equation can be

simplified to:

P_IND= I_OUT²x R_DCR

(23)

The LM26420 conduction loss is mainly associated with the two internal FETs:

2

'i_L

1

3

P_{COND_TOPꢀ}= (I_OUT²x D)

x

R_{DSON_TOP}

1 +

I_OUT

2

'i_L

I_OUT

1

3

P_{COND_BOTꢀ}= (I_OUT²x (1-D))

x

R_{DSON_BOT}

1 +

(24)

If the inductor ripple current is fairly small, the conduction losses can be simplified to:

P_{COND_TOP}= (I_OUT²× R_{DSON_TOP}× D)

(25)

(26)

(27)

P_{COND_BOT}= (I_OUT²× R_{DSON_BOT}× (1-D))

P_COND= P_{COND_TOP}+ P_{COND_BOT}

Switching losses are also associated with the internal FETs. They occur during the switch on and off transition

periods, where voltages and currents overlap resulting in power loss. The simplest means to determine this loss

is to empirically measuring the rise and fall times (10% to 90%) of the switch at the switch node.

Switching Power Loss is calculated as follows:

P_SWR= 1/2(V_IN× I_OUT× F_SW× T_RISE

)

(28)

(29)

(30)

P_SWF= 1/2(V_IN× I_OUT× F_SW× T_FALL

P_SW= P_SWR+ P_SWF

)

Another loss is the power required for operation of the internal circuitry:

P_Q= I_Q× V_IN

(31)

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I_Qis the quiescent operating current, and is typically around 8.4 mA (I_QVINC= 4.7 mA + I_QVIND= 3.7 mA) for the

550-kHz frequency option.

Due to Dead-Time-Control Logic in the converter, there is a small delay (~4 nsec) between the turn ON and OFF

of the TOP and BOTTOM FET. During this time, the body diode of the BOTTOM FET is conducting with a

voltage drop of V_BDIODE(~0.65 V). This allows the inductor current to circulate to the output, until the BOTTOM

FET is turned ON and the inductor current passes through the FET. There is a small amount of power loss due

to this body diode conducting and it can be calculated as follows:

P_BDIODE= 2 × (V_BDIODE× I_OUT× F_SW× T_BDIODE

)

(32)

Typical Application power losses are:

P_LOSS= ΣP_COND+ P_SW+ P_BDIODE+ P_IND+ P_Q

P_INTERNAL= ΣP_COND+ P_SW+ P_BDIODE+ P_Q

(33)

(34)

Table 3. Power Loss Tabulation

DESIGN PARAMETER

VALUE

5 V

DESIGN PARAMETER

VALUE

1.2 V

V_IN

I_OUT

V_OUT

P_OUT

2 A

2.4 W

F_SW

550 kHz

0.65 V

8.4 mA

1.5 nsec

75 mΩ

55 mΩ

20 mΩ

0.262

V_BDIODE

I_Q

P_BDIODE

P_Q

5.7 mW

42 mW

4.1 mW

81 mW

167 mW

80 mW

384 mW

304 mW

T_RISE

T_FALL

R_{DSON_TOP}

R_{DSON_BOT}

IND_DCR

D

P_SWR

P_SWF

P_{COND_TOP}

P_{COND_BOT}

P_IND

P_LOSS

η

86.2%

P_INTERNAL

These calculations assume a junction temperature of 25°C. The R_DSONvalues will be larger due to internal

heating; therefore, the internal power loss (P_INTERNAL) must be first calculated to estimate the rise in junction

temperature.

24

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8.2.1.3 Application Curves

V_OUT= 1.2 V

25-100% Load Transient

V_OUT= 1.2 V

25-100% Load Transient

Figure 46. Load Transient Response - Y Version

Figure 45. Load Transient Response - X Version

V_IN= 5 V

V_OUT= 1.8 V @ 1 A

V_IN= 5 V

V_OUT= 1.8 V @ 1 A

Figure 47. Start-Up (Soft-Start)

Figure 48. Enable - Disable

8.2.2 LM26420X 2.2-MHz, 1.8-V Typical High-Efficiency Application Circuit

Vin

4.5V to

5.5V

C

R

7

C

5

C

4

3

R

5

R

6

VIN

1

VIN

c

VIN

2

PG

EN

SW

FB

1

2

LM26420

EN

1

V_OUT2

1.8V/2A

V_OUT1

3.3V/2A

L

2

1

SW

1

R

1

R

2

FB

1

C

2

1

PGND , PGND ,

1

2

AGND, DAP

R

3

R

4

Figure 49. LM26420X (2.2 MHz): V_IN= 5 V, V_OUT1= 3.3 V at 2 A and V_OUT2= 1.8 V at 2 A

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8.2.2.1 Design Requirements

See Design Requirements above.

8.2.2.2 Detailed Design Procedure

Table 4. Bill Of Materials

PART ID

U1

PART VALUE

MANUFACTURER

PART NUMBER

2 A Buck Regulator

15 µF, 6.3 V, 1206, X5R

22 µF, 6.3 V, 1206, X5R

33 µF, 6.3 V, 1206, X5R

0.47 µF, 10 V, 0805, X7R

1.0 µH, 7.9 A

TI

LM26420X

C3216X5R0J156M

C3216X5R0J226M

C3216X5R0J336M

VJ0805Y474KXQCW1BC

RLF7030T-1R0M6R4

CRCW060310K0F

CRCW060312K7F

CRCW060649K9F

CRCW060331K6F

CRCW06034R99F

C3, C4

C1

TDK

C2

TDK

C5

Vishay

TDK

L1, L2

R3, R4

R2

10.0 kΩ, 0603, 1%

Vishay

12.7 kΩ, 0603, 1%

R5, R6

R1

49.9 kΩ, 0603, 1%

31.6 kΩ, 0603, 1%

R7

4.99 Ω, 0603, 1%

Also see Detailed Design Procedure above.

8.2.2.3 Application Curves

See Application Curves above.

8.2.3 LM26420X 2.2-MHz, 2.5-V Typical High-Efficiency Application Circuit

Vin

3V to 5.5V

C

R

7

C

5

C

4

3

R

5

R

6

VIN

1

VIN

c

VIN

2

PG

1

2

LM26420

EN

1

EN

2

V_OUT2

2.5V/2A

V_OUT1

1.2V/2A

L

2

1

SW

FB

1

2

R

1

R

2

FB

1

C

2

1

PGND , PGND ,

1

2

AGND, DAP

R

3

R

4

Figure 50. LM26420X (2.2 MHz): V_IN= 5 V, V_OUT1= 1.2 V at 2 A and V_OUT2= 2.5 V at 2 A

8.2.3.1 Design Requirements

See Design Requirements above.

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8.2.3.2 Detailed Design Procedure

Table 5. Bill Of Materials

PART ID

U1

PART VALUE

MANUFACTURER

TI

PART NUMBER

LM26420X

2 A Buck Regulator

15 µF, 6.3 V, 1206, X5R

33 µF, 6.3 V, 1206, X5R

22 µF, 6.3 V, 1206, X5R

0.47 µF, 10 V, 0805, X7R

1.0 µH, 7.9A

C3, C4

C1

TDK

C3216X5R0J156M

C3216X5R0J336M

C3216X5R0J226M

VJ0805Y474KXQCW1BC

RLF7030T-1R0M6R4

RLF7030T-1R5M6R1

CRCW060310K0F

CRCW06034K99F

CRCW060649K9F

CRCW060321K5F

CRCW06034R99F

TDK

C2

TDK

C5

Vishay

TDK

L1

L2

1.5 µH, 6.5A

TDK

R3, R4

R1

10.0 kΩ, 0603, 1%

4.99 kΩ, 0603, 1%

49.9 kΩ, 0603, 1%

21.5 kΩ, 0603, 1%

4.99 Ω, 0603, 1%

Vishay

R5, R6

R2

R7

Also see Detailed Design Procedure above.

8.2.3.3 Application Curves

See Application Curves above.

8.2.4 LM26420Y 550 kHz, 0.8-V Typical High-Efficiency Application Circuit

Vin

3V to 5.5V

C

R

7

C

5

C

4

3

R

5

R

6

VIN

1

VIN

c

VIN

2

PG

EN

SW

FB

1

2

LM26420

EN

1

V_OUT2

0.8V/2A

V_OUT1

1.8V/2A

L

2

1

SW

1

R

1

2

FB

1

C₁

C

1

C

6

PGND , PGND ,

1

2

AGND, DAP

R

3

R

4

Figure 51. LM26420Y (550 kHz): V_IN= 5 V, V_OUT1= 1.8 V at 2 A and V_OUT2= 0.8 V at 2 A

8.2.4.1 Design Requirements

See Design Requirements above.

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8.2.4.2 Detailed Design Procedure

Table 6. Bill Of Materials

PART ID

PART VALUE

MANUFACTURER

PART NUMBER

U1

2 A Buck Regulator

22 µF, 6.3 V, 1206, X5R

47 µF, 6.3 V, 1206, X5R

0.47 µF, 10 V, 0805, X7R

5.0 µH, 2.82 A

TI

LM26420Y

C3216X5R0J226M

C3216X5R0J476M

VJ0805Y474KXQCW1BC

MSS7341-502NL

C3, C4

TDK

C1, C2, C6, C7, C8

TDK

C5

L1

Vishay

Coilcraft

Vishay

L2

3.3 µH, 3.28 A

MSS7341-332NL

R3, R4

R5, R6

R1

10.0 kΩ, 0603, 1%

49.9 kΩ, 0603, 1%

12.7 kΩ, 0603, 1%

4.99 Ω, 0603, 1%

CRCW060310K0F

CRCW060649K9F

CRCW060312K7F

CRCW06034R99F

R7, R2

Also see Detailed Design Procedure above.

8.2.4.3 Application Curves

See Application Curves above.

8.2.5 LM26420Y 550-kHz, 1.8-V Typical High-Efficiency Application Circuit

Vin

4.5V to

5.5V

C

R

7

C

5

C

4

3

R

5

R

6

VIN

1

VIN

c

VIN

2

PG

EN

SW

FB

1

2

LM26420

EN

1

V_OUT2

1.8V/2A

V_OUT1

3.3V/2A

L

2

1

SW

1

R

1

R

2

FB

1

C

2

1

PGND , PGND ,

1

2

AGND, DAP

R

3

R

4

Figure 52. LM26420Y (550 kHz): V_IN= 5 V, V_OUT1= 3.3 V at 2 A and V_OUT2= 1.8 V at 2 A

8.2.5.1 Design Requirements

See Design Requirements above.

28

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8.2.5.2 Detailed Design Procedure

Table 7. Bill Of Materials

PART ID

U1

PART VALUE

MANUFACTURER

TI

PART NUMBER

LM26420Y

2 A Buck Regulator

22 µF, 6.3 V, 1206, X5R

47 µF, 6.3 V, 1206, X5R

0.47 µF, 10 V, 0805, X7R

5.0 µH, 2.82 A

C3, C4

C1, C2, C6

C5

TDK

C3216X5R0J226M

C3216X5R0J476M

VJ0805Y474KXQCW1BC

MSS7341-502NL

CRCW060310K0F

CRCW060312K7F

CRCW060649K9F

CRCW060331K6F

CRCW06034R99F

TDK

Vishay

Coilcraft

Vishay

L1, L2

R3, R4

R2

10.0 kΩ, 0603, 1%

12.7 kΩ, 0603, 1%

49.9 kΩ, 0603, 1%

31.6 kΩ, 0603, 1%

4.99 Ω, 0603, 1%

R5, R6

R1

R7

Also see Detailed Design Procedure above.

8.2.5.3 Application Curves

See Application Curves above.

8.2.6 LM26420Y 550-kHz, 2.5-V Typical High-Efficiency Application Circuit

Vin

3V to 5.5V

C

R

7

C

5

C

4

3

R

5

R

6

VIN

1

VIN

c

VIN

2

PG

1

2

LM26420

EN

1

EN

2

V_OUT2

2.5V/2A

V_OUT1

1.2V/2A

L

2

1

SW

FB

1

2

R

1

R

2

FB

1

C

2

1

PGND , PGND ,

1

2

AGND, DAP

R

3

R

4

Figure 53. LM26420Y (550 kHz): V_IN= 5 V, V_OUT1= 1.2 V at 2 A and V_OUT2= 2.5 V at 2 A

8.2.6.1 Design Requirements

See Design Requirements above.

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8.2.6.2 Detailed Design Procedure

Table 8. Bill Of Materials

PART ID

U1

PART VALUE

MANUFACTURER

PART NUMBER

2 A Buck Regulator

22 µF, 6.3 V, 1206, X5R

33 µF, 6.3 V, 1206, X5R

47 µF, 6.3 V, 1206, X5R

0.47 µF, 10 V, 0805, X7R

3.3 µH, 3.28 A

TI

LM26420Y

C3216X5R0J226M

C3216X5R0J336M

C3216X5R0J476M

VJ0805Y474KXQCW1BC

MSS7341-332NL

C3, C4

C1, C6, C7

C2

TDK

C5

Vishay

Coilcraft

Vishay

L1

L2

5.0 µH, 2.82 A

MSS7341-502NL

R3, R4

R1

10.0 kΩ, 0603, 1%

4.99 kΩ, 0603, 1%

49.9 kΩ, 0603, 1%

21.5 kΩ, 0603, 1%

4.99 Ω, 0603, 1%

CRCW060310K0F

CRCW06034K99F

CRCW060649K9F

CRCW060321K5F

CRCW06034R99F

R5, R6

R2

R7

Also see Detailed Design Procedure above.

8.2.6.3 Application Curves

See Application Curves above.

9 Power Supply Recommendations

The LM26420 is designed to operate from an input voltage supply range between 3 V and 5.5 V. This input

supply should be well regulated and able to withstand maximum input current and maintain a stable voltage. The

resistance of the input supply rail should be low enough that an input current transient does not cause a high

enough drop at the LM26420 supply voltage that can cause a false UVLO fault triggering and system reset. If the

input supply is located more than a few inches from the LM26420, additional bulk capacitance may be required in

addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF

electrolytic capacitor is a typical choice.

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10 Layout

10.1 Layout Guidelines

When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The

most important consideration is the close coupling of the GND connections of the input capacitor and the PGND

pin. These ground ends should be close to one another and be connected to the GND plane with at least two

through-holes. Place these components as close to the device as possible. Next in importance is the location of

the GND connection of the output capacitor, which should be near the GND connections of VIND and PGND.

There should be a continuous ground plane on the bottom layer of a two-layer board except under the switching

node island. The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid

noise pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the

device, with the GND of R1 placed as close as possible to the GND of the device. The VOUT trace to R2 should

be routed away from the inductor and any other traces that are switching. High AC currents flow through the VIN,

SW, and VOUT traces, so they should be as short and wide as possible. However, making the traces wide

increases radiated noise, so the designer must make this trade-off. Radiated noise can be decreased by

choosing a shielded inductor. The remaining components should also be placed as close as possible to the

device. Please see Application Note AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines (SNVA054) for

further considerations, and the LM26420 demo board as an example of a four-layer layout.

Figure 54. Internal Connection

For certain high power applications, the PCB land may be modified to a dog bone shape (see Figure 55). By

increasing the size of ground plane, and adding thermal vias, the R_θJAfor the application can be reduced.

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10.2 Layout Example

VIN

C_INC

Place bypass cap close

to VINC and DAP

1

2

20

19

VINC

EN1

AGND

EN2

R_INC

Place ceramic

VIND1

18

17

bypass caps close to

VIND and PGND pins

3

4

VIND2

L₁

VIND1

SW1

L₂

C_IN1

C_IN2

16

15

14

13

12

11

5

SW2

C_OUT1

C_OUT2

PGND1

6

PGND2

VOUT2

VOUT1

7

PGND1

FB1

PGND2

FB2

R_FBT1

8

V_OUTdistribution

point is away

from inductor

and past C_OUT

R_FBT2

R_FBB2

9

PG1

PG2

R_FBB1

Thermal Vias under DAP

10

DAP

GND

As much copper area as possible for GND, for better thermal performance

Figure 55. Typical Layout For DC-DC Converter

10.3 Thermal Considerations

T_J= Chip junction temperature

T_A= Ambient temperature

R

_θJC= Thermal resistance from chip junction to device case

_θJA= Thermal resistance from chip junction to ambient air

R

Heat in the LM26420 due to internal power dissipation is removed through conduction and/or convection.

Conduction: Heat transfer occurs through cross sectional areas of material. Depending on the material, the

transfer of heat can be considered to have poor to good thermal conductivity properties (insulator vs. conductor).

Heat Transfer goes as:

Silicon → package → lead frame → PCB

Convection: Heat transfer is by means of airflow. This could be from a fan or natural convection. Natural

convection occurs when air currents rise from the hot device to cooler air.

Thermal impedance is defined as:

'T

R_Tꢀ=

Power

(35)

Thermal impedance from the silicon junction to the ambient air is defined as:

T_J- T_A

R_TJAꢀ

=

P_INTERNAL

(36)

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Thermal Considerations (continued)

The PCB size, weight of copper used to route traces and ground plane, and number of layers within the PCB can

greatly affect R_θJA. The type and number of thermal vias can also make a large difference in the thermal

impedance. Thermal vias are necessary in most applications. They conduct heat from the surface of the PCB to

the ground plane. Five to eight thermal vias should be placed under the exposed pad to the ground plane if the

WQFN package is used. Up to 12 thermal vias should be used in the HTSSOP-20 package for optimum heat

transfer from the device to the ground plane.

Thermal impedance also depends on the thermal properties of the application's operating conditions (V_IN, V_OUT

,

I_OUT, etc.), and the surrounding circuitry.

10.3.1 Method 1: Silicon Junction Temperature Determination

To accurately measure the silicon temperature for a given application, two methods can be used. The first

method requires the user to know the thermal impedance of the silicon junction to top case temperature.

Some clarification needs to be made before we go any further.

R

_θJCis the thermal impedance from silicon junction to the exposed pad.

_θJTis the thermal impedance from top case to the silicon junction.

R

In this data sheet we will use R_θJTso that it allows the user to measure top case temperature with a small

thermocouple attached to the top case.

R_θJTis approximately 20°C/W for the 16-pin WQFN package with the exposed pad. Knowing the internal

dissipation from the efficiency calculation given previously, and the case temperature, which can be empirically

measured on the bench we have:

T_J- T_T

R_TJTꢀ

=

P_INTERNAL

(37)

(38)

(39)

Therefore:

T_J= (R_θJT× P_INTERNAL) + T_C

From the previous example:

T_J= 20°C/W × 0.304W + T_C

10.3.2 Thermal Shutdown Temperature Determination

The second method, although more complicated, can give a very accurate silicon junction temperature.

The first step is to determine R_θJAof the application. The LM26420 has over-temperature protection circuitry.

When the silicon temperature reaches 165°C, the device stops switching. The protection circuitry has a

hysteresis of about 15°C. Once the silicon junction temperature has decreased to approximately 150°C, the

device will start to switch again. Knowing this, the R_θJAfor any application can be characterized during the early

stages of the design one may calculate the R_θJAby placing the PCB circuit into a thermal chamber. Raise the

ambient temperature in the given working application until the circuit enters thermal shutdown. If the SW pin is

monitored, it will be obvious when the internal FETs stop switching, indicating a junction temperature of 165°C.

Knowing the internal power dissipation from the above methods, the junction temperature, and the ambient

temperature R_θJAcan be determined.

165°- T _A

R_TJAꢀ=

P_INTERNAL

(40)

Once this is determined, the maximum ambient temperature allowed for a desired junction temperature can be

found.

An example of calculating R_θJAfor an application using the LM26420 WQFN demonstration board is shown

below.

The four layer PCB is constructed using FR4 with 1 oz copper traces. The copper ground plane is on the bottom

layer. The ground plane is accessed by eight vias. The board measures 3 cm × 3 cm. It was placed in an oven

with no forced airflow. The ambient temperature was raised to 152°C, and at that temperature, the device went

into thermal shutdown.

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Thermal Considerations (continued)

From the previous example:

P_INTERNAL= 304 mW

(41)

(42)

165^oC - 152^oC

= 42.8^oC/W

=

R_TJAꢀ

304 mW

If the junction temperature was to be kept below 125°C, then the ambient temperature could not go above

112°C.

T_J- (R_θJA× P_INTERNAL) = T_A

(43)

(44)

125°C – (42.8°C/W × 304 mW) = 112.0°C

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Documentation

Application Note AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines (SNVA054).

11.3 Related Links

Table 9 lists quick access links. Categories include technical documents, support and community resources,

tools and software, and quick access to sample or buy.

Table 9. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

LM26420

LM26420Q0

LM26420Q1

Click here

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

25-Aug-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM26420Q0XMHX/NOPB HTSSOP PWP

LM26420Q1XMHX/NOPB HTSSOP PWP

20

16

20

16

20

16

2500

1000

4500

2500

1000

4500

2500

1000

4500

330.0

178.0

330.0

178.0

330.0

178.0

330.0

16.4

12.4

16.4

12.4

16.4

12.4

6.95

4.3

7.1

4.3

7.1

4.3

7.1

4.3

1.6

1.3

1.6

1.3

1.6

1.3

8.0

16.0

12.0

16.0

12.0

16.0

12.0

Q1

LM26420Q1XSQ/NOPB WQFN

LM26420Q1XSQX/NOPB WQFN

RUM

4.3

LM26420XMHX/NOPB HTSSOP PWP

6.95

4.3

LM26420XSQ/NOPB

LM26420XSQX/NOPB

WQFN

RUM

4.3

LM26420YMHX/NOPB HTSSOP PWP

6.95

4.3

LM26420YSQ/NOPB

LM26420YSQX/NOPB

WQFN

RUM

4.3

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

25-Aug-2015

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM26420Q0XMHX/NOPB

LM26420Q1XMHX/NOPB

LM26420Q1XSQ/NOPB

LM26420Q1XSQX/NOPB

LM26420XMHX/NOPB

LM26420XSQ/NOPB

HTSSOP

WQFN

PWP

RUM

PWP

RUM

PWP

RUM

20

16

20

16

20

16

2500

1000

4500

2500

1000

4500

2500

1000

4500

367.0

213.0

367.0

213.0

367.0

213.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

35.0

55.0

35.0

55.0

35.0

55.0

35.0

WQFN

HTSSOP

WQFN

LM26420XSQX/NOPB

LM26420YMHX/NOPB

LM26420YSQ/NOPB

WQFN

HTSSOP

WQFN

LM26420YSQX/NOPB

WQFN

Pack Materials-Page 2

MECHANICAL DATA

PWP0020A

MXA20A (Rev C)

www.ti.com

MECHANICAL DATA

RUM0016A

SQB16A (Rev A)

www.ti.com

IMPORTANT NOTICE

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Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

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Energy and Lighting

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dsp.ti.com

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power.ti.com

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www.ti.com/omap

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Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM26420-Q1
厂家：	TEXAS INSTRUMENTS
描述：	LM26420/LM26420-Q0/Q1 Dual 2-A Automotive-Qualified, High-Efficiency Synchronous DC-DC Converter
文件：	总44页 (文件大小：1515K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM26420-Q1 [TI]

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