LM2650 [TI]

Synchronous Step-Down DC/DC Converter;


型号：	LM2650
厂家：	TEXAS INSTRUMENTS
描述：	Synchronous Step-Down DC/DC Converter
文件：	总19页 (文件大小：938K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM2650

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SNVS133C –JUNE 1999–REVISED APRIL 2013

LM2650 Synchronous Step-Down DC/DC Converter

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FEATURES

DESCRIPTION

The LM2650 is

a step-down DC/DC converter

•

Ultra High Efficiencies (95% possible)

featuring high efficiency over a 3A to milliamperes

load range. This feature makes the LM2650 an ideal

fit in battery-powered applications that demand long

battery life in both run and standby modes.

High Efficiency Over a 3A to Milliamperes

Load Range

•

Synchronous Switching of Internal NMOS

Power FETs

The LM2650 also features

shutdown mode in which it draws at most 25μA from

the input power supply.

logic-controlled

•

Wide Input Voltage Range (4.5V to 18V)

Output Voltage Adjustable from 1.5V to 16V

Automatic Low-Power Sleep Mode

The LM2650 employs a fixed-frequency pulse-width

modulation (PWM) and synchronous rectification to

achieve very high efficiencies. In many applications,

efficiencies reach 95%+ for loads around 1A and

exceed 90% for moderate to heavy loads from 0.2A

to 2A.

Logic-Controlled Micropower Shutdown (I_QSD

25 µA)

≤

•

Frequency Adjustable up to 300 kHz

Frequency Synchronization with External

Signal

low-power hysteretic or "sleep" mode keeps

•

Programmable Soft-Start

efficiencies high at light loads. The LM2650 enters

and exits sleep mode automatically as the load

crosses "sleep in" and "sleep out" thresholds. The

LM2650 provides nodes for programming both

thresholds via external resistors. A logic input allows

the user to override the automatic sleep feature and

keep the LM2650 in PWM mode regardless of the

load level.

Short-Circuit Current Limiting

Thermal Shutdown

Available in 24-lead Small-Outline Package

APPLICATIONS

•

Notebook and Palmtop Personal Computers

Portable Data Terminals

An optional soft-start feature limits current surges

from the input power supply at start up and provides

Modems

simple means of sequencing multiple power

Portable Instruments

supplies.

Global Positioning Devices (GPSs)

Battery-Powered Digital Devices

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM2650

SNVS133C –JUNE 1999–REVISED APRIL 2013

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Typical Application

Figure 1. Converting a Four-Cell Li Ion Battery to 5V

LM2650-ADJ Efficiency

Figure 2.

Connection Diagram

Figure 3. Top View

24-Lead Small Outline Package (DW)

See Package Number DW0024B

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PIN DESCRIPTIONS⁽¹⁾

Pins

Description

1, 12

SUB: These pins make electrical contact with the substrate of the die. Ground them. For best thermal performance,

ground them to the same large, uninterrupted copper plane as the PGND pins.

SLEEP LOGIC: Use this logic input to select the conversion mode; low selects PWM, high selects sleep, and high

impedance (open) permits the LM2650 to move freely and automatically between the modes, using PWM for moderate to

heavy loads and sleep for light loads.

3, 4, 9, 10

5, 8

PGND: The ground return of the power stage. The power stage consists of the two power switches Q1 and Q2, the gate

drivers DH and DL, and the linear voltage regulators VRegH and VRegL. For best electrical and thermal performance,

ground these pins to a large, uninterrupted copper plane.

SW: The output node of the power stage. It swings from slightly below ground to slightly below the voltage to PV_IN. To

minimize the effects of switching noise on nearby circuitry, keep all traces originating from SW short and to the point.

Route all traces carrying signals well away from the SW traces.

6, 7

PV_IN: The positive supply rail of the power stage. Bypass each PV_INpin to PGND with a 0.1 μF capacitor. Use capacitors

having low ESL and low ESR, and locate them close to the IC.

BOOT: The positive supply rail of the high-side gate driver DH. Connect a 0.1 μF capacitor from this node to SW.

Bootstrapping action creates a supply rail about 9V above that at PV_IN, and DH uses this rail to override the gate of the

NMOS power FET Q1. Overriding ensures low R_DS(on)

FB: The feedback input.

V_DD: An internal regulator steps the input voltage down to a 4V rail used by the signal-level circuitry. V_DDis the output

node of this regulator. Bypass V_DDto GND close to the IC with a 0.2 μF capacitor.

COMP: The inverting input of the error amplifier EA.

EA OUT: The output node of the error amplifier EA.

SS: The soft start node. Connect a capacitor from SS to GND.

GND: The ground return of the signal-level circuitry.

V_IN: The positive supply rail of the internal 4V regulator. Bypass V_INto GND close to the IC with a 0.1 μF capacitor.

FREQ ADJ: The LM2650 switches at a nominal 90 kHz. Connect a resistor between FREQ ADJ and GND to adjust the

frequency up from the nominal. Use the graph under Typical performance Characteristics to select the resistor.

SYNC: The synchronization input. If the switching frequency is to be synchronized with an external clock signal, apply the

clock signal here. Ground if not used.

SD: Use this logic input to control shutdown; pull low for operation, high for shutdown.

SLEEP OUT ADJ (SOA): The value of the resistor connected between SIA and ground programs the sleep-in threshold.

Higher values program lower thresholds.

SLEEP IN ADJ (SIA): The value of the resistor connected between SIA and ground programs the sleep-in threshold.

Higher values program lower thresholds.

(1) Refer to the Block Diagrams.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings⁽¹⁾⁽²⁾

(All voltages are referenced to the PGND and GND pins.)

DC Voltage at PV_INand V_IN

20V

15V

DC Voltage at SD, SLEEP LOGIC and SYNC

DC current into SW

±7.5A

Junction Temperature

DC Power Dissipation⁽³⁾

Limited by the IC

1.28W

Storage Temperature

Soldering Time, Temperature⁽⁴⁾

−65°C to +150°C

260°C

Wave (4 seconds)

Infrared (10 seconds)

240°C

Vapor Phase (75 seconds)

219°C

ESD Susceptibility⁽⁵⁾

1.3 kV

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which the

device operates correctly. Operating ratings do not imply performance limits. For performance limits and associated test conditions, see

the Electrical Characteristics.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) This rating is calculated using the formula P_DCmax= (T_Jmax− T_A) / θ_JA, where P_DCmaxis the absolute maximum power dissipation, T_Jmax

is the maximum junction temperature, and θ_JAis the junction ot ambient thermal resistance of the package. The P_DCmaxrating of 1.28W

results from substituting 170°C, 70°C and 78°C/W for T_Jmax, T_Aand θ_JArespectively. A θ_JAof 78°C represents the worst condition of no

heat sinking of the DW0024B small-outline package. Heat sinking allows the safe dissipation of more power. See Application Notes on

thermal management. The LM2650 actively limits its junction temperature to about 170°C.

(4) For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook published by Texas Instruments.

(5) ESD is applied using the human-body model, a 100pF capacitor discharged through a 1.5kΩ resistor.

Operating Ratings⁽¹⁾

Supply Voltage Range (PV_INand V_IN

)

4.5V to 18V

Junction Temperature Range

−40°C to +125°C

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which the

device operates correctly. Operating ratings do not imply performance limits. For performance limits and associated test conditions, see

the Electrical Characteristics.

Electrical Characteristics

V_PVIN= 15V, V_{SLEEP LOGIC}= 0V and V_SD= 0V unless superseded under Conditions. Typicals and limits appearing in plain type

apply for T_A= T_J= +25°C. Limits appearing in boldface type apply over the full junction temperature range shown under

Operating Ratings.

Symbol

V_OUT

Parameter

Output Voltage

Conditions

Typ⁽¹⁾

Limit⁽²⁾

Units

R1 = 75 kΩ, 1%,

5.00

R2 = 25 kΩ, 1%,

7.5V ≤ V_PVIN≤ 18V

0.12A ≤ I_LOAD≤ 3A

4.80/4.75

5.20/5.25

V(min)

V(max)

η1

System Efficiency

I_LOAD= 1A, T_A= 25°C,

F_OSCNot Adjusted

η2

System Efficiency

I_LOAD= 3A, T_A= 25°C,

F_OSCNot Adjusted

V_REF

I_Q

Reference Voltage

V_SLEEPLOGIC= 3V⁽³⁾

1.281/1.294

1.219/1.206

V(min)

V(max)

1.25

4.0

Quiescent Current in PWM mode

Quiescent Current in Sleep mode

V_FB= V_REF

mA(max)

−20mV⁽⁴⁾

6.50/7.0

I_QS

IV_FB= V_REF−20mV,

850

μA

mA(max)

V_SLEEPLOGIC= 3V⁽⁴⁾

1.35/1.60

(1) A typical is the center of characterization data taken at T_A= T_J= 25°C.

(2) Tested at T_A= T_J= 125°C and statistical correlation for room temperature and cold limits.

(3) V_REFis measured at SLEEP OUT ADJ.

(4) Quiescent current is the total current flowing into the P_VINand V_INpins. I_Qincludes the current used to drive the gates of the two NMOS

power FETs at the nominal switching frequency. I_QSincludes no such current.

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Electrical Characteristics (continued)

V_PVIN= 15V, V_{SLEEP LOGIC}= 0V and V_SD= 0V unless superseded under Conditions. Typicals and limits appearing in plain type

apply for T_A= T_J= +25°C. Limits appearing in boldface type apply over the full junction temperature range shown under

Operating Ratings.

Symbol

I_QSD

Parameter

Conditions

Typ⁽¹⁾

Limit⁽²⁾

Units

Quiescent Current in Shutdown

mode

V_SD= 3V⁽⁵⁾

μA

μA(max)

20/25

R_DS(on)HS

DC On-Resistance

Drain-to-Source of the High-Side

Power Switch

I_DS= 1A,

V_SLEEPLOGIC= 3V,

V_FB= 3V,

130

125

mΩ

mΩ(max)

170/245

V_BOOT= 24V

R_DS(on)LS

DC On-Resistance

Drain-to-Source of the Low-Side

Power Switch

I_DS= 1A,

V_FB= 3V

mΩ

mΩ(max)

175/245

I_{L HS}

I_{L LS}

I_LIMIT

Leakage current of the High-Side

Power Switch

V_PVIN= 18V, V_SW= 0V,

V_SD= 3V

100

μA(max)

Leakage current of the Low-Side

Power Switch

V_PVIN= 18V, V_SW= 18V,

V_SD= 3V

μA

μA(max)

210

Active Current Limit of the High-

Side Power Switch

V_PVIN= 15V,

V_BOOT= 24V,

V_FB= 3V,

5.5

3.5

7.5

A(min)

A(max)

V_SLEEPLOGIC= 3V,

F_OSC

Oscillator Frequency

V_FB= V_REF−20 mV

kHz

80/75

100/105

kHz(min)

kHz(max)

F_MAX

Maximum Oscillator Frequency

I_{FREQ ADJ}= 100μA,⁽⁶⁾

V_FB= V_REF−20 mV

315

kHz

kHz(min)

kHz(max)

270/260

360/370

D_MAX

D_MIN

V_DD

Maximum Duty Cycle

Minimum Duty Cycle

Internal Rail Voltage

V_FB= V_REF−20 mV,

F_OSCNot Adjusted

2.8

4.0

%(min)

94/93

V_FB= V_REF+50 mV,

F_OSCNot Adjusted

%(min)

I_VDD= 1 mA

3.6/3.4

4.2/4.3

V(min)

V(max)

V_BOOT

I_SS

Bootstrap Regulator Voltage

(VRegH)

I_BOOT= 1 mA

7.5

6.5/6.0

V(min)

Soft Start Current

μA

μA(max)

13.5/20.0

V_HYST

Hysteresis of the Sleep

V_SLEEPLOGIC= 3V

Comparator (C2 Figure 16)

mV(min)

mV(max)

V_ILof SD

0.95

2.10

0.9

V(max)

V(min)

V(max)

V(min)

V(max)

V(min)

°C

V_IHof SD

V_ILof SLEEP LOGIC

V_IHof SLEEP LOGIC

V_ILof SYNC

2.0

0.50

1.45

V_IHof SYNC

T_SD

T_Jfor Thermal Shutdown

170

(5) Quiescent current is the total current flowing into the P_VINand V_INpins. I_Qincludes the current used to drive the gates of the two NMOS

power FETs at the nominal switching frequency. I_QSincludes no such current.

(6) Pulling 100μA out of FREQ ADJ simulates adjusting the oscillator frequency with a 12.5 kΩ resistor connected from FREQ ADJ to GND.

The sleep mode cannot be used at switching frequencies above 250 kHz.

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Typical Performance Characteristics

I_QSD

Input Voltage

I_QS

Input Voltage

Figure 4.

Figure 5.

I_Q

Input Voltage

Oscillator Frequency

Figure 6.

Figure 7.

R_DS(on)Low-Side

Input Voltage

R_DS(on)High-Side

Input Voltage

Figure 8.

Figure 9.

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Typical Performance Characteristics (continued)

R_DS(on)Low-Side

Junction Temperature

R_DS(on)High-Side

Junction Temperature

Figure 10.

Figure 11.

Oscillator Frequency

Junction Temperature

Oscillator Frequency

Adjusting Resistor

Figure 12.

Figure 13.

Current Limit

Junction Temperature

Figure 14.

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Block Diagrams

Figure 15. The PWM Circuit with External Components in a Closed Control Loop

Figure 16. The Hysteretic or "Sleep" Circuit with External Components in a Closed Control Loop

Figure 17. The Internal Voltage Regulator and Voltage Reference used by Both the PWM and Hysteretic

Circuits

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OPERATION

OVERVIEW

The LM2650 uses two step-down conversion modes: fixed-frquency pulse-width modulation (PWM) and

hysteretic. It moves freely and automatically between them, using PWM for moderate to heavy loads and

hysteretic for light loads.

For clarity, separate block diagrams for each conversion mode have been included. See Figure 15 and

Figure 16. Blocks used in both modes appear in both diagrams with the same label. For example, both modes

use the input buffer B. To keep the diagrams simple, most power supply rails have been omitted. R3, C10, R_C,

C_C, C_B, L1, R1, R2, and C_OUTare outside the IC.

THE PWM CIRCUIT (Figure 15)

The PWM is a fixed-frequency, voltage-mode pulse-width modulator. It consists of four functional blocks: an input

buffer, an error amplifier, a modulator, and a power stage.

1. The input buffer B: B is a voltage follower. A fraction of the output voltage is fed back to its noninverting input

FB. Circumventing B by using the COMP input as the feedback input will cause the IC to malfunction.

2. The error amplifier EA: EA is a voltage amplifier. It subtracts the feedback voltage from the 1.25V reference

and amplifies the difference to produce an error voltage for the control loop. For the purpose of loop

compensation, EA is typically configured as an integrator. In this configuration, a capacitor C_Cand a resistor

R_Care connected in series between the inverting input COMP and the output terminal EA OUT. The

capacitor and the internal 6.5kΩ resistor create a pole, while the capacitor and series resistor create a zero.

3. The modulator: The modulator is the heart of the PWM circuit. It consists of the 90 kHz oscillator, the voltage

comparator C1, and output logic represented here as a simple SR latch.

–

The modulator generates a continuous stream of rectangular, signal-level. It generates the pulses at a

fixed frequency, and it modulates or varies their widths in response to variations in the error voltage. The

pulses appear at Q, the output of the SR latch. An increase in the error voltage results in a proportional

increase in the pulse widths, and, conversely, a decrease in the error voltage results in a proportional

decrease in the pulse widths.

–

The oscillator produces a 90 kHz sawtooth that ramps between 1V and 2V. At the beginning of each

ramp, the oscillator sets the SR latch sending Q high. As the ramp voltage surpasses the error voltage,

C1 resets the SR latch sending Q low. An increase in the error voltage increases the time between the

setting and the resetting of the SR latch which , in turn, results in an equal increase in pulse widths: that

is, an equal increase in the time Q spends high in each cycle. A decrease in the error voltage has the

opposite effect on the pulse widths as it decreases the time between the setting and resetting of the SR

latch.

4. The power stage: The power stage puts some punch between the output of the modulator by translating the

stream of signal-level pulses generated by the modulator into a stream of power pulses that swing from

ground up to the input voltage while sinking and sourcing as much as 3.5A. The power stage consists of two

gate drivers DH and DL, two linear voltage regulators VRegH and VRegL, and two NMOS power FETs Q1

and Q2.

–

The power pulses appear at the SW mode. When Q goes high, DL drives the gate of Q2 low turning Q23

off. While Q2 turns off, the SW potential may remain at just below ground as the body diode of Q2

conducts what was previously reverse current (source-to-drain) in Q2, or the SW potential may swing up

to just above the input voltage as the body diode of Q1 conducts what was previously forward current

(drain-to-source) in Q2. About 50 ns after Q goes high, DH drives the gate of Q1 high turning Q1 on. If

the task remains, Q1 pulls the SW potential up, if not, Q1 simply takes over the conduction responsibility

from its own body diode. When Q goes low, the inverse action occurs resulting in the SW potential

swinging from the input voltage to the ground. The 50 ns delay between one switch beginning to turn off

and the other switch beginning to turn on prevents the switches from "shooting through" directly from the

input supply to the ground.

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–

The PWM circuit drives the pulse stream into the low-pass filter made up of L1 and C_OUT. The filter

passed the DC component of the stream and attenuates the AC components. The output of the filter is

the DC voltage V_OUTsuperimposed with a small ripple voltage. Since the DC component of any periodic

waveforms the average value of the waveform, V_OUTcan be found using:

(1)

–

Here T is the switching period in seconds V(t) is the pulse stream. Under DC steady-state conditions, (1)

yields

(2)

–

Here V_INis the input voltage, and therefore the height of the pulses, in volts, is the width of the pulses in

seconds, and D is the ratio of t_ONto T, the duty or the duty cycle.

The output voltage is programmed using the resistive divider made up for R1 and R2,

(3)

–

As Q1 turns on, its source voltage swings up to just below the input voltage. The LM2650 uses a simple

technique called "bootstrapping" to pull the positive supply rail of DH (at BOOT) up along with the source

voltage of Q1, but to a voltage above the input voltage. Because the source of Q1 and the positive supply

rail of DH make the same voltage swing together, DH maintains the positive gate-to-source voltage

required to turn Q1 on. Q12 plays an active role in pulling the supply rail of DH up and is therefore said to

pull itself up by its "bootstraps", thus the name of the technique and of the BOOT pin.

–

In the typical application, a capacitor CB is connected outside the IC between the BOOT and SW pins.

When Q2 is on, the input supply charges CB through VRegH and the internal diode D.

THE HYSTERETIC CIRCUIT AND LOOP (Figure 16)

Except for C2, the hysteretic circuit borrows all its circuit blocks from the PWM circuit.

The hysteretic comparator C2 is a voltage comparator with built-in hysteresis V_HYSTof typically 30mV centered at

1.25V.

The diode D2 is the body diode of Q2. The hysteretic circuit uses D2 as a rectifier instead of switching Q2 as a

synchronous rectifier.

When the load current drops below the prescribed sleep-in threshold, the LM2650 shuts down the PWM loop and

starts up the hysteretic loop. The hysteretic loop supports light loads more efficiently because it uses less power

to support its own operation; it uses less bias power because it's a simpler loop having less circuit blocks to bias,

and it switches slower, so it incurs lower switching losses.

The hysteretic control loop does not switch at a constant frequency. Instead, it monitors V_OUTand switches only

when V_OUTreaches either side of a narrow window centered on the desired output voltage. C2 directs the

switching based on its reading of the feedback voltage. Switching in this manner yields a regulated voltage

consisting of the desired output voltage and an AC ripple voltage. The magnitude of the AC component can be

approximated using

(4)

For example, with V_OUTset to 5V, V_{OUT_PP}is approximately 120mV,

(5)

When it starts up, the hysteretic loop turns Q1 on. While Q1 is on, the input power supply charges C_OUTand

supplies current to the load. Current from the supply reaches C and the load via the series path provided by Q1

and L1. As the feedback voltage just surpasses the upper hysteretic threshold of C2, the output of C2 changes

from high to low, and HD responds by pulling the gate of Q1 down turning Q1 off. As Q1 turns off, L1 generates

a negative-going voltage transient that D2 clamps at just below ground. D2 remains on only briefly as the current

in L1 runs out. While both Q1 and D2 are off, C_OUTalone supplies current to the load. As the feedback voltage

just surpasses the lower hysteretic threshold of C2, the output of C2 changes states from low to high, and DH

responds by pulling the gate of Q1 up turning Q1 on and starting the hysteretic cycle over.

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Note that as the load current decreases, it takes increasingly longer periods for the load current to discharge

C_OUTthrough the hysteretic window, and as the load current increases, the periods become even shorter. It can

be seen from the above observation that the switching frequency of the hysteretic loop varies as the load varies.

The switching frequency can be approximated using

(6)

Here f is the switching frequency in hertz, I is the load current in amperes, C_OUTis the value of the capacitor in

farads, and V_{OUT_PP}is the magnitude of the AC ripple voltage in volts. Typical switching frequencies range

anywhere from a few hertz for very light loads to a few thousand hertz for light loads bordering on the moderate

level.

Application Circuits

Figure 18 is a schematic of the typical application circuit. use the component values shown in the figure and

those contained in Table 1 to build a 5V, 3A, or 3.3V, 3A step-down DC/DC converter. As with the design of any

DC/DC converter, the design of these circuits involved tradeoffs between efficiency, size, and cost. Here more

weight was given to efficiency than to size as evidenced by the low switching frequency which keeps switching

losses low but pushes the value and size of the inductor up.

From a smaller circuit, use the component values shown in Figure 18 and those contained in Table 3. These

circuits trade slightly higher switching losses for a much smaller inductor. Note, Figure 18 does not show R_FA, the

resistor required to adjust the switching frequency from 90 kHz up to 200 kHz. Connect R_FAbetween the FREQ

ADJ pin and ground.

Figure 18. The Typical 90 kHz Application Circuit

Table 1. Components for the Typical 90 kHz Application Circuit

Input Voltage

Applicable Cell Stacks

Output

7V to 18V IN

8 to 12 Cell NiCd or NiMh, 3 to 4 Cell Li Ion, 8 to 11 Cell Alkaline, 6 Cell Lead Acid

5V, 3A Out

3.3V, 3A out

Input Capacitor C_IN

2 x 22 μF, 35V AVX TPS

Series or Sprague 593D Series

Inductor L1

40μH (See Table 2)

33μH (See Table 2)

Output Capacitor C_OUT

3x220 μF, 10V AVX TPS

Series or Sprague 593D Series

Feedback Resistors R1 and R2

R1 = 75kΩ, 1%, R2 = 24.9kΩ, 1%,

R1 = 41.2kΩ, 1%, R2 = 24.9kΩ, 1%,

Compensation Components R_C, C_C,

R₃, and C₁₀

R_C= 37.4 kΩ, C_C= 4.7 nF,

R₃= 3.57 kΩ, C₁₀= 5.6 nF

R_C= 23.2 kΩ, C_C= 8.2 nF,

R₃= 2.0 kΩ, C₁₀= 10 nF

Sleep Resistors R_SIAand R_SOA

R_SIA= 33 kΩ, R_SOA= 200 kΩ

R_SIA= 39 kΩ, R_SOA= 130 kΩ

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Table 2. Toroidal Inductors Using Cores from MICROMETALS, INC.

Core Number

T38

Core Material

Wire Gauge

AWG # 23

AWG # 21

Number of Strands

Number of Turns

15μH

20μH

33μH

40μH

−52

−18

T38

T50

T50 (B)

Table 3. Components for Typical 200 kHz Applications

Input Voltage

7V to 18V IN

Applicable Cell Stacks

Output

8 to 12 Cell NiCd or NiMh, 3 to 4 Cell Li Ion, 8 to 11 Cell Alkaline, 6 Cell Lead Acid

5V, 3A Out

3.3V, 3A out

Input Capacitor C_IN

2 x 22 μF, 35V AVX TPS

Series or Sprague 593D Series

Inductor L1

20μH (See Table 2)

15μH (See Table 2)

Output Capacitor C_OUT

3x220 μF, 10V AVX TPS

Series or Sprague 593D Series

Feedback Resistors R1 and R2

R1 = 75kΩ, 1%,

R2 = 24.9kΩ, 1%,

R1 = 41.2kΩ, 1%,

R2 = 24.9kΩ, 1%,

Compensation Components R_C, C_C,

R₃, and C₁₀

R_C= 53.6 kΩ, C_C= 2.7 nF,

R₃= 4.02 kΩ, C₁₀= 4.7 nF

R_C= 33.2 kΩ, C_C= 3.9 nF,

R₃= 3.01 kΩ, C₁₀= 6.8 nF

Sleep Resistors R_SIAand R_SOA

Frequency Adjusting Resistor R_FA

R_SIA= 33 kΩ, R_SOA= 200 kΩ

R_FA= 24.9 kΩ

R_SIA= 47 kΩ, R_SOA= 91 kΩ

R_FA= 24.9 kΩ

Figure 19. An Efficient, 2% Accurate 5V to 3.3V Converter

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Product Folder Links: LM2650

LM2650

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SNVS133C –JUNE 1999–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision B (April 2013) to Revision C

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 12

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Product Folder Links: LM2650

PACKAGE OPTION ADDENDUM

www.ti.com

11-Dec-2014

PACKAGING INFORMATION

Orderable Device

LM2650M-ADJ/NOPB

LM2650MX-ADJ/NOPB

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 125

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU SN

Level-3-260C-168 HR

LM2650M

-ADJ

ACTIVE

1000

Green (RoHS

& no Sb/Br)

CU SN | Call TI

Level-3-260C-168 HR

-40 to 125

LM2650M

-ADJ

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Dec-2014

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Dec-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM2650MX-ADJ/NOPB

SOIC

1000

330.0

24.4

10.8

15.9

3.2

12.0

24.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Dec-2014

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC DW 24

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 45.0

LM2650MX-ADJ/NOPB

1000

Pack Materials-Page 2

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LM2650 [TI]

相关型号：

LM2650M-ADJ

LM2650M-ADJ/NOPB

LM2650M-ADJ/NOPB

LM2650MX-ADJ

LM2650MX-ADJ/NOPB

LM2650_15

LM2651

LM2651

LM2651MTC-1.8

LM2651MTC-1.8/NOPB

LM2651MTC-2.5

LM2651MTC-3.3