LM26LV-Q1 [TI]
汽车级、±3°C、1.6V-5.5V、出厂预设跳变点温度开关;
| 型号： | LM26LV-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级、±3°C、1.6V-5.5V、出厂预设跳变点温度开关 开关 |
| 文件： | 总36页 (文件大小：1390K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM26LV, LM26LV-Q1
SNIS144G –JULY 2007–REVISED SEPTEMBER 2016
LM26LV and LM26LV-Q1 1.6-V, WSON-6 Factory Preset Temperature Switch and
Temperature Sensor
1 Features
3 Description
The LM26LV and LM26LV-Q1 are low-voltage,
precision, dual-output, low-power temperature
switches and temperature sensors. The temperature
trip point (TTRIP) can be preset at the factory to any
temperature in the range of 0°C to 150°C in 1°C
1
•
Low 1.6-V Operation
•
•
Low Quiescent Current
Latching Function: Device Can Latch the Over
Temperature Condition
increments. Built-in temperature hysteresis (THYST
keeps the output stable in an environment of
temperature instability.
)
•
Push-Pull and Open-Drain Temperature Switch
Outputs
•
•
Wide Trip Point Range of 0°C to 150°C
In normal operation the LM26LV or LM26LV-Q1
temperature switch outputs assert when the die
temperature exceeds TTRIP. The temperature switch
outputs will reset when the temperature falls below a
Very Linear Analog VTEMP Temperature Sensor
Output
•
•
VTEMP Output Short-Circuit Protected
temperature equal to (TTRIP
–
THYST). The
Accurate Over –50°C to 150°C Temperature
Range
OVERTEMP digital output, is active-high with a push-
pull structure, while the OVERTEMP digital output, is
active-low with an open-drain structure.
•
•
Excellent Power Supply Noise Rejection
LM26LVQISD-130 and LM26LVQISD-135 are
AEC-Q100 Qualified and are Manufactured on an
Automotive Grade Flow:
The analog output, VTEMP, delivers an analog output
voltage with Negative Temperature Coefficient (NTC).
Driving the TRIP_TEST input high causes the digital
outputs to be asserted for in-situ verification and
causes the threshold voltage to appear at the VTEMP
output pin, which could be used to verify the
temperature trip point.
–
Device Temperature Grade 0: –40°C to 150°C
Ambient Operating Temperature Range
–
–
–
Device HBM ESD Classification Level 3 A
Device CDM ESD Classification Level C6
Device MM ESD Classification Level M3
The LM26LV's and LM26LV-Q1's low minimum
supply voltage makes them ideal for 1.8-V system
designs. The wide operating range, low supply
2 Applications
current, and excellent accuracy provide
temperature switch solution for a wide range of
commercial and industrial applications.
a
•
•
•
•
•
•
Cell Phones and Wireless Transceivers
Digital Cameras
Battery Management Systems
Automotive Applications
Disk Drives
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LM26LV, LM26LV-Q1 WSON (6)
2.20 mm × 2.50 mm
Games and Appliances
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Redundant Protection and Monitoring
Typical Transfer Characteristic
V
V
Supply
DD
DD
Analog
(+1.6V to +5.5V)
V
ADC Input
TEMP
Example: 2 to 3
Battery Cells
LM26LV
Microcontroller
OVERTEMP
OVERTEMP
TRIP TEST
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM26LV, LM26LV-Q1
SNIS144G –JULY 2007–REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 21
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application .................................................. 23
Power Supply Recommendations...................... 25
9.1 Power Supply Noise Immunity................................ 25
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings: LM26LV.............................................. 4
6.3 ESD Ratings: LM26LV-Q1........................................ 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 5
6.6 Electrical Characteristics........................................... 5
6.7 Switching Characteristics.......................................... 6
6.8 Accuracy Characteristics........................................... 7
6.9 Typical Characteristics.............................................. 9
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
8
9
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1 Documentation Support ........................................ 27
11.2 Related Links ........................................................ 27
11.3 Receiving Notification of Documentation Updates 27
11.4 Community Resources.......................................... 27
11.5 Trademarks........................................................... 27
11.6 Electrostatic Discharge Caution............................ 27
11.7 Glossary................................................................ 27
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2013) to Revision G
Page
•
•
Added Device Information table, Pin Configuration and Functions section, Specifications section, ESD Ratings table,
Thermal Information table, Switching Characteristics table, Detailed Description section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
Updated values in the Thermal Information table to align with JEDEC standards................................................................. 5
Changes from Revision E (February 2013) to Revision F
Page
•
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
2
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SNIS144G –JULY 2007–REVISED SEPTEMBER 2016
5 Pin Configuration and Functions
NGF Package
6-Pin WSON
Top View
TRIP_TEST
GND
1
6
VTEMP
Thermal
Pad
2
3
5
4
OVERTEMP
VDD
OVERTEMP
Not to scale
Pin Functions
PIN
EQUIVALENT
CIRCUIT
TYPE
DESCRIPTION
NAME
NO.
GND
2
GND Power supply ground
—
V
DD
Overtemperature switch output. Active high, push-pull.
OVERTEMP
5
O
Asserted when the measured temperature exceeds the trip point temperature or
if TRIP_TEST = 1. This pin may be left open if not used.
GND
Overtemperature switch output. Active low, open-drain (See Determining the
Pullup Resistor Value).
Asserted when the measured temperature exceeds the trip point temperature or
if TRIP_TEST = 1. This pin may be left open if not used.
OVERTEMP
3
O
GND
V
DD
TRIP_TEST pin. Active high input.
If TRIP_TEST = 0 (Default) then: VTEMP = VTS, temperature sensor output
voltage.
If TRIP_TEST = 1 then: OVERTEMP and OVERTEMP outputs are asserted and
VTEMP = VTRIP, temperature trip voltage.
TRIP_TEST
1
4
6
I
1 mA
This pin may be left open if not used.
GND
—
VDD
PWR Positive supply voltage
V
DD
V
SENSE
VTEMP analog voltage output.
If TRIP_TEST = 0 then: VTEMP = VTS, temperature sensor output voltage.
If TRIP_TEST = 1 then: VTEMP = VTRIP, temperature trip voltage.
VTEMP
O
This pin may be left open if not used.
GND
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Pin Functions (continued)
PIN
EQUIVALENT
CIRCUIT
TYPE
DESCRIPTION
NAME
NO.
The best thermal conductivity between the device and the PCB is achieved by
soldering the DAP of the package to the thermal pad on the PCB. The thermal
pad can be a floating node. However, for improved noise immunity the thermal
pad must be connected to the circuit GND node, preferably directly to pin 2
(GND) of the device.
Thermal Pad
—
—
—
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
–0.3
–0.3
–7
MAX
UNIT
V
Supply voltage
6
Voltage at OVERTEMP pin
Voltage at OVERTEMP and VTEMP pins
TRIP_TEST input voltage
6
V
VDD + 0.5
V
VDD + 0.5
V
Output current, any output pin
Input current at any pin(3)
7
mA
mA
°C
°C
5
Maximum junction temperature, TJ(MAX)
Storage temperature, Tstg
155
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For soldering specifications, see Absolute Maximum Ratings for Soldering.
(3) When the input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > VDD), the current at that pin must be limited to 5 mA.
6.2 ESD Ratings: LM26LV
VALUE
±4500
±1000
±300
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Machine model (MM)(3)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) The machine model (MM) is a 200-pF capacitor charged to the specified voltage then discharged directly into each pin.
6.3 ESD Ratings: LM26LV-Q1
VALUE
±4500
±1000
±300
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Machine model (MM)
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
V
VDD
Supply voltage
1.6
5.5
Supply current
8
µA
°C
TA
Specified ambient temperature
–50
150
4
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SNIS144G –JULY 2007–REVISED SEPTEMBER 2016
6.5 Thermal Information
LM26LV and
LM26LV-Q1
THERMAL METRIC(1)
UNIT
NGF (WSON)
6 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
100.7
121.7
70
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.1
ψJB
70.3
15.9
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Electrical Characteristics
Typical values apply for TA = TJ = 25°C; minimum and maximum limits apply for TA = TJ = –50°C to 150°C,
VDD = 1.6 V to 5.5 V (unless otherwise noted).(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GENERAL SPECIFICATIONS
IS
Quiescent power supply current
Hysteresis
OVERTEMP DIGITAL OUTPUT—ACTIVE HIGH, PUSH-PULL
8
5
16
µA
°C
4.5
5.5
V
V
V
V
V
V
DD ≥ 1.6 V, Source ≤ 340 µA
VDD – 0.2
VDD – 0.2
VDD – 0.2
VDD – 0.45
VDD – 0.45
VDD – 0.45
DD ≥ 2 V, Source ≤ 498 µA
DD ≥ 3.3 V, Source ≤ 780 µA
DD ≥ 1.6 V, Source ≤ 600 µA
DD ≥ 2 V, Source ≤ 980 µA
DD ≥ 3.3 V, Source ≤ 1.6 mA
VOH
Logic High output voltage
V
BOTH OVERTEMP AND OVERTEMP DIGITAL OUTPUTS
V
V
V
V
V
V
DD ≥ 1.6 V, Source ≤ 385 µA
0.2
0.2
DD ≥ 2 V, Source ≤ 500 µA
DD ≥ 3.3 V, Source ≤ 730 µA
DD ≥ 1.6 V, Source ≤ 690 µA
DD ≥ 2 V, Source ≤ 1.05 mA
DD ≥ 3.3 V, Source ≤ 1.62 mA
0.2
VOL
Logic Low output voltage
V
0.45
0.45
0.45
OVERTEMP DIGITAL OUTPUT—ACTIVE LOW, OPEN DRAIN
TA = 30°C
0.001
0.025
1
1
Logic High output leakage
IOH
µA
current(3)
TA = 150°C
(1) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) Typical values apply for TJ = TA = 25°C and represent most likely parametric norm.
(3) The 1-µA limit is based on a testing limitation and does not reflect the actual performance of the part. Expect to see a doubling of the
current for every 15°C increase in temperature. For example, the 1-nA typical current at 25°C would increase to 16 nA at 85°C.
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Electrical Characteristics (continued)
Typical values apply for TA = TJ = 25°C; minimum and maximum limits apply for TA = TJ = –50°C to 150°C,
VDD = 1.6 V to 5.5 V (unless otherwise noted).(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VTEMP ANALOG TEMPERATURE SENSOR OUTPUT
Gain 1 (trip point = 0°C to 69°C)
–5.1
–7.7
Gain 2 (trip point = 70°C to 109°C)
Gain 3 (trip point = 110°C to 129°C)
Gain 4 (trip point = 130°C to 150°C)
Source ≤ 90 µA,
VTEMP sensor gain
mV/°C
–10.3
–12.8
–1
–1
–0.1
0.1
VDD – VTEMP ≥ 200 mV
1.6 V ≤ VDD < 1.8 V
Sink ≤ 100 µA, VTEMP ≥ 260 mV
1
mV
VTEMP load regulation(4)
Source ≤ 120 µA,
–0.1
VDD – VTEMP ≥ 200 mV
VDD ≥ 1.8 V
Sink ≤ 200 µA, VTEMP ≥ 260 mV
0.1
1
1
Source or sink = 100 µA
Ω
0.29
74
mV
µV/V
dB
pF
Supply to VTEMP DC line
regulation(5)
VDD = 1.6 V to 5.5 V
–82
1100
CL
VTEMP output load capacitance
Without series resistor. See Capacitive Loads.
TRIP_TEST DIGITAL INPUT
VIH
VIL
IIH
Logic High threshold voltage
VDD – 0.5
V
Logic Low threshold voltage
Logic High input current
Logic Low input current(3)
0.5
1.5
2.5
1
µA
µA
IIL
0.001
(4) Source currents are flowing out of the LM26LV or LM26LV-Q1. Sink currents are flowing into the LM26LV or LM26LV-Q1.
(5) Line regulation (DC) is calculated by subtracting the output voltage at the highest supply voltage from the output voltage at the lowest
supply voltage. The typical DC line regulation specification does not include the output voltage shift discussed in Voltage Shift.
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Time from power ON to digital output enabled(1)
Time from power ON to analog temperature valid(1) CL = 0 pF to 1100 pF
TEST CONDITIONS
MIN
TYP
1.1
1
MAX UNIT
tEN
2.3
2.9
ms
ms
tVTEMP
(1) Figure 1 and Figure 2 show the definitions of tEN and tVTEMP
.
6
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6.8 Accuracy Characteristics
(1)
See
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
TRIP POINT ACCURACY
Trip point accuracy(2)
TA = 0°C to 150°C, VDD = 5 V
–2.2
2.2
°C
VTEMP ANALOG TEMPERATURE SENSOR OUTPUT ACCURACY(3)
TA = 20°C to 40°C, VDD = 1.6 V to 5.5 V
TA = 0°C to 70°C, VDD = 1.6 V to 5.5 V
TA = 0°C to 90°C, VDD = 1.6 V to 5.5 V
TA = 0°C to 120°C, VDD = 1.6 V to 5.5 V
TA = 0°C to 150°C, VDD = 1.6 V to 5.5 V
TA = –50°C to 0°C, VDD = 1.7 V to 5.5 V
TA = 20°C to 40°C, VDD = 1.8 V to 5.5 V
TA = 0°C to 70°C, VDD = 1.9 V to 5.5 V
TA = 0°C to 90°C, VDD = 1.9 V to 5.5 V
TA = 0°C to 120°C, VDD = 1.9 V to 5.5 V
TA = 0°C to 150°C, VDD = 1.9 V to 5.5 V
TA = –50°C to 0°C, VDD = 2.3 V to 5.5 V
TA = 20°C to 40°C, VDD = 2.3 V to 5.5 V
TA = 0°C to 70°C, VDD = 2.5 V to 5.5 V
TA = 0°C to 90°C, VDD = 2.5 V to 5.5 V
TA = 0°C to 120°C, VDD = 2.5 V to 5.5 V
TA = 0°C to 150°C, VDD = 2.5 V to 5.5 V
TA = –50°C to 0°C, VDD = 3 V to 5.5 V
TA = 20°C to 40°C, VDD = 2.7 V to 5.5 V
TA = 0°C to 70°C, VDD = 3 V to 5.5 V
TA = 0°C to 90°C, VDD = 3 V to 5.5 V
TA = 0°C to 120°C, VDD = 3 V to 5.5 V
TA = 0°C to 150°C, VDD = 3 V to 5.5 V
TA = –50°C to 0°C, VDD = 3.6 V to 5.5 V
–1.8
–2
1.8
2
–2.1
–2.2
–2.3
–1.7
–1.8
–2
2.1
2.2
2.3
1.7
1.8
2
Gain 1
trip point = 0°C to 69°C
–2.1
–2.2
–2.3
–1.7
–1.8
–2
2.1
2.2
2.3
1.7
1.8
2
Gain 2
trip point = 70°C to 109°C
VTEMP temperature accuracy(2)
°C
–2.1
–2.2
–2.3
–1.7
–1.8
–2
2.1
2.2
2.3
1.7
1.8
2
Gain 3
trip point = 110°C to 129°C
–2.1
–2.2
–2.3
–1.7
2.1
2.2
2.3
1.7
Gain 4
trip point = 130°C to 150°C
(1) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) Accuracy is defined as the error between the measured and reference output voltages, tabulated in Table 1 at the specified conditions of
supply gain setting, voltage, and temperature (°C). Accuracy limits include line regulation within the specified conditions. Accuracy limits
do not include load regulation; they assume no DC load.
(3) Changes in output due to self heating can be computed by multiplying the internal dissipation by the temperature thermal resistance.
V
DD
1.3V
t
EN
OVERTEMP
Enabled
Enabled
OVERTEMP
Figure 1. Definition of tEN
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V
DD
t
VTEMP
Valid
V
TEMP
Figure 2. Definition of tVTEMP
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6.9 Typical Characteristics
Figure 3. VTEMP Output Temperature Error vs Temperature
Figure 4. Minimum Operating Temperature
vs Supply Voltage
Figure 5. Supply Current vs Temperature
Figure 6. Supply Current vs Supply Voltage
100-mV overhead
TA = 80°C
Sourcing current
200-mV overhead
TA = 80°C
Sourcing Current
(1)
Figure 7. Load Regulation
Figure 8. Load Regulation(1)
(1) The curves shown represent typical performance under worst-case conditions. Performance improves with larger VTEMP, larger VDD, and
lower temperatures.
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Typical Characteristics (continued)
400-mV overhead
TA = 80°C
Sourcing current
1.72-V overhead TA = 150°C
VDD = 2.4 V Sourcing current
Figure 9. Load Regulation(1)
Figure 10. Load Regulation(1)
VDD = 1.6 V
Sinking Current
VDD = 1.8 V
Sinking Current
Figure 12. Load Regulation(1)
Figure 11. Load Regulation(1)
VDD = 2.4 V
Sinking Current
Figure 13. Load Regulation(1)
Figure 14. Change in VTEMP vs Overhead Voltage
(1) The curves shown represent typical performance under worst-case conditions. Performance improves with larger VTEMP, larger VDD, and
lower temperatures.
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Typical Characteristics (continued)
Gain 1 (Trip Points = 0°C tp 69°C)
Figure 15. VTEMP Supply-Noise Rejection vs Frequency
Figure 16. Line Regulation VTEMP vs Supply Voltage
Gain 2 (Trip Points = 70°C to 109°C)
Gain 3 (Trip Points = 110°C to 129°C)
Figure 17. Line Regulation VTEMP vs Supply Voltage
Figure 18. Line Regulation VTEMP vs Supply Voltage
Gain 4 (Trip Points = 130°C to 150°C)
Figure 19. Line Regulation VTEMP vs Supply Voltage
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7 Detailed Description
7.1 Overview
The LM26LV and LM26LV-Q1 are precision, dual-output, temperature switches with analog temperature sensor
output. The trip temperature (TTRIP) is factory selected by the order number. The VTEMP class AB analog output
provides a voltage that is proportional to temperature. The LM26LV and LM26LV-Q1 include an internal
reference DAC (TEMP THRESHOLD), analog temperature sensor and analog comparator. The reference DAC is
connected to one of the comparator inputs. The reference DAC output voltage (VTRIP) is preprogrammed by TI.
The result of the reference DAC voltage and the temperature sensor output comparison is provided on two
output pins OVERTEMP and OVERTEMP.
The VTEMP output has a programmable gain. The output gain has 4 possible settings as described in Table 1.
The gain setting is dependent on the temperature trip point selected.
Built-in temperature hysteresis (THYST) prevents the digital outputs from oscillating. The OVERTEMP and
OVERTEMP activates when the die temperature exceeds TTRIP and releases when the temperature falls below a
temperature equal to TTRIP minus THYST. OVERTEMP is active-high with a push-pull structure. OVERTEMP, is
active-low with an open-drain structure. The comparator hysteresis is fixed at 5°C.
Driving the TRIP-TEST high activates the digital outputs. A processor can check the logic level of the
OVERTEMP or OVERTEMP, confirming that they changed to their active state. This allows for system
production testing verification that the comparator and output circuitry are functional after system assembly.
When the TRIP-TEST pin is high, the trip-level reference voltage appears at the VTEMP pin. Tying OVERTEMP to
TRIP-TEST latches the output after it trips. It can be cleared by forcing TRIP-TEST low or powering off the
LM26LV or LM26LV-Q1.
7.2 Functional Block Diagram
V
DD
4
TRIP TEST = 0
(Default)
LM26LV
6
3
V
TEMP
TRIP TEST = 1
OVERTEMP
V
V
TRIP
TS
V
DD
TEMP
SENSOR
TEMP
5
THRESHOLD
OVERTEMP
1
2
GND
TRIP
TEST
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7.3 Feature Description
7.3.1 LM26LV and LM26LV-Q1 VTEMP vs Die Temperature Conversion Table
The LM26LV and LM26LV-Q1 have one out of four possible factory-set gains, Gain 1 through Gain 4, depending
on the range of the Temperature Trip Point. The VTEMP temperature sensor voltage, in millivolts, at each discrete
die temperature over the complete operating temperature range, and for each of the four Temperature Trip Point
ranges, is shown in Table 1. This table is the reference from which the LM26LV and LM26LV-Q1 accuracy
specifications (listed in Accuracy Characteristics) are determined. This table can be used, for example, in a host
processor look-up table. See The Second-Order Equation (Parabolic) for the parabolic equation used in the
Conversion Table.
Table 1. VTEMP Temperature Sensor Output Voltage vs Die Temperature Conversion Table
ANALOG OUTPUT VOLTAGE, VTEMP (mV)(1)
DIE TEMPERATURE (°C)
GAIN 1
1312
1307
1302
1297
1292
1287
1282
1277
1272
1267
1262
1257
1252
1247
1242
1237
1232
1227
1222
1217
1212
1207
1202
1197
1192
1187
1182
1177
1172
1167
1162
1157
1152
1147
1142
1137
1132
1127
1122
GAIN 2
1967
1960
1952
1945
1937
1930
1922
1915
1908
1900
1893
1885
1878
1870
1863
1855
1848
1840
1833
1825
1818
1810
1803
1795
1788
1780
1773
1765
1757
1750
1742
1735
1727
1720
1712
1705
1697
1690
1682
GAIN 3
2623
2613
2603
2593
2583
2573
2563
2553
2543
2533
2523
2513
2503
2493
2483
2473
2463
2453
2443
2433
2423
2413
2403
2393
2383
2373
2363
2353
2343
2333
2323
2313
2303
2293
2283
2272
2262
2252
2242
GAIN 4
3278
3266
3253
3241
3229
3216
3204
3191
3179
3166
3154
3141
3129
3116
3104
3091
3079
3066
3054
3041
3029
3016
3004
2991
2979
2966
2954
2941
2929
2916
2903
2891
2878
2866
2853
2841
2828
2815
2803
–50
–49
–48
–47
–46
–45
–44
–43
–42
–41
–40
–39
–38
–37
–36
–35
–34
–33
–32
–31
–30
–29
–28
–27
–26
–25
–24
–23
–22
–21
–20
–19
–18
–17
–16
–15
–14
–13
–12
(1) VDD = 5 V. Values are bold for each gain's respective trip point range.
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Feature Description (continued)
Table 1. VTEMP Temperature Sensor Output Voltage vs Die Temperature Conversion Table (continued)
ANALOG OUTPUT VOLTAGE, VTEMP (mV)(1)
DIE TEMPERATURE (°C)
GAIN 1
1116
1111
1106
1101
1096
1091
1086
1081
1076
1071
1066
1061
1056
1051
1046
1041
1035
1030
1025
1020
1015
1010
1005
1000
995
GAIN 2
1674
1667
1659
1652
1644
1637
1629
1621
1614
1606
1599
1591
1583
1576
1568
1561
1553
1545
1538
1530
1522
1515
1507
1499
1492
1484
1477
1469
1461
1454
1446
1438
1431
1423
1415
1407
1400
1392
1384
1377
1369
1361
1354
1346
1338
1331
1323
1315
1307
GAIN 3
2232
2222
2212
2202
2192
2182
2171
2161
2151
2141
2131
2121
2111
2101
2090
2080
2070
2060
2050
2040
2029
2019
2009
1999
1989
1978
1968
1958
1948
1938
1927
1917
1907
1897
1886
1876
1866
1856
1845
1835
1825
1815
1804
1794
1784
1774
1763
1753
1743
GAIN 4
2790
2777
2765
2752
2740
2727
2714
2702
2689
2676
2664
2651
2638
2626
2613
2600
2587
2575
2562
2549
2537
2524
2511
2498
2486
2473
2460
2447
2435
2422
2409
2396
2383
2371
2358
2345
2332
2319
2307
2294
2281
2268
2255
2242
2230
2217
2204
2191
2178
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
990
985
980
974
969
964
959
954
949
944
939
934
928
923
918
913
908
903
898
892
887
882
877
872
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Feature Description (continued)
Table 1. VTEMP Temperature Sensor Output Voltage vs Die Temperature Conversion Table (continued)
ANALOG OUTPUT VOLTAGE, VTEMP (mV)(1)
DIE TEMPERATURE (°C)
GAIN 1
867
862
856
851
846
841
836
831
825
820
815
810
805
800
794
789
784
779
774
769
763
758
753
748
743
737
732
727
722
717
711
706
701
696
690
685
680
675
670
664
659
654
649
643
638
633
628
622
617
GAIN 2
1300
1292
1284
1276
1269
1261
1253
1245
1238
1230
1222
1214
1207
1199
1191
1183
1176
1168
1160
1152
1144
1137
1129
1121
1113
1105
1098
1090
1082
1074
1066
1059
1051
1043
1035
1027
1019
1012
1004
996
GAIN 3
1732
1722
1712
1701
1691
1681
1670
1660
1650
1639
1629
1619
1608
1598
1588
1577
1567
1557
1546
1536
1525
1515
1505
1494
1484
1473
1463
1453
1442
1432
1421
1411
1400
1390
1380
1369
1359
1348
1338
1327
1317
1306
1296
1285
1275
1264
1254
1243
1233
GAIN 4
2165
2152
2139
2127
2114
2101
2088
2075
2062
2049
2036
2023
2010
1997
1984
1971
1958
1946
1933
1920
1907
1894
1881
1868
1855
1842
1829
1816
1803
1790
1776
1763
1750
1737
1724
1711
1698
1685
1672
1659
1646
1633
1620
1607
1593
1580
1567
1554
1541
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
988
980
972
964
957
949
941
933
925
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Feature Description (continued)
Table 1. VTEMP Temperature Sensor Output Voltage vs Die Temperature Conversion Table (continued)
ANALOG OUTPUT VOLTAGE, VTEMP (mV)(1)
DIE TEMPERATURE (°C)
GAIN 1
612
607
601
596
591
586
580
575
570
564
559
554
549
543
538
533
527
522
517
512
506
501
496
490
485
480
474
469
464
459
453
448
443
437
432
427
421
416
411
405
400
395
389
384
379
373
368
362
357
GAIN 2
917
909
901
894
886
878
870
862
854
846
838
830
822
814
807
799
791
783
775
767
759
751
743
735
727
719
711
703
695
687
679
671
663
655
647
639
631
623
615
607
599
591
583
575
567
559
551
543
535
GAIN 3
1222
1212
1201
1191
1180
1170
1159
1149
1138
1128
1117
1106
1096
1085
1075
1064
1054
1043
1032
1022
1011
1001
990
GAIN 4
1528
1515
1501
1488
1475
1462
1449
1436
1422
1409
1396
1383
1370
1357
1343
1330
1317
1304
1290
1277
1264
1251
1237
1224
1211
1198
1184
1171
1158
1145
1131
1118
1105
1091
1078
1065
1051
1038
1025
1011
998
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
979
969
958
948
937
926
916
905
894
884
873
862
852
841
831
820
809
798
788
985
777
971
766
958
756
945
745
931
734
918
724
904
713
891
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Feature Description (continued)
Table 1. VTEMP Temperature Sensor Output Voltage vs Die Temperature Conversion Table (continued)
ANALOG OUTPUT VOLTAGE, VTEMP (mV)(1)
DIE TEMPERATURE (°C)
GAIN 1
352
346
341
336
330
325
320
314
309
303
298
293
287
282
277
GAIN 2
527
519
511
503
495
487
479
471
463
455
447
438
430
422
414
GAIN 3
702
691
681
670
659
649
638
627
616
606
595
584
573
562
552
GAIN 4
878
864
851
837
824
811
797
784
770
757
743
730
716
703
690
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
7.3.2 VTEMP vs Die Temperature Approximations
The LM26LV's and LM26LV-Q1's VTEMP analog temperature output is very linear. Table 1 and the equation in
The Second-Order Equation (Parabolic) represent the most accurate typical performance of the VTEMP voltage
output versus temperature.
7.3.2.1 The Second-Order Equation (Parabolic)
The data from Table 1, or Equation 1, when plotted, has an umbrella-shaped parabolic curve. VTEMP is in mV.
GAIN1: VTEMP = 907.9 - 5.132´(TDIE - 30°C) -1.08-3 ´(TDIE - 30°C)
GAIN2 : VTEMP = 1361.4 - 7.701´(TDIE - 30°C) -1.6-3 ´(TDIE - 30°C)
GAIN3 : VTEMP = 1814.6 -10.27 ´(TDIE - 30°C) - 2.12-3 ´(TDIE - 30°C)
GAIN4 : VTEMP = 2268.1-12.838 ´(TDIE - 30°C) - 2.64-3 ´(TDIE - 30°C)
(1)
7.3.2.2 The First-Order Approximation (Linear)
For a quicker approximation, although less accurate than the second-order, over the full operating temperature
range the linear formula below can be used. Using Equation 2, with the constant and slope in the following set of
equations, the best-fit VTEMP versus die temperature performance can be calculated with an approximation error
less than 18 mV. VTEMP is in mV.
GAIN1: VTEMP = 1060 - 5.18 ´ TDIE
GAIN2 : VTEMP = 1590 - 7.77 ´ TDIE
GAIN3 : VTEMP = 2119 -10.36´ TDIE
GAIN4 : VTEMP = 2649 -12.94´ TDIE
(2)
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7.3.2.3 First-Order Approximation (Linear) Over Small Temperature Range
For a linear approximation, a line can easily be calculated over the desired temperature range from Table 1 using
the two-point equation:
æ
ç
è
ö
V2 - V1
V - V =
´(T - T )
1
÷
1
T2 - T1 ø
where
•
•
•
•
V is in mV
T is in °C
T1 and V1 are the coordinates of the lowest temperature
T2 and V2 are the coordinates of the highest temperature
(3)
For example, to determine the equation of a line with GAIN4, with a temperature from 20°C to 50°C, proceed
using Equation 4, Equation 5, and Equation 6:
2010 mV - 2396 mV
50°C - 20°C
æ
ö
V - 2396 mV =
´(T - 20°C)
ç
÷
è
ø
(4)
(5)
(6)
V – 2396 mV = –12.8 mV/°C × (T – 20°C)
V = –12.8 mV/°C × (T – 20°C) + 2396 mV
Using this method of linear approximation, the transfer function can be approximated for one or more
temperature ranges of interest.
7.3.3 OVERTEMP and OVERTEMP Digital Outputs
The OVERTEMP active high, push-pull output and the OVERTEMP active low, open-drain output both assert at
the same time whenever the die temperature reaches the factory preset temperature trip point. They also assert
simultaneously whenever the TRIP_TEST pin is set high. Both outputs deassert when the die temperature goes
below the temperature trip point hysteresis. These two types of digital outputs enable the user the flexibility to
choose the type of output that is most suitable for his design.
Either the OVERTEMP or the OVERTEMP digital output pins can be left open if not used.
7.3.3.1 OVERTEMP Open-Drain Digital Output
The OVERTEMP active low, open-drain digital output, if used, requires a pullup resistor between this pin and
VDD. The following section shows how to determine the pullup resistor value.
7.3.3.1.1 Determining the Pullup Resistor Value
V
DD
i
T
R
Pull-Up
V
OUT
OVERTEMP
Digital Input
i
L
i
sink
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The pullup resistor value is calculated at the condition of maximum total current, IT, through the resistor. The total
current is:
IT = IL + ISINK
where
•
•
IT is the maximum total current through the pullup resistor at VOL
IL is the load current, which is very low for typical digital inputs.
.
(7)
The pullup resistor maximum value can be found by using Equation 8.
VDD(MAX) - VOL
=
RPULLUP
IT
where
•
•
VDD(MAX) is the maximum power supply voltage to be used in the customer's system.
VOUT is the Voltage at the OVERTEMP pin. Use VOL for calculating the pullup resistor.
(8)
7.3.3.1.1.1 Example Calculation
Suppose, for this example, a VDD of 3.3 V ± 0.3 V, a CMOS digital input as a load, a VOL of 0.2 V.
•
•
For VOL of 0.2 V the electrical specification for OVERTEMP shows a maximum ISINK of 385 µA.
Let IL = 1 µA, then IT is about 386 µA maximum. If 35 µA is selected as the current limit then IT for the
calculation becomes 35 µA.
•
•
VDD(MAX) is 3.3 V + 0.3 V = 3.6 V, then calculate the pullup resistor as RPULLUP = (3.6 – 0.2) / 35 µA = 97 kΩ.
Based on this calculated value, select the closest resistor value in the tolerance family used.
In this example, if 5% resistor values are used, then the next closest value is 100 kΩ.
7.3.4 TRIP_TEST Digital Input
The TRIP_TEST pin simply provides a means to test the OVERTEMP and OVERTEMP digital outputs
electronically by causing them to assert, at any operating temperature, as a result of forcing the TRIP_TEST pin
high.
When the TRIP_TEST pin is pulled high the VTEMP pin is at the VTRIP voltage.
If not used, the TRIP_TEST pin may either be left open or grounded.
7.3.5 VTEMP Analog Temperature Sensor Output
The VTEMP push-pull output provides the ability to sink and source significant current. This is beneficial when, for
example, driving dynamic loads like an input stage on an analog-to-digital converter (ADC). In these applications
the source current is required to quickly charge the input capacitor of the ADC. See Application and
Implementation for more discussion of this topic. The LM26LV and LM26LV-Q1 are ideal for applications which
require strong source or sink current.
7.3.5.1 Noise Considerations
The LM26LV's and LM26LV-Q1's supply-noise rejection (the ratio of the AC signal on VTEMP to the AC signal on
VDD) was measured during bench tests. The device's typical attenuation is shown in Typical Characteristics. A
load capacitor on the output can help to filter noise.
For operation in very noisy environments, some bypass capacitance must be present on the supply within
approximately 2 inches of the LM26LV or LM26LV-Q1.
7.3.5.2 Capacitive Loads
The VTEMP Output handles capacitive loading well. In an extremely noisy environment, or when driving a switched
sampling input on an ADC, it may be necessary to add some filtering to minimize noise coupling. Without any
precautions, the VTEMP can drive a capacitive load less than or equal to 1100 pF as shown in Figure 20. For
capacitive loads greater than 1100 pF, a series resistor is required on the output, as shown in Figure 21, to
maintain stable conditions.
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V
DD
V
TEMP
LM26LV
GND
OPTIONAL
BYPASS
CAPACITANCE
C
LOAD
Ç 1100 pF
Figure 20. LM26LV or LM26LV-Q1 No Decoupling Required for Capacitive Loads Less Than 1100 pF.
V
DD
R
S
V
TEMP
LM26LV
GND
OPTIONAL
BYPASS
CAPACITANCE
C
>
LOAD
1100 pF
Figure 21. LM26LV or LM26LV-Q1 With Series Resistor for Capacitive Loading Greater Than 1100 pF
Table 2. Minimum Series Resistence for Capacitive
Loads
CLOAD
1.1 nF to 99 nF
100 nF to 999 nF
1 µF
MINIMUM RS
3 kΩ
1.5 kΩ
800 Ω
7.3.5.3 Voltage Shift
The LM26LV and LM26LV-Q1 are very linear over temperature and supply voltage range. Due to the intrinsic
behavior of an NMOS/PMOS rail-to-rail buffer, a slight shift in the output can occur when the supply voltage is
ramped over the operating range of the device. The location of the shift is determined by the relative levels of
VDD and VTEMP. The shift typically occurs when VDD – VTEMP = 1 V.
This slight shift (a few millivolts) takes place over a wide change (approximately 200 mV) in VDD or VTEMP
.
Because the shift takes place over a wide temperature change of 5°C to 20°C, VTEMP is always monotonic. The
accuracy specifications Accuracy Characteristics already includes this possible shift.
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7.4 Device Functional Modes
The LM26LV and LM26LV-Q1 have several modes of operation as detailed in the following drawings.
V
DD
V
DD
4
4
100k
OVERTEMP
1
5
6
3
OVERTEMP
1
3
6
NC
NC
Asserts when T
NC
> T
TRIP
DIE
Asserts when T
> T
TRIP
DIE
LM26LV
LM26LV
NC
See text.
See text.
5
NC
NC
2
2
GND
GND
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Figure 22. Temperature Switch Using Push-Pull
Output
Figure 23. Temperature Switch Using Open-Drain
Output
V
4
DD
100k
3
TRIP TEST
1
OVERTEMP
6
LM26LV
NC
OVERTEMP
5
2
GND
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Figure 24. TRIP_TEST Digital Output Test Circuit
The TRIP_TEST pin, normally used to check the operation of the OVERTEMP and OVERTEMP pins, may be
used to latch the outputs whenever the temperature exceeds the programmed limit and causes the digital outputs
to assert. As shown in Figure 25, when OVERTEMP goes high the TRIP_TEST input is also pulled high and
causes OVERTEMP output to latch high and the OVERTEMP output to latch low. The latch can be released by
either momentarily pulling the TRIP_TEST pin low (GND), or by toggling the power supply to the device. The
resistor limits the current out of the OVERTEMP output pin.
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Device Functional Modes (continued)
V
DD
100k
4
TRIP TEST
1
5
6
OVERTEMP
LM26LV
NC
RESET
Momentary
OVERTEMP
3
2
GND
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Figure 25. Latch Circuit Using OVERTEMP Output
Alternately, the circuit in Figure 25 the 100 kΩ can be replaced with a short and the momentary reset switch may
be removed. In this configuration, when OVERTEMP goes active high, it drives TRIP_TEST high. THRIP TEST
high causes OVERTEMP to stay high. It is therefore latched. To release the latch, power down, then power up
the LM26LV or LM26LV-Q1. The LM26LV and LM26LV-Q1 always come up in a released condition.
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LM26LV, LM26LV-Q1
www.ti.com
SNIS144G –JULY 2007–REVISED SEPTEMBER 2016
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 ADC Input Considerations
The LM26LV and LM26LV-Q1 have an analog temperature sensor output VTEMP that can be directly connected to
an ADC (Analog-to-Digital Converter) input. Most CMOS ADCs found in microcontrollers and ASICs have a
sampled data comparator input structure. When the ADC charges the sampling cap, it requires instantaneous
charge from the output of the analog source such as the LM26LV or LM26LV-Q1 temperature sensor. This
requirement is easily accommodated by the addition of a capacitor (CFILTER). The size of CFILTER depends on the
size of the sampling capacitor and the sampling frequency. Because not all ADCs have identical input stages, the
charge requirements vary. This general ADC application is shown as an example only.
SAR Analog-to-Digital Converter
Reset
+1.6V to +5.5V
Input
Pin
LM26LV
Sample
R
IN
4
6
5
V
V
DD
TEMP
C
BP
C
PIN
C
C
TRIP
TEST
FILTER
1
2
SAMPLE
OT
3
OT
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Suggested Connection to a Sampling Analog-to-Digital Converter Input Stage
8.2 Typical Application
V
V
Supply
DD
DD
Analog
(+1.6V to +5.5V)
V
ADC Input
TEMP
Example: 2 to 3
Battery Cells
LM26LV
Microcontroller
OVERTEMP
OVERTEMP
TRIP TEST
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 27. Typical Application Schematic
Copyright © 2007–2016, Texas Instruments Incorporated
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Product Folder Links: LM26LV LM26LV-Q1
LM26LV, LM26LV-Q1
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www.ti.com
Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
PARAMETER
EXAMPLE VALUE
Temperature
Accuracy
VDD
0°C to 150°C (LM26LV), –40°C to 85°C for microcontroller
±2.3°C (Gain1, TA = 0°C to 150°C)
3.3 V
8 µA
IDD
8.2.2 Detailed Design Procedure
The LM26LV and LM26LV-Q1 come with a factory preset trip point. See Mechanical, Packaging, and Orderable
Information for available trip point options. Figure 27 shows the device's OVERTEMP output driving a
microcontroller interrupt input to indicate an overtemperature event. In addition to the OVERTEMP output, a
OVERTEMP output is available for use depending on the interrupt polarity of the microcontroller's interrupt pin. A
VTEMP analog output is available to drive the microcontroller ADC input allowing the microcontroller to
determine the sensing temperature of the LM26LV or LM26LV-Q1. The TRIP_TEST input is connected to a
microcontroller output pin allowing the microcontroller to run on the fly electrical conductivity testing. For normal
operation TRIP_TEST must be driven low by the microcontroller output. If no testing is required, the TRIP_TEST
pin may be continuously grounded.
8.2.3 Application Curves
VTEMP Output
(Temp. of Leads)
Trip Point
Trip Point - Hysteresis
OVERTEMP
OVERTEMP
Figure 28. VTEMP Analog Output Temperature Error
Figure 29. Switch Output Function
24
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Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: LM26LV LM26LV-Q1
LM26LV, LM26LV-Q1
www.ti.com
SNIS144G –JULY 2007–REVISED SEPTEMBER 2016
9 Power Supply Recommendations
Bypass capacitors are optional, and maybe required if the supply line is extremely noisy at high frequencies. TI
recommends that a local supply decoupling capacitor be used to reduce noise. For noisy environments, TI
recommends a 100-nF supply decoupling capacitor placed closed across the VDD and GND pins of the LM26LV
or LM26LV-Q1.
9.1 Power Supply Noise Immunity
The LM26LV and LM26LV-Q1 are virtually immune from false triggers on the OVERTEMP and OVERTEMP
digital outputs due to noise on the power supply. Test have been conducted showing that, with the die
temperature within 0.5°C of the temperature trip point, and the severe test of a 3 V***pp square wave "***noise"
signal injected on the VDD line, with VDD from 2 V to 5 V, there were no false triggers.
10 Layout
10.1 Layout Guidelines
10.1.1 Mounting and Temperature Conductivity
The LM26LV or LM26LV-Q1 can be applied easily in the same way as other integrated-circuit temperature
sensors. The devices can be glued or cemented to a surface.
The best thermal conductivity between the device and the PCB is achieved by soldering the DAP of the package
to the thermal pad on the PCB. The temperatures of the lands and traces to the other leads of the LM26LV and
LM26LV-Q1 also affect the temperature reading.
Alternatively, the LM26LV or LM26LV-Q1 can be mounted inside a sealed-end metal tube, and can then be
dipped into a bath or screwed into a threaded hole in a tank. As with any IC, the LM26LV or LM26LV-Q1 and
accompanying wiring and circuits must be kept insulated and dry, to avoid leakage and corrosion. This is
especially true if the circuit may operate at cold temperatures where condensation can occur. If moisture creates
a short circuit from the VTEMP output to ground or VDD, the VTEMP output from the LM26LV or LM26LV-Q1 is not
correct. Printed-circuit coatings are often used to ensure that moisture cannot corrode the leads or circuit traces.
The thermal resistance junction-to-ambient (RθJA) is the parameter used to calculate the rise of a device junction
temperature due to its power dissipation. The equation used to calculate the rise in the LM26LV's and LM26LV-
Q1's die temperature is
TJ = TA + RqJA ´ (VDD ´IQ ) + (VDD - VTEMP )´IL
(
)
where
•
•
•
•
TA is the ambient temperature
IQ is the quiescent current
IL is the load current on the output
VO is the output voltage
(9)
For example, in an application where TA = 30°C, VDD = 5 V, IDD = 9 µA, Gain 4, VTEMP = 2231 mV, and IL = 2 µA,
the junction temperature would be 30.021°C, showing a self-heating error of only 0.021°C. Because the
LM26LV's and LM26LV-Q1's junction temperature is the actual temperature being measured, minimize the load
current that the VTEMP output is required to drive. If OVERTEMP is used with a 100‑k pullup resistor, and is
asserted (low), then for this example the additional contribution is (152°C/W) × (5 V)2 / 100 kΩ = 0.038°C for a
total self-heating error of 0.059°C. Thermal Information shows the thermal resistance of the LM26LV and
LM26LV-Q1.
Copyright © 2007–2016, Texas Instruments Incorporated
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Product Folder Links: LM26LV LM26LV-Q1
LM26LV, LM26LV-Q1
SNIS144G –JULY 2007–REVISED SEPTEMBER 2016
www.ti.com
10.2 Layout Example
Optional thermal VIA to ground plane
and back side of board for thermal
conductivity path
VIA to power plane
VIA to ground plane
R is optional maybe directly
connected to GND if TRIP TEST not used
TRIP TEST
VTEMP
GND
OVERTEMP
VDD
OVERTEMP
0.1 µ F
Figure 30. Typical Layout Example
Optional thermal VIA to ground plane
and back side of board for thermal
conductivity path
VIA to power plane
VIA to ground plane
TRIP TEST
GND
VTEMP
OVERTEMP
VDD
OVERTEMP
0.1 µ F
Figure 31. Latching Layout Example
26
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Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: LM26LV LM26LV-Q1
LM26LV, LM26LV-Q1
www.ti.com
SNIS144G –JULY 2007–REVISED SEPTEMBER 2016
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Absolute Maximum Ratings for Soldering (SNOA549)
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
LM26LV
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
LM26LV-Q1
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2007–2016, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: LM26LV LM26LV-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM26LVCISD-050/NOPB
LM26LVCISD-060/NOPB
LM26LVCISD-065/NOPB
LM26LVCISD-070/NOPB
LM26LVCISD-075/NOPB
LM26LVCISD-080/NOPB
LM26LVCISD-085/NOPB
LM26LVCISD-090/NOPB
LM26LVCISD-095/NOPB
LM26LVCISD-100/NOPB
LM26LVCISD-105/NOPB
LM26LVCISD-110/NOPB
LM26LVCISD-115/NOPB
LM26LVCISD-120/NOPB
LM26LVCISD-125/NOPB
LM26LVCISD-135/NOPB
LM26LVCISD-140/NOPB
LM26LVCISD-145/NOPB
LM26LVCISD-150/NOPB
LM26LVCISDX-060/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
4500 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
050
060
065
070
075
080
085
090
095
100
105
110
115
120
125
135
140
145
150
060
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
SN
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM26LVCISDX-120/NOPB
LM26LVQISD-130/NOPB
LM26LVQISDX-130/NOPB
LM26LVQISDX-135/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
NGF
NGF
NGF
NGF
6
6
6
6
4500 RoHS & Green
1000 RoHS & Green
4500 RoHS & Green
4500 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 150
-40 to 150
-40 to 150
-40 to 150
120
Q30
Q30
Q35
SN
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM26LV, LM26LV-Q1 :
Catalog: LM26LV
•
Automotive: LM26LV-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM26LVCISD-050/NOPB WSON
LM26LVCISD-060/NOPB WSON
LM26LVCISD-065/NOPB WSON
LM26LVCISD-070/NOPB WSON
LM26LVCISD-075/NOPB WSON
LM26LVCISD-080/NOPB WSON
LM26LVCISD-085/NOPB WSON
LM26LVCISD-090/NOPB WSON
LM26LVCISD-095/NOPB WSON
LM26LVCISD-100/NOPB WSON
LM26LVCISD-105/NOPB WSON
LM26LVCISD-110/NOPB WSON
LM26LVCISD-115/NOPB WSON
LM26LVCISD-120/NOPB WSON
LM26LVCISD-125/NOPB WSON
LM26LVCISD-135/NOPB WSON
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM26LVCISD-140/NOPB WSON
LM26LVCISD-145/NOPB WSON
LM26LVCISD-150/NOPB WSON
LM26LVCISDX-060/NOPB WSON
LM26LVCISDX-120/NOPB WSON
LM26LVQISD-130/NOPB WSON
NGF
NGF
NGF
NGF
NGF
NGF
NGF
6
6
6
6
6
6
6
1000
1000
1000
4500
4500
1000
4500
178.0
178.0
178.0
330.0
330.0
178.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.5
2.5
2.5
2.5
2.5
2.5
2.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
LM26LVQISDX-130/
NOPB
WSON
LM26LVQISDX-135/
NOPB
WSON
NGF
6
4500
330.0
12.4
2.8
2.5
1.0
8.0
12.0
Q1
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM26LVCISD-050/NOPB
LM26LVCISD-060/NOPB
LM26LVCISD-065/NOPB
LM26LVCISD-070/NOPB
LM26LVCISD-075/NOPB
LM26LVCISD-080/NOPB
LM26LVCISD-085/NOPB
LM26LVCISD-090/NOPB
LM26LVCISD-095/NOPB
LM26LVCISD-100/NOPB
LM26LVCISD-105/NOPB
LM26LVCISD-110/NOPB
LM26LVCISD-115/NOPB
LM26LVCISD-120/NOPB
LM26LVCISD-125/NOPB
LM26LVCISD-135/NOPB
LM26LVCISD-140/NOPB
LM26LVCISD-145/NOPB
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
NGF
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM26LVCISD-150/NOPB
LM26LVCISDX-060/NOPB
LM26LVCISDX-120/NOPB
LM26LVQISD-130/NOPB
LM26LVQISDX-130/NOPB
LM26LVQISDX-135/NOPB
WSON
WSON
WSON
WSON
WSON
WSON
NGF
NGF
NGF
NGF
NGF
NGF
6
6
6
6
6
6
1000
4500
4500
1000
4500
4500
210.0
367.0
367.0
210.0
367.0
367.0
185.0
367.0
367.0
185.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 4
MECHANICAL DATA
NGF0006A
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