LM2744MTCX/NOPB [TI]
1-16V, Voltage Mode Synchronous Buck Controller with External Reference 14-TSSOP -40 to 125;
| 型号： | LM2744MTCX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-16V, Voltage Mode Synchronous Buck Controller with External Reference 14-TSSOP -40 to 125 开关 光电二极管 |
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LM2744
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SNVS292F –SEPTEMBER 2004–REVISED MARCH 2013
LM2744 Low Voltage N-Channel MOSFET Synchronous Buck Regulator Controller with
External Reference
Check for Samples: LM2744
1
FEATURES
DESCRIPTION
The LM2744 is a high-speed synchronous buck
regulator controller with an externally adjustable
reference voltage (between 0.5V to 1.5V). It can
provide simple down conversion to output voltages as
low as 0.5V. Though the control sections of the IC
are rated for 3 to 6V, the driver sections are designed
to accept input supply rails as high as 16V. The use
of adaptive non-overlapping MOSFET gate drivers
helps avoid potential shoot-through problems while
maintaining high efficiency. The IC is designed for the
more cost-effective option of driving only N-channel
MOSFETs in both the high-side and low-side
positions. It senses the low-side switch voltage drop
for providing a simple, adjustable current limit.
2
•
Power Stage Input Voltage from 1V to 16V
Control stage Input Voltage from 3V to 6V
Output Voltage Adjustable Down to 0.5V
Power Good Flag and Shutdown
•
•
•
•
Output Overvoltage and Undervoltage
Detection
•
•
•
•
External Reference Voltage 0.5V to 1.5V
Low-side Adjustable Current Sensing
Adjustable Soft-Start
Tracking and Sequencing with Shutdown and
Soft Start Pins
•
•
Switching Frequency from 50 kHz to 1 MHz
14-Pin TSSOP Package
The fixed-frequency voltage-mode PWM control
architecture is adjustable from 50 kHz to 1 MHz with
one external resistor. This wide range of switching
frequency gives the power supply designer the
flexibility to make better tradeoffs between
component size, cost and efficiency.
APPLICATIONS
•
•
•
•
•
•
3.3V Buck Regulation
Cable Modem, DSL and ADSL
Laser Jet and Ink Jet Printers
Low Voltage Power Modules
DSP, ASIC, Core and I/O
Features include soft-start, input undervoltage lockout
(UVLO) and Power Good (based on both
undervoltage and overvoltage detection). In addition,
the shutdown pin of the IC can be used for providing
startup delay, and the soft-start pin can be used for
implementing precise tracking, for the purpose of
sequencing with respect to an external rail.
DDR Memory Termination Supply
TYPICAL APPLICATION
V
= 3.3V
V
IN
= 3.3V
CC
C
BOOT
D1
R
Q1
PULL-UP
R
C
C
1,2
CC
IN
V
HG
CC
SD
BOOT
R
CS
L1
CC
V
OUT
= 1.2V@4A
I
PWGD
SEN
LM2744
FREQ
LG
R
C
FADJ
+
R
FB2
SGND
PGND
FB
SS/TRACK
C 1,2
O
V
REF
SS
EAO
R
C2
C
C3
R
FB1
C
C1
External
Reference
0.5 to 1.5V
C
C2
R
C1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LM2744
SNVS292F –SEPTEMBER 2004–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CONNECTION DIAGRAM
1
2
3
4
5
6
7
14
13
12
11
BOOT
LG
HG
REF
SD
V
PGND
SGND
FREQ
10
9
V
FB
SS/TRACK
EAO
CC
PWGD
8
I
SEN
14-Lead TSSOP
θJA = 155°C/W
See PW Package
PIN DESCRIPTIONS
Bootstrap pin. This is the supply rail for the high-side gate driver. When the high-side MOSFET turns on, the
voltage on this pin should be at least one gate threshold above the regulator input voltage VIN to properly turn on
the MOSFET. See MOSFET Gate Drivers in the Application Information section for more details on how to select
MOSFETs.
BOOT (Pin 1) -
Low-gate drive pin. This is the gate drive for the low-side N-channel MOSFET. This signal is interlocked with the
high-side gate drive HG (Pin 14), so as to avoid shoot-through.
LG (Pin 2) -
Power ground. This is also the ground for the low-side MOSFET driver. This pin must be connected on the PCB
ground plane, which is usually also the system ground.
PGND (Pin 3) -
SGND (Pin 4) -
Signal ground. It should be connected appropriately to the ground plane with due regard to good layout practices in
switching power regulator circuits.
Supply rail for the control sections of the IC.
VCC (Pin 5)
Power Good pin. This is an open drain output, which is typically meant to be connected to VCC or any other low
voltage source through a pull-up resistor. The voltage on this pin is thus pulled low under output fault conditions
(undervoltage or overvoltage) and also under UVLO.
PWGD (Pin 6) -
Current limit threshold setting pin. This sources a fixed 40 µA current. A resistor of appropriate value should be
connected between this pin and the drain of the low-side MOSFET (switch node).
ISEN (Pin 7) -
Output of the error amplifier. The voltage level on this pin is compared with an internally generated ramp signal to
determine the duty cycle. This pin is necessary for compensating the control loop
EAO (Pin 8) - .
SS/TRACK (Pin 9) -
Soft-start and tracking pin. This pin is internally connected to the non-inverting input of the error amplifier during
soft-start, and in fact any time the SS/TRACK pin voltage happens to be below the internal reference voltage. For
the basic soft-start function, a capacitor of minimum value 1nF is connected from this pin to ground. To track the
rising ramp of another power supply’s output, connect a resistor divider from the output of that supply to this pin as
described in Application Information
Feedback pin. This is the inverting input of the error amplifier, which is used for sensing the output voltage and
compensating the control loop.
FB (Pin 10) -
Frequency adjust pin. The switching frequency is set by connecting a resistor of suitable value between this pin and
ground. The equation for calculating the exact value is provided in Application Information, but some typical values
(rounded up to the nearest standard values) are 324 kΩ for 100 kHz, 97.6 kΩ for 300 kHz, 56.2 kΩ for 500 kHz,
24.9 kΩ for 1 MHz.
FREQ (Pin 11) -
IC shutdown pin. Pull this pin to VCC to ensure the IC is enabled. Connect to ground to disable the IC. Under
shutdown, both high-side and low-side drives are off. This pin also features a precision threshold for power supply
sequencing purposes, as well as a low threshold to ensure minimal quiescent current.
SD (Pin 12) -
External reference. This goes to the non-inverting input of the error amplifier. Any desired reference voltage
between 0.5V to 1.5V can be connected to this pin (with appropriate filtering if necessary).
VREF (Pin 13) -
HG (Pin 14) -
High-gate drive pin. This is the gate drive for the high-side N-channel MOSFET. This signal is interlocked with LG
(Pin 2) to avoid shoot-through.
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
ABSOLUTE MAXIMUM RATINGS
VCC
-0.3 to 7V
-0.3 to 21V
-0.3 to VCC + 0.3V
150°C
BOOT Voltage
All other pins
Junction Temperature
Storage Temperature
−65°C to 150°C
260°C
Lead Temperature (soldering, 10sec)
Infrared or Convection (20sec)
Soldering Information
ESD Rating(3)
235°C
2 kV
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for
which the device operates correctly. Operating Ratings do not imply ensured performance limits.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The human body model is a 100pF capacitor discharged through a 1.5k resistor into each pin.
RECOMMENDED OPERATING CONDITIIONS
Supply Voltage Range (VCC
)
3V to 6V
−40°C to +125°C
155°C/W
Junction Temperature Range (TJ)
Thermal Resistance (θJA
)
Voltage on FB and VREF
0.5V to 1.5V
ELECTRICAL CHARACTERISTICS(1)
VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= 25°C. Limits appearing in
boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are specified by design,
test, or statistical analysis.
Symbol
Parameter
UVLO Thresholds
Conditions
Min
Typ
Max
Units
VON
Rising
Falling
2.76
2.42
V
VCC = 3.3V, VSD = 3.3V
Fsw = 600kHz
1.0
1.0
1.5
1.7
2.1
Operating VCC Current
mA
IQ_VCC
VCC = 5V, VSD = 3.3V
Fsw = 600kHz
2.1
25
Shutdown VCC Current
VCC = 3.3V, VSD = 0V
VFB Rising
1
6
µA
µs
µs
µA
tPWGD1
tPWGD2
ISS-ON
ISS-OC
PWGD Pin Response Time
PWGD Pin Response Time
SS Pin Source Current
VFB Falling
6
VSS = 0V
5
10
15
SS Pin Sink Current During Over
Current
VSS = 2.5V
90
40
µA
µA
ISEN-TH
ISEN Pin Source Current Trip Point
20
-8
60
8
ERROR AMPLIFIER
VOS
GBW
G
Error Amplifier Input Offset Voltage
1
9
mV
MHz
dB
Error Amplifier Unity Gain Bandwidth
Error Amplifier DC Gain
106
3.2
SR
Error Amplifier Slew Rate
V/µs
IEAO
EAO Pin Current Sourcing and Sinking
Capability
VEAO = 1.5, FB = 0.55V
VEAO = 1.5, FB = 0.65V
2.6
9.2
mA
VEA
Error Amplifier Output Voltage
Minimum
Maximum
1
2
V
V
(1) The power MOSFETs can run on a separate 1V to 16V rail (Input voltage, VIN). Practical lower limit of VIN depends on selection of the
external MOSFET.
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ELECTRICAL CHARACTERISTICS(1) (continued)
VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= 25°C. Limits appearing in
boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are specified by design,
test, or statistical analysis.
Symbol
IVREF
Parameter
Current into VREF Pin
Conditions
1.5V ≥ VREF ≥ 0.5V
Min
Typ
Max
Units
50
nA
GATE DRIVE
IQ-BOOT
BOOT Pin Quiescent Current
VBOOT = 12V, VSD = 0
18
3
90
µA
RHG_UP
High-Side MOSFET Driver Pull-Up ON
resistance
VBOOT - VSW = 9.5V at 350mA
Ω
RHG_DN
RLG_UP
High-Side MOSFET Driver Pull-Down
ON resistance
VBOOT - VSW = 4.5V at 350mA
VBOOT - VSW = 9.5V at 350mA
VBOOT - VSW = 4.5V at 350mA
2
3
2
Ω
Ω
Ω
Low-Side MOSFET Driver Pull-Up ON
resistance
RLG_DN
Low-Side MOSFET Driver Pull-Down
ON resistance
OSCILLATOR
RFADJ = 702.1 kΩ
RFADJ = 98.74 kΩ
RFADJ = 45.74 kΩ
RFADJ = 24.91 kΩ
50
300
600
1000
FSW
PWM Frequency
kHz
%
475
725
D
Max High-Side Duty Cycle
FSW = 300kHz
FSW = 600kHz
FSW = 1MHz
80
76
73
LOGIC INPUTS AND OUTPUTS
V STBY-IH Standby High Trip Point
VFB = 0.575V, VBOOT = 3.3V, VSD
Rising
1.1
1.3
V
V
V STBY-IL
Standby Low Trip Point
VFB = 0.575V, VBOOT = 3.3V, VSD
Falling
0.232
V SD-IH
V SD-IL
SD Pin Logic High Trip Point
SD Pin Logic Low Trip Point
PWGD Pin Trip Points
VSD Rising
V
V
V
V
V
V
VSD Falling
0.8
VPWGD-TH-LO
FB Falling, VREF = 0.5V
FB Falling, VREF = 1.5V
FB Rising, VREF = 0.5V
FB Rising, VREF = 1.5V
0.3262
0.993
0.551
1.6692
0.347
1.045
0.586
1.757
0.3678
1.097
VPWGD-TH-HI
PWGD Pin Trip Points
PWGD Hysteresis
0.621
1.8448
VPWGD-HYS
FB Falling
FB Rising
60
90
mV
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SNVS292F –SEPTEMBER 2004–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency (VOUT = 1.2V, VREF = 0.6V)
VCC = 3.3V, FSW = 300kHz
Efficiency (VOUT = 2.5V, VREF = 0.8V)
VCC = 3.3V, FSW = 300kHz
100
90
80
70
60
50
100
V
IN
= 3.3V
90
80
70
60
50
V
= 12V
IN
VIN = 3.3V
VIN = 5V
V
= 5V
IN
40
30
20
VIN = 12V
40
30
20
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
OUTPUT CURRENT (A)
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
OUTPUT CURRENT (A)
Figure 1.
Figure 2.
Efficiency (VOUT = 3.3V, VREF = 1.2V)
VCC = 5V, FSW = 300kHz
100
Output Voltage vs
Temperature
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
V
= 0.8V
90
80
70
60
50
REF
V
IN
= 5V
V
= 0.6V
REF
V
= 12V
IN
V
= 1.2V
REF
40
30
20
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
50
65 80 95 110 125
-40 -25 -10
5
20 35
TEMPERATURE (oC)
OUTPUT CURRENT (A)
Figure 3.
Figure 4.
VCC Operating Current plus BOOT Current vs Frequency
FDS6898A FET (TA = 25°C)
BOOT Pin Current vs Temperature for BOOT Voltage = 3.3V
FSW = 300kHz, FDS6898A FET, No-Load
10
25
9.9
9.8
9.7
19
13
9.6
9.5
6
0
9.4
9.3
50
65 80 95 110125
-40 -25 -10
5
20 35
0.05
0.25
0.45
0.65
0.85
1.05
FREQUENCY (MHz)
TEMPERATURE (oC)
Figure 5.
Figure 6.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
BOOT Pin Current vs Temperature for BOOT Voltage = 5V
BOOT Pin Current vs Temperature for BOOT Voltage = 12V
FSW = 300kHz, FDS6898A FET, No-Load
FSW = 300kHz, FDS6898A FET, No-Load
24.9
6.7
24.8
24.7
24.6
6.6
6.5
6.4
24.5
24.4
24.3
24.2
6.3
6.2
6.1
6
24.1
24
5.9
-40 -25 -10
23.9
50
65 80 95 110125
5
20 35
50
65 80 95 110125
-40 -25 -10
5
20 35
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 7.
Figure 8.
Frequency vs Temperature
(FSW set to 600kHz nominal)
Output Voltage vs Output Current
(VOUT set to 1.2V nominal)
1.210
640
620
1.209
1.208
1.207
1.206
1.205
1.204
1.203
1.202
1.201
1.200
600
580
560
540
520
45
-55 -35 -15
5
25
65 85 105 125
0
0.4 0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
4
TEMPERATURE (oC)
OUTPUT CURRENT (A)
Figure 9.
Figure 10.
Switch Waveforms (HG Rising)
VCC = 3.3V, VIN = 5V, VREF = 0.6V, VOUT = 1.2V
IOUT = 4A, CSS = 12nF, FSW = 300kHz
Switch Waveforms (HG Falling)
VCC = 3.3V, VIN = 5V, VREF = 0.6V, VOUT = 1.2V,
IOUT = 4A, CSS = 12nF, FSW = 300kHz
1V/div
HG
LG
2V/div
1V/div
2V/div
HG
SW
LG
SW
5V/div
5V/div
100 ns/DIV
100 ns/DIV
Figure 11.
Figure 12.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Start-Up (No-Load)
VCC = 3.3V, VIN = 5V, VREF = 0.6V, VOUT = 1.2V
CSS = 12nF, FSW = 300kHz
Start-Up (Full-Load)
VCC = 3.3V, VIN = 5V, VREF = 0.6V, VOUT = 1.2V
IOUT = 4A, CSS = 12nF, FSW = 300kHz
1V/div
1V/div
1V/div
V
1V/div
1A/div
OUT
V
V
OUT
V
CSS
CSS
1A/div
I
I
IN
IN
2V/div
2V/div
PWGD
PWGD
1 ms/DIV
1 ms/DIV
Figure 13.
Figure 14.
Shutdown (Full-Load)
VCC = 3.3V, VIN = 5V, VREF = 0.6V, VOUT = 1.2V
IOUT = 4A, CSS = 12nF, FSW = 300kHz
Load Transient Response (IOUT = 0A to 4A)
VCC = 3.3V, VIN = 5V, VREF = 0.6V, VOUT = 1.2V
CSS = 12nF, FSW = 300kHz
V
OUT
1V/div
1V/div
V
OUT
V
CSS
50 mV/div
1A/div
I
IN
2A/div
PWGD
I
OUT
2V/div
1 ms/DIV
40 ms/DIV
Figure 15.
Figure 16.
Load Transient Response (IOUT = 4A to 0A)
VCC = 3.3V, VIN = 5V, VREF = 0.6V, VOUT = 1.2V
CSS = 12nF, FSW = 300kHz
Load Transient Response
VCC = 3.3V, VIN = 5V, VREF = 0.6V, VOUT = 1.2V
CSS = 12nF, FSW = 300kHz
VOUT
V
OUT
20 mV/div
20mV/div
I
OUT
2A/div
2A/div
IOUT
40 ms/DIV
100 ms/DIV
Figure 17.
Figure 18.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Line Transient Response (VIN = 3V to 7V)
VCC = 3.3V, VREF = 0.6V, VOUT = 1.2V
IOUT = 2A, FSW = 300kHz
Line Transient Response (VIN = 7V to 3V)
VCC = 3.3V, VREF = 0.6V, VOUT = 1.2V
IOUT = 2A, FSW = 300kHz
100mV/div
100 mV/div
VOUT
VOUT
5V/div
VIN
5V/div
VIN
100 ms/DIV
100 ms/DIV
Figure 19.
Figure 20.
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SNVS292F –SEPTEMBER 2004–REVISED MARCH 2013
BLOCK DIAGRAM
V
CC
PGND
SD
SGND
FREQ
CLOCK &
RAMP
UVLO
SHUT DOWN
LOGIC
BOOT
10 ms
DELAY
HG
PWGD
SSDONE
SYNCHRONOUS
DRIVER LOGIC
OV
UV
LG
REF x 1.18
REF x 0.7
10 mA
SSDONE
SS/TRACK
2V
0.85V
PWM LOGIC
PWM
40 mA
Soft-Start
Comparator
+ Logic
REF
-
I
+
-
SEN
90 mA
EA
ILIM
+
V
REF
FB
EAO
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APPLICATION INFORMATION
THEORY OF OPERATION
The LM2744 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is
designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high
efficiency buck converters. It has output shutdown (SD), input undervoltage lock-out (UVLO) mode and power
good (PWGD) flag (based on overvoltage and undervoltage detection). The overvoltage and undervoltage
signals are OR-gated to drive the power good signal and provide a logic signal to the system if the output voltage
goes out of regulation. Current limit is achieved by sensing the voltage VDS across the low side MOSFET.
START UP/SOFT-START
When VCC exceeds 2.76V and the shutdown pin (SD) sees a logic high, the soft-start period begins. Then an
internal, fixed 10 µA source begins charging the soft-start capacitor. During soft-start the voltage on the soft-start
capacitor CSS is connected internally to the non-inverting input of the error amplifier. The soft-start period lasts
until the voltage on the soft-start capacitor exceeds the LM2744 reference voltage. At this point the reference
voltage takes over at the non-inverting error amplifier input. The capacitance of CSS determines the length of the
soft-start period, and can be approximated by:
CSS = tSS / (100 x VREF
)
where
•
•
CSS is in µF
tSS is in ms
(1)
During soft-start the Power Good flag is forced low and it is released when the FB pin voltage reaches 70% of
VREF. At this point the chip enters normal operation mode, and the output overvoltage and undervoltage
monitoring starts.
NORMAL OPERATION
While in normal operation mode, the LM2744 regulates the output voltage by controlling the duty cycle of the
high-side and low-side MOSFETs (see Typical Application Circuit).The equation governing output voltage is:
+
RFB1 RFB2
VOUT
=
VREF
RFB1
(2)
The PWM frequency is adjustable between 50 kHz and 1 MHz and is set by an external resistor, RFADJ, between
the FREQ pin and ground. The resistance needed for a desired frequency is approximately:
107
FSW
1012
+ 0.24
RFADJ = -5.93 + 3.06
F2
SW
where
•
•
FSW is in Hz
RFADJ is in kΩ
(3)
TRACKING A VOLTAGE LEVEL
The LM2744 can track the output of a master power supply during soft-start by connecting a resistor divider to
the SS/TRACK pin. In this way, the output voltage slew rate of the LM2744 will be controlled by the master
supply for loads that require precise sequencing. Because the output of the master supply is divided down, in
order to track properly the output voltage of the LM2744 must be lower than the voltage of the master supply.
When the tracking function is used no soft-start capacitor should be connected to the SS/TRACK pin. However in
all other cases, a CSS value of at least 1nF between the soft-start pin and ground should be used.
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Master Power
Supply
V
= 5V
OUT1
R
T2
1 kW
V
OUT2
= 1.8V
SS/TRACK
LM2744
V
= 0.65V
SS
R
R
FB2
10 kW
T1
FB
150W
V
FB
R
FB1
5 kW
Figure 21. Tracking Circuit
One way to use the tracking feature is to design the tracking resistor divider so that the master supply’s output
voltage (VOUT1) and the LM2744’s output voltage (represented symbolically in Figure 21 as VOUT2, i.e. without
explicitly showing the power components) both rise together and reach their target values at the same time. For
this case, the equation governing the values of the tracking divider resistors RT1 and RT2 is:
RT1
VREF + 0.05 =
RT1 + RT2
(4)
The current through RT1 should be about 3-4 mA for precise tracking. The final voltage of the SS/TRACK pin
should be set slightly higher than the reference voltage (say about 50mV higher as in the above equation). If the
master supply voltage was 5V and the LM2744 output voltage was 1.8V, for example, then the value of RT1
needed to give the two supplies identical soft-start times would be 150Ω if VREF was set to 0.6V. A timing
diagram for the equal soft-start time case is shown in Figure 22.
5V
VOUT1
1.8V
VOUT2
Figure 22. Tracking with Equal Soft-Start Time
TRACKING A VOLTAGE SLEW RATE
The tracking feature can alternatively be used not to make both rails reach regulation at the same time but rather
to have similar rise rates (in terms of output dV/dt). This method ensures that the output voltage of the LM2744
always reaches regulation before the output voltage of the master supply. In this case, the tracking resistors can
be determined based on the following equation:
RT1
VOUT2
=
VOUT1
RT1 + RT2
(5)
For the example case of VOUT1 = 5V and VOUT2 = 1.8V, with RT1 set to 150Ω as before, RT2 is calculated from the
above equation to be 267Ω. A timing diagram for the case of equal slew rates is shown in Figure 23.
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5V
1.8V
VOUT1
1.8V
VOUT2
Figure 23. Tracking with Equal Slew Rates
SEQUENCING
The start up/soft-start of the LM2744 can be delayed for the purpose of sequencing by connecting a resistor
divider from the output of a master power supply to the SD pin, as shown in Figure 24.
Master Power
Supply
V
OUT1
V
R
R
OUT2
S2
S1
SD
LM2744
R
FB2
FB
V
FB
R
FB1
Figure 24. Sequencing Circuit
A desired delay time tDELAY between the startup of the master supply output voltage and the LM2744 output
voltage can be set based on the SD pin low-to-high threshold VSD-IH and the slew rate of the voltage at the SD
pin, SRSD
:
tDELAY = VSD-IH / SRSD
(6)
Note again, that in Figure 24, the LM2744’s output voltage has been represented symbolically as VOUT2, i.e.
without explicitly showing the power components.
VSD-IH is typically 1.08V and SRSD is the slew rate of the SD pin voltage. The values of the sequencing divider
resistors RS1 and RS2 set the SRSD based on the master supply output voltage slew rate, SROUT1, using the
following equation:
RS1
SRSD = SROUT1
RS1 + RS2
(7)
For example, if the master supply output voltage slew rate was 1V/ms and the desired delay time between the
startup of the master supply and LM2744 output voltage was 5ms, then the desired SD pin slew rate would be
(1.08V/5ms) = 0.216V/ms. Due to the internal impedance of the SD pin, the maximum recommended value for
RS2 is 1kΩ. To achieve the desired slew rate, RS2 would then be 274Ω. A timing diagram for this example is
shown in Figure 25.
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5V
V
SD-IH
1.08V
V
OUT1
1.8V
V
OUT2
t = 5 ms
Figure 25. Delay for Sequencing
SD PIN IMPEDANCE
When connecting a resistor divider to the SD pin of the LM2744 some care has to be taken. Once the SD voltage
goes above VSD-IH, a 17 µA pull-up current is activated as shown in Figure 26. This current is used to create the
internal hysteresis (≊170mV); however, high external impedances will affect the SD pin logic thresholds as well.
The external impedance used for the sequencing divider network should preferably be a small fraction of the
impedance of the SD pin for good performance (around 1kΩ).
17 mA
8 mA
Bias Enable
SD
10k
Soft-Start Enable
+
-
1.25V
Figure 26. SD Pin Logic
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MOSFET GATE DRIVERS
The LM2744 has two gate drivers designed for driving N-channel MOSFETs in a synchronous mode. Note that
unlike most other synchronous controllers, the bootstrap capacitor of the LM2744 provides power not only to the
driver of the upper MOSFET, but the lower MOSFET driver too (both drivers are ground referenced, i.e. no
floating driver). To fully turn the top MOSFET on, the BOOT voltage must be at least one gate threshold greater
than VIN when the high-side drive goes high. This bootstrap voltage is usually supplied from a local charge pump
structure. But looking at the Typical Application schematic, this also means that the difference voltage VCC - VD1
,
which is the voltage the bootstrap capacitor charges up to, must be always greater than the maximum tolerance
limit of the threshold voltage of the upper MOSFET. Here VD1 is the forward voltage drop across the bootstrap
diode D1. This therefore may place restrictions on the minimum input voltage and/or type of MOSFET used.
The most basic charge bootstrap pump circuit can be built using one Schottky diode and a small capacitor, as
shown in Figure 27. The capacitor CBOOT serves to maintain enough voltage between the top MOSFET gate and
source to control the device even when the top MOSFET is on and its source has risen up to the input voltage
level. The charge pump circuitry is fed from VCC, which can operate over a range from 3.0V to 6.0V. Using this
basic method the voltage applied to the gates of both high-side and low-side MOSFETs is VCC - VD. This method
works well when VCC is 5V±10%, because the gate drives will get at least 4.0V of drive voltage during the worst
case of VCC-MIN = 4.5V and VD-MAX = 0.5V. Logic level MOSFETs generally specify their on-resistance at VGS
=
4.5V. When VCC = 3.3V±10%, the gate drive at worst case could go as low as 2.5V. Logic level MOSFETs are
not ensured to turn on, or may have much higher on-resistance at 2.5V. Sub-logic level MOSFETs, usually
specified at VGS = 2.5V, will work, but are more expensive, and tend to have higher on-resistance. The circuit in
Figure 27 works well for input voltages ranging from 1V up to 16V and VCC = 5V ±10%, because the drive
voltage depends only on VCC
.
LM2744
BOOT
D1
V
CC
+
C
BOOT
V
IN
O
HG
+
+
V
LG
Figure 27. Basic Charge Pump (Bootstrap)
Note that the LM2744 can be paired with a low cost linear regulator like the LP8340 to run from a single input rail
between 6.0 and 16V. The 5V output of the linear regulator powers both the VCC and the bootstrap circuit,
providing efficient drive for logic level MOSFETs. An example of this circuit is shown in Figure 28.
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LM2744
V
CC
5V
LP8340
D1
BOOT
C
BOOT
V
IN
+
HG
LG
V
O
+
Figure 28. LP8340 Feeding Basic Charge Pump
Figure 29 shows a second possibility for bootstrapping the MOSFET drives using a doubler. This circuit provides
an equal voltage drive of VCC - 3VD + VIN to both the high-side and low-side MOSFET drives. This method should
only be used in circuits that use 3.3V for both VCC and VIN. Even with VIN = VCC = 3.0V (10% lower tolerance on
3.3V) and VD = 0.5V both high-side and low-side gates will have at least 4.5V of drive. The power dissipation of
the gate drive circuitry is directly proportional to gate drive voltage, hence the thermal limits of the LM2744 IC will
quickly be reached if this circuit is used with VCC or VIN voltages over 5V.
LM2744
BOOT
V
D1
D3
D2
CC
V
IN
HG
+
+
V
O
LG
Figure 29. Charge Pump with Added Gate Drive
All the gate drive circuits shown in the above figures typically use 100nF ceramic capacitors in the bootstrap
locations.
POWER GOOD SIGNAL
The Power Good signal is an OR-gated flag which takes into account both output overvoltage and undervoltage
conditions. If the feedback pin (FB) voltage is 18% above its nominal value or falls 28% below that value the
Power Good flag goes low. The Power Good flag can be used to signal other circuits that the output voltage has
fallen out of regulation, however the switching of the LM2744 continues regardless of the state of the Power
Good signal. The Power Good flag will return to logic high whenever the feedback pin voltage is between 72%
and 118% of VREF
.
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UVLO
The 2.76V turn-on threshold on VCC has a built in hysteresis of about 300mV. If VCC drops below 2.42V, the chip
enters UVLO mode. UVLO consists of turning off the top and bottom MOSFETS and remaining in that condition
until VCC rises above 2.76V. As with shutdown, the soft-start capacitor is discharged through an internal
MOSFET, ensuring that the next start-up will be controlled by the soft-start circuitry.
CURRENT LIMIT
Current limit is realized by sensing the voltage across the low-side MOSFET while it is on. The RDSON of the
MOSFET is a known value; hence the current through the MOSFET can be determined as:
VDS = IOUT * RDSON
(8)
The current through the low-side MOSFET while it is on is also the falling portion of the inductor current. The
current limit threshold is determined by an external resistor, RCS, connected between the switching node and the
ISEN pin. A constant current of 40 µA is forced through RCS, causing a fixed voltage drop. This fixed voltage is
compared against VDS and if the latter is higher, the current limit of the chip has been reached. RCS can be found
by using the following equation:
RCS = RDSON x ILIM / 40 µA
(9)
For example, a conservative 15A current limit in a 10A design with a minimum RDSON of 10mΩ would require a
3.74kΩ resistor. Because current sensing is done across the low-side MOSFET, no minimum high-side on-time is
necessary. The LM2744 enters current limit mode if the inductor current exceeds the current limit threshold at the
point where the high-side MOSFET turns off and the low-side MOSFET turns on. (The point of peak inductor
current, see Figure 30). Note that in normal operation mode the high-side MOSFET always turns on at the
beginning of a clock cycle. In current limit mode, by contrast, the high-side MOSFET on-pulse is skipped. This
causes inductor current to fall. Unlike a normal operation switching cycle, however, in a current limit mode
switching cycle the high-side MOSFET will turn on as soon as inductor current has fallen to the current limit
threshold. The LM2744 will continue to skip high-side MOSFET pulses until the inductor current peak is below
the current limit threshold, at which point the system resumes normal operation.
Normal Operation
Current Limit
ILIM
IL
D
Figure 30. Current Limit Threshold
Unlike a high-side MOSFET current sensing scheme, which limits the peaks of inductor current, low-side current
sensing is only allowed to limit the current during the converter off-time, when inductor current is falling.
Therefore in a typical current limit plot the valleys are normally well defined, but the peaks are variable, according
to the duty cycle. The PWM error amplifier and comparator control the off-pulse of the high-side MOSFET, even
during current limit mode, meaning that peak inductor current can exceed the current limit threshold. Assuming
that the output inductor does not saturate, the maximum peak inductor current during current limit mode can be
calculated with the following equation:
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VIN - VO
L
IPK-CL = ILIM + (TOSC - 200ns)
where
•
TOSC is the inverse of switching frequency FSW
(10)
The 200ns term represents the minimum off-time of the duty cycle, which ensures enough time for correct
operation of the current sensing circuitry.
In order to minimize the time period in which peak inductor current exceeds the current limit threshold, the IC
also discharges the soft-start capacitor through a fixed 90 µA sink. The output of the LM2744 internal error
amplifier is limited by the voltage on the soft-start capacitor. Hence, discharging the soft-start capacitor reduces
the maximum duty cycle D of the controller. During severe current limit this reduction in duty cycle will reduce the
output voltage if the current limit conditions last for an extended time. Output inductor current will be reduced in
turn to a flat level equal to the current limit threshold. The third benefit of the soft-start capacitor discharge is a
smooth, controlled ramp of output voltage when the current limit condition is cleared.
SHUTDOWN
If the shutdown pin is pulled low, (below 0.8V) the LM2744 enters shutdown mode, and discharges the soft-start
capacitor through a MOSFET switch. The high and low-side MOSFETs are turned off. The LM2744 remains in
this state as long as VSD sees a logic low (see the Electrical Characteristics table). To assure proper IC start-up
the shutdown pin should not be left floating. For normal operation this pin should be connected directly to VCC or
to another voltage between 1.3V to VCC (see the Electrical Characteristics table).
DESIGN CONSIDERATIONS
The following is a design procedure for all the components needed to create the Typical Application Circuit
shown on the front page. This design converts 3.3V (VIN) to 1.2V (VOUT) at a maximum load of 4A with an
efficiency of 89% and a switching frequency of 300kHz. The same procedures can be followed to create many
other designs with varying input voltages, output voltages, and load currents.
Input Capacitor
The input capacitors in a Buck converter are subjected to high stress due to the input current trapezoidal
waveform. Input capacitors are selected for their ripple current capability and their ability to withstand the heat
generated since that ripple current passes through their ESR. Input rms ripple current is approximately:
IRMS_RIP = IOUT
x
D(1 - D)
where
•
duty cycle D = VOUT/VIN
(11)
The power dissipated by each input capacitor is:
(IRMS_RIP)2 x ESR
PCAP
=
n2
where
•
•
n is the number of capacitors
ESR is the equivalent series resistance of each capacitor
(12)
The equation above indicates that power loss in each capacitor decreases rapidly as the number of input
capacitors increases. The worst-case ripple for a Buck converter occurs during full load and when the duty cycle
(D) is 0.5. For this 3.3V to 1.2V design the duty cycle is 0.364. For a 4A maximum load the ripple current is
1.92A.
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Output Inductor
The output inductor forms the first half of the power stage in a Buck converter. It is responsible for smoothing the
square wave created by the switching action and for controlling the output current ripple (ΔIOUT). The inductance
is chosen by selecting between tradeoffs in efficiency and response time. The smaller the output inductor, the
more quickly the converter can respond to transients in the load current. However, as shown in the efficiency
calculations, a smaller inductor requires a higher switching frequency to maintain the same level of output current
ripple. An increase in frequency can mean increasing loss in the MOSFETs due to the charging and discharging
of the gates. Generally the switching frequency is chosen so that conduction loss outweighs switching loss. The
equation for output inductor selection is:
VIN - VOUT
x D
L =
DIOUT x FSW
(13)
3.3V - 1.2V
1.2V
3.3V
x
L =
0.4 x 4A x 300 kHz
(14)
(15)
L = 1.6µH
Here we have plugged in the values for output current ripple, input voltage, output voltage, switching frequency,
and assumed a 40% peak-to-peak output current ripple. This yields an inductance of 1.6 µH. The output inductor
must be rated to handle the peak current (also equal to the peak switch current), which is (IOUT + 0.5*ΔIOUT) =
4.8A, for a 4A design. The Coilcraft DO3316P-222P is 2.2 µH, is rated to 7.4A peak, and has a direct current
resistance (DCR) of 12mΩ.
After selecting an output inductor, inductor current ripple should be re-calculated with the new inductance value,
as this information is needed to select the output capacitor. Re-arranging the equation used to select inductance
yields the following:
VIN(max) - VO
x D
DIOUT
=
fSW x LACTUAL
(16)
VIN(MAX) is assumed to be 10% above the steady state input voltage, or 3.6V. The actual current ripple will then
be 1.2A. Peak inductor/switch current will be 4.6A.
Output Capacitor
The output capacitor forms the second half of the power stage of a Buck switching converter. It is used to control
the output voltage ripple (ΔVOUT) and to supply load current during fast load transients.
In this example the output current is 4A and the expected type of capacitor is an aluminum electrolytic, as with
the input capacitors. Other possibilities include ceramic, tantalum, and solid electrolyte capacitors, however the
ceramic type often do not have the large capacitance needed to supply current for load transients, and tantalums
tend to be more expensive than aluminum electrolytic. Aluminum capacitors tend to have very high capacitance
and fairly low ESR, meaning that the ESR zero, which affects system stability, will be much lower than the
switching frequency. The large capacitance means that at the switching frequency, the ESR is dominant, hence
the type and number of output capacitors is selected on the basis of ESR. One simple formula to find the
maximum ESR based on the desired output voltage ripple, ΔVOUT and the designed output current ripple, ΔIOUT
,
is:
DVOUT
ESRMAX
=
DIOUT
(17)
In this example, in order to maintain a 2% peak-to-peak output voltage ripple and a 40% peak-to-peak inductor
current ripple, the required maximum ESR is 20mΩ. The Sanyo 4SP560M electrolytic capacitor will give an
equivalent ESR of 14mΩ. The capacitance of 560 µF is enough to supply energy even to meet severe load
transient demands.
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MOSFETs
Selection of the power MOSFETs is governed by a tradeoff between cost, size, and efficiency. One method is to
determine the maximum cost that can be endured, and then select the most efficient device that fits that price.
Breaking down the losses in the high-side and low-side MOSFETs and then creating spreadsheets is one way to
determine relative efficiencies between different MOSFETs. Good correlation between the prediction and the
bench result is not ensured, however. Single-channel buck regulators that use a controller IC and discrete
MOSFETs tend to be most efficient for output currents of 2-10A.
Losses in the high-side MOSFET can be broken down into conduction loss, gate charging loss, and switching
loss. Conduction, or I2R loss, is approximately:
PC = D (IO2 x RDSON-HI x 1.3) (High-Side MOSFET)
PC = (1 - D) x (IO2 x RDSON-LO x 1.3) (Low-Side MOSFET)
(18)
(19)
In the above equations the factor 1.3 accounts for the increase in MOSFET RDSON due to heating. Alternatively,
the 1.3 can be ignored and the RDSON of the MOSFET estimated using the RDSON Vs. Temperature curves in the
MOSFET datasheets.
Gate charging loss results from the current driving the gate capacitance of the power MOSFETs, and is
approximated as:
PGC = n x (VDD) x QG x FSW
where
•
•
•
‘n’ is the number of MOSFETs (if multiple devices have been placed in parallel)
VDD is the driving voltage (see MOSFET Gate Drivers section)
QGS is the gate charge of the MOSFET
(20)
If different types of MOSFETs are used, the ‘n’ term can be ignored and their gate charges simply summed to
form a cumulative QG. Gate charge loss differs from conduction and switching losses in that the actual
dissipation occurs in the LM2744, and not in the MOSFET itself.
Switching loss occurs during the brief transition period as the high-side MOSFET turns on and off, during which
both current and voltage are present in the channel of the MOSFET. It can be approximated as:
PSW = 0.5 x VIN x IO x (tr + tf) x FSW
where
•
tR and tF are the rise and fall times of the MOSFET
(21)
Switching loss occurs in the high-side MOSFET only.
For this example, the maximum drain-to-source voltage applied to either MOSFET is 3.6V. The maximum drive
voltage at the gate of the high-side MOSFET is 3.1V, and the maximum drive voltage for the low-side MOSFET
is 3.3V. Due to the low drive voltages in this example, a MOSFET that turns on fully with 3.1V of gate drive is
needed. For designs of 5A and under, dual MOSFETs in SO-8 provide a good tradeoff between size, cost, and
efficiency.
Support Components
CIN2 - A small (0.1 to 1 µF) ceramic capacitor should be placed as close as possible to the drain of the high-side
MOSFET and source of the low-side MOSFET (dual MOSFETs make this easy). This capacitor should be X5R
type dielectric or better.
RCC, CCC- These are standard filter components designed to ensure smooth DC voltage for the chip supply. RCC
should be 1-10Ω. CCC should be 1 µF, X5R type or better.
CBOOT- Bootstrap capacitor, typically 100nF.
RPULL-UP – This is a standard pull-up resistor for the open-drain power good signal (PWGD). The recommended
value is 10 kΩ connected to VCC. If this feature is not necessary, the resistor can be omitted.
D1 - A small Schottky diode should be used for the bootstrap. It allows for a minimum drop for both high and low-
side drivers. The MBR0520 or BAT54 work well in most designs.
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RCS - Resistor used to set the current limit. Since the design calls for a peak current magnitude (IOUT+0.5*ΔIOUT
)
of 4.8A, a safe setting would be 6A. (This is below the saturation current of the output inductor, which is 7A.)
Following the equation from the Current Limit section, a 1.3kΩ resistor should be used.
RFADJ - This resistor is used to set the switching frequency of the chip. The resistor value is calculated from
equation in Normal Operation section. For 300 kHz operation, a 97.6 kΩ resistor should be used.
CSS - The soft-start capacitor depends on the user requirements and is calculated based on the equation given in
the section titled START UP/SOFT-START. Therefore, for a 700 µs delay, a 12nF capacitor is suitable.
Control Loop Compensation
The LM2744 uses voltage-mode (‘VM’) PWM control to correct changes in output voltage due to line and load
transients. One of the attractive advantages of voltage mode control is its relative immunity to noise and layout.
However VM requires careful small signal compensation of the control loop for achieving high bandwidth and
good phase margin.
The control loop is comprised of two parts. The first is the power stage, which consists of the duty cycle
modulator, output inductor, output capacitor, and load. The second part is the error amplifier, which for the
LM2744 is a 9MHz op-amp used in the classic inverting configuration. Figure 31 shows the regulator and control
loop components.
R
L
L
+
C
O
V
IN
R
O
+
-
R
C
V
RAMP
-
+
R
C2
C
R
C1
C2
10 kW
10 kW
C
C3
C
C1
-
+
+
-
V
REF
Figure 31. Power Stage and Error Amp
One popular method for selecting the compensation components is to create Bode plots of gain and phase for
the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the
regulator easy to see. Software tools such as Excel, MathCAD, and Matlab are useful for showing how changes
in compensation or the power stage affect system gain and phase.
The power stage modulator provides a DC gain ADC that is equal to the input voltage divided by the peak-to-peak
value of the PWM ramp. This ramp is 1.0VP-P for the LM2744. The inductor and output capacitor create a
double pole at frequency fDP, and the capacitor ESR and capacitance create a single zero at frequency fESR. For
this example, with VIN = 3.3V, these quantities are:
VIN
3.3
=
= 10.4 dB
ADC
=
1.0
VRAMP
(22)
(23)
RO + RL
1
2p
= 4.5 kHz
fDP
=
LCO(RO + ESR)
1
= 20.3 kHz
fESR
=
2pCOESR
(24)
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In the equation for fDP, the variable RL is the power stage resistance, and represents the inductor DCR plus the
on resistance of the high-side MOSFET. RO is the output voltage divided by output current. The power stage
transfer function GPS is given by the following equation, and Figure 32 shows Bode plots of the phase and gain in
this example.
sCORC + 1
a x s2 + b x s + c
PVIN x RO
VRAMP
x
GPS
=
(25)
a = LCO(RO + RC)
b = L + CO(RORL + RORC + RCRL)
c = RO + RL
20
4
0
-30
-12
-60
-28
-44
-60
-90
-120
-150
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 32. Power Stage Gain and Phase
The double pole at 4.5kHz causes the phase to drop to approximately -130° at around 10kHz. The ESR zero, at
20.3kHz, provides a +90° boost that prevents the phase from dropping to -180º. If this loop were left
uncompensated, the bandwidth would be approximately 10kHz and the phase margin 53°. In theory, the loop
would be stable, but would suffer from poor DC regulation (due to the low DC gain) and would be slow to
respond to load transients (due to the low bandwidth.) In practice, the loop could easily become unstable due to
tolerances in the output inductor, capacitor, or changes in output current, or input voltage. Therefore, the loop is
compensated using the error amplifier and a few passive components.
For this example, a Type III, or three-pole-two-zero approach gives optimal bandwidth and phase.
In most voltage mode compensation schemes, including Type III, a single pole is placed at the origin to boost DC
gain as high as possible. Two zeroes fZ1 and fZ2 are placed at the double pole frequency to cancel the double
pole phase lag. Then, a pole, fP1 is placed at the frequency of the ESR zero. A final pole fP2 is placed at one-half
of the switching frequency. The gain of the error amplifier transfer function is selected to give the best bandwidth
possible without violating the Nyquist stability criteria. In practice, a good crossover point is one-fifth of the
switching frequency, or 60kHz for this example. The generic equation for the error amplifier transfer function is:
s
s
+ 1
+ 1
2pfZ1
2pfZ2
GEA = AEA
x
s
s
+ 1
s
+ 1
2pfP1
2pfP2
(26)
In this equation the variable AEA is a ratio of the values of the capacitance and resistance of the compensation
components, arranged as shown inFigure 32. AEA is selected to provide the desired bandwidth. A starting value
of 80,000 for AEA should give a conservative bandwidth. Increasing the value will increase the bandwidth, but will
also decrease phase margin. Designs with 45-60° are usually best because they represent a good tradeoff
between bandwidth and phase margin. In general, phase margin is lowest and gain highest (worst-case) for
maximum input voltage and minimum output current. One method to select AEA is to use an iterative process
beginning with these worst-case conditions.
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1. Increase AEA
2. Check overall bandwidth and phase margin
3. Change VIN to minimum and recheck overall bandwidth and phase margin
4. Change IO to maximum and recheck overall bandwidth and phase margin
The process ends when the both bandwidth and the phase margin are sufficiently high. For this example input
voltage can vary from 3.0 to 3.6V and output current can vary from 0 to 4A, and after a few iterations a moderate
gain factor of 110,000 is used.
The error amplifier of the LM2744 has a unity-gain bandwidth of 9MHz. In order to model the effect of this
limitation, the open-loop gain can be calculated as:
2p x 9 MHz
OPG =
s
(27)
The new error amplifier transfer function that takes into account unity-gain bandwidth is:
GEA x OPG
HEA
=
1 + GEA + OPG
(28)
The gain and phase of the error amplifier are shown in Figure 33.
50
20
60
48
-10
36
-40
-70
24
12
0
-100
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 33. Error Amp Gain and Phase
In VM regulators, the top feedback resistor RFB2 forms a part of the compensation. Setting RFB2 to 10kΩ, ±1%
usually gives values for the other compensation resistors and capacitors that fall within a reasonable range.
(Capacitances > 1pF, resistances < 1MΩ) CC1, CC2, CC3, RC1, and RC2 are selected to provide the poles and
zeroes at the desired frequencies, using the following equations:
fZ1
= 27 pF
CC1
CC2
CC3
RC1
=
=
=
=
AEA x 10,000 x fP2
(29)
(30)
(31)
(32)
1
- CC1 = 882 pF
AEA x 10,000
1
1
1
-
-
= 2.73 nF
fZ2 fP1
2p x 10,000
1
= 39.8 kW
= 2.55 kW
2p x CC2 x fZ1
1
RC2
=
2p x CC3 x fP1
(33)
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In practice, a good trade off between phase margin and bandwidth can be obtained by selecting the closest
±10% capacitor values above what are suggested for CC1 and CC2, the closest ±10% capacitor value below the
suggestion for CC3, and the closest ±1% resistor values below the suggestions for RC1, RC2. Note that if the
suggested value for RC2 is less than 100Ω, it should be replaced by a short circuit. Following this guideline, the
compensation components will be:
CC1 = 27pF ±10%, CC2 = 820pF ±10%
CC3 = 2.7nF ±10%, RC1 = 39.2kΩ ±1%
RC2 = 2.55kΩ ±1%
The transfer function of the compensation block can be derived by considering the compensation components as
impedance blocks ZF and ZI around an inverting op-amp:
ZF
GEA-ACTUAL
=
ZI
(34)
1
1
x
10,000 +
sCC2
sCC1
ZF =
1
1
10,000 +
+
sCC1 sCC2
(35)
(36)
1
RC2
+
RC1
sCC3
ZI =
1
+
RC1 + RC2
sCC3
As with the generic equation, GEA-ACTUAL must be modified to take into account the limited bandwidth of the error
amplifier. The result is:
GEA-ACTUAL x OPG
HEA
=
1 + GEA-ACTUAL+ OPG
(37)
The total control loop transfer function H is equal to the power stage transfer function multiplied by the error
amplifier transfer function.
H = GPS x HEA
(38)
The bandwidth and phase margin can be read graphically from Bode plots of HEA are shown in Figure 34.
-60
-84
60
40
-108
20
-132
-156
-180
0
-20
-40
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 34. Overall Loop Gain and Phase
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The bandwidth of this example circuit is 59kHz, with a phase margin of 60°.
EFFICIENCY CALCULATIONS
The following is a sample calculation.
A reasonable estimation of the efficiency of a switching buck controller can be obtained by adding together the
Output Power (POUT) loss and the Total Power (PTOTAL) loss:
POUT
x 100%
h =
POUT + PTOTAL
(39)
The Output Power (POUT) for the Typical Application Circuit design is (1.2V * 4A) = 4.8W. The Total Power
(PTOTAL), with an efficiency calculation to complement the design, is shown below.
The majority of the power losses are due to low and high-side of MOSFET’s losses. The losses in any MOSFET
are group of switching (PSW) and conduction losses(PCND).
PFET = PSW + PCND = 61.38mW + 270.42mW
PFET = 331.8mW
(40)
(41)
FET Switching Loss (PSW
)
PSW = PSW(ON) + PSW(OFF)
(42)
(43)
(44)
(45)
PSW = 0.5 * VIN * IOUT * (tr + tf)* FOSC
PSW = 0.5 x 3.3V x 4A x 300kHz x 31ns
PSW = 61.38mW
The FDS6898A has a typical turn-on rise time tr and turn-off fall time tf of 15ns and 16ns, respectively. The
switching losses for this type of dual N-Channel MOSFETs are 0.061W.
FET Conduction Loss (PCND
)
PCND = PCND1 + PCND2
PCND1 = I2OUT x RDS(ON) x k x D
PCND2 = I2OUT x RDS(ON) x k x (1-D)
(46)
(47)
(48)
RDS(ON) = 13mΩ and the factor is a constant value (k = 1.3) to account for the increasing RDS(ON) of a FET due to
heating.
PCND1 = (4A)2 x 13mΩ x 1.3 x 0.364
PCND2 = (4A)2 x 13mΩ x 1.3 x (1 - 0.364)
PCND = 98.42mW + 172mW = 270.42mW
(49)
(50)
(51)
There are few additional losses that are taken into account:
IC Operating Loss (PIC)
PIC = IQ_VCC x VCC
,
(52)
(53)
where IQ-VCC is the typical operating VCC current
PIC= 1.5mA *3.3V = 4.95mW
FET Gate Charging Loss (PGATE
)
PGATE = n * VCC * QGS * FOSC
(54)
(55)
(56)
PGATE = 2 x 3.3V x 3nC x 300kHz
PGATE = 5.94mW
The value n is the total number of FETs used and QGS is the typical gate-source charge value, which is 3nC. For
the FDS6898A the gate charging loss is 5.94mW.
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Input Capacitor Loss (PCAP
)
(IRMS_RIP)2 x ESR
PCAP
=
n2
where
•
IRMS_RIP = IOUT
x
D(1 - D)
(57)
Here n is the number of paralleled capacitors, ESR is the equivalent series resistance of each, and PCAP is the
dissipation in each. So for example if we use only one input capacitor of 24 mΩ.
(1.924A)2 x 24mW
PCAP
=
I2
(58)
(59)
PCAP = 88.8mW
Output Inductor Loss (PIND
)
PIND = I2OUT * DCR
(60)
where DCR is the DC resistance. Therefore, for example
PIND = (4A)2 x 11mΩ
(61)
(62)
PIND = 176mW
Total System Efficiency
POUT
x 100%
h =
h =
POUT + PTOTAL
(63)
(64)
4.8W
= 89%
4.8W + 0.6W
Example Circuits
V
= 5V
CC
C
BOOT
D1
V
IN
= 5V
R
PULL-UP
Q1
C 1,2
IN
R
CC
V
HG
CC
SD
BOOT
R
CS
C
CC
L1
V
OUT
=3.3V@2A
I
PWGD
FREQ
SEN
LM2744
LG
SGND
PGND
FB
R
FADJ
+
R
FB2
SS/TRACK
C 1,2
O
V
REF
C
SS
EAO
C
C3
R
C2
R
FB1
C
C1
V
= 1.2V
REF
C
C2
R
C1
Figure 35. 5V to 3.3V at 2A, VREF = 1.2V, FSW = 300kHz
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Table 1. Bill of Materials
PART
U1
PART NUMBER
LM2744
TYPE
PACKAGE
DESCRIPTION
VENDOR
Synchronous Controller
Dual N-MOSFET
TSSOP-14
SO-8
NSC
Q1
FDS6898A
20V, 10mΩ@ 4.5V,
Fairchild
16nC
D1
L1
MBR0520LTI
DO3316P-472
Schottky Diode
Inductor
SOD-123
12.95 x 9.4 x
5.21mm
4.7µH, 4.8Arms 18mΩ Coilcraft
CIN
1
16SP100M
6SP220M
Aluminum Electrolytic
Aluminum Electrolytic
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Resistor
10mm x 6mm
10mm x 6mm
0805
100µF, 16V, 2.89Arms Sanyo
CO1
220µF, 6.3V 3.1Arms
0.1µF, 10%
1µF, 20%
Sanyo
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
CBOOT, CIN2, CO2 VJ0805Y104KXXA
CCC
VJ0805M104MXQ
VJ0805Y332KXXA
VJ0805A123KXAA
VJ0805Y122KXXA
VJ0805A270KXAA
CRCW08051002F
CRCW08055761F
CRCW08051103F
CRCW08052101F
CRCW08057870F
CRCW080510R0F
CRCW08053832F
CRCW08051003J
0805
CC3
0805
3300pF, 10%
12nF, 10%
1200pF 10%
27pF, 10%
10.0kΩ 1%
5.76kΩ1%
CSS
0805
CC2
0805
CC1
0805
RFB2
RFB1
RFADJ
RC2
0805
Resistor
0805
Resistor
0805
110kΩ 1%
Resistor
0805
2.1kΩ 1%
RCS
Resistor
0805
787Ω 1%
RCC
Resistor
0805
10.0Ω 1%
RC1
Resistor
0805
38.3kΩ 1%
100kΩ 5%
RPULL-UP
Resistor
0805
V
= 3.3V
CC
C
D1
BOOT
V
IN
= 3.3V
R
PULL-UP
Q1
C
1,2
R
C
IN
CC
V
HG
CC
SD
BOOT
R
CS
L1
CC
V
OUT
=2.5V@2A
I
PWGD
FREQ
SEN
LM2744
LG
SGND
PGND
FB
R
FADJ
+
R
FB2
SS/TRACK
C
O
1,2
C
SS
V
REF
EAO
R
C2
C
C3
R
FB1
C
C1
V
REF
= 0.8V
C
C2
R
C1
Figure 36. 3.3V to 2.5V at 2A, VREF = 0.8V, FSW = 300kHz
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Table 2. Bill of Materials
PART
U1
PART NUMBER
LM2744
TYPE
PACKAGE
DESCRIPTION
VENDOR
NSC
Synchronous Controller
Dual N-MOSFET
Schottky Diode
Inductor
TSSOP-14
SO-8
Q1
FDS6898A
20V, 10mΩ@ 4.5V, 16nC
3.3µH, 5.4Arms 15mΩ
Fairchild
D1
MBR0520LTI
DO3316P-332
SOD-123
L1
12.95 x 9.4 x
5.21mm
Coilcraft
CIN
1
16SP100M
Aluminum Electrolytic
Aluminum Electrolytic
Capacitor
10mm x 6mm
10mm x 6mm
0805
100µF, 16V 2.89Arms
220µF, 6.3V 3.1Arms
0.1µF, 10%
Sanyo
Sanyo
Vishay
CO1
6SP220M
CBOOT, CIN2,
CO2
VJ0805Y104KXXA
CCC
VJ0805M104MXQ
VJ0805Y222KXXA
VJ0805A123KXAA
VJ0805Y272KXAA
VJ0805A820KXAA
CRCW08051002F
CRCW08054641F
CRCW08051103F
CRCW08052551F
CRCW08058450F
CRCW080510R0F
CRCW08051372F
CRCW08051003J
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
0805
0805
0805
0805
0805
0805
0805
0805
0805
0805
0805
0805
0805
1µF, 20%
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
CC3
2200pF, 10%
12nF, 10%
2700pF 10%
82pF, 10%
10.0kΩ 1%
4.64kΩ 1%
110kΩ 1%
2.55kΩ 1%
845Ω 1%
CSS
CC2
CC1
RFB2
RFB1
RFADJ
RC2
RCS
RCC
10.0Ω 1%
13.7kΩ 1%
100kΩ 5%
RC1
RPULL-UP
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REVISION HISTORY
Changes from Revision E (March 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 27
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PACKAGE OPTION ADDENDUM
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5-Nov-2017
PACKAGING INFORMATION
Orderable Device
LM2744MTC/NOPB
LM2744MTCX/NOPB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
OBSOLETE
TSSOP
TSSOP
PW
14
14
TBD
Call TI
Call TI
2744
MTC
OBSOLETE
PW
TBD
Call TI
Call TI
-40 to 125
2744
MTC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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5-Nov-2017
Addendum-Page 2
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相关型号：
LM2745MTCX
Synchronous Buck Controller with Pre-bias Startup, and Optional Clock Synchronization
NSC
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