LM2765M6X/NOPB [TI]
50kHz 开关电容倍压器 | DBV | 6 | -40 to 85;
| 型号： | LM2765M6X/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 50kHz 开关电容倍压器 | DBV | 6 | -40 to 85 开关 光电二极管 |
| 文件： | 总21页 (文件大小：903K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM2765
SNVS070D –MARCH 2000–REVISED SEPTEMBER 2016
LM2765 Switched-Capacitor Voltage Converter
1 Features
3 Description
The LM2765 CMOS charge-pump voltage converter
operates as a voltage doubler for an input voltage in
the range of 1.8 V to 5.5 V. Two low-cost capacitors
and a diode are used in this circuit to provide up to 20
mA of output current.
1
•
•
•
•
•
Doubles Input Supply Voltage
SOT-23 6-Pin Package
20-Ω Typical Output Impedance
90% Typical Conversion Efficiency at 20 mA
0.1-µA Typical Shutdown Current
The LM2765 operates at 50-kHz switching frequency
to reduce output resistance and voltage ripple. With
an operating current of only 130 µA (operating
efficiency greater than 90% with most loads) and 0.1-
µA typical shutdown current, the LM2765 provides
ideal performance for battery powered systems. The
device is manufactured in a 6-pin SOT-23 package.
2 Applications
•
•
•
•
•
•
Cellular Phones
Pagers
PDAs
Operational Amplifier Power Supplies
Interface Power Supplies
Handheld Instruments
Device Information(1)
PART NUMBER
LM2765
PACKAGE
BODY SIZE (NOM)
SOT-23 (6)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
space
space
Voltage Doubler
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM2765
SNVS070D –MARCH 2000–REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Applications .................................................. 9
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics ............................................. 5
Parameter Measurement Information .................. 7
7.1 Test Circuit................................................................ 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
9
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1 Device Support...................................................... 14
12.2 Receiving Notification of Documentation Updates 14
12.3 Community Resources.......................................... 14
12.4 Trademarks........................................................... 14
12.5 Electrostatic Discharge Caution............................ 14
12.6 Glossary................................................................ 14
7
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2013) to Revision D
Page
•
Added Pin Configuration and Functions section, ESD Rating table, Feature Description , Device Functional Modes,
Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and
Mechanical, Packaging, and Orderable Information sections; change pin name "VOUT" to "OUT"...................................... 1
Added top nav icon for TI design .......................................................................................................................................... 1
Changed RθJA value from 210°C/W to 185.2°C/W; add additional thermal values ................................................................ 4
•
•
Changes from Revision B (May 2013) to Revision C
Page
•
Changed layout of National Semiconductor data sheet to TI format.................................................................................... 12
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5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
1
2
3
6
5
4
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
V+
Power
Ground
Power
Input
Power supply positive voltage input
2
GND
CAP−
SD
Power supply ground input
3
Connect this pin to the negative terminal of the charge-pump capacitor.
Shutdown control pin; tie this pin to ground in normal operation.
Positive voltage output
4
5
OUT
CAP+
Power
Power
6
Connect this pin to the positive terminal of the charge-pump capacitor.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
MAX
UNIT
Supply voltage (V+ to GND or V+ to OUT)
SD
5.8
V
(GND − 0.3 V)
(V+ + 0.3 V)
OUT continuous output current
Output short-circuit duration to GND(3)
Continuous power dissipation (TA = 25°C)(4)
40
1
mA
sec
mW
°C
600
150
150
(4)
TJ-MAX
Storage temperature, Tstg
−65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) OUT may be shorted to GND for one second without damage. However, shorting OUT to V+ may damage the device and must be
avoided. Also, for temperatures above 85°C, OUT must not be shorted to GND or V+, or device may be damaged.
(4) The maximum allowable power dissipation is calculated by using PD-MAX = (TJ-MAX − TA)/RθJA, where TJ-MAX is the maximum junction
temperature, TA is the ambient temperature, and RθJA is the junction-to-ambient thermal resistance of the specified package.
6.2 ESD Ratings
VALUE
±2000
200
UNIT
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Machine model
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–40
–40
NOM
MAX
85
UNIT
°C
Ambient temperature
Junction temperature
100
°C
6.4 Thermal Information
LM2765
THERMAL METRIC(1)
DBV (SOT-23)
6 PINS
185.2
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
131.5
34.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
21.6
ψJB
34.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
MIN and MAX limits apply over the full operating temperature range. Unless otherwise specified: TJ = 25°C, V+ = 5 V,
C1 = C2 = 3.3 μF.(1)
PARAMETER
Supply voltage
Supply current
TEST CONDITIONS
MIN
TYP
MAX UNIT
V+
IQ
1.8
5.5
450
0.5
V
No load
130
0.1
0.2
µA
ISD
VSD
IL
Shutdown supply current
Shutdown pin input voltage
Output current
µA
V
TA = 85°C
Shutdown mode
Normal operation
2.5 V ≤ VIN ≤ 5.5 V
1.8 V ≤ VIN ≤ 2.5 V
IL = 20 mA
2
0.6
20
10
mA
ROUT
ƒOSC
ƒSW
Output resistance(2)
Oscillator frequency
Switching frequency
Power efficiency
20
100
40
200
100
Ω
See(3)
See(3)
40
20
kHz
kHz
50
PEFF
VOEFF
RL (1 kΩ) between GND and OUT
No load
92%
Voltage conversion efficiency
99.96%
(1) In the test circuit, capacitors C1 and C2 are 3.3-µF, 0.3-Ω maximum ESR capacitors. Capacitors with higher ESR increase output
resistance, reduce output voltage, and efficiency.
(2) Specified output resistance includes internal switch resistance and capacitor ESR. See the details in Application and Implementation for
simple negative voltage converter.
(3) The output switches operate at one half of the oscillator frequency, ƒOSC = 2ƒSW
.
6.6 Typical Characteristics
(Circuit of Test Circuit, VIN = 5V, TA = 25°C unless otherwise specified)
Figure 2. Output Resistance vs Capacitance
Figure 1. Supply Current vs Supply Voltage
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Typical Characteristics (continued)
(Circuit of Test Circuit, VIN = 5V, TA = 25°C unless otherwise specified)
Figure 3. Output Resistance vs Supply Voltage
Figure 5. Output Voltage vs Load Current
Figure 7. Switching Frequency vs Temperature
Figure 4. Output Resistance vs Temperature
Figure 6. Switching Frequency vs Supply Voltage
Figure 8. Output Ripple vs Load Current
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7 Parameter Measurement Information
7.1 Test Circuit
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8 Detailed Description
8.1 Overview
The LM2765 CMOS charge-pump voltage converter operates as a voltage doubler for an input voltage in the
range of 1.8 V to 5.5 V. Two low-cost capacitors and a diode (needed during start-up) are used in this circuit to
provide up to 20 mA of output current.
8.2 Functional Block Diagram
LM2765
V+
OUT
CAP+
CAP-
GND
{ꢀitcꢁ !rray
{ꢀitcꢁ 5rivers
SD
h{/L[[!Çhw
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8.3 Feature Description
8.3.1 Circuit Description
The LM2765 contains four large CMOS switches which are switched in a sequence to double the input supply
voltage. Energy transfer and storage are provided by external capacitors. Figure 9 shows the voltage conversion
scheme. When S2 and S4 are closed, C1 charges to the supply voltage V+. During this time interval, switches S1
and S3 are open. In the next time interval, S2 and S4 are open; at the same time, S1 and S3 are closed, the sum
of the input voltage V+ and the voltage across C1 gives the 2 V+ output voltage when there is no load. The
output voltage drop when a load is added is determined by the parasitic resistance (Rds(on) of the MOSFET
switches and the ESR of the capacitors) and the charge transfer loss between capacitors. See Application and
Implementation for more details.
Figure 9. Voltage Doubling Principle
8.4 Device Functional Modes
8.4.1 Shutdown Mode
A shutdown (SD) pin is available to disable the device and reduce the quiescent current to 1 µA. In normal
operating mode, the SD pin is connected to ground. The device can be brought into the shutdown mode by
applying to the SD pin a voltage greater than 40% of the V+ pin voltage.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers must
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LM2765 provides a simple and efficient means of creating an output voltage level equal to twice that of the
input voltage. Without the need of an inductor, the application solution size can be reduced versus the magnetic
DC-DC converter solution.
9.2 Typical Applications
9.2.1 Voltage Doubler
The main application of the LM2765 is to double the input voltage. The range of the input supply voltage is 1.8 V
to 5.5 V.
Figure 10. Voltage Doubler
9.2.1.1 Design Requirements
Example requirements for LM2765 device applications:
DESIGN PARAMETER
Input voltage range
Output current
EXAMPLE VALUE
1.8 V to 5.5 V
0 mA to 20 mA
20 kHz
Boost switching frequency
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9.2.1.2 Detailed Design Requirements
9.2.1.2.1 Positive Voltage Doubler
The output characteristics of this circuit can be approximated by an ideal voltage source in series with a
resistance. The voltage source equals 2 V+. The output resistance ROUT is a function of the ON resistance of the
internal MOSFET switches, the oscillator frequency, the capacitance and equivalent series resistance (ESR) of
C1 and C2. Since the switching current charging and discharging C1 is approximately twice as the output current,
the effect of the ESR of the pumping capacitor C1 will be multiplied by four in the output resistance. The output
capacitor C2 is charging and discharging at a current approximately equal to the output current, therefore, its
ESR only counts when in the output resistance. A good approximation of ROUT is:
2
× %1
4176 ꢀ 2459
+
+ 4'54%1 + '54%2
&
15%
where
•
RSW is the sum of the ON resistance of the internal MOSFET switches shown in Figure 9. RSW is typically 8 Ω
for the LM2765. (1)
The peak-to-peak output voltage ripple is determined by the oscillator frequency, the capacitance and ESR of the
output capacitor C2:
+
.
8
4+22.'
=
+ 2 × +. × '54%2
&
× %2
15%
(2)
High capacitance, low-ESR capacitors can reduce both the output resistance and the voltage ripple.
The Schottky diode D1 is only needed for start-up. The internal oscillator circuit uses the OUT pin and the GND
pin. Voltage across OUT and GND must be larger than 1.8 V to insure the operation of the oscillator. During
start-up, D1 is used to charge up the voltage at the OUT pin to start the oscillator; also, it protects the device from
turning-on its own parasitic diode and potentially latching-up. Therefore, the Schottky diode D1 must have
enough current carrying capability to charge the output capacitor at start-up, as well as a low forward voltage to
prevent the internal parasitic diode from turning-on. A Schottky diode such as 1N5817 can be used for most
applications. If the input voltage ramp is less than 10 V/ms, a smaller Schottky diode such as MBR0520LT1 can
be used to reduce the circuit size.
9.2.1.2.2 Capacitor Selection
As discussed in Positive Voltage Doubler, the output resistance and ripple voltage are dependent on the
capacitance and ESR values of the external capacitors. The output voltage drop is the load current times the
output resistance, and the power efficiency is:
2
2176
+. 4.
ß =
=
2
2
2
+0
+. 4. + +. 4176 + +3(8+)
where
•
•
IQ(V+) is the quiescent power loss of the device; and
2
IL Rout is the conversion loss associated with the switch on-resistance, the two external capacitors and their
ESRs.
(3)
The selection of capacitors is based on the specifications of the dropout voltage (which equals IOUT ROUT), the
output voltage ripple, and the converter efficiency. Low ESR capacitors are recommended to maximize efficiency,
reduce the output voltage drop and voltage ripple.
9.2.1.2.3 Paralleling Devices
Any number of LM2765 devices can be paralleled to reduce the output resistance. Each device must have its
own pumping capacitor C1, while only one output capacitor, COUT, is required as shown in Figure 11. The
composite output resistance is:
ROUT = ROUT of each LM2765 / number of devices
(4)
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Figure 11. Lowering Output Resistance by Paralleling Devices
9.2.1.2.4 Cascading Devices
Cascading the LM2765 devices is an easy way to produce a greater voltage (a two-stage cascade circuit is
shown in Figure 12).
The effective output resistance is equal to the weighted sum of each individual device, shown in Equation 5:
ROUT = 1.5 ROUT_1 + ROUT_2
(5)
Note that the increasing of the number of cascading stages is practically limited since it significantly reduces the
efficiency, increases the output resistance and output voltage ripple.
Figure 12. Increasing Output Voltage by Cascading Devices
9.2.1.2.5 Regulating VOUT
It is possible to regulate the output of the LM2765 by use of a low dropout regulator (such as LP2980-5.0). The
whole converter is depicted in Figure 13.
A different output voltage is possible by use of LP2980-3.3, LP2980-3.0, or LP2980-ADJ.
Note that the following conditions must be satisfied simultaneously for worst-case design:
2Vin_min > Vout_min + Vdrop_max (LP2980) + Iout_max × Rout_max (LM2765)
2Vin_max < Vout_max + Vdrop_min (LP2980) + Iout_min × Rout_min (LM2765)
(6)
(7)
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Figure 13. Generating a Regulated +5-V From +3-V Input Voltage
9.2.1.3 Application Curve
Figure 14. Efficiency vs Load Current
10 Power Supply Recommendations
The LM2765 is designed to operate from as an inverter over an input voltage supply range between 1.8 V and
5.5 V. This input supply must be well regulated and capable to supply the required input current. If the input
supply is located far from the device, additional bulk capacitance may be required in addition to the ceramic
bypass capacitors.
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11 Layout
11.1 Layout Guidelines
The high switching frequency and large switching currents of the LM2765 make the choice of layout important.
Use the following steps as a reference to ensure the device is stable and maintains proper LED current
regulation across its intended operating voltage and current range.
•
Place CIN on the top layer (same layer as the LM2765) and as close as possible to the device. Connecting
the input capacitor through short, wide traces to both the V+ and GND pins reduces the inductive voltage
spikes that occur during switching which can corrupt the V+ line.
•
Place COUT on the top layer (same layer as the LM2765) and as close as possible to the OUT and GND pin.
The returns for both CIN and COUT must come together at one point, as close as possible to the GND pin.
Connecting COUT through short, wide traces reduce the series inductance on the OUT and GND pins that can
corrupt the VOUT and GND lines and cause excessive noise in the device and surrounding circuitry.
•
Place C1 on the top layer (same layer as the LM2765 device) and as close as possible to the device.
Connect the flying capacitor through short, wide traces to both the CAP+ and CAP– pins.
11.2 Layout Example
LM2765
V+
CAP+
OUT
SD
GND
CAP-
Figure 15. Typical Layout for LM2765
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM2765M6X/NOPB
ACTIVE
SOT-23
DBV
6
3000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
S15B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM2765M6X/NOPB
SOT-23
DBV
6
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
LM2765M6X/NOPB
6
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
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EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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