LM2854MH-1000 [TI]
4A 500kHz/1MHz 同步降压稳压器 | PWP | 16 | -40 to 85;
| 型号： | LM2854MH-1000 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4A 500kHz/1MHz 同步降压稳压器 | PWP | 16 | -40 to 85 开关 光电二极管 稳压器 |
| 文件： | 总36页 (文件大小：1199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
LM2854 4A 500kHz/1MHz 同步降压稳压器
1 特性
3 描述
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
输入电压范围：2.95V 至 5.5V
LM2854 PowerWise™降压转换器是一款 500kHz 或
1MHz 降压开关稳压器，能够驱动高达 4A 的负载，并
且拥有出色的电源转换效率、线路和负载调节性能以及
输出精度。LM2854 的输入电压轨范围为 2.95V 至
5.5V，提供的高精度可调节输出电压低至 0.8V。可通
过外部小电容实现软启动，以便控制启动过程，从而使
LM2854 能够正常进入预偏置输出电压。部分内部补偿
功能减少了外部无源组件数以及电压模式降压转换器应
用中通常所需的 PCB 电路板空间，同时仍然能够灵活
处理陶瓷和/或电解电容。该器件采用无损逐周期峰值
电流限制为负载提供过流或短路故障保护，并通过使能
比较器来简化电源排序 进行了优化。LM2854 采用外
露焊盘 HTSSOP-16 封装，提升了稳压器的散热性
能。
最大负载电流为 4A
高带宽电压模式控制环路，部分内部补偿
固定开关频率：500kHz 或 1MHz
35mΩ 集成 MOSFET 开关
可调输出电压低至 0.8V
经优化的基准电压初始精度和温漂
外部软启动控制，带跟踪功能
带滞后的使能引脚
待机电流低至 230µA
预偏置负载启动功能
集成欠压锁定 (UVLO)、过流保护 (OCP) 和热关断
100% 占空比性能
散热薄型小外形尺寸 (TSSOP)-16 外露焊盘封装
器件信息(1)
2 应用
器件型号
LM2854
封装
封装尺寸（标称值）
•
•
从 5V 或 3.3V 电源轨到低压负载点 (POL) 的稳压
HTSSOP (16)
4.40mm × 5.00mm
面向现场可编程门阵列 (FPGA)/数字信号处理器
(DSP)/特定用途集成电路 (ASIC)/微处理器 (µP) 内
核或 I/O 电源的本地解决方案
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
宽带联网和通信基础设施
便携式计算
典型应用电路
V
IN
L
O
V
OUT
LM2854
SW
FB
PVIN
AVIN
EN
C
O
C
IN
AGND
PGND
SS
R
FB1
C
SS
C
R
COMP
COMP
R
FB2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVS560
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
www.ti.com.cn
目录
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
Power Supply Recommendations...................... 25
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
描述.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
8
9
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 26
11 器件和文档支持 ..................................................... 27
11.1 文档支持................................................................ 27
11.2 商标....................................................................... 27
11.3 静电放电警告......................................................... 27
11.4 Glossary................................................................ 27
12 机械、封装和可订购信息....................................... 27
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (April 2013) to Revision D
Page
•
添加了 ESD 额定值 表、特性 说明 部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文
档支持部分以及机械、封装和可订购信息部分........................................................................................................................ 1
•
•
Removed Soldering and Infrared values from Absolute Maximum Ratings. ......................................................................... 4
Added thermal information generated using TI standard methodology. ............................................................................... 4
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 24
Changes from Revision D (January 2016) to Revision E
Page
•
已删除 从说明 部分和详细 说明 部分中删除了 Simple Switcher ............................................................................................ 1
2
Copyright © 2008–2017, Texas Instruments Incorporated
LM2854
www.ti.com.cn
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
NC
PGND
PGND
PGND
PVIN
PVIN
PVIN
NC
1
2
3
4
5
6
7
8
16 FB
15 AGND
14 SS
13 SW
12 SW
11 EN
EXP
10 AVIN
9
NC
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
NC
1, 8, 9
—
—
Reserved for factory use, this pin should be connected to GND to ensure proper operation.
Power ground pins for the internal power switches. These pins should be connected together
locally at the device and tied to the PC board ground plane.
PGND
2, 3, 4
Input voltage to the power switches inside the device. These pins should be connected
together at the device. A low ESR input capacitance should be located as close as possible
to these pins.
PVIN
5, 6, 7
—
Analog input voltage supply that generates the internal bias. The UVLO circuit derives its
input from this pin also. Thus, if the voltage on AVIN falls below the UVLO threshold, both
internal FETs are turned off. TI recommends connecting PVIN to AVIN through a low pass
RC filter to minimize the influence of input rail ripple and noise on the analog control circuitry.
The series resistor should be 1 Ω and the bypass capacitor should be a X7R ceramic type
0.1 µF to 1 µF.
AVIN
10
—
Active high enable input for the device. Typically, turnon threshold is 1.23 V with 0.15-V
hysteresis. An external resistor divider from PVIN can be used to effectively increase the
UVLO turnon threshold. If not used, the EN pin should be connected to PVIN.
EN
SW
SS
11
12, 13
14
I
Switch node pins. This is the PWM output of the internal MOSFET power switches. These
pins should be tied together locally and connected to the filter inductor.
O
Soft-start control pin. An internal 2-µA current source charges an external capacitor
connected between this pin and AGND to set the output voltage ramp rate during start-up.
This pin can also be used to configure the tracking feature.
I/O
AGND
FB
15
16
—
I
Quiet analog ground for the internal bias circuitry.
Feedback pin is connected to the inverting input of the voltage loop error amplifier. An 0.8-V
bandgap reference is connected to the noninverting input of the error amplifier.
Exposed metal pad on the underside of the package with a weak electrical connection to
PGND. TI recommends connecting this pad to the PC board ground plane in order to
improve thermal dissipation.
Exposed Pad
—
Copyright © 2008–2017, Texas Instruments Incorporated
3
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)(2)
MIN
MAX
UNIT
PVIN, AVIN, SW, EN, FB, SS to GND(3)
Power Dissipation
–0.3
6
Internally Limited
150
V
Junction Temperature
°C
°C
Storage Temperature
−65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) PGND and AGND are electrically connected together on the PC board and the resultant net is termed GND.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. Test method is per JESD22-AI14.
6.3 Recommended Operating Conditions
MIN
2.95
2.95
−40
MAX
5.5
UNIT
V
PVIN to GND(1)
AVIN to GND(1)
5.5
V
Junction Temperature
125
°C
(1) PGND and AGND are electrically connected together on the PC board and the resultant net is termed GND.
6.4 Thermal Information
LM2854
PWP (HTSSOP)
THERMAL METRIC(1)
UNIT
16 PINS
38.4
27.6
17.1
1.5
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
16.9
1.3
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, Semiconductor and IC Package Thermal Metrics.
4
Copyright © 2008–2017, Texas Instruments Incorporated
LM2854
www.ti.com.cn
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
6.5 Electrical Characteristics
All Typical specifications are for TJ = 25°C only; all Maximum and Minimum limits apply over the operating junction
temperature range TJ range of –40°C to 125°C. Minimum and maximum limits are ensured through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes
only. AVIN = PVIN = EN = 5 V, unless otherwise indicated in the Test Conditions column.
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1) UNIT
SYSTEM PARAMETERS
VREF
Reference Voltage(3)
Line Regulation(3)
Load Regulation
Measured at the FB pin
ΔAVIN = 2.95 V to 5.50 V
Normal operation
Rising
0.790
0.8
0.04%
0.25
2.6
0.808
0.6%
V
ΔVREF/ΔAVIN
ΔVREF/ΔIO
mV/A
V
2.95
375
VON
UVLO Threshold (AVIN)
Falling hysteresis
ISW = 4 A
25
170
35
mV
RDS(ON)-P
PFET On Resistance
NFET On Resistance
Soft-Start Current
65 mΩ
65 mΩ
µA
RDS(ON)-N
ISW = 4 A
34
ISS
2
ICL
Peak Current Limit Threshold
Operating Current
4.5
6
6.7
3
A
IQ
Non-switching
EN = 0 V
1.7
mA
µA
ISD
Shut Down Quiescent Current
230
500
PWM SECTION
1-MHz option
800
400
0%
1050
525
1160 kHz
580 kHz
100%
fSW
Switching Frequency
500-kHz option
Drange
PWM Duty Cycle Range
ENABLE CONTROL
VIH
EN Pin Rising Threshold
EN Pin Hysteresis
0.8
1.23
150
1.65
V
VEN(HYS)
mV
THERMAL CONTROL
TSD
TJ for Thermal Shutdown
165
10
°C
°C
TSD-HYS
Hysteresis for Thermal Shutdown
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
(3) VREF measured in a non-switching, closed-loop configuration.
Copyright © 2008–2017, Texas Instruments Incorporated
5
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
www.ti.com.cn
6.6 Typical Characteristics
Unless otherwise specified, the following conditions apply: VIN = PVIN = AVIN = EN = 5, TJ = 25°C.
2.65
2.60
0.802
0.801
0.800
0.799
0.798
0.797
0.796
0.795
2.55
2.50
2.45
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 2. UVLO Threshold vs Temperature
Figure 1. Feedback Voltage vs Temperature
2.1
1.250
2.0
1.9
1.8
1.225
1.200
1.175
1.7
1.6
-50 -25
0
25
TEMPERATURE (°C)
50
75 100
125
-50
-25
0
25
50
75 100 125
TEMPERATURE (°C)
Figure 4. Enable Threshold vs Temperature
Figure 3. Soft Start Current vs Temperature
1200
60
55
50
1100
1 MHz
1000
900
800
700
V
= 3.3V
IN
45
40
35
30
25
20
V
= 5.0V
IN
600
500 kHz
500
400
-50 -25
0
25
50 75 100 125
-50 -25
0
25
50 75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Switching Frequency vs Temperature
Figure 6. PMOS RDS(ON) vs Temperature
6
Copyright © 2008–2017, Texas Instruments Incorporated
LM2854
www.ti.com.cn
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = PVIN = AVIN = EN = 5, TJ = 25°C.
50
45
40
35
30
1.8
1.7
25°C
V
= 3.3V
IN
1.6
1.5
1.4
125°C
V
= 5.0V
IN
85°C
-40°C
25
20
1.3
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
-50 -25
0
25
50 75 100 125
TEMPERATURE (°C)
V
IN
Figure 7. NMOS RDS(ON) vs Temperature
Figure 8. IQ (operating) vs VIN and Temperature
6.50
0.8010
6.25
6.00
5.75
5.50
V
IN
= 5.0V
0.8005
0.8000
V
IN
= 3.3V
0.7995
0.7990
5.25
5.00
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
-50 -25
0
25
50 75 100 125
TEMPERATURE (°C)
V
IN
Figure 9. Peak Current Limit vs Temperature
Figure 10. Feedback Voltage vs VIN
1100
1 MHz
260
1000
900
800
700
600
500
400
25°C
85°C
240
125°C
220
-40°C
500 kHz
200
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
IN
IN
Figure 11. IQ (disabled) vs VIN and Temperature, EN = 0 V
Figure 12. Switching Frequency vs VIN
Copyright © 2008–2017, Texas Instruments Incorporated
7
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
www.ti.com.cn
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = PVIN = AVIN = EN = 5, TJ = 25°C.
Figure 13. LM2854 500-kHz Switch Node Voltage (oscilloscope set at infinite persistence) VIN = 5 V, VOUT = 2.5 V, IOUT = 4 A
8
Copyright © 2008–2017, Texas Instruments Incorporated
LM2854
www.ti.com.cn
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
7 Detailed Description
7.1 Overview
The LM2854 PowerWise synchronous DC-DC buck regulator belongs to the Texas Instruments family of
switching regulators. Integration of the power MOSFETs and associated drivers, compensation component
network, and the PWM controller reduces the number of external components necessary for a complete power
supply design, without sacrificing performance.
7.2 Functional Block Diagram
AGND
PVIN
Ramp and Clock
Current Limit
0.8V
Reference
Generator
Oscillator
UVLO
AVIN
EN
+
-
Gate
Drive
Error
Amplifier
SW
1.23V
-
Reference
Selector
+
-
+
SS
PWM
Comparator
Zc2
PGND
FB
7.3 Feature Description
7.3.1 Switching Frequency
The LM2854 is available in two switching frequency options, 500 kHz and 1 MHz. Generally, a higher switching
frequency allows for faster transient response and a reduction in the footprint area and volume of the external
power stage components, while a lower switching frequency affords better efficiency. These factors should be
considered when selecting the appropriate switching frequency for a given application.
7.3.2 Enable
The LM2854 features a enable (EN) pin and associated comparator to allow the user to easily sequence the
LM2854 from an external voltage rail, or to manually set the input UVLO threshold. The turnon or rising threshold
and hysteresis for this comparator are typically 1.23 V and 0.15 V, respectively. The precise reference for the
enable comparator allows the user to ensure that the LM2854 will be disabled when the system demands it to
be.
7.3.3 Soft-Start
The LM2854 begins to operate when both the AVIN and EN voltages exceed the rising UVLO and enable
thresholds, respectively. A controlled soft-start eliminates inrush currents during start-up and allows the user
more control and flexibility when sequencing the LM2854 with other power supplies. An external soft-start
capacitor is used to control the LM2854 start-up time. During soft-start, the voltage on the feedback pin is
connected internally to the non-inverting input of the error amplifier. The soft-start period lasts until the voltage on
the soft-start pin exceeds the LM2854 reference voltage of 0.8 V. At this point, the reference voltage takes over
at the non-inverting amplifier input.
Copyright © 2008–2017, Texas Instruments Incorporated
9
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
www.ti.com.cn
Feature Description (continued)
In the event of either AVIN or EN decreasing below the falling UVLO or enable threshold respectively, the
voltage on the soft-start pin is collapsed by discharging the soft-start capacitor through a 5-kΩ transistor to
ground.
7.3.4 Tracking
The LM2854 can track the output of a master power supply during soft-start by connecting a resistor divider to
the SS pin. In this way, the output voltage slew rate of the LM2854 will be controlled by a master supply for loads
that require precise sequencing. When the tracking function is used, a small value soft-start capacitor can be
connected to the SS pin to alleviate output voltage overshoot when recovering from a current limit fault.
Master Power
Supply
VOUT1
VIN
LM2854
LO
VOUT2
PVIN
SW
FB
RT2
RT1
AVIN
SS
CO
VSS
CIN
AGND
PGND
Figure 14. Simplified Schematic Showing Use of Tracking
7.3.5 Pre-Biased Start-up Capability
The LM2854 is in a pre-biased state when the device starts up with an output voltage greater than zero. This
often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. The output can be
pre-biased in these applications through parasitic conduction paths from one supply rail to another. Even though
the LM2854 is a synchronous converter, it will not pull the output low when a pre-bias condition exists. The
LM2854 will not sink current during start up until the soft-start voltage exceeds the voltage on the FB pin. Since
the device can not sink current it protects the load from damage that might otherwise occur if current is
conducted through the parasitic paths of the load.
7.3.6 Feedback Voltage Accuracy
The FB pin is connected to the inverting input of the voltage loop error amplifier and during closed loop operation
its reference voltage is 0.8 V. The FB voltage is accurate to within –1.25% / +1% over temperature. Additionally,
the LM2854 contains error nulling circuitry to substantially eliminate the feedback voltage over temperature drift
as well as the long term aging effects of the internal amplifiers. In addition, the 1/f noise of the bandgap amplifier
and reference are dramatically reduced. The manifestation of this circuit action is that the duty cycle will have two
slightly different but distinct operating points, each evident every other switching cycle. The oscilloscope plot
shown previously of the SW pin with infinite persistence set shows this behavior. No discernible effect is evident
on the output due to LC filter attenuation. For further information, a Texas Instruments white paper is available on
this topic.
7.3.7 Positive Current Limit
The LM2854 employs lossless cycle-by-cycle high-side current limit circuitry to limit the peak current through the
high-side FET. The peak current limit threshold, denoted ICL, is nominally set at 6 A internally. When a current
greater than ICL is sensed through the PFET, its on-time is immediately terminated and the NFET is activated.
The NFET stays on for the entire next four switching cycles (effectively four PFET pulses are skipped). During
these skipped pulses, the voltage on the soft-start pin is reduced by discharging the soft-start capacitor by a
current sink on the soft-start pin of nominally 6 µA or 14 µA for the 500-kHz or 1-MHz options, respectively.
Subsequent overcurrent events will drain more and more charge from the soft-start capacitor, effectively
decreasing the reference voltage as the output droops due to the pulse skipping. Reactivation of the soft-start
circuitry ensures that when the overcurrent situation is removed, the part will resume normal operation smoothly.
10
Copyright © 2008–2017, Texas Instruments Incorporated
LM2854
www.ti.com.cn
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
Feature Description (continued)
7.3.8 Negative Current Limit
The LM2854 implements negative current limit detection circuitry to prevent large negative current in the
inductor. When the negative current sensed in the low-side NFET is below approximately –0.4 A, the present
switching cycle is immediately terminated and both FETs are turned off. When both FETs are off, the negative
inductor current originally flowing in the low-side NFET and into the SW pin commutates to the high-side PFET’s
body diode and ramps back to zero. At this point, the SW pin becomes a high impedance node and ringing can
be observed on the SW node as the stored energy in the inductor is dissipated while resonating with the parasitic
nodal capacitance.
7.3.9 Overtemperature Protection
When the LM2854 senses a junction temperature greater than 165°C, both switching FETs are turned off and the
part enters a sleep state. Upon sensing a junction temperature below 155°C, the part will re-initiate the soft-start
sequence and begin switching once again. This feature is provided to prevent catastrophic failure due to
excessive thermal dissipation.
7.3.10 Loop Compensation
The LM2854 preserves flexibility by integrating the control components around the error amplifier while using
three small external compensation components from VOUT to FB. An integrated type II (two pole, one zero)
voltage-mode compensation network is featured. To ensure stability, an external resistor and small value
capacitor can be added across the upper feedback resistor as a pole-zero pair to complete a type III (three pole,
two zero) compensation network. For correct selection of these components, see Detailed Design Procedure.
7.4 Device Functional Modes
7.4.1 Shutdown Mode
If EN is less than VIH – VEN(HSY), the LM2854 shuts down. Most internal circuitry is shut down, and the SW output
is high-impedance. Once EN voltage exceeds VIH, the LM2854 enters soft-start mode.
7.4.2 Soft-Start and Track Mode
Once operation is initiated, the LM2854 starts charging its SS node. If a voltage is already present on the
LM2854 circuit output, the LM2854 does not attempt to pull the circuit output low. If only a capacitor is connected
to the SS pin, voltage on this pin rises, and once voltage exceeds 0.8 V, normal operating mode commences. If
the high-side current limit is exceeded, the voltage on the SS pin is reduced, prolonging soft-start and track
mode.
If a resistor divider is used to connect the SS pin to another power supply, Soft Start and Track mode can be
used to cause the output of the LM2854 Buck to track this supply.
7.4.3 Normal Operating Mode
If the EN input of the LM2854 is above VIH and the SS pin is above 0.8 V, output is regulated normally. If EN is
reduced to less than VIH – VEN(HSY), the LM2854 enters shutdown mode. If the high-side current limit is activated
or SS is pulled to below 0.8 V, the LM2854 enters soft-start and track mode.
Copyright © 2008–2017, Texas Instruments Incorporated
11
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM2854 is designed to convert voltage between 2.95 V and 5.5 V to a well-regulated voltage between input
voltage and 0.8 V.
8.2 Typical Application
V
IN
L
O
V
OUT
LM2854
SW
FB
PVIN
AVIN
EN
C
O
C
IN
AGND
PGND
SS
R
FB1
C
SS
C
R
COMP
COMP
R
FB2
Figure 15. Typical Application Diagram
8.2.1 Design Requirements
Before starting a design, the following five design criteria should be considered. These criteria are the basic
inputs into the detailed design procedure listed below.
•
•
•
Output voltage: Choose an output voltage between 0.8 V and the lowest expected input voltage.
Size vs efficiency: Choose 1 MHz for small physical size, and 500 kHz switching frequency for efficiency.
Step load response and ripple: Use this criterion to select output capacitance. Also see compensation in
Detailed Design Procedure.
•
•
UVLO: Input UVLO voltage should be selected. A voltage divider connected to the EN input can be used to
select input start-up voltage.
Tracking: If tracking is desired, a voltage divider can be connected to the SS node.
8.2.2 Detailed Design Procedure
8.2.2.1 Input Filter Capacitor
Fast switching currents place a large strain on the input supply to a buck regulator. A capacitor placed close to
the PVIN and PGND pins of the LM2854 helps to supply the instantaneous charge required when the regulator
demands a pulse of current every switching cycle. In fact, the input capacitor conducts a square-wave current of
peak-to-peak amplitude equal to IOUT. With this high AC current present in the input capacitor, the RMS current
rating becomes an important parameter. The necessary RMS current rating of the input capacitor to a buck
regulator can be estimated using Equation 1.
ICin(RMS) = IOUT
D(1-D)
(1)
where the PWM duty cycle, D, is given in Equation 2.
VOUT
D =
VIN
(2)
12
Copyright © 2008–2017, Texas Instruments Incorporated
LM2854
www.ti.com.cn
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
Typical Application (continued)
Neglecting capacitor ESR, the resultant input capacitor AC ripple voltage is a triangular waveform with peak-to-
peak amplitude specified in Equation 3.
VOUTD(1-D)
DVin =
fSWCIN
(3)
The maximum input capacitor ripple voltage and RMS current occur at 50% duty cycle. A 22-µF or 47-µF high-
quality dielectric (X5R, X7R) ceramic capacitor with adequate voltage rating is typically sufficient as an input
capacitor to the LM2854. The input capacitor should be placed as close as possible to the PVIN and PGND pins
to substantially eliminate the parasitic effects of any stray inductance or resistance on the PC board and supply
lines. Additional bulk capacitance with higher ESR may be required to damp any resonance effects of the input
capacitance and parasitic inductance.
8.2.2.2 AVIN Filtering Components
In addition to the large input filter capacitor, a smaller ceramic capacitor such as a 0.1 µF or 1.0 µF is
recommended between AVIN and AGND to filter high frequency noise present on the PVIN rail from the quiet
AVIN supply. For additional filtering in noisy environments, a small RC filter can be used on the AVIN pin as
shown below.
V
IN
LM2854
PVIN
AVIN
SW
FB
R
F
EN
C
IN
C
F
AGND
SS
PGND
Figure 16. Filtering of AVIN
In general, RF is typically selected between 1 Ω and 10 Ω so that the steady state voltage drop across the
resistor due to the AVIN bias current does not affect the UVLO level. Recommended filter capacitor, CF, is 1 µF
in X5R or X7R dielectric.
8.2.2.3 Soft-Start Capacitor
When the LM2854 is enabled, the output voltage will ramp up linearly in the time dictated by the relationship
shown in Equation 4.
CSS x VREF
tSS
=
ISS
(4)
where VREF is the internal reference voltage (nominally 0.8V), ISS is the soft-start charging current (nominally 2
µA) and CSS is the external soft-start capacitance. Rearranging this equation allows for the necessary soft-start
capacitor for a given start-up time to be calculated as in Equation 5.
tSS x 2 mA
CSS
=
0.8V
(5)
(6)
Thus, the required soft start capacitor per unit output voltage start-up time is given in Equation 6.
CSS = 2.5 nF / ms
For example, a 10 nF soft-start capacitor will yield a 4 ms soft-start time.
8.2.2.4 Tracking - Equal Soft-Start Time
One way to use the tracking feature is to design the tracking resistor divider so that the master supply output
voltage, VOUT1, and the LM2854 output voltage, VOUT2, both rise together and reach their target values at the
same time. This is termed ratiometric start-up. For this case, the equation governing the values of tracking divider
resistors RT1 and RT2 is given in Equation 7.
Copyright © 2008–2017, Texas Instruments Incorporated
13
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
www.ti.com.cn
Typical Application (continued)
RT2
RT1
=
VOUT1 -1.0V
(7)
The above equation includes an offset voltage to ensure that the final value of the SS pin voltage exceeds the
reference voltage of the LM2854. This offset will cause the LM2854 output voltage to reach regulation slightly
before the master supply. A value of 33 kΩ 1% is recommended for RT2 as a compromise between high
precision and low quiescent current through the divider while minimizing the effect of the 2 µA soft-start current
source.
For example, If the master supply voltage VOUT1 is 3.3V and the LM2854 output voltage was 1.8V, then the value
of RT1 needed to give the two supplies identical soft-start times would be 14.3 kΩ. A timing diagram for this
example, the equal soft-start time case, is shown in Figure 17.
RATIOMETRIC STARTUP
VOUT1
VOUT2
EN
TIME
Figure 17. Simplified Start-up Waveforms When Using Proportional Tracking
8.2.2.5 Tracking - Equal Slew Rates
Alternatively, the tracking feature can be used to have similar output voltage ramp rates. This is referred to as
simultaneous start-up. In this case, the tracking resistors can be calculated using Equation 8.
0.8V
RT2
RT1
=
VOUT2 - 0.8V
(8)
(9)
and to ensure proper overdrive of the SS pin as calculated in Equation 9.
VOUT2 < 0.8 VOUT1
For the example case of VOUT1 = 5 V and VOUT2 = 2.5 V, with RT2 set to 33 kΩ as before, RT1 is calculated from
the above equation to be 15.5 kΩ. A timing diagram for the case of equal slew rates is shown in Figure 18.
SIMULTANEOUS STARTUP
VOUT1
VOUT2
EN
TIME
Figure 18. Simplified Start-up Waveforms, Showing Tracking Used to Achieve Equal Slew Rates
14
Copyright © 2008–2017, Texas Instruments Incorporated
LM2854
www.ti.com.cn
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
Typical Application (continued)
8.2.2.6 Enable and UVLO
Using a resistor divider from VIN to EN as shown in the schematic diagram below, the input voltage at which the
part begins switching can be increased above the normal input UVLO level as shown in Equation 10.
REN1 + REN2
VIN(UVLO) = 1.23V
REN2
(10)
For example, suppose that the required input UVLO level is 3.69 V. Choosing REN2 = 10 kΩ, then we calculate
REN1 = 20 kΩ.
V
IN
LM2854
PVIN
SW
FB
AVIN
EN
R
R
EN1
C
IN
SS
AGND
PGND
EN2
Figure 19. Simplified Schematic Showing Use of EN as an Input UVLO
Alternatively, the EN pin can be driven from another voltage source to cater for system sequencing requirements
commonly found in FPGA and other multi-rail applications. The following schematic shows an LM2854 that is
sequenced to start based on the voltage level of a master system rail.
V
OUT1
V
IN
LM2854
L
O
V
OUT2
PVIN
SW
FB
R
EN1
AVIN
EN
C
O
C
IN
R
EN2
SS
AGND
PGND
Figure 20. Simplified Schematic Showing EN Used to Cascade Power Supply Start-up
8.2.2.7 Output Voltage Setting
A divider resistor network from VOUT to the FB pin determines the desired output voltage as shown in
Equation 11.
RFB1 + RFB2
VOUT = 0.8V
RFB2
(11)
RFB1 is defined based on the voltage loop requirements and RFB2 is then selected for the desired output voltage.
These resistors are normally selected as 0.5% or 1% tolerance.
8.2.2.8 Compensation Component Selection
The power stage transfer function of a voltage mode buck converter has a complex double pole related to the LC
output filter and a left half plane zero due to the output capacitor ESR, denoted RESR. The locations of these
singularities are given respectively in Equation 12.
Copyright © 2008–2017, Texas Instruments Incorporated
15
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
www.ti.com.cn
Typical Application (continued)
1
1
@
fLC
=
2p
LOCO
RESR + RL
RDCR + RL
2p LOCO
fESR
1
=
2pRESRCO
where
•
•
•
CO is the output capacitance value appropriately derated for applied voltage and operating temperature
RL is the effective load resistance
RDCR is the series damping resistance associated with the inductor and power switches
(12)
VIN
RDCR LO
LM2854
VOUT
SW
PVIN
EN
RESR
CO
RL
Ramp
Error
AVIN
V
REF
Amp
-
+
RFB1
+
-
FB
PWM
Comp
RCOMP
RFB2
CCOMP
SS
AGND
PGND
Figure 21. LM2854 Compensation Scheme
The conventional compensation strategy employed with voltage mode control is to use two compensator zeros to
offset the LC double pole, one compensator pole located to cancel the output capacitor ESR zero and one
compensator pole located between one third and one half switching frequency for high frequency noise
attenuation.
The LM2854 internal compensation components are designed to locate a pole at the origin and a pole at high
frequency as mentioned above. Furthermore, a zero is located at 8.8 kHz or 17.6 kHz for the 500 kHz or 1 MHz
options, respectively, to approximately cancel the likely location of one LC filter pole.
The three external compensation components, RFB1, RCOMP and CCOMP, are selected to position a zero at or
below the LC pole location and a pole to cancel the ESR zero. The voltage loop crossover frequency, floop, is
usually selected between one tenth to one fifth of the switching frequency, as shown in Equation 13.
0.1fSW ≤ floop ≤ 0.2fSW
(13)
A simple solution for the required external compensation capacitor, CCOMP, with type III voltage mode control can
be expressed as in Equation 14.
LO(mH)CO(mF)
CCOMP(pF) = a
floop (kHz)
VIN (V)
(14)
where the constant α is nominally 0.038 or 0.075 for the 500 kHz or 1 MHz options, respectively. This assumes a
compensator pole cancels the output capacitor ESR zero. Furthermore, since the modulator gain is proportional
to VIN, the loop crossover frequency increases with VIN. Thus, it is recommended to design the loop at maximum
expected VIN.
The upper feedback resistor, RFB1, is selected to provide adequate mid-band gain and to locate a zero at or
below the LC pole frequency. The series resistor, RCOMP, is selected to locate a pole at the ESR zero frequency,
as shown in Equation 15.
16
Copyright © 2008–2017, Texas Instruments Incorporated
LM2854
www.ti.com.cn
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
Typical Application (continued)
1
RFB1
=
2pCCOMP LC
f
1
RCOMP
=
2pCCOMP ESR
f
(15)
Note that the lower feedback resistor, RFB2, has no impact on the control loop from an AC standpoint since the
FB pin is the input to an error amplifier and effectively at AC ground. Hence, the control loop can be designed
irrespective of output voltage level. The only caveat here is the necessary derating of the output capacitance with
applied voltage. Having chosen RFB1 as above, RFB2 is then selected for the desired output voltage.
Table 1 and Table 2 list inductor and ranges of capacitor values that work well with the LM2854, along with the
associated compensation components to ensure stable operation. Values different than those listed may be
used, but the compensation components may need to be recalculated to avoid degradation in phase margin.
Note that the capacitance ranges specified refer to in-circuit values where the nominal capacitance value is
adequately derated for applied voltage.
8.2.2.9 Filter Inductor and Output Capacitor Selection
In a buck regulator, selection of the filter inductor and capacitor will affect many key system parameters,
including stability, transient response and efficiency The LM2854 can accommodate relatively wide ranges of
output capacitor and filter inductor values in a typical application and still achieve excellent load current transient
performance and low output voltage ripple.
The inductance is chosen such that the peak-to-peak inductor current ripple, ΔiL, is approximately 25 to 40% of
IOUT as shown in Equation 16.
VOUT(1-D)
VOUT(1-D)
@
LO =
DiLfSW
0.3IOUTfSW
(16)
Note that the peak inductor current is the DC output current plus half the ripple current and reaches its highest
level at lowest duty cycle (or highest VIN). It is recommended that the inductor should have a saturation current
rating in excess of the current limit level.
When operating the LM2854 at input voltages above 5.2 V, the inductor should be sized to keep the minimum
inductor current above –0.5 A. For most applications this should only occur at light loads or when the inductor is
drastically undersized. To ensure the current never goes below –0.5 A for any application, the peak-to-peak
ripple current (ΔiL) in the inductor should be less than 1 A. Keeping the minimum inductor current above –0.5 A
limits the energy storage in the inductor and helps prevent the switch node voltage from exceeding the absolute
maximum specification when the low side FET turns off.
Table 3 lists examples of off-the-shelf powdered iron and ferrite based inductors that are suitable for use with the
LM2854. The output capacitor can be of ceramic or electrolytic chemistry. The chosen output capacitor requires
sufficient DC voltage rating and RMS ripple current handling capability.
The output capacitor RMS current and peak-to-peak output ripple are given respectively as in Equation 17.
DiL
ICout(RMS)
=
12
2
1
2
DVOUT = DiL
RESR
+
8fSWCO
(17)
In general, 22 µF to 100 µF of ceramic output capacitance is sufficient for both LM2854 frequency options given
the optimal high frequency characteristics and low ESR of ceramic dielectric. It is advisable to consult the
manufacturer’s derating curves for capacitance voltage coefficient as the in-circuit capacitance may drop
significantly with applied voltage.
Copyright © 2008–2017, Texas Instruments Incorporated
17
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
www.ti.com.cn
Typical Application (continued)
Tantalum or organic polymer electrolytic capacitance may be suitable with the LM2854 500 kHz option,
particularly in applications where substantial bulk capacitance per unit volume is required. However, the high
loop bandwidth achievable with the LM2854 obviates the necessity for large bulk capacitance during transient
loading conditions.
Table 4 lists some examples of commercially available capacitors that can be used with the LM2854.
Table 1. LM2854 500-kHz Compensation Component Values
CO (µF)
ESR (mΩ)
MIN
VIN (V)
LO (µH)
RFB1 (kΩ)
CCOMP (pF)
RCOMP (kΩ)
MIN
40
MAX
100
200
220
100
200
220
100
200
220
100
200
220
MAX
10
5
1.5
1.5
1.5
2.2
2.2
2.2
1.5
1.5
1.5
2.2
2.2
2.2
2
1
150
150
150
150
150
120
150
100
100
150
100
100
47
1
1
100
100
40
100
120
68
15
2
25
10
5
25
1
5
100
100
40
1
120
120
68
1
15
2
25
10
5
15
1
100
100
40
1
150
150
100
220
220
1
15
2
25
10
5
15
1
3.3
100
100
1
1
15
25
10
Table 2. LM2854 1-MHz Compensation Component Values
CO (µF)
ESR (mΩ)
MIN
VIN (V)
LO (µH)
RFB1 (kΩ)
CCOMP (pF)
RCOMP (kΩ)
MIN
20
MAX
60
MAX
10
5
0.68
0.68
0.68
1
2
1
120
75
33
100
100
56
1
1
60
150
220
60
100
20
15
2
25
10
5
100
100
75
20
1
5
1
60
150
220
60
1
150
150
56
1
1
100
20
15
2
25
10
5
75
15
1
0.68
0.68
0.68
1
75
60
150
220
60
1
50
150
150
82
1
100
20
15
2
25
10
5
50
12
1
3.3
75
1
60
150
220
1
50
220
330
1
1
100
15
25
33
10
Table 3. Recommended Filter Inductors
INDUCTANCE (µH)
DCR (mΩ)
MANUFACTURER
Vishay Dale
Vishay Dale
Vishay Dale
Vishay Dale
Vishay Dale
Vishay Dale
Vishay Dale
Vishay Dale
MANUFACTURER P/N
IHLP1616BZERR47M11
CASE SIZE (mm)
4.06 × 4.45 × 2.00
4.06 × 4.45 × 2.00
6.47 × 6.86 × 1.80
6.47 × 6.86 × 2.40
6.47 × 6.86 × 2.40
6.47 × 6.86 × 2.40
6.47 × 6.86 × 2.40
6.47 × 6.86 × 2.40
0.47
1
14.5
24
IHLP1616BZER1R0M11
IHLP2525AHERR47M01
IHLP2525BDERR47M01
IHLP2525BDERR68M01
IHLP2525BDERR82M01
IHLP2525BDER1R0M01
IHLP2525BDER1R5M01
0.47
0.47
0.68
0.82
1
8.4
6
8.7
10.6
13.1
18.5
1.5
18
Copyright © 2008–2017, Texas Instruments Incorporated
LM2854
www.ti.com.cn
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
Table 3. Recommended Filter Inductors (continued)
INDUCTANCE (µH)
DCR (mΩ)
15.7
3.5
MANUFACTURER
Vishay Dale
Sumida
Sumida
Sumida
Sumida
Sumida
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Coilcraft
TDK
MANUFACTURER P/N
IHLP2525CZER2R2M11
CDMC6D28NP-R47M
CDMC6D28NP-R68M
CDMC6D28NP-1R0M
CDMC6D28NP-1R5M
CDMC6D28NP-2R2M
DO1813H-561ML
CASE SIZE (mm)
6.47 × 6.86 × 3.00
6.50 × 7.25 × 3.00
6.50 × 7.25 × 3.00
6.50 × 7.25 × 3.00
6.50 × 7.25 × 3.00
6.50 × 7.25 × 3.00
6.10 × 8.89 × 5.00
7 × 7 × 3
2.2
0.47
0.68
1
4.5
17.3
10.4
16.1
10
1.5
2.2
0.56
0.47
0.68
1
3.3
HA3619-471ALC
4.8
HA3619-681ALC
7 × 7 × 3
7.5
HA3619-102ALC
7 × 7 × 3
1.2
1.5
1.8
0.47
0.68
1
9.4
HA3619-122ALC
7 × 7 × 3
11.5
16.5
3.3
HA3619-152ALC
7 × 7 × 3
HA3619-182ALC
7 × 7 × 3
SPM6530T-R47M170
SPM6530T-R68M140
SPM6530T-1R0M120
SPM6530T-1R5M100
PCMC042T-0R47MN
PCMC063T-1R0MN
PCMC063T-1R5MN
7.1 × 6.5 × 3
7.1 × 6.5 × 3
7.1 × 6.5 × 3
7.1 × 6.5 × 3
4 × 4.5 × 2
4.9
TDK
7.1
TDK
1.5
0.47
1.0
1.5
9.7
TDK
14
Cyntec
9
Cyntec
6.5 × 6.9 × 3
6.5 × 6.9 × 3
14
Cyntec
Table 4. Recommended Filter Capacitors
CAPACITANCE VOLTAGE (V), ESR
CHEMISTRY
MANUFACTURER MANUFACTURER P/N
CASE SIZE
(µF)
(mΩ)
22
6.3, < 5
6.3, < 5
6.3, < 5
10, < 5
6.3, < 5
6.3, 50
6.3, 25
6.3, 18
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Tantalum
TDK
TDK
C3216X5R0J226M
C3216X5R0J476M
C3225X5R0J476M
C3225X5R1A476M
C3225X5R0J107M
TPSD157M006#0050
6TPE100MPB2
1206
1206
47
47
TDK
1210
47
TDK
1210
100
100
100
150
TDK
1210
AVX
D, 7.5 × 4.3 × 2.9 mm
B2, 3.5 × 2.8 × 1.9 mm
C2, 6 × 3.2 × 1.8 mm
Organic Polymer
Organic Polymer
Sanyo
Sanyo
6TPE150MIC2
D3L, 7.3 × 4.3 × 2.8
mm
330
470
6.3, 18
6.3, 23
Organic Polymer
Niobium Oxide
Sanyo
AVX
6TPE330MIL
NOME37M006#0023
E, 7.3 × 4.3 × 4.1 mm
Copyright © 2008–2017, Texas Instruments Incorporated
19
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
www.ti.com.cn
8.2.3 Application Curves
Unless otherwise specified, the following conditions apply: VIN = PVIN = AVIN = EN = 5 V, CIN is 47-μF 10-V X5R ceramic
capacitor, LO is from TDK SPM6530T family; TAMBIENT = 25°C.
97
96
95
92
90
88
86
84
82
80
78
76
74
V
= 3.3V
IN
V
= 3.3V
IN
94
93
92
V
IN
= 5.0V
V
= 5.0V
IN
91
90
89
0
1
2
3
4
0
1
2
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 22. LM2854 1-MHz Efficiency vs IOUT VOUT = 0.8 V,
Figure 23. LM2854 1-MHz Efficiency vs IOUT VOUT = 2.5 V,
LO = 0.47 µH, 3.3-mΩ DCR
LO = 1 µH, 7.1-mΩ DCR
94
98
97
V
IN
= 3.3V
92
90
V
= 4.0V
IN
96
95
94
V
= 5.0V
IN
88
86
84
V
= 5.0V
IN
93
92
82
80
0
1
2
3
4
0
1
2
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 24. LM2854 1-MHz Efficiency vs IOUT VOUT = 1.2 V,
Figure 25. LM2854 1-MHz Efficiency vs IOUT VOUT = 3.3 V,
LO = 0.68 µH, 4.9-mΩ DCR
LO = 1 µH, 7.1-mΩ DCR
96
94
94
92
90
V
= 3.3V
IN
V
= 5.0V
IN
92
90
88
88
86
84
82
80
78
76
V
= 5.0V
IN
V
= 3.3V
IN
86
84
0
1
2
3
4
0
1
2
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 26. LM2854 1-MHz Efficiency vs IOUT VOUT = 1.8 V,
Figure 27. LM2854 500-kHz Efficiency vs IOUT VOUT = 0.8 V,
LO = 1 µH, 7.1-mΩ DCR
LO = 1 µH, 7.1-mΩ DCR
20
Copyright © 2008–2017, Texas Instruments Incorporated
LM2854
www.ti.com.cn
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
Unless otherwise specified, the following conditions apply: VIN = PVIN = AVIN = EN = 5 V, CIN is 47-μF 10-V X5R ceramic
capacitor, LO is from TDK SPM6530T family; TAMBIENT = 25°C.
96
94
92
99
98
97
96
95
94
93
92
91
90
V
= 3.3V
IN
90
88
86
V
IN
= 5.0V
V
= 5.0V
IN
V
= 3.3V
IN
84
82
80
0
1
2
3
4
0
1
2
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 28. LM2854 500-kHz Efficiency vs IOUT VOUT = 2.5 V,
Figure 29. LM2854 500-kHz Efficiency vs IOUT VOUT = 1.2 V,
LO = 2.2 µH, 16-mΩ DCR
LO = 1.5 µH, 9.7-mΩ DCR
99
98
98
96
V
= 4.0V
V
= 3.3V
IN
IN
97
94
96
95
94
92
90
88
V
= 5.0V
IN
V
= 5.0V
IN
93
92
86
84
0
1
2
3
4
0
1
2
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 30. LM2854 500-kHz Efficiency vs IOUT VOUT = 3.3 V,
Figure 31. LM2854 500-kHz Efficiency vs IOUT VOUT = 1.8 V,
LO = 1.5 µH, 9.7-mΩ DCR
LO = 1.5 µH, 9.7-mΩ DCR
Figure 32. LM2854 1-MHz Bode Plot VIN = 3.3 V, VOUT = 1.8
V, IOUT = 4 A RFB1 = 150 kΩ, RCOMP = 1 kΩ, CCOMP = 100 pF,
LOUT = 0.82 µH, COUT = 100-µF Ceramic
Figure 33. LM2854 500-kHz Bode Plot VIN = 3.3 V,
VOUT = 1.8 V, IOUT = 4 A RFB1 = 250 kΩ, RCOMP = 1 kΩ,
CCOMP = 47 pF, LOUT = 1.5 µH, COUT = 100-µF Ceramic
Copyright © 2008–2017, Texas Instruments Incorporated
21
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
www.ti.com.cn
Unless otherwise specified, the following conditions apply: VIN = PVIN = AVIN = EN = 5 V, CIN is 47-μF 10-V X5R ceramic
capacitor, LO is from TDK SPM6530T family; TAMBIENT = 25°C.
Figure 35. LM2854 500-kHz Bode Plot VIN = 5 V,
VOUT = 1.8 V, IOUT = 4 A RFB1 = 250 kΩ, RCOMP = 1 kΩ,
CCOMP = 47 pF, LOUT = 1.5 µH, COUT = 100-µF Ceramic
Figure 34. LM2854 1-MHz Bode Plot VIN = 5 V, VOUT = 1.8 V,
IOUT = 4 A RFB1 = 150 kΩ, RCOMP = 1 kΩ, CCOMP = 100 pF,
LOUT = 0.82 µH, COUT = 100 µF
Figure 36. LM2854 1-MHz Bode Plot VIN = 5 V, VOUT = 3.3 V,
IOUT = 4 A RFB1 = 150 kΩ, RCOMP = 1 kΩ, CCOMP = 68 pF,
LOUT = 0.82 µH, COUT = 100-µF Ceramic
Figure 37. LM2854 500-kHz Bode Plot VIN = 5 V,
VOUT = 3.3 V, IOUT = 4 A RFB1 = 250 kΩ, RCOMP = 1 kΩ,
CCOMP = 33 pF, LOUT = 1.5 µH, COUT = 100-µF Ceramic
Figure 39. LM2854 500-kHz Power On through Enable
VIN = 5 V, VOUT = 1.8 V, IOUT = 4 A, CSS = 220 pF
Figure 38. LM2854 500-kHz Power On Characteristic
VIN = 5 V, VOUT = 1.8 V, IOUT = 4 A, CSS = 220 pF
22
Copyright © 2008–2017, Texas Instruments Incorporated
LM2854
www.ti.com.cn
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
Unless otherwise specified, the following conditions apply: VIN = PVIN = AVIN = EN = 5 V, CIN is 47-μF 10-V X5R ceramic
capacitor, LO is from TDK SPM6530T family; TAMBIENT = 25°C.
Figure 40. LM2854 500-kHz Power Off Characteristic
VIN = 5 V, VOUT = 1.8 V, IOUT = 4 A, CSS = 220 pF
Figure 41. LM2854 1-MHz Load Transient Response
VIN = 5 V, VOUT = 3.3 V, IOUT = 0.5-A to 4-A to 0.5-A step
di/dt ≊ 4 A/µs, CO = 100-µF Ceramic
Figure 43. LM2854 500-kHz Pre-Biased Start-up Waveform
(Oscilloscope Set at Infinite Persistence) VOUT = 2.5 V,
IOUT = 0 A, VPRE-BIAS = 1.25 V
Figure 42. LM2854 500-kHz Start-up Waveform VOUT
2.5 V, IOUT = 0 A
=
8.2.4 System Examples
This section provides several application solutions with an associated bill of materials, listed in Table 5 to
Table 7. All bill of materials reference the schematic in Figure 44. The compensation for each solution was
optimized to work over the full input range. Many applications have a fixed input voltage rail. It is possible to
modify the compensation to obtain a faster transient response for a given input voltage operating point.
V
IN
U1
L
O
V
OUT
LM2854
SW
FB
PVIN
EN
C
O
R
C
F
C
IN
AVIN
SS
AGND
PGND
F
R
FB1
C
SS
C
R
COMP
COMP
R
FB2
Figure 44. LM2854 Application Circuit Schematic
Copyright © 2008–2017, Texas Instruments Incorporated
23
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
www.ti.com.cn
Unless otherwise specified, the following conditions apply: VIN = PVIN = AVIN = EN = 5 V, CIN is 47-μF 10-V X5R ceramic
capacitor, LO is from TDK SPM6530T family; TAMBIENT = 25°C.
Table 5. LM2854 500-kHz Bill of Materials, VIN = 5 V, VOUT = 3.3 V, IOUT(MAX) = 4 A, Optimized for
Efficiency
REF DES
DESCRIPTION
CASE SIZE
MANUFACTURER
MANUFACTURER P/N
Synchronous Buck
Regulator
U1
HTSSOP-16
Texas Instruments
LM2854MHX-500
CIN
CO
47 µF, X5R, 10 V
100 µF, X5R, 6.3 V
1.5 µH, 9.7 mΩ, 10 A
249 kΩ
1210
1210
TDK
TDK
C3225X5R1A476M
C3225X5R0J107M
LO
7.1 × 6.5 × 3.0 mm
0603
TDK
SPM6530T-1R5M100
CRCW06032493F-e3
CRCW060328062F-e3
CRCW06031001F-e3
CRCW06031R0F-e3
C1608C0G1H330J
RFB1
RFB2
RCOMP
RF
Vishay Dale
Vishay Dale
Vishay Dale
Vishay Dale
TDK
80.6 kΩ
0603
1 kΩ
0603
1 Ω
0603
CCOMP
CSS
CF
33 pF, ±5%, C0G, 50 V
10 nF, ±10%, X7R, 16 V
1.0 µF, ±10%, X7R, 10 V
0603
0603
Murata
GRM188R71C103KA01
GRM188R71A105KA61
0603
Murata
Table 6. LM2854 1-MHz Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 4 A, Optimized for
Electrolytic Input and Output Capacitance
REF DES
U1
DESCRIPTION
Synchronous Buck Regulator
150 µF, 6.3 V, 18 mΩ
330 µF, 6.3 V, 18 mΩ
2.2 µH, 16 mΩ, 7 A
100 kΩ
CASE SIZE
MANUFACTURER
Texas Instruments
Sanyo
MANUFACTURER P/N
LM2854MHX-1000
6TPE150MIC2
HTSSOP-16
CIN
C2, 6 × 3.2 × 1.8 mm
CO
D3L, 7.3 × 4.3 × 2.8 mm
Sanyo
6TPE330MIL
LO
6.47 × 6.86 × 3 mm
Vishay Dale
Vishay Dale
Vishay Dale
Vishay Dale
Vishay Dale
TDK
IHLP2525CZER2R2M11
CRCW06031003F-e3
CRCW060324752F-e3
CRCW06031502F-e3
CRCW06031R0F-e3
C1608C0G1H331J
GRM188R71C103KA01
GRM188R71A105KA61
RFB1
RFB2
RCOMP
RF
0603
0603
0603
0603
0603
0603
0603
47.5 kΩ
15 kΩ
1 Ω
CCOMP
CSS
330 pF, ±5%, C0G, 50 V
10 nF, ±10%, X7R, 16 V
1 µF,±10%, X7R, 10 V
Murata
CF
Murata
Table 7. LM2854 1-MHz Bill of Materials, VIN = 3.3 V, VOUT = 0.8 V, IOUT (MAX) = 4 A, Optimized for Solution
Size and Transient Response
REF DES
U1
DESCRIPTION
Synchronous Buck Regulator
47 µF, X5R, 6.3 V
47 µF, X5R, 6.3 V
0.47 µH, 14.5 mΩ, 7 A
110 kΩ
CASE SIZE
MANUFACTURER
Texas Instruments
TDK
MANUFACTURER P/N
LM2854MHX-1000
HTSSOP-16
CIN
1206
C3216X5R0J476M
CO
1206
TDK
C3216X5R0J476M
LO
4.06 × 4.45 × 2.00 mm
Vishay Dale
Vishay Dale
Vishay Dale
Vishay Dale
Murata
IHLP1616BZER0R47M11
CRCW04021103F-e3
CRCW04021001F-e3
CRCW04021R0F-e3
GRM1555C1H270JZ01
GRM155R71C103KA01
GRM155R61A105KE15
RFB1
RCOMP
RF
0402
0402
0402
0402
0402
0402
1 kΩ
1 Ω
CCOMP
CSS
27 pF, ±5%, C0G, 50 V
10 nF, ±10%, X7R, 16 V
1 µF, ±10%, X7R, 10 V
Murata
CF
Murata
24
Copyright © 2008–2017, Texas Instruments Incorporated
LM2854
www.ti.com.cn
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
9 Power Supply Recommendations
The LM2854 is designed to operate from an input voltage supply range from 2.95 V to 5.5 V. This input supply
should be able to source the maximum input current and maintain a voltage above either 2.95 V or the output
voltage, whichever is higher. In cases where input supply is located at a distance (more than a few inches) from
the device, drop due to traces and wires must be considered.
10 Layout
10.1 Layout Guidelines
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops.
There are two loops where currents are switched at high di/dt slew rates in a buck regulator. The first loop
represents the path taken by AC current flowing during the high side PFET on time. This current flows from
the input capacitor to the regulator PVIN pins, through the high side FET to the regulator SW pin, filter
inductor, output capacitor and returning via the PCB ground plane to the input capacitor.
The second loop represents the path taken by AC current flowing during the low side NFET on time. This
current flows from the output capacitor ground to the regulator PGND pins, through the NFET to the inductor
and output capacitor. From an EMI reduction standpoint, it is imperative to minimize this loop area during PC
board layout by physically locating the input capacitor close to the LM2854. Specifically, it is advantageous to
place CIN as close as possible to the LM2854 PVIN and PGND pins. Grounding for both the input and output
capacitor should consist of a localized top side plane that connects to PGND and the exposed die attach pad
(DAP). The inductor should be placed close to the SW pin and output capacitor.
2. Minimize the copper area of the switch node.
The LM2854 has two SW pins optimally located on one side of the package. In general the SW pins should
be connected to the filter inductor on the top PCB layer. The inductor should be placed close to the SW pins
to minimize the copper area of the switch node.
3. Have a single point ground for all device analog grounds located under the DAP.
The ground connections for the Feedback, Soft-start, Enable and AVIN components should be routed to the
AGND pin of the device. The AGND pin should connect to PGND under the DAP. This prevents any
switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding
can result in degraded load regulation or erratic switching behavior.
4. Minimize trace length to the FB pin.
Since the feedback (FB) node is high impedance, the trace from the output voltage setpoint resistor divider to
FB pin should be as short as possible. This is most important as relatively high value resistors are used to
set the output voltage. The FB trace should be routed away from the SW pin and inductor to avoid noise
pickup from the SW pin. Both feedback resistors, RFB1 and RFB2, and the compensation components, RCOMP
and CCOMP, should be located close to the FB pin.
5. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing
so will correct for voltage drops and provide optimum output accuracy.
6. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the DAP to the ground plane on the bottom PCB layer. If the
PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner
layer heat-spreading ground planes. For best results use a 5 x 3 via array with minimum via diameter of 10
mils. Ensure enough copper area is used to keep the junction temperature below 125°C.
Copyright © 2008–2017, Texas Instruments Incorporated
25
LM2854
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
www.ti.com.cn
Layout Guidelines (continued)
7. Keep sensitive system signals away from SW node.
SW is a high-voltage, rapidly changing signal which can couple to adjacent signal lines. Signal integrity of
lines that have high impedances or are very sensitive to noise can be compromised by capacitive coupling to
SW node.
10.2 Layout Example
V
IN
L
O
V
OUT
LM2854
SW
PVIN
C
IN
C
O
PGND
Loop 2
Loop 1
Figure 45. High Current Loops
Guideline 4:
Minimize FB
node
Guideline 3:
Kelvin connect
AGND to DAP
Connect to VOUT
CCOMP
RFB1
Guideline 5: Wide
input and output
traces
Guideline 1:
RCOMP
minimize current
loops œ place CIN
adjacent to the
LM2854
PGND and
Thermal
RFB2
FB
GND
CSS
GND
AGND
SS
CIN
CO More COUT
More CIN
LO
Thermal
Connection
SW
+
+
EN
VIN
VOUT
AVIN
10 ꢁ
10 ꢀF
VIN
GND
GND and
Thermal
Guidelines 2 and 7: Minimize
SW node. The SW node is
should be designed to carry
output current but should not
be sized larger than
necessary. Also keep
sensitive signals away from
this node
GND
Guideline 5: Wide
input and output
traces
Guideline 6: Provide
adequate heat sinking using
thermal vias and wide
connections from GND to EP
Figure 46. Recommended Layout for the LM2854
26
版权 © 2008–2017, Texas Instruments Incorporated
LM2854
www.ti.com.cn
ZHCS532E –MARCH 2008–REVISED OCTOBER 2017
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
相关文档如下：
•
•
•
•
•
•
•
•
•
•
•
AN-1786《LM2854 500kHz 降压稳压器评估板》（版本B），SNVA323
AN-1880《LM2854 1MHz 降压稳压器演示板》（版本B），SNVA358
AN-1149《开关电源布局指南》，SNVA021
《AN-1229 PCB 布局指南》，SNVA054
《构建电源 - 布局注意事项》，SLUP230
《使用 LM4360x 与 LM4600x 简化低辐射 EMI 布局》，SNVA721
AN-2020《富于洞见的热设计》，SNVA419
AN-1520《外露焊盘封装实现最佳热敏电阻特性的电路板布线指南》，SNVA183
《半导体和 IC 封装热指标》，SPRA953
《使用 LM43603 与 LM43602 简化热设计》，SNVA719
《使用新的热指标》，SBVA025
11.2 商标
PowerWise is a trademark of Texas Instrumetns, Inc.
All other trademarks are the property of their respective owners.
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2008–2017, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM2854MH-1000
NRND
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
16
16
16
16
16
92
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LM2854
-1000
LM2854MH-1000/NOPB
LM2854MH-500/NOPB
LM2854MHX-1000/NOPB
LM2854MHX-500/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PWP
92
RoHS & Green
SN
SN
SN
SN
LM2854
-1000
PWP
92
RoHS & Green
LM2854
-500
PWP
2500 RoHS & Green
2500 RoHS & Green
LM2854
-1000
PWP
LM2854
-500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM2854MHX-1000/NOPB HTSSOP PWP
LM2854MHX-500/NOPB HTSSOP PWP
16
16
2500
2500
330.0
330.0
12.4
12.4
6.95
6.95
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM2854MHX-1000/NOPB
LM2854MHX-500/NOPB
HTSSOP
HTSSOP
PWP
PWP
16
16
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM2854MH-1000
LM2854MH-1000
PWP
PWP
PWP
PWP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
16
16
16
16
92
92
92
92
495
495
495
495
8
8
8
8
2514.6
2514.6
2514.6
2514.6
4.06
4.06
4.06
4.06
LM2854MH-1000/NOPB
LM2854MH-500/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
0.19
4.5
4.3
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
4X 0.166 MAX
NOTE 5
2X 1.34 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
3.3
2.7
17
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
3.3
2.7
4214868/A 02/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3.3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
17
SYMM
(3.3)
(5)
NOTE 9
14X (0.65)
8
9
(
0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4214868/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3.3)
17
SYMM
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.69 X 3.69
3.3 X 3.3 (SHOWN)
3.01 X 3.01
0.125
0.15
0.175
2.79 X 2.79
4214868/A 02/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明