LM2904LV-Q1 [TI]
LM290xLV Industry Standard, Low Voltage Operational Amplifiers;
| 型号： | LM2904LV-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LM290xLV Industry Standard, Low Voltage Operational Amplifiers |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM2902LV, LM2904LV
SBOS960C – SEPTEMBER 2018 – REVISED FEBRUARY 2022
LM290xLV Industry Standard, Low Voltage Operational Amplifiers
1 Features
3 Description
•
Industry standard amplifier for cost-sensitive
systems
Low input offset voltage: ±1 mV
Common-mode voltage range includes ground
Unity-gain bandwidth: 1 MHz
Low broadband noise: 40 nV/√Hz
Low quiescent current: 90 µA/Ch
Unity-gain stable
Operational at supply voltages from 2.7 V to 5.5 V
Offered in dual- and quad-channel variants
Robust ESD specification: 2-kV HBM
Extended temperature range: –40°C to 125°C
The LM290xLV family includes the dual LM2904LV
and quad LM2902LV operational amplifiers, or op
amps. The devices operate from a low voltage of
2.7 V to 5.5 V.
•
•
•
•
•
•
•
•
•
•
These op amps supply an alternative to the
LM2904 and LM2902 in low-voltage applications
that are sensitive to cost. Some applications are
large appliances, smoke detectors, and personal
electronics. The LM290xLV devices supply better
performance than the LM290x devices at low voltage,
and have lower power consumption. The op amps are
stable at unity gain, and do not have reverse phase
in overdrive conditions. The design for ESD gives the
LM290xLV family an HBM specification for a minimum
of 2 kV.
2 Applications
•
•
•
•
•
•
•
Cordless appliances
Uninterruptible power supply
Battery pack, charger, and test equipment
Power supply modules
Environmental sensors signal conditioning
Field transmitter: temperature sensors
Oscilloscopes, digital multimeters, and signal
analyzers
Rack mount server
HVAC: heating, ventilating, and air conditioning
DC motor control
The LM290xLV family is available in packages that
have industry standards. The packages include SOIC,
VSSOP, and TSSOP packages.
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
8.65 mm × 3.91 mm
4.40 mm × 5.00 mm
4.20 mm × 2.00 mm
3.91 mm × 4.90 mm
3.00 mm × 4.40 mm
1.60 mm × 2.90 mm
3.00 mm × 3.00 mm
SOIC (14)
•
•
•
•
LM2902LV
TSSOP (14)
SOT-23 (14)
SOIC (8)
Low-side current sensing
TSSOP (8)
SOT-23 (8)
VSSOP (8)
LM2904LV
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
RF
RG
R1
VOUT
VIN
C1
1
2pR1C1
f
=
-3 dB
VOUT
VIN
RF
1
1 + sR1C1
=
1 +
(
(
RG
Single-Pole, Low-Pass Filter
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM2902LV, LM2904LV
SBOS960C – SEPTEMBER 2018 – REVISED FEBRUARY 2022
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information: LM2904LV.................................5
6.5 Thermal Information: LM2902LV.................................6
6.6 Electrical Characteristics.............................................6
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................14
8 Application and Implementation..................................15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 15
9 Power Supply Recommendations................................17
9.1 Input and ESD Protection......................................... 17
10 Layout...........................................................................18
10.1 Layout Guidelines................................................... 18
10.2 Layout Example...................................................... 18
11 Device and Documentation Support..........................19
11.1 Documentation Support.......................................... 19
11.2 Receiving Notification of Documentation Updates..19
11.3 Support Resources................................................. 19
11.4 Trademarks............................................................. 19
11.5 Electrostatic Discharge Caution..............................19
11.6 Glossary..................................................................19
12 Mechanical, Packaging, and Orderable
Information.................................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2019) to Revision C (February 2022)
Page
•
•
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Added SOT-23 (DYY) package to Device Information table...............................................................................1
Added DYY (SOT-23) package to Pin Configuration and Functions section......................................................3
Added DYY (SOT-23) package to Thermal Information: LM2902LV section......................................................6
Changes from Revision A (May 2019) to Revision B (October 2019)
Page
•
Deleted all SOT-23 (DDF) preview notations......................................................................................................1
Changes from Revision * (September 2018) to Revision A (May 2019)
Page
•
•
•
Added SOT-23 (DDF) package to Device Information table...............................................................................1
Added DDF (SOT-23) package to Pin Configuration and Functions section......................................................3
Added DDF (SOT-23) Thermal Information: LM2904LV section........................................................................ 5
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5 Pin Configuration and Functions
OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
OUT2
IN2œ
IN2+
Not to scale
Figure 5-1. LM2904LV D, DGK, PW, and DDF Package
8-Pin SOIC, VSSOP, TSSOP, and SOT-23
(Top View)
Table 5-1. Pin Functions: LM2904LV
PIN
I/O
DESCRIPTION
NAME
NO.
2
IN1–
IN1+
IN2–
IN2+
I
I
Inverting input, channel 1
Noninverting input, channel 1
Inverting input, channel 2
Noninverting input, channel 2
Output, channel 1
3
6
I
5
I
OUT1
OUT2
V–
1
O
O
7
Output, channel 2
4
I or — Negative (low) supply or ground (for single-supply operation)
V+
8
I
Positive (high) supply
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OUT1
IN1œ
IN1+
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT4
IN4œ
IN4+
Vœ
IN2+
IN2œ
OUT2
IN3+
IN3œ
OUT3
8
Not to scale
Figure 5-2. LM2902LV D, PW, DYY and Package
14-Pin SOIC, TSSOP, and SOT-23
(Top View)
Table 5-2. Pin Functions: LM2902LV
PIN
I/O
DESCRIPTION
NAME
NO.
2
IN1–
IN1+
IN2–
IN2+
IN3–
IN3+
IN4–
IN4+
I
I
Inverting input, channel 1
Noninverting input, channel 1
Inverting input, channel 2
Noninverting input, channel 2
Inverting input, channel 3
Noninverting input, channel 3
Inverting input, channel 4
Noninverting input, channel 4
Output, channel 1
3
6
I
5
I
9
I
10
13
12
1
I
I
I
OUT1
OUT2
OUT3
OUT4
V–
O
O
O
O
7
Output, channel 2
8
Output, channel 3
14
11
4
Output, channel 4
I or — Negative (low) supply or ground (for single-supply operation)
V+
I
Positive (high) supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
0
MAX
UNIT
V
Supply voltage, ([V+] – [V–])
6
Common-mode
Voltage(2)
(V–) – 0.5
(V+) + 0.5
V
Signal input pins
Differential
(V+) – (V–) + 0.2
V
Current(2)
–10
–55
–65
10
mA
Output short-circuit(3)
Operating, TA
Continuous
125
°C
°C
°C
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
2.7
MAX
UNIT
V
VS
VIN
TA
Supply voltage [(V+) – (V–)]
Input-pin voltage range
Specified temperature
5.5
(V+) – 1
125
(V–) – 0.1
–40
V
°C
6.4 Thermal Information: LM2904LV
LM2904LV
THERMAL METRIC(1)
D (SOIC)
8 PINS
207.9
92.8
DGK (VSSOP)
8 PINS
201.2
PW (TSSOP)
8 PINS
200.7
DDF (SOT-23)
8 PINS
183.7
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
85.7
95.4
112.5
RθJB
ψJT
Junction-to-board thermal resistance
129.7
26
122.9
128.6
98.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
21.2
27.2
18.8
ψJB
127.9
121.4
127.2
97.6
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
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6.5 Thermal Information: LM2902LV
LM2902LV
PW (TSSOP)
14 PINS
148.3
THERMAL METRIC(1)
D (SOIC)
14 PINS
102.1
56.8
DYY (SOT-23)
14 PINS
154.6
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
68.1
86.3
RθJB
ψJT
Junction-to-board thermal resistance
58.5
92.7
67.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
20.5
16.9
9.8
ψJB
58.1
91.8
67.1
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.6 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 5.5 V (±1.35 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT
VS / 2 (unless otherwise noted)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = 5 V
±1
±3
±5
VOS
Input offset voltage
mV
VS = 5 V, TA = –40°C to 125°C
TA = –40°C to 125°C
dVOS/dT
PSRR
VOS vs temperature
±4
µV/°C
dB
Power-supply rejection ratio
VS = 2.7 V to 5.5 V, VCM = (V–)
80
100
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
No phase reversal
(V–) – 0.1
(V+) – 1
V
VS = 2.7 V, (V–) – 0.1 V < VCM < (V+) – 1 V
TA = –40°C to 125°C
84
92
CMRR
Common-mode rejection ratio
dB
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1 V
TA = –40°C to 125°C
63
INPUT BIAS CURRENT
IB
Input bias current
VS = 5 V
±15
±5
pA
pA
IOS
NOISE
En
Input offset current
Input voltage noise (peak-to-peak)
Input voltage noise density
ƒ = 0.1 Hz to 10 Hz, VS = 5 V
ƒ = 1 kHz, VS = 5 V
5.1
40
µVPP
en
nV/√ Hz
INPUT CAPACITANCE
CID
CIC
Differential
2
pF
pF
Common-mode
5.5
OPEN-LOOP GAIN
VS = 2.7 V, (V–) + 0.15 V < VO < (V+) – 0.15 V, RL = 2 kΩ
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V, RL = 2 kΩ
110
125
AOL
Open-loop voltage gain
dB
FREQUENCY RESPONSE
GBW
φm
Gain-bandwidth product
VS = 5 V
1
75
1.5
4
MHz
°
Phase margin
Slew rate
VS = 5.5 V, G = 1
SR
VS = 5 V
V/µs
To 0.1%, VS = 5 V, 2-V step, G = 1, CL = 100 pF
To 0.01%, VS = 5 V, 2-V step, G = 1, CL = 100 pF
VS = 5 V, VIN × gain > VS
tS
Settling time
µs
µs
5
tOR
Overload recovery time
1
VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = 1, ƒ = 1 kHz,
80-kHz measurement BW
THD+N
Total harmonic distortion + noise
0.005%
OUTPUT
VOH
Voltage output swing from positive supply RL ≥ 2 kΩ, TA = –40°C to 125°C
Voltage output swing from negative supply RL ≤ 10 kΩ, TA = –40°C to 125°C
1
V
VOL
40
±40
75
mV
mA
Ω
ISC
Short-circuit current
VS = 5.5 V
ZO
Open-loop output impedance
VS = 5 V, ƒ = 1 MHz
1200
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6.6 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 5.5 V (±1.35 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT
=
VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS
Specified voltage range
2.7 (±1.35)
5.5 (±2.75)
150
V
IO = 0 mA, VS = 5.5 V
90
IQ
Quiescent current per amplifier
µA
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C
160
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6.7 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
10
8
160
140
120
100
80
6
4
2
0
IB-
IB+
IOS
-2
-4
-6
-8
-10
60
40
20
VS = 5.5 V
VS = 2.5 V
0
-40
-20
0
20
40
60
80
100 120 140
-3 -2.5 -2 -1.5 -1 -0.5
0
Common-Mode Voltage (V)
0.5
1
1.5
2
2.5
3
Temperature (èC)
D008
D007
Figure 6-2. Open-Loop Gain vs Temperature
Figure 6-1. IB and IOS vs Common-Mode Voltage
100
80
60
40
20
0
120
160
140
120
100
80
100
80
60
40
20
0
60
40
Gain
Phase
20
-20
0
1k
10k
100k
Frequency (Hz)
1M
-3
-2
-1 0
Output Voltage (V)
1
2
3
D009
D010
CL = 10 pF
Figure 6-4. Open-Loop Gain vs Output Voltage
Figure 6-3. Open-Loop Gain and Phase vs Frequency
80
70
60
50
40
30
20
10
0
Gain = -1
Gain = 1
Gain = 10
Gain = 100
Gain = 1000
-10
-20
100
1k
10k 100k
Frequency (Hz)
1M
D011
CL = 10 pF
Figure 6-5. Closed-Loop Gain vs Frequency
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6.7 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
2
1.5
1
120
100
80
60
40
20
0
PSRR+
PSRR-
0.5
0
-40 èC
25 èC
85 èC
125 èC
-0.5
-1
-1.5
-2
-2.5
-3
0
5
10
15
20
25
30
Output Current (mA)
35
40
45
50
100
1k
10k
Frequency (Hz)
100k
1M
D012
D013
Figure 6-6. Output Voltage vs Output Current (Claw)
Figure 6-7. PSRR vs Frequency
120
120
100
80
60
40
20
0
100
80
60
40
20
0
-40
-20
0
20
40
60
80
100 120 140
100
1k
10k
Frequency (Hz)
100k
1M
Temperature (èC)
D014
D015
Figure 6-9. CMRR vs Frequency
VS = 2.7 V to 5.5 V
Figure 6-8. DC PSRR vs Temperature
120
100
80
60
40
20
0
VS = 2.7 V
VS = 5.5 V
Time (1 s/div)
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D017
D016
Figure 6-11. 0.1-Hz to 10-Hz Integrated Voltage Noise
VCM = (V–) – 0.1 V to (V+) – 1.5 V
Figure 6-10. DC CMRR vs Temperature
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6.7 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
-50
140
120
100
80
-60
-70
60
-80
40
-90
20
RL = 2K
RL = 10K
-100
0
100
1k
Frequency (Hz)
10k
10
100
1k
Frequency (Hz)
10k
100k
D019
D018
VS = 5.5 V
BW = 80 kHz
VCM = 2.5 V
G = 1
Figure 6-12. Input Voltage Noise Spectral Density
VOUT = 0.5 VRMS
Figure 6-13. THD + N vs Frequency
0
100
90
80
70
60
G = +1, RL = 2 kW
G = +1, RL = 10 kW
G = -1, RL = 2 kW
G = -1, RL = 10 kW
-20
-40
-60
-80
-100
0.001
0.01
0.1
Amplitude (VRMS
1
2
2.5
3
3.5
4
Voltage Supply (V)
4.5
5
5.5
)
D020
D021
VS = 5.5 V
G = 1
VCM = 2.5 V
f = 1 kHz
Figure 6-15. Quiescent Current vs Supply Voltage
BW = 80 kHz
Figure 6-14. THD + N vs Amplitude
100
90
80
70
60
2000
1800
1600
1400
1200
1000
800
600
400
200
0
1k
10k
100k
Frequency (Hz)
1M
10M
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D023
D022
Figure 6-17. Open-Loop Output Impedance vs Frequency
Figure 6-16. Quiescent Current vs Temperature
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6.7 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
Overshoot (+)
Overshoot (–)
Overshoot (+)
Overshoot (–)
0
0
0
200
400 600
Capacitance Load (pF)
800
1000
0
200
400 600
Capacitance Load (pF)
800
1000
D024
D025
G = 1
VIN = 100 mVpp
G = –1
VIN = 100 mVpp
Figure 6-18. Small Signal Overshoot vs Capacitive Load
Figure 6-19. Small Signal Overshoot vs Capacitive Load
90
80
70
60
50
40
30
20
10
0
VOUT
VIN
Time (100 ms/div)
0
200
400 600
Capacitance Load (pF)
800
1000
D027
D026
G = 1
VIN = 6.5 VPP
Figure 6-20. Phase Margin vs Capacitive Load
Figure 6-21. No Phase Reversal
VOUT
VIN
VOUT
VIN
Time (20 ms/div)
Time (10 ms/div)
D028
D029
G = –10
VIN = 600 mVPP
G = 1
VIN = 100 mVPP
CL = 10 pF
Figure 6-22. Overload Recovery
Figure 6-23. Small-Signal Step Response
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6.7 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
VOUT
VIN
Time (1 μs/div)
Time (10 ms/div)
D031
D030
G = 1
CL = 100 pF
2-V step
G = 1
CL = 10 pF
VIN = 4 VPP
Figure 6-25. Large-Signal Settling Time (Negative)
Figure 6-24. Large-Signal Step Response
80
60
40
20
0
-20
-40
-60
-80
Sinking
Sourcing
-40
-20
0
20
40
60
80
100
120
Time (1 ms/div)
Temperature (èC)
D033
D032
Figure 6-27. Short-Circuit Current vs Temperature
G = 1
CL = 100 pF
2-V step
Figure 6-26. Large-Signal Settling Time (Positive)
140
0
-20
120
100
80
60
40
20
0
-40
-60
-80
-100
-120
-140
1k
10k
100k
Frequency (Hz)
1M
10M
10M
100M
Frequency (Hz)
1G
10G
D036
D035
Figure 6-29. Channel Separation
Figure 6-28. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
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7 Detailed Description
7.1 Overview
The LM290xLV family of low-power op amps is intended for cost-optimized systems. These devices operate
from 2.7 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications.
The input common-mode voltage range includes the negative rail and allows the LM290xLV family to be used in
many single-supply applications.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VIN-
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V-
(Ground)
7.3 Feature Description
7.3.1 Operating Voltage
The LM290xLV family of op amps is specified for operation from 2.7 V to 5.5 V. In addition, many specifications
apply from –40°C to 125°C. Parameters that vary significantly with operating voltages or temperature are shown
in the section.
7.3.2 Common-Mode Input Range Includes Ground
The input common-mode voltage range of the LM290xLV family extends to the negative supply rail and within
1 V below the positive rail for the full supply voltage range of 2.7 V to 5.5 V. This performance is achieved with a
P‑channel differential pair, as shown in the Functional Block Diagram. Additionally, a complementary N‑channel
differential pair has been included in parallel to eliminate issues with phase reversal that are common with
previous generations of op amps. However, the N-channel pair is not optimized for operation, and significant
performance degradation occurs while this pair is operational. TI recommends limiting any voltage applied at the
inputs to at least 1 V below the positive supply rail (V+) to ensure that the op amp conforms to the specifications
detailed in the section.
7.3.3 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the specified output voltage swing, because of the high input voltage or the high gain. After the
device enters the saturation region, the charge carriers in the output devices require time to return to the linear
state. After the charge carriers return to the linear state, the device begins to slew at the specified slew rate.
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Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and
the slew time. The overload recovery time for the LM290xLV family is typically 1 µs.
7.3.4 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can also involve the supply voltage pins. Each of
these different pin functions has electrical stress limits determined by the voltage breakdown characteristics of
the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal
electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events
both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 7-1 shows the ESD circuits contained in the LM290xLV. The ESD protection circuitry involves
several current-steering diodes connected from the input and output pins and routed back to the internal power
supply lines, where they meet at an absorption device internal to the operational amplifier. This protection
circuitry is intended to remain inactive during normal circuit operation.
V+
Power Supply
ESD Cell
+IN
+
œ
OUT
œ IN
Vœ
Figure 7-1. Equivalent Internal ESD Circuitry
7.3.5 EMI Susceptibility and Input Filtering
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The Figure 6-28 plot illustrates
the performance of the LM290xLV family's EMI filters across a wide range of frequencies. For more detailed
information, see EMI Rejection Ratio of Operational Amplifiers available for download from www.ti.com.
7.4 Device Functional Modes
The LM290xLV family has a single functional mode. The devices are powered on as long as the power-supply
voltage is between 2.7 V (±1.35 V) and 5.5 V (±2.75 V).
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LM290xLV devices are a family of low-power, cost-optimized operational amplifiers. The devices operate
from 2.7 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose applications.
The input common-mode voltage range includes the negative rail, and allows the LM290xLV to be used in any
single-supply applications.
8.2 Typical Application
Figure 8-1 shows the LM290xLV device configured in a low-side current sensing application.
VBUS
ILOAD
ZLOAD
5 V
+
VOUT
Þ
+
RSHUNT
VSHUNT
RF
0.1 Ω
255 kΩ
Þ
RG
7.5 kΩ
Figure 8-1. LM290xLV Device in a Low-Side, Current-Sensing Application
8.2.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 3.5 V
Maximum shunt voltage: 100 mV
8.2.2 Detailed Design Procedure
The transfer function of the circuit in Figure 8-1 is given in Equation 1:
VOUT = ILOAD ìRSHUNT ìGain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest allowable shunt
resistor is shown using Equation 2:
VSHUNT _MAX
100mV
1A
RSHUNT
=
=
=100mW
ILOAD_MAX
(2)
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Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the LM290xLV device to produce an output voltage of approximately 0 V to 3.5 V. The gain needed
by the LM290xLV to produce the necessary output voltage is calculated using Equation 3:
V
OUT _MAX - VOUT _MIN
(
)
Gain =
VIN_MAX - V
IN_MIN
(3)
Using Equation 3, the required gain is calculated to be 35 V/V, which is set with resistors RF and RG. Equation 4
sizes the resistors RF and RG, to set the gain of the LM290xLV device to 35 V/V.
R
(
)
F
Gain = 1+
R
G
(4)
8.2.3 Application Curve
Selecting RF as 255 kΩ and RG as 7.5 kΩ provides a combination that equals 35 V/V. Figure 8-2 shows the
measured transfer function of the circuit shown in Figure 8-1. Notice that the gain is only a function of the
feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors
values are determined by the impedance levels that the designer wants to establish. The impedance level
determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no
optimal impedance selection that works for every system, you must choose an impedance that is ideal for your
system parameters.
3.5
3
2.5
2
1.5
1
0.5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
ILOAD (A)
1
Outp
Figure 8-2. Low-Side, Current-Sense Transfer Function
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9 Power Supply Recommendations
The LM290xLV family is specified for operation from 2.7 V to 5.5 V (±1.35 V to ±2.75 V); many specifications
apply from –40°C to 125°C. Section 6.6 presents parameters that may exhibit significant variance with regard to
operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V may permanently damage the device; see the Section 6.1.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see Section 10.1.
9.1 Input and ESD Protection
The LM290xLV family incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA, as stated in the section. Figure 9-1 shows how a series input resistor can be added to the driven input to
limit the input current. The added resistor contributes thermal noise at the amplifier input and the value must be
kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
VOUT
Device
VIN
5 kW
Figure 9-1. Input Current Protection
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
•
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds. Use thermal signatures or EMI measurement techniques
to determine where the majority of the ground current is flowing and be sure to route this path away from
sensitive analog circuitry. For more detailed information, see Circuit Board Layout Techniques.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace at a 90° angle is much better as opposed
to running the traces in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible, as shown in Figure 10-2. Keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive
part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
VIN 1
VIN 2
+
+
VOUT 1
VOUT 2
RG
RG
RF
RF
Figure 10-1. Schematic Representation for
Place components
close to device and to
each other to reduce
parasitic errors.
OUT 1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
VS+
GND
OUT1
V+
RF
RG
OUT 2
GND
IN1œ
IN1+
Vœ
OUT2
IN2œ
IN2+
RF
VIN 1
GND
RG
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor . Place as
close to the device
as possible .
VSœ
Ground (GND) plane on another layer
as possible .
Figure 10-2. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
•
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM2902LVIDR
LM2902LVIDYYR
LM2902LVIPWR
LM2904LVIDDFR
LM2904LVIDGKR
LM2904LVIDR
ACTIVE
SOIC
D
14
14
14
8
2500 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LM2902LV
ACTIVE SOT-23-THIN
ACTIVE TSSOP
ACTIVE SOT-23-THIN
DYY
PW
DDF
DGK
D
NIPDAU
SN
LM2902I
LM2902LV
L904
NIPDAU
NIPDAUAG
SN
ACTIVE
ACTIVE
ACTIVE
VSSOP
SOIC
8
1SQX
8
2904LV
2904
LM2904LVIPWR
TSSOP
PW
8
NIPDAU | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Mar-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM2902LV, LM2904LV :
Automotive : LM2902LV-Q1, LM2904LV-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Mar-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM2902LVIDR
LM2902LVIDR
SOIC
SOIC
D
D
14
14
14
2500
2500
3000
330.0
330.0
330.0
16.4
15.4
12.4
6.5
6.4
4.8
9.0
5.2
3.6
2.1
2.1
1.6
8.0
8.0
8.0
16.0
12.0
12.0
Q1
Q1
Q3
LM2902LVIDYYR
SOT-
DYY
23-THIN
LM2902LVIPWR
LM2904LVIDDFR
TSSOP
PW
14
8
2000
3000
330.0
180.0
12.4
8.4
6.9
3.2
5.6
3.2
1.6
1.4
8.0
4.0
12.0
8.0
Q1
Q3
SOT-
DDF
23-THIN
LM2904LVIDGKR
LM2904LVIDR
VSSOP
SOIC
DGK
D
8
8
8
8
2500
2500
2000
2000
330.0
330.0
330.0
330.0
12.4
15.4
12.4
12.4
5.3
6.4
7.0
7.0
3.4
5.2
3.6
3.6
1.4
2.1
1.6
1.6
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
LM2904LVIPWR
LM2904LVIPWR
TSSOP
TSSOP
PW
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Mar-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM2902LVIDR
LM2902LVIDR
SOIC
SOIC
D
D
14
14
14
14
8
2500
2500
3000
2000
3000
2500
2500
2000
2000
853.0
336.6
336.6
366.0
210.0
366.0
336.6
366.0
853.0
449.0
336.6
336.6
364.0
185.0
364.0
336.6
364.0
449.0
35.0
41.3
31.8
50.0
35.0
50.0
41.3
50.0
35.0
LM2902LVIDYYR
LM2902LVIPWR
LM2904LVIDDFR
LM2904LVIDGKR
LM2904LVIDR
SOT-23-THIN
TSSOP
DYY
PW
DDF
DGK
D
SOT-23-THIN
VSSOP
8
SOIC
8
LM2904LVIPWR
LM2904LVIPWR
TSSOP
PW
PW
8
TSSOP
8
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.4
0.2
8X
0.1
C A
B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
12X 0.5
14
1
4.3
4.1
NOTE 3
2X
3
7
8
0.31
0.11
14X
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224643/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB
www.ti.com
EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224643/B 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224643/B 07/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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