LM3281 [TI]
3.3V、1.2A、6MHz 微型降压直流/直流转换器;
| 型号： | LM3281 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V、1.2A、6MHz 微型降压直流/直流转换器 转换器 |
| 文件： | 总25页 (文件大小：685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM3281
SNVSA38 –NOVEMBER 2014
LM3281 3.3-V, 1.2-A, 6-MHz Miniature Step-Down DC-DC Converter
for Wireless Connectivity Solutions
1 Features
3 Description
The LM3281 is a high-efficiency low-noise miniature
DC-DC converter optimized for powering noise-
sensitive wireless connectivity chipsets and RF Front
End Modules (FEMs) from a single Lithium-Ion cell.
The LM3281 is ideal for “always on” applications with
very low unloaded quiescent current of 16 µA (typ.).
1
•
•
•
•
•
Operates from a Single Li-Ion Cell (3 V to 5.5 V)
6-MHz (typ.) PWM Switching Frequency
Fixed Output Voltage: 3.3 V
Up to 1.2-A Maximum Load Capability
High Efficiency: 94% (typ.) with 3.8-V VIN at
300 mA
The LM3281 steps down an input supply voltage to a
fixed output voltage of 3.3 V with output current up to
1200 mA. Five different modes of operation are used
to optimize efficiency and minimize battery drain. In
Pulse Width Modulation (PWM) mode, the device
operates at a fixed frequency of 6 MHz which
minimizes RF interference when driving medium-to-
heavy loads. At light load, the device automatically
enters into Economy (ECO) mode with reduced
quiescent current. In a low-battery voltage condition,
a bypass mode reduces the voltage dropout to 60 mV
(typ.) at 600 mA. If very low output voltage ripple is
desired at light loads, the device can also be forced
into PWM mode. Shutdown mode turns the device off
and reduces battery consumption to 0.1 μA (typ.).
•
•
•
•
•
•
•
•
Analog Bypass: 60-mV (typ.) Drop-Out at 600 mA
Low IQ: 16 µA typical, 25 µA maximum
Automatic ECO/PWM/Bypass Mode Change
Forced PWM Mode for Low Output-Voltage Ripple
Soft-Start Limits Input Current on Start-Up
Current Overload Protection
Thermal Overload Protection
Small Total Solution Size: < 7.5 mm2
2 Applications
•
•
•
WLAN, WiFi Station Devices
WiFi RF PC Cards
Device Information(1)
Battery-Powered RF Devices
PART NUMBER
PACKAGE
BODY SIZE
LM3281
DSBGA (6)
1.465 mm x 1.190 (MAX)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
V
IN
3 V - 5.5 V
CIN
2.2 µF
LSW
0.47 µH
VIN
VIN_a
VIN_b
VIN_c
V
MODE
SW
FB
OUT
CLOAD2
4.7 µF
GPO2
GPO1
3.3 V
LM3281
EN
COUT
CLOAD1
10 µF
GND
2.2 µF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3281
SNVSA38 –NOVEMBER 2014
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
Power Supply Recommendations...................... 18
1
2
3
4
5
6
Features.................................................................. 1
8
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings ...................................................... 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 System Characteristics ............................................. 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 19
10.3 DSBGA Package Assembly And Use................... 19
11 Device and Documentation Support ................. 20
11.1 Device Support .................................................... 20
11.2 Documentation Support ........................................ 20
11.3 Trademarks........................................................... 20
11.4 Electrostatic Discharge Caution............................ 20
11.5 Glossary................................................................ 20
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
DATE
REVISION
NOTES
November 2014
*
Initial release.
2
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5 Pin Configuration and Functions
DSBGA (YFQ)
6 Pins
Top
FB
VIN
A
B
MODE
SW
EN
GND
C
1
2
A2
VIN
B1
C1
B2
A1
MODE
SW
FB
LM3281
EN
GND
C2
Figure 1. Pin Out
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
Connect to the output at the output filter capacitor COUT by lowest inductance path with a
trace rated for 2 A.
A1
FB
Power
Power
Connect to input filter capacitor CIN by lowest inductance path, then connect to supply
voltage with a trace rated for 2 A.
A2
B1
VIN
Selects automatic ECO/PWM mode or forced PWM mode. When MODE is HIGH the
LM3281 automatically transitions between PWM and ECO operation. When MODE is LOW
the LM3281 operates in PWM mode only. Do not leave MODE pin floating.
MODE
Logic
B2
C1
SW
EN
Power
Logic
Connect to inductor LSW with a trace rated for 2 A.
Set this digital input logic high for normal operation. For shutdown, set to logic low. Do not
leave EN pin floating.
Connect to input filter capacitor CIN by lowest inductance path, then to system ground by a
very low inductance path.
C2
GND
Ground
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SNVSA38 –NOVEMBER 2014
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)(2)
MIN
–0.2
–0.2
MAX
UNIT
V
VIN pin to GND pin voltage
6
EN, FB, MODE, SW pins to GND pin
voltage
VIN + 0.2 or 6
(whichever is smaller)
Junction temperature (TJ)
150
°C
Continuous power dissipation(3)
Internally limited
260
Maximum lead temperature (soldering)
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. It engages at TJ = 150°C (typ.) and disengages at TJ =
125°C (typ.).
6.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
–1000
–250
1000
250
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.5
UNIT
VIN
Input voltage (with respect to GND pin)
Output current
3
0
V
(1)
ILOAD
1200
1400
VIN
mA
(1)
ILOAD_BURST
Output current, short bursts (< 100 µS burst at < 10% duty cycle)
EN pin voltage (with respect to GND pin)
Mode select pin voltage (with respect to GND pin)
Junction temperature
0
EN
MODE
TJ
0
V
0
VIN
–30
–30
–30
125
90
TA
Ambient temperature
°C
TB
PC board temperature
105
(1) Refer to section High Maximum Current in this data sheet for load current use case profile.
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SNVSA38 –NOVEMBER 2014
6.4 Thermal Information
DSBGA
THERMAL METRIC(1)
YFQ
6 PINS
131.2
1.7
UNIT
(2)
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
25.6
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
4.7
ψJB
25.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) θJA is not useful for CSP packages because the dominant heat loss mechanism is through the PCB. Instead, RθJB is more useful and
is used.
R
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
(1)(2)(3)
PARAMETER
Input voltage range(4)
TEST CONDITIONS
MIN
3
TYP
MAX
5.5
3.4
1
UNIT
VIN
V
VOUT
ISHDN_IN
Output voltage measured at FB pin
Total supply current in shutdown
3.2
3.3
0.1
EN = SW = FB = MODE = 0 V,
Steady State
µA
MHz
V
IQ_OL
FOSC
VIH
Quiescent current
No switching
15
6
25
Internal oscillator frequency
5.4
1.2
6.6
EN, MODE pins high level input
voltage
VIL
IIH
IIL
EN, MODE pins low level input voltage
EN, MODE high level input current
EN, MODE low level input current
0.4
1
µA
EN = MODE = 0 V
–1
(1) All voltages are with respect to the GND pin.
(2) All characteristics apply to the Simplified Schematic with VIN = 3.8 V, EN = MODE = VIN, at TA = 25°C, device in PWM operation unless
otherwise noted.
(3) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis over the ambient temperature operating
range –30°C to 90°C. Limits are not specified by production testing.
(4) Device is functional at a minimum VIN = 2.6 V but is specified for operation over the range VIN = 3 V to 5.5 V.
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6.6 System Characteristics(1)(2)(3)(4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(5)
ILOAD_MAX
Maximum load current
PWM mode VOUT ripple
ECO mode VOUT ripple
PWM mode VOUT
1200
mA
VO_RIPPLE_PWM
VO_RIPPLE_ECO
VO_PWM_ACC
VO_ECO_ACC
ILOAD = 600 mA
1
60
mV
V
ILOAD = 30 mA
3.2
3.2
3.3
3.3
3.4
3.4
VIN = 3.8 V
ECO mode VOUT
ITRIG_PWM_TO_ECO
PWM to ECO mode ILOAD
threshold
ILOAD falling
50
70
mA
ITRIG_ECO_TO_PWM
VDROPOUT_BYPASS
ECO to PWM mode ILOAD
threshold
ILOAD rising
Bypass mode total dropout ILOAD = 600 mA, VIN = 3.2V
60
80
voltage with LSW inductor
ILOAD = 1200 mA, VIN = 3.2V
DCR = 40 mΩ
mV
mA
120
160
ION_SOFT_START
Soft-start supply current
during turnon averaged in
any 10-µs window
EN = low-to-high,
LOAD ≤ 1 mA
I
500
1000
150
TON
Turnon transient time from EN = low-to-high,
EN = high until VOUT is
ILOAD ≤ 1 mA
settled to within ±50 mV of
settled value, and full 1200-
mA load may be applied
µs
ILOAD = 1200 mA
ILOAD = 600 mA
ILOAD = 300 mA
ILOAD = 30 mA
ILOAD = 0 mA
89%
93%
94%
91%
PWM mode efficiency
ECO mode efficiency
η
IQ_CL
Closed loop quiescent
current
16
20
25
µA
(6)
(7)
VLINE_TR_PWM_PWM
TLINE_TR_PWM_PWM
ILOAD = 600 mA
mVpk
PWM-to-PWM line
transient response
VIN = 4.2 V to 3.8 V
VIN = 3.8 V to 4.2 V with 7-µs
edge rate
0(8)
µS
(6)
(7)
VLOAD_TR_PWM_PWM
TLOAD_TR_PWM_PWM
ILOAD = 150 mA to 600 mA or
ILOAD = 600 mA to 150 mA with
1-µs edge rate, VIN = 3.8 V
80
3
mVpk
µS
PWM-to-PWM load
transient response
(6)
(7)
VLOAD_TR_ECO_TO_PWM
TLOAD_TR_ECO_TO_PWM
200
6
mVpk
µS
ECO-to-PWM load
transient response
ILOAD = 30 mA to 600 mA with
1-µs edge rate, VIN = 3.8 V
(9)
VIN_RAMP
ILOAD = 0 mA
Input voltage ramp time
Input power supply rising from
1.2 V to 2.6 V
20
µs
(1) All voltages are with respect to the GND pin.
(2) All TYP characteristics apply to the Simplified Schematic with VIN = 3.8 V, EN = MODE = VIN, at TA = 25°C, device in PWM operation,
unless otherwise noted and assume the following passive components:
(a) CIN = COUT = Samsung 2.2 µF 0201 case size (PN: CL03A225MQ3CRNC)
(b) LSW = Murata 0.47 µH 2012 case size (PN: LQM21PNR47MGH)
(c) CLOAD1 = Samsung 10 µF 0402 case size (PN: CL05A106MP5NUNC)
(d) CLOAD2 = Samsung 4.7 µF 0402 case size (PN: CL05A475MP5NRNC)
(3) All system characteristics are specified by design, test or statistical analysis and are not specified by production testing.
(4) Minimum (MIN) and Maximum (MAX) limits apply over the ambient temperature operating range –30°C to 90°C and over the VIN range
3 V to 5.5 V, unless otherwise noted.
(5) Refer to section High Maximum Current in this data sheet for load current use case profile.
(6) Transient magnitude is defined as maximum deviation from final settled value during transient time.
(7) Transient time is defined as time elapsed from the start of the event to when VOUT is finally within ±50 mV of settled value.
(8) Transient magnitude does not exceed ± 50 mV of settled value, so transient time is 0 µS.
(9) This parameter is only applicable when EN is tied to VIN. See Power-On Reset section for further details.
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6.7 Typical Characteristics
All curves are at TA = 25°C and VIN = 3.8 V, unless otherwise specified. CIN, COUT = 2.2 µF, CLOAD2 = 4.7 µF, CLOAD1 = 10 µF,
LSW = 0.47 µH.
100
95
90
85
80
75
70
65
60
55
50
45
100
95
90
85
80
VIN = 3.4 V
VIN = 3.8 V
VIN = 4.2 V
VIN = 4.8 V
VIN = 5.5 V
VIN = 3.4 V
VIN = 3.8 V
VIN = 4.8 V
VIN = 5.5 V
0
10
20
30
40
50
60
70
80
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Output Current (mA)
Output Current (A)
D001
D002
Figure 2. ECO Efficiency vs Output Current
Figure 3. PWM Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
25
20
15
10
5
VIN = 3.4 V
VIN = 3.8 V
VIN = 4.8 V
VIN = 5.5 V
0
0
20
40
60
80
100
120
140
160
2.5
3
3.5
4
4.5
5
5.5
Load Current (mA)
Vin (V)
D003
D012
Figure 4. Forced PWM Efficiency vs Output Current
Figure 5. No Load ECO Input Current vs VIN
14
12
10
8
VOUT (V)
20 mV/DIV
6
SW (V)
2 V/DIV
4
PWM-Bypass Transition
2
0
2.5
Time (4 µs/DIV)
3
3.5
4
4.5
5
5.5
Vin (V)
D011
IOUT = 10 mA
Figure 6. No Load Forced PWM Input Current vs VIN
Figure 7. Output Voltage Ripple in ECO Mode
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Typical Characteristics (continued)
All curves are at TA = 25°C and VIN = 3.8 V, unless otherwise specified. CIN, COUT = 2.2 µF, CLOAD2 = 4.7 µF, CLOAD1 = 10 µF,
LSW = 0.47 µH.
VOUT (V)
1 mV/DIV
VOUT (V)
1 mV/DIV
SW (V)
2 V/DIV
SW (V)
2 V/DIV
Time (40 ns/DIV)
Time (40 ns/DIV)
IOUT = 100 mA
IOUT = 10 mA
Figure 8. Output Voltage Ripple in PWM Mode
Figure 9. Output Voltage Ripple in Forced PWM Mode
130
120
110
100
90
6.5
6.4
6.3
6.2
6.1
6
80
70
60
5.9
5.8
5.7
5.6
5.5
50
40
30
VIN = 3.4 V
VIN = 3.8 V
VIN = 4.8 V
20
10
0
0
5
10 15 20 25 30 35 40 45 50 55 60
Load (mA)
3.5
4
4.5
Vin (V)
5
5.5
D004
D005
Figure 10. ECO Burst Frequency vs Output Current
Figure 11. PWM Switching Frequency vs VIN
3.48
3.44
3.4
3.48
3.44
3.4
+3% Limit
+3% Limit
3.36
3.32
3.28
3.24
3.2
3.36
3.32
3.28
3.24
3.2
-3% Limit
-3% Limit
3.16
3.12
3.08
3.04
3.16
3.12
3.08
3.04
IOUT = 300 mA
IOUT = 500 mA
IOUT = 600 mA
IOUT = 700 mA
IOUT = 800 mA
IOUT = 1000 mA
IOUT = 1200 mA
IOUT = 300 mA
IOUT = 500 mA
IOUT = 600 mA
IOUT = 700 mA
IOUT = 800 mA
IOUT = 1 A
IOUT = 1.2 A
3.26 3.28 3.3 3.32 3.34 3.36 3.38 3.4 3.42 3.44 3.46 3.48
Vin (V)
3.26 3.28 3.3 3.32 3.34 3.36 3.38 3.4 3.42 3.44 3.46 3.48
Vin (V)
D006
D007
Figure 12. PWM-to-Analog Bypass Transition, Falling VIN
Figure 13. Analog Bypass-to-PWM Transition, Rising VIN
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Typical Characteristics (continued)
All curves are at TA = 25°C and VIN = 3.8 V, unless otherwise specified. CIN, COUT = 2.2 µF, CLOAD2 = 4.7 µF, CLOAD1 = 10 µF,
LSW = 0.47 µH.
3.5
3.45
3.4
3.5
3.45
3.4
+3% Limit
+3% Limit
3.35
3.3
3.35
3.3
3.25
3.2
3.25
3.2
-3% Limit
-3% Limit
3.15
3.1
3.15
3.1
Falling VIN
Rising VIN
IOUT = 30 mA
IOUT = 150 mA
IOUT = 600 mA
IOUT = 1200 mA
3.26
3.28
3.3
3.32
Vin (V)
3.34
3.36
3.38
3.4
3.2 3.4 3.6 3.8
4
4.2 4.4 4.6 4.8
Vin (V)
5
5.2 5.4
D008
D009
IOUT = 30 mA
Figure 14. Analog Bypass Transition at Light Load vs VIN
Figure 15. Line Regulation vs Output Current
3.5
3.45
+3% Limit
3.4
3.35
3.3
3.25
-3% Limit
3.2
3.15
3.1
VIN = 3.4 V
VIN = 3.8 V
VIN = 4.8 V
VIN = 5.5 V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Load Current (A)
1 1.1 1.2 1.3 1.4
D010
Figure 16. Load Regulation vs Output Current
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7 Detailed Description
7.1 Overview
The LM3281 is a size- and performance-optimized step-down DC-DC converter for powering power amplifiers,
front-end modules, wireless connectivity solutions, and a wide variety of other applications. The device
complements the portfolio of SuPA (Supply for PA) products by combining small solution size, low dropout
analog bypass with smooth mode transitions, very low standby current for always-on applications, very low ripple
with “forced PWM” mode operation, high maximum output current, ability to drive large load capacitance while
retaining transient performance, and soft start to limit start-up current.
7.2 Functional Block Diagram
EN MODE
VIN
ECO COMP
BYPASS
CONTROL
FB
OLP
OVERVOLTAGE
DETECTOR
Ref2
Ref1
PWM
COMP.
CONTROL LOGIC
DRIVER
ERROR
AMP
FB
SW
RAMP
GENERATOR
NCP
Ref3
OSCILLATOR
Ref4
OUTPUT
SHORT
PROTECTION
LIGHT-LOAD
CHECK COMP
SOFT
START
THERMAL
SHUTDOWN
GND
7.3 Feature Description
7.3.1 Small Solution Size
Solution size less than 7.5 mm2 is possible using the LM3281 in combination with only three small passive
components.
7.3.2 Automatic Analog Bypass with Low Dropout
An internal bypass transistor under analog control automatically engages as VIN falls below the VOUT target.
Output stays regulated in analog bypass mode until full dropout. The parallel impedance of this additional bypass
transistor with normal DC-DC output path reduces VOUT voltage drop-out, maximizing VOUT supply voltage to the
load at low VIN conditions. The analog implementation provides a smooth transition among regulation and bypass
modes, avoiding VOUT distortion.
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Feature Description (continued)
7.3.3 Low IQ
An ECOnomy (ECO) mode of operation draws 16 µA (typ.) quiescent current, permitting the LM3281 to be used
in “always-on” applications. This low IQ is achieved over the entire input supply range of 5.5 V to 2.6 V,
irrespective of whether LM3281 is operating in regulation (ECO Mode or Analog Bypass mode) or in full dropout
(full bypass).
7.3.4 Forced PWM Operation
ECO mode provides low IQ while PWM mode optimizes output voltage ripple and transient performance. When
high, the MODE pin permits automatic mode selection based on load current. When MODE is pulled low the
LM3281 enters “forced PWM” operation with very low ripple and optimized transient response. Alternately, the
MODE pin can be tied high in an application to allow the device to always select a mode of operation
automatically.
7.3.5 High Maximum Current
Load current of 1.2 A is supported with short bursts (of < 100 µS with < 10% duty cycle) up to 1.4 A.
A wide variety of load current use cases are accommodated by the LM3281. Examples are described in Table 1
and Table 2: one for high ambient temperature all the time, and one for a more typical ambient temperature use
case. Many alternate use case scenarios are available; please contact TI to discuss the load current relevant for
a given application.
For the high ambient temperature of 85°C for the entire device operational lifetime, see Table 1:
Table 1. ILOAD Example for Constant 85°C Ambient Temperature
ILOAD
AMBIENT TEMPERATURE
PERCENT OPERATIONAL LIFETIME
100 mA
700 mA
1400 mA
85°C
85°C
85°C
Up to 100%
Up to 60%
Up to 3%
For a more typical ambient temperature distribution of TA ≤ 70°C for ≥ 80% of the operational lifetime and 70°C <
TA ≤ 85% for ≤ 20% of the operational lifetime, see Table 2:
Table 2. ILOAD Example for a More Typical Ambient Temperature Use
ILOAD
AMBIENT TEMPERATURE
PERCENT OPERATIONAL LIFETIME
100 mA
70°C < TA ≤ 85°C for ≤ 20% of time
Up to 100%
T
A ≤ 70°C for ≥ 80% of time
70°C < TA ≤ 85°C for ≤ 20% of time
A ≤ 70°C for ≥ 80% of time
70°C < TA ≤ 85°C for ≤ 20% of time
A ≤ 70°C for ≥ 80% of time
850 mA
Up to 60%
Up to 3%
T
1400 mA
T
7.3.6 High-Capacitance Load and Line Transient Performance
The LM3281 is internally compensated to drive loads with large bypass capacitance, including transceiver
modules, without sacrificing transient performance. Please reference Total Effective Output Capacitance (COUT
CLOAD1 + CLOAD2) regarding output capacitance requirements.
+
7.3.7 Soft Start
During start-up a soft-start feature prevents high input current which could cause supply voltage bus drops and
interfere with other subsystems sharing the supply bus. Soft start is especially valuable in applications where
large load capacitance must be charged on start-up. Loading of the output during start-up condition will extend
the soft-start time. Excessive loading may even prevent the output from reaching the target voltage, and the
device may therefore stay in the soft-start condition indefinitely.
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7.3.8 Thermal Overload Protection
The LM3281 device has a thermal overload protection that protects the device from short-term misuse and
overload conditions. If the junction temperature exceeds 150°C, the LM3281 shuts itself down. Normal operation
resumes after the temperature drops below 125°C. Prolonged operation in thermal overload condition may
damage the device and is therefore not recommended.
7.3.9 Current Limit
The current limit feature allows the LM3281 to protect itself and external components during overload conditions.
In PWM mode, the cycle-by-cycle current limit of the SW pin is 1.9-A peak, and the bypass current limit is 1.3 A.
Thus, the total current limit is 2.2 A (typ.). During the start-up condition or when the output voltage is less than
0.34 V, the SW pin current limit is reduced to 0.85 A peak, and the bypass current is disabled. If excessive load
prevents the output from rising above 0.34 V for more than 40 μs, the LM3281 enters the short-circuit-protection
state.
7.3.10 Power-On Reset
Some applications may require tying the EN pin directly to the VIN pin. For this reason, the LM3281 features a
Power on Reset (POR) that ensures that the part will enter a deterministic state when power is first applied.
When the EN pin is tied directly to the VIN pin, the input power supply needs to rise fast enough for the POR
circuit to work properly. The VIN voltage should not stay between 1.2 V and 2.6 V for longer than 20 µs. This is
not required if the EN pin voltage remains below VIL (below 0.2 V) until VIN is at least at 2.6 V.
7.4 Device Functional Modes
The LM3281 includes five steady-state modes of operation depending on MODE, VIN, and ILOAD conditions: PWM
(Pulse Width Modulation), Forced PWM, ECO (ECOnomy), Analog Bypass, and Shutdown. Two protection
mechanisms include current limiting and thermal overload protection. Finally, soft-start operation is active to
prevent excessive input current only when the part is first enabled.
7.4.1 PWM Mode
When the LM3281 operates in PWM mode, the switching frequency is constant, and the switcher regulates the
output voltage by changing the energy per cycle to support the load required. During the first portion of each
switching cycle, the control block in the LM3281 turns on the internal PFET switch. This allows current to flow
from the input through the inductor and to the output filter capacitor and load. The inductor limits the current to a
ramp with a slope of (VIN – VOUT)/L, by storing energy in its magnetic field. During the second portion of each
cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET
synchronous rectifier on. The inductor draws current from ground through the NFET and to the output filter
capacitor and load, which ramps the inductor current down with a slope of –VOUT/L. The output filter capacitor
stores charge when the inductor current is greater than the load current and releases it when the inductor current
is less than the load current, smoothing the voltage across the load. At the next rising edge of the clock, the
cycle repeats. An increase of load pulls the output voltage down, increasing the error signal. As the error signal
increases, the peak inductor current becomes higher, thus increasing the average inductor current. The output
voltage is therefore regulated by modulating the PFET switch on-time to control the average current sent to the
load. The circuit generates a duty-cycle modulated rectangular signal that is averaged using a low pass filter
formed by the inductor and output capacitor. The output voltage is equal to the average of the duty-cycle
modulated rectangular signal.
7.4.2 Forced PWM (FPWM) Mode
To maintain high efficiency at lighter loads, LM3281 automatically goes into what is called ECO mode which has
low IQ but higher ripple compared to PWM mode. If an application requires very low ripple and/or fast transient
response, LM3281 can be forced to operate in PWM mode even at lighter loads. When high, the MODE pin
permits automatic PWM or ECO mode operation based on load current. When MODE is pulled low the LM3281
enters “forced PWM” operation with very low ripple and optimized transient response. If automatic PWM/ECO
mode operation is desired, the MODE pin can be permanently tied high in an application to allow the device to
always select a mode of operation automatically based on the load current conditions.
It should be noted that LM3281 transient performance is quite good in ECO mode, and it may not be necessary
to operate in FPWM mode for transient performance reasons alone. Normally, FPWM operation is selected for
lower output voltage ripple.
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Device Functional Modes (continued)
7.4.3 Analog Bypass Mode
The LM3281 contains an internal BPFET (Bypass FET) transistor connected from the battery directly to the
output for bypassing the PWM DC-DC converter when VIN approaches VOUT. In Analog Bypass mode, this
BPFET is turned on just enough for the PWM DC-DC to maintain regulation by providing a parallel path from the
battery directly to the load for maximum usable battery range and extended operating time while maintaining
regulation. When the part is in dropout and is operating in full bypass mode, the output voltage will be the input
voltage less the voltage drop across the resistance of the BPFET in parallel with the PFET + Switch Inductor.
Analog Bypass mode is more efficient than operating in PWM mode at 100% duty cycle because the combined
resistance of the circuit is significantly less than the series resistance of just the PWM PFET and inductor. This
translates into higher voltage available at the output in Analog Bypass mode for a given battery voltage. The
bypass operation is very system resource friendly in that the bypass PFET is gradually turned on automatically
when the input voltage gets close to the output voltage (while always maintaining regulation), a typical scenario
of a discharging battery. Likewise, it is also automatically gradually turned off when the input voltage rises, a
typical scenario when connecting a charger.
7.4.4 ECO (Economy) Mode
At light load current, the converter enters ECO mode operation with reduced quiescent supply current to maintain
high efficiency. During ECO mode operation, a switching burst brings the output just above target voltage. This
period of switching is followed by no switching in which the output coasts to just below target voltage, and then
this cycle is repeated. The frequency of how often the switching burst occurs is dependent on the load current.
PWM operation resumes once the load current reaches a specific threshold.
7.4.5 Shutdown Mode
Setting the EN digital input pin low (< 0.4 V) places the LM3281 in Shutdown mode where it consumes less than
0.1 μA current typically. In shutdown, the PFET switch, the NFET synchronous rectifier, the BPFET, reference
voltage source, control, and bias circuitry of the LM3281 are turned off. Setting EN high (> 1.2 V) enables normal
operation.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM3281 is a high efficiency DC-DC converter optimized to power Wireless Connectivity Solutions in cell
phones, portable communication devices or other battery-powered RF devices. The device is designed to
operate from an input supply voltage between 3 V and 5.5 V with a maximum load current of 1.2 A. It operates in
PWM mode for medium to heavy load conditions and in ECO mode for light load conditions to optimize for best
efficiency , transient performance and output voltage ripple at varying load conditions. In PWM mode the LM3281
converter operates with nominal switching frequency of 6 MHz, thus enabling use of smaller size capacitors and
inductor. The converter operates in ECO mode at lighter load conditions to maintain high efficiency. In this mode
a period of switching burst charges the output capacitor to the regulation target. This is followed by a period of no
switching where the output voltages coasts to a lower voltage threshold due to light load current consumption.
Upon reaching this lower voltage threshold, the cycle repeats by starting a new switching burst. The LM3281
automatically transitions into Analog Bypass operation as input voltage approaches output voltage.
Figure 17 shows one of many application configurations for LM3281. A battery-connected system boost bypass
(normally part of system PMU) provides input supply to LM3281 which in turn very efficiently converts this input
to a fixed 3.3-V output with superior transient response and output noise, thereby saving the Wireless
Connectivity Solution from having to operate from a higher supply voltage, such as a direct connection to a
battery or a system boost/bypass. This results in significant power dissipation savings and consequently cooler
operation for the connectivity solution without sacrificing its RF performance. In applications where low voltage
battery operation is not a significant feature, system boost/bypass can be eliminated, and the LM3281 can be
directly connected to a battery for high efficiency power conversion and excellent RF performance. These types
of always-on applications are feasible because of very low IQ of LM3281.
8.2 Typical Application
VBAT
DC/DC
10 µF
2G
VBST
DC/DC
10 µF
3G/4G
VBAT
V
IN
2.7 V to 4.5 V
3 V - 5.5 V
2.2 µF
System
Boost/Bypass
WLAN/BT
Module
VIN
0.47 µH
VIN_a
VIN_b
V
MODE
SW
FB
OUT
VBAT
VBST
3.3 V
LM3281
VIN_c
VIN_d
GPO
EN
2.2 µF
GND
10 µF + 4.7 µF (0402)
Figure 17. LM3281 Typical Application
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Typical Application (continued)
8.2.1 Design Requirements
Design requirements for LM3281 pertain to the use of appropriate passive components. The recommended
passive components (inductors and capacitors) are optimally selected to provide best performance for a typical
application.
8.2.1.1 Suggested Passive Components
Referencing the Simplified Schematic on page 1, the LM3281 Inductor Selection, Total Effective Output
Capacitance (COUT + CLOAD1 + CLOAD2), LM3281 Capacitor (CIN and COUT) Selection, Recommended Load
Bypass Capacitors (CLOAD1 and CLOAD2), and Alternate Output Capacitor Configuration sections provide
suggested passive components. Please consult the TI applications team to select suitable alternatives.
8.2.1.1.1 LM3281 Inductor Selection
The solution inductor shown in the Simplified Schematic can be optimized for size or solution efficiency. The
2012-size inductor listed below will perform well but other suitable smaller size inductors may be available in the
future.
Table 3. Suggested Inductor
INDUCTANCE
DCR
ISAT
SIZE
PART NUMBER
VENDOR
LSW
0.47 µH ± 20%
40 mΩ
2.4 A
2.00 x 1.25 x 1.00 mm
LQM21PNR47MGH
Murata
The inductor used in LM3281 designs should have following characteristics over operating temperature range:
•
•
•
•
DC resistance (DCR) ≤ 70 mΩ
Inductance at 0-mA current = 0.47 µH ±20%
Inductance at 1.4-A current ≥ 0.29 µH
Inductance at 2-A current ≥ 0.26 µH
If an application requires less than 1.4A peak load current, it is possible to trade maximum load current for DCR
of the inductor (hence smaller physical size) by using Equation 1:
DCR_IND_MAX = (0.217/I_MAX) - 0.085
(1)
where DCR_IND_MAX is the maximum DC resistance of inductor in Ohms and I_MAX is the maximum load
current in Amperes.
8.2.1.1.2 Total Effective Output Capacitance (COUT + CLOAD1 + CLOAD2
)
Total effective output capacitance including load capacitance (CLOAD1 and CLOAD2) and solution capacitance
(COUT), de-rated for 3.3-V DC bias, operating temperature range, aging, etc. must be 3.4 μF to 9 μF.
Table 4. Total Effective Output Capacitance
MIN
TYP
MAX
UNIT
Effective COUT (capacitor placed closest to LM3281), de-rated for 3.3-
V DC bias, operating temperature and aging
0.8
9
μF
Total effective output capacitance (COUT + CLOAD1 + CLOAD2), de-
rated for 3.3-V DC bias, operating temperature range, and aging
3.4
7
9
μF
8.2.1.1.3 LM3281 Capacitor (CIN and COUT) Selection
The LM3281 is designed for use with ceramic capacitors for its input and output filters. Ceramic capacitors types
such as X5R, X7R are recommended for both filters. Note that suggested LM3281 solution capacitors are de-
rated by 50% to 65% at 3.3-V DC bias.
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Table 5. Suggested Capacitors
CAPACITANCE
CAPACITANCE
SIZE
PART NUMBER
VENDOR
@3.3V DC BIAS
(IMPERIAL)
CIN
2.2 μF ± 10%
2.2 μF ± 20%
1.1 µF
0402, 0.50 mm height
0201, 0.30 mm height
CL05A225KQ5NNNC
CL03A225MQ3CRNC
Samsung
Samsung
COUT
CIN
0.8 µF
COUT
8.2.1.1.4 Recommended Load Bypass Capacitors (CLOAD1 and CLOAD2
)
Suggested load capacitors are de-rated by 55% to 60% at 3.3-V DC bias. Contact TI for additional
recommendations regarding load bypass capacitor value and case sizes.
Table 6. Recommended Load Capacitors
CAPACITANCE
@3.3V DC BIAS
SIZE
(IMPERIAL)
CAPACITANCE
PART NUMBER
VENDOR
CLOAD1
CLOAD1
CLOAD2
10 μF ± 20%
10 μF ± 10%
4.7 μF ± 20%
4.2 μF
5.2 μF
2 μF
0402, 0.50 mm height
0603, 0.80 mm height
0402, 0.50 mm height
CL05A106MP5NUNC
CL10A106KP8NNNC
CL05A475MP5NRNC
Samsung
Samsung
Samsung
8.2.1.1.5 Alternate Output Capacitor Configuration
If only one output capacitor is desired for minimum system solution size components in Table 7 can be used. In
this case components COUT, CLOAD1, and CLOAD2 are absorbed into COUT; CLOAD1 and and CLOAD2 are eliminated.
COUT must be placed very close to the LM3281.
Table 7. Other Recommended Capacitors
CAPACITANCE
@3.3V DC BIAS
SIZE
(IMPERIAL)
CAPACITANCE
PART NUMBER
VENDOR
COUT
22 μF ± 20%
7.3 μF
0603, 0.80 mm height
GRM188R60J226MEA0D
Murata
8.2.2 Detailed Design Procedure
The LM3281 is designed to use ceramic capacitors for its input and output filters. Use a 2.2-µF capacitor for
input that provides a minimum of 0.8 µF effective capacitance under bias and worst-case temperature conditions.
For output filter, combination of COUT, CLOAD1 and CLOAD2 should yield at least 3.4 µF (but not more than 9 µF) of
effective capacitance under bias and worst-case temperature conditions. Please refer to Table 5, Table 6, and
Table 7 for specific recommended components.
The input filter capacitor supplies AC current drawn by the PFET switch of the LM3281 in the first part of each
cycle and reduces the voltage ripple imposed on the input power source. The output filter capacitor absorbs the
AC inductor current, helps maintain a steady output voltage during transient load changes and reduces output
voltage ripple. These capacitors must be selected with sufficiently low ESR (Equivalent Series Resistance) to
perform these functions. The ESR of the filter capacitors is generally a major factor in voltage ripple.
There are two main considerations when choosing an inductor: the inductor should not saturate (inductance
should not drop significantly with current), and DC resistance of the inductor should not be excessively high.
Different manufacturers follow different saturation current rating specifications, so attention must be given to
details. Saturation current ratings are typically specified at 25°C so ratings over the ambient temperature range of
the application should be requested from the manufacturer. Refer to LM3281 Inductor Selection for a
recommendation about a specific part number and other useful guidelines about inductor selection.
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8.2.3 Application Curves
VIN (V)
500 mV/DIV
500 mV/DIV
VIN (V)
500 mV/DIV
VOUT (V)
VOUT (V)
50 mV/DIV
Time (100 µs/DIV)
Time (100 µs/DIV)
3.8 V → 4.2V → 3.8 V
IOUT = 600 mA
3.2 V → 3.8 V → 3.2 V
IOUT = 600 mA
Figure 18. Line Transient Response
Figure 19. Line Transient Response: Bypass Region
VOUT (V)
100 mV/DIV
VOUT (V)
200 mV/DIV
Load Current
(mA)
Load Current
(mA)
500 mA/DIV
1 A/DIV
Time (20 µs/DIV)
Time (20 µs/DIV)
PWM-PWM 150 mA → 600 mA → 150 mA
PWM-PWM Heavy Step 150 mA →1200 mA → 150 mA
Figure 20. Load Transient Response
Figure 21. Load Transient Response
VOUT (V)
100 mV/DIV
VOUT (V)
100 mV/DIV
Load Current
(mA)
Load Current
(mA)
500 mA/DIV
500 mA/DIV
Time (20 µs/DIV)
Time (20 µs/DIV)
ECO-PWM-ECO 30 mA → 600 mA → 30 mA
Forced PWM 30 mA → 600 mA → 30 mA
Figure 22. Load Transient Response
Figure 23. Load Transient Response
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ENABLE
IIN (A)
5 V/DIV
1 A/DIV
ENABLE
IIN (A)
5 V/DIV
200 mA/DIV
IIND (A)
1 A/DIV
1 V/DIV
IIND (A)
1 A/DIV
1 V/DIV
VOUT (V)
VOUT (V)
Time (10 µs/DIV)
Time (40 µs/DIV)
IOUT = 1 mA
Output shorted to Ground
Figure 24. Start-Up Response
Figure 25. Start-Up into Short-Circuit Response
9 Power Supply Recommendations
The LM3281 device is designed to operate from a supply voltage range between 3 V and 5.5 V. This input
supply should be well regulated. If the input supply is located more than a few inches from the LM3281
converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An
electrolytic or tantalum capacitor with a value of 47 μF is a typical choice.
10 Layout
10.1 Layout Guidelines
Optimal LM3281 performance is realized when two important layout considerations are observed. TI-provided
layout guidance in this section illustrates best practices, and a customer layout review with the TI applications
team will ensure best performance is achieved.
10.1.1 COUT-to-CLOAD Inductance
Minimize inductance in the path between LM3281 COUT capacitor and the load bypass capacitors CLOAD1
and CLOAD2 for best performance. Total power path inductance from the LM3281 output to the load (including
vias and traces) should target < 1 nH and must not exceed 2 nH.
10.1.2 LM3281-to-CIN Inductance
Minimize inductance between LM3281 pins (VIN, GND) and the LM3281 input bypass capacitor CIN for best
performance. The LM3281 device and CIN capacitor should be placed to permit shortest possible top-metal
routing for these connections.
Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to
EMI, ground bounce, and resistive voltage loss in the traces resulting in poor regulation or instability. Poor layout
can also result in re-flow problems leading to poor solder joints between the DSBGA package and board pads
which can result in erratic or degraded performance of the converter. By its very nature, any switching converter
generates electrical noise, and the circuit board designer’s challenge is to minimize, contain, or attenuate such
switcher-generated noise. A high-frequency switching converter, such as the LM3281, switches Ampere level
currents within nanoseconds, and the traces interconnecting the associated components can act as radiating
antennas. The following general guidelines are offered to help mitigate EMI and facilitate good layout design.
•
Place the LM3281 switcher, its input capacitor, and output filter inductor and capacitor close together, and
make the Inter-connecting traces as short as possible.
•
Arrange the components so that the switching current loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor, through the internal PFET of the LM3281 and the
inductor, to the output filter capacitor, then back through ground, forming a current loop. In the second half of
each cycle, current is pulled up from ground, through the internal synchronous NFET of the LM3281 by the
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Layout Guidelines (continued)
inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing
these loops so the current curls in the same direction prevents magnetic field reversal between the two half-
cycles and reduces radiated noise.
•
•
Make the current loop area(s) as small as possible.
Reduce the amount of switching current that circulates through the ground plane: Connect the ground bump
of the LM3281 and its input filter capacitor together using generous component-side copper fill as a pseudo-
ground plane. Then connect this copper fill to the system ground-plane (if one is used) with multiple vias.
These multiple vias help to minimize ground bounce at the LM3281 by giving it a low-impedance ground
connection.
•
•
Minimize resistive losses by using wide traces between the power components and doubling up traces on
multiple layers when needed.
Route noise sensitive traces, such as the voltage feedback path, as directly as possible from the switcher FB
pad to the VOUT pad of the output capacitor, but keep it away from noisy traces between the power
components.
•
Take advantage of the inherent inductance of circuit traces to reduce coupling among various function blocks
on the board, by way of the power supply traces.
10.2 Layout Example
Figure 26. LM3281 Layout Example
10.3 DSBGA Package Assembly And Use
Use of the DSBGA package requires specialized board layout, precision mounting, and careful re-flow
techniques, as detailed in Texas Instruments Application Note 1112 DSBGA Wafer Level Chip Scale Package
(SNVA009). Refer to the section Surface Mount Technology (SMD) Assembly Considerations. For best results in
assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style
used with DSBGA package should be the NSMD (non-solder mask defined) type. This means that the solder-
mask opening is larger than the pad size. This prevents a lip that otherwise forms if the solder-mask and pad
overlap from holding the device off the surface of the board and interfering with mounting. See Application Note
1112 for specific instructions how to do this.
The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque
cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is
vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed
circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA
devices are sensitive to light (in the red and infrared range) shining on the package's exposed die edges.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
Texas Instruments Application Note 1112 DSBGA Wafer Level Chip Scale Package (SNVA009).
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM3281YFQR
ACTIVE
DSBGA
YFQ
6
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-30 to 90
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3281YFQR
DSBGA
YFQ
6
3000
178.0
8.4
1.29
1.56
0.76
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
DSBGA YFQ
SPQ
Length (mm) Width (mm) Height (mm)
208.0 191.0 35.0
LM3281YFQR
6
3000
Pack Materials-Page 2
MECHANICAL DATA
YFQ0006x
D
0.600±0.075
E
TMD06XXX (Rev B)
D: Max = 1.465 mm, Min =1.405 mm
E: Max = 1.19 mm, Min = 1.13 mm
4215075/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
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