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LM3421-Q1, LM3423-Q1

SNVSB95 –JULY 2019

LM342x-Q1 N -Channel Controllers for Constant-Current LED Drivers

1 Features

3 Description

The LM3421-Q1 and LM3423-Q1 family of devices

are versatile high voltage N-channel MOSFET

controllers for LED drivers. They can be easily

configured in buck, boost, buck-boost and SEPIC

topologies. This flexibility, along with an input voltage

rating of 75 V, makes the these controllers ideal for

illuminating LEDs in a large family of applications.

1

•

AEC Qualified for Automotive Applications

–

Device Temperature Grade 1: −40°C ≤ T_A≤

125°C (LM3421-Q1 and LM3423-Q1)

–

Device Temperature Grade 0: −40°C ≤ T_A≤

150°C (LM3421-Q0 and LM3423-Q0)

•

V_INRange From 4.5 V to 75 V

Adjustable high-side current sense voltage allows for

tight regulation of the LED current with the highest

efficiency possible. The LM3421-Q1 and LM3423-Q1

devices use predictive off-time (PRO) control, which

is a combination of peak current-mode control and a

predictive off-timer. This method of control eases the

design of loop compensation while providing inherent

input voltage feed-forward compensation.

High-Side Adjustable Current Sense

2-Ω, 1-A Peak MOSFET Gate Driver

Input Undervoltage and Output Overvoltage

Protection

•

PWM and Analog Dimming

Cycle-by-Cycle Current Limit

Programmable Switching Frequency

Zero Current Shutdown and Thermal Shutdown

The LM3421-Q1 and LM3423-Q1 devices include a

high-voltage start-up regulator that operates over a

wide input range of 4.5 V to 75 V. The internal PWM

controller is designed for adjustable switching

frequencies of up to 2 MHz, thus enabling compact

solutions.

LED Output Status Flag (LM3423-Q1 and

LM3423-Q0 Only)

•

Fault Status Flag and Timer(LM3423-Q1 and

LM3423-Q0 Only)

Device Information⁽¹⁾

2 Applications

PART NUMBER

LM3421-Q1

PACKAGE

HTSSOP (16)

HTSSOP (20)

BODY SIZE (NOM)

5.00 mm × 4.40 mm

6.50 mm × 4.40 mm

•

LED Drivers: Buck, Boost, Buck-Boost, and

SEPIC

LM3423-Q1

•

Indoor and Outdoor Area SSL

Automotive

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

General Illumination

Constant-Current Regulators

Typical Boost Application

V_IN

1

2

3

4

5

6

7

8

VIN

HSN 16

HSP 15

RPD 14

IS 13

EN

COMP

CSH

RCT

AGND

OVP

nDIM

I_LED

VCC 12

GATE 11

PGND 10

PWM

DDRV

9

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM3421-Q1, LM3423-Q1

SNVSB95 –JULY 2019

www.ti.com

Table of Contents

1

2

3

4

5

6

7

Features.................................................................. 1

9

Application and Implementation ........................ 28

9.1 Application Information............................................ 28

9.2 Typical Applications ................................................ 32

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Device Comparison ............................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ..................................... 5

7.2 ESD Ratings ............................................................ 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics .......................................... 7

7.6 Typical Characteristics ........................................... 11

Detailed Description ............................................ 13

8.1 Overview ................................................................. 13

8.2 Functional Block Diagram ....................................... 13

8.3 Feature Description................................................. 14

10 Power Supply Recommendations ..................... 65

10.1 General Recommendations .................................. 65

10.2 Input Supply Current Limit .................................... 65

11 Layout................................................................... 65

11.1 Layout Guidelines ................................................. 65

11.2 Layout Example .................................................... 66

12 Device and Documentation Support ................. 67

12.1 Device Support...................................................... 67

12.2 Related Links ........................................................ 67

12.3 Community Resources.......................................... 67

12.4 Trademarks........................................................... 67

12.5 Electrostatic Discharge Caution............................ 67

12.6 Glossary................................................................ 67

8

13 Mechanical, Packaging, and Orderable

Information ........................................................... 67

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

Initial release of separate data sheet for atomotive grade devices. For revision history

before December 2018, see the LM3421 and LM3423 data sheet.

Changed EN Pulldown Resistance maximum value for LM3421-Q1 and LM3423-Q1 from:

1.3 MΩ to: 2.85 MΩ in the table.

July 2019

*

Changed EN Pulldown Resistance maximum value for LM3421-Q0 and LM3423-Q0 from:

1.3 MΩ to: 3.15 MΩ in the table.

Changed EN Pulldown Resistance minimum value from: 0.45 MΩ to: 0.245 MΩ in the table.

2

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5 Device Comparison

Table 1. Device Comparison

AEC-Q100 TEMPERATURE

GRADE

QUASI-PART NUMBER

TEMPERATURE RANGE, T_A

LM3421Q0

LM3421Q1

LM3423Q0

LM3423Q1

Grade 0

Grade 1

Grade 0

Grade 1

–40°C to +150°C

–40°C to +125°C

–40°C to +150°C

–40°C to +125°C

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6 Pin Configuration and Functions

PWP Package

16-Pin HTSSOP

Top View

PWP Package

20-Pin HTSSOP

Top View

VIN

EN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

HSN

HSP

RPD

IS

VIN

EN

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

HSN

HSP

RPD

IS

COMP

CSH

COMP

CSH

RCT

VCC

GATE

PGND

DDRV

VCC

GATE

AGND

OVP

AGND

OVP

nDIM

FLT

17 Thermal

Pad

0

14

PGND

DDRV

IADJ

nDIM

9

13

21 Thermal

Pad

12

11

TIMR

VREF

Pin Functions

I/O⁽¹⁾

FUNCTION

NAME

LM3423-Q1 LM3421-Q1

Analog ground. Connect to PGND through the DAP copper pad to provide ground return

for CSH, COMP, RCT, and TIMR.

AGND

COMP

6

3

6

3

G

I

Compensation. Connect a capacitor to AGND to set the compensation.

Current sense high. Connect a resistor to AGND to set the signal current. For analog

dimming, connect a controlled current source or a potentiometer to AGND as detailed in

the Analog Dimming section.

CSH

4

I

DDRV

DPOL

13

12

9

O

I

Dim gate drive output. Connect to the gate of the dimming MOSFET.

Dim polarity. Connect to AGND if dimming with a series P-channel MOSFET or leave

open when dimming with series N-channel MOSFET.

—

Enable. Connect to AGND for zero current shutdown or apply more than 2.4 V to enable

device.

EN

2

I

Fault flag. Connect to pullup resistor from VIN and N-channel MOSFET open-drain

output is high when a fault condition is latched by the timer.

FLT

9

—

11

16

I

O

I

GATE

HSN

15

20

Main gate drive output. Connect to the gate of the main switching MOSFET.

LED current sense negative. Connect through a series resistor to the negative side of

the LED current sense resistor.

LED current sense positive. Connect through a series resistor to the positive side of the

LED current sense resistor.

HSP

IS

19

17

11

15

13

—

I

Main switch current sense. Connect to the drain of the main N-channel MOSFET switch

for R_DS-ONsensing or to a sense resistor installed in the source of the same device.

LED ready flag. Connect to pullup resistor from VIN and N-channel MOSFET open-drain

output pulls down when the LED current is not in regulation.

LRDY

O

Dimming input and undervoltage protection. Connect a PWM signal for dimming as

detailed in the PWM Dimming section and/or a resistor divider from V_INto program input

undervoltage lockout (UVLO). Turnon threshold is 1.24 V and hysteresis for turnoff is

provided by a 23-µA current source.

nDIM

OVP

8

7

8

7

I

Overvoltage protection. Connect to a resistor divider from V_Oto program output

overvoltage lockout (OVLO). Turnoff threshold is 1.24 V and hysteresis for turnon is

provided by 23-µA current source.

Power ground. Connect to AGND through the DAP copper pad to provide ground return

for GATE and DDRV.

PGND

RCT

14

5

10

5

G

I

Resistor capacitor timing. External RC network sets the predictive off-time and thus the

switching frequency.

(1) G = Ground, I = Input, O = Output

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Pin Functions (continued)

I/O⁽¹⁾

FUNCTION

NAME

LM3423-Q1 LM3421-Q1

Resistor pulldown. Connect the low side of all external resistor dividers (V_INUVLO,

OVP) to implement zero-current shutdown.

RPD

18

10

14

—

I

Fault timer. Connect a capacitor to AGND to set the time delay before a sensed fault

condition is latched.

TIMR

V_IN

Input voltage. Bypass with 100-nF capacitor to AGND as close to the device as possible

in the printed-circuit-board layout.

1

V_CC

16

12

I

Internal regulator output. Bypass with 2.2-µF to 3.3-µF ceramic capacitor to PGND.

Thermal PAD on bottom of IC. Star ground, connecting AGND and PGND.

Star ground, connecting AGND and PGND.

Thermal PAD

DAP

G

DAP (21)

DAP (17)

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

MAX

UNIT

V

76

V_IN, EN, RPD, nDIM

OVP, HSP, HSN, LRDY, FLT, DPOL

RCT

–1 continuous

–0.3

mA

V

76

–100 continuous

–0.3

µA

V

76

5 continuous

76

–1 continuous

–0.3

mA

V

IS

–2 for 100 ns

–1 continuous

–0.3

mA

V

V_CC

8

–0.3

7

100 continuous

6

V

TIMR

–100 continuous

–0.3

µA

V

COMP, CSH

GATE, DDRV

PGND

–200 continuous

–0.3

200 continuous

V_CC

µA

V

mA

V

–2.5 for 100 ns

–1 continuous

–0.3

V_CC+ 2.5 for 100 ns

1 continuous

0.3

–2.5 for 100 ns

2.5 for 100 ns

Continuous power dissipation

Maximum junction temperature

Internally Limited

(3)

Maximum lead temperature (solder and reflow)

260

150

°C

Storage temperature

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) Refer to http://www.ti.com/packaging for more detailed information and mounting techniques.

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7.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

V

V_(ESD)

Electrostatic discharge

All Pins

Pin 4

Charged-device model (CDM), per AEC

Q100-011

±500

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

MIN

MAX

125

150

75

UNIT

°C

Operating junction temperature, T_J

Input voltage, V_IN

LM3421-Q1 , LM3423-Q1

LM3421-Q0, LM3423-Q0

−40

4.5

°C

V

7.4 Thermal Information

LM3421-Q1

LM3423-Q1

THERMAL METRIC⁽¹⁾

PWP (HTSSOP)

UNIT

16 PINS

38.9

23.1

16.8

0.6

20 PINS

36.7

21.5

18

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JB

16.6

1.7

17.8

1.9

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6

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7.5 Electrical Characteristics

V_IN= 14, −40°C ≤ T_J≤ 150°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

START-UP REGULATOR

TEST CONDITIONS

MIN

6.3

20

TYP

MAX

UNIT

I_CC= 0 mA

7.35

V_CCREG

V_CCregulation

V

I_CC= 0 mA, T_A= 25°C

V_CC= 0 V

6.9

25

I_CCLIM

V_CCcurrent limit

mA

V_CC= 0 V, T_A= 25°C

LM3421-Q1,

LM3423-Q1

3

V_EN= 3 V, Static

I_Q

Quiescent current

Shutdown current

LM3421-Q0,

LM3423-Q0

3.5

mA

µA

V_EN= 3 V, Static, −40°C ≤ T_J≤ 125°C

V_EN= 0 V

2

1

I_SD

V_EN= 0 V, T_A= 25°C

0.1

V_CCSUPPLY

V_CCIncreasing

4.5

V_CCIncreasing, T_A= 25°C

V_CCDecreasing

4.17

V_CCUV

V_CCUVLO Threshold

V_CCUVLO Hysteresis

V

3.7

V_CCDecreasing, T_A= 25°C

T_A= 25°C

4.08

0.1

V_CCHYS

ENABLE THRESHOLDS

LM3421-Q1,

LM3423-Q1

2.4

V_ENIncreasing

V

EN_ST

EN start-up threshold

LM3421-Q0,

LM3423-Q0

2.75

V_ENIncreasing, T_A= 25°C

V_ENDecreasing

1.75

0.8

EN_ST

EN start-up threshold

EN start-up hysteresis

V

V_ENDecreasing, T_A= 25°C

T_A= 25°C

1.63

0.1

EN_STHYS

LM3421-Q1,

LM3423-Q1

0.245

2.85

3.15

V_EN= 1 V

R_EN

EN pulldown resistance

LM3421-Q0,

LM3423-Q0

MΩ

V_EN= 1 V, T_A= 25°C

0.82

CSH THRESHOLDS

CSH high fault

CSH Increasing, T_A= 25°C

CSH increasing, T_A= 25°C

1.6

1

V

CSH low condition on LRDY

LM3423-Q1,

LM3423-Q0

OV THRESHOLDS

OVP Increasing

1.185

1.285

OVP_CB

OVP OVLO threshold

V

OVP Increasing, T_A= 25°C

1.24

23

LM3421-Q1,

LM3423-Q1

20

25

26

OVP Active (high)

OVP_HYS

OVP hysteresis source current

LM3421-Q0,

LM3423-Q0

µA

OVP Active (high), T_A= 25°C

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Electrical Characteristics (continued)

V_IN= 14, −40°C ≤ T_J≤ 150°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

DPOL THRESHOLDS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DPOL Increasing

2

2.6

DPOL_THRSHDPOL logic threshold

V

DPOL Increasing, T_A= 25°C

2.3

1200

R_DPOL

DPOL pullup resistance

kΩ

T_A= 25°C

500

FAULT TIMER

LM3421-Q1,

LM3423-Q1

1.185

1.285

1.29

V

V_FLTTH

Fault threshold

LM3421-Q0,

LM3423-Q0

T_A= 25°C

1.24

11.5

LM3421-Q1,

LM3423-Q1

10

13

I_FLT

FAULT pin source current

LM3421-Q0,

LM3423-Q0

µA

13.5

ERROR AMPLIFIER

w/r/t to AGND

1.21

1.26

V_REF

CSH reference voltage

V

w/r/t to AGND, T_J= 25°C

1.235

0

Error amplifier input bias

current

T_J= 25°C

–0.6

22

0.6

35

36

µA

LM3421-Q1,

LM3423-Q1

COMP sink or source current

LM3421-Q0,

LM3423-Q0

µA

22

T_J= 25°C

30

100

Transconductance

Linear input range

T_J= 25°C

µA/V

mV

⁽¹⁾, T_J= 25°C

±125

(1)

–6dB Unloaded Response

MIN = T_J= 25°C

,

Transconductance bandwidth

0.5

1

MHz

OFF TIMER

LM3421-Q1,

LM3423-Q1

75

90

RCT = 1 V through 1 kΩ

t_OFF(min)

Minimum OFF-time

LM3421-Q0,

LM3423-Q0

ns

RCT = 1 V through 1 kΩ, T_J= 25°C

LM3421-Q1,

35

36

120

125

LM3423-Q1

Ω

R_RCT

RCT reset pulldown resistance

V_IN/25 reference voltage

LM3421-Q0,

LM3423-Q0

T_J= 25°C

LM3421-Q1,

LM3423-Q1

540

585

590

V_IN= 14 V

V_RCT

LM3421-Q0,

LM3423-Q0

mV

V_IN= 14 V, T_J= 25°C

565

(1) Specified by design. Not production tested.

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Electrical Characteristics (continued)

V_IN= 14, −40°C ≤ T_J≤ 150°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Continuous conduction

switching frequency

(2)

f

2.2 nF > C_T> 470 pF, T_J= 25°C

(See

)

Hz

PWM COMPARATOR

COMP-to-PWM offset voltage

CURRENT LIMIT (IS)

700

215

900

275

mV

T_J= 25°C

800

245

I_LIM

Current limit threshold

LM3421-Q1,

LM3423-Q1

75

90

Current limit delay-to-output

LM3421-Q0,

LM3423-Q0

ns

T_J= 25°C

35

210

11.5

119

0

115

325

Leading edge blanking (LEB)

time

t_LEB

HIGH SIDE TRANSCONDUCTANCE AMPLIFIER

Input bias current

T_J= 25°C

µA

20

–1.5

–7

g_M

Transconductance

mA/V

T_J= 25°C

1.5

7

Input offset current

µA

Input offset voltage

mV

T_J= 25°C

0

g_M(BW)

Transconductance bandwidth

I_CSH= 100 µA⁽¹⁾, T_J= 25°C

250

500

kHz

GATE DRIVER (GATE)

GATE = High

6

R_SRC(GATE)GATE sourcing resistance

Ω

GATE = High, T_J= 25°C

GATE = Low

2

4.5

R_SNK(GATE)

GATE sinking resistance

GATE = Low, T_J= 25°C

1.3

DIM DRIVER (DIM, DDRV)

1.185

1.285

nDIM_VTH

nDIM_HYS

nDIM / UVLO threshold

V

T_J= 25°C

1.24

LM3421-Q1,

LM3423-Q1

20

25

26

nDIM hysteresis current

LM3421-Q0,

LM3423-Q0

µA

T_J= 25°C

23

13.5

3.5

DDRV = High

30

10

R_SRC(DDRV)

DDRV sourcing resistance

DDRV sinking resistance

Ω

DDRV = High, T_J= 25°C

DDRV = Low

R_SNK(DDRV)

DDRV = Low, T_J= 25°C

(2) f = 25/(C_T× R_T

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Electrical Characteristics (continued)

V_IN= 14, −40°C ≤ T_J≤ 150°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PULLDOWN N-CHANNEL MOSFETS

LM3421-Q1,

LM3423-Q1

300

350

R_RPD

RPD pulldown resistance

FLT pulldown resistance

LRDY pulldown resistance

LM3421-Q0,

LM3423-Q0

Ω

T_J= 25°C

145

135

LM3421-Q1,

LM3423-Q1

300

350

R_FLT

LM3421-Q0,

LM3423-Q0

Ω

LM3421-Q1,

LM3423-Q1

300

350

R_LRDY

LM3421-Q0,

LM3423-Q0

T_J= 25°C

THERMAL SHUTDOWN

T_SD

Thermal shutdown threshold⁽¹⁾

165

°C

LM3421-Q1,

LM3423-Q1

T_SD

Thermal shutdown threshold⁽¹⁾

T_J= 25°C

LM3421-Q0,

LM3423-Q0

210

25

Thermal shutdown

hysteresis⁽¹⁾

T_HYS

°C

10

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7.6 Typical Characteristics

T_A= 25°C, V_IN= 14 V unless otherwise specified

V_O= 32 V (9 LEDs)

V_O= 21 V (6 LEDs)

Figure 2. Buck-Boost Efficiency vs. Input Voltage

Figure 1. Boost Efficiency vs. Input Voltage

V_O= 21 V (6 LEDs)

Figure 4. Buck-Boost LED Current vs. Input Voltage

V_O= 32V (9 LEDs)

Figure 3. Boost LED Current vs. Input Voltage

V_O= 21 V (6 LEDs), V_IN= 24 V

V_O= 32 V (9 LEDs), V_IN= 24 V

Figure 5. Analog Dimming

Figure 6. PWM Dimming

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Typical Characteristics (continued)

T_A= 25°C, V_IN= 14 V unless otherwise specified

Figure 8. V_CCvs Junction Temperature

Figure 7. V_CSHvs Junction Temperature

567

566

565

564

563

562

-50

-14

22

58

94

130

TEMPERATURE (°C)

Figure 9. V_RCTvs Junction Temperature

Figure 10. V_LIMvs Junction Temperature

225

220

215

210

205

200

195

-50

-14

22

58

94

130

TEMPERATURE (°C)

Figure 11. t_ON(min)vs Junction Temperature

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8 Detailed Description

8.1 Overview

The LM3421-Q1 and LM3423-Q1 are N-channel MOSFET ( N-channel FET ) controllers for buck, boost and

buck-boost current regulators which are ideal for driving LED loads. The controller has wide input voltage range

allowing for regulation of a variety of LED loads. The high-side differential current sense, with low adjustable

threshold voltage, provides an excellent method for regulating output current while maintaining high system

efficiency.

The devices use a Predictive Off-time (PRO) control architecture that allows the regulator to be operated using

minimal external control loop compensation, while providing an inherent cycle-by-cycle current limit. The

adjustable current sense threshold provides the capability to amplitude (analog) dim the LED current and the

output enable and disable function with external dimming FET driver allows for fast PWM dimming of the LED

load. The maximum attainable LED current is not internally limited because the device is a controller. Instead,

current is a function of the system operating point, component choices, and switching frequency that allows the

device to easily provide constant currents up to 5 A. This controller contains all the features necessary to

implement a high-efficiency versatile LED driver.

8.2 Functional Block Diagram

V_IN

6.9V LDO

Regulator

EN

V_CC

V

UVLO

820k

CC

UVLO

(4.1V)

1.235V

REFERENCE

Standby

500k

V

IN

UVLO

HYSTERESIS

DPOL

DDRV

V

CC

23 mA

TLIM

Thermal

Limit

nDIM

RCT

Dimming

1.24V

OVLO

LatchOff

PGND

Reset

Dominant

Start new on time

V

CC

V

IN

/25

Q

S

R

LEB

GATE

PGND

t = 150 ns

COMP

CSH

RPD

PWM

23 mA

OVP

HYSTERESIS

1.235V

EN

OVLO

OVP

800 mV

1.24V

LOGIC

HSP

HSN

LRDY

CURRENT

LIMIT

IS

0.245V

11.5 mA

LED CURRENT LOW

LED CURRENT HIGH

LEB

1.0V

1.6V

LatchOff

TIMR

FLT

1.24V

AGND

TLIM

Grey pins are available in the LM3423 only.

V

UVLO

CC

In the LM3421, TIMR is internally shorted to AGND.

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8.3 Feature Description

8.3.1 Current Regulators

i_L(t)

I

L-MAX

Âi

L-PP

I

L

I

L-MIN

t

= DT

t

= (1-D)T

OFF S

ON

S

0

t

T

S

Figure 12. Ideal CCM Regulator Inductor Current i_L(t)

Current regulators can create three basic topologies: buck, boost, or buck-boost. All three topologies in their

most basic form contain a main switching MOSFET, a recirculating diode, an inductor and capacitors. The

controller is designed to drive a ground referenced N-channel FET which is perfect for a standard boost

regulator. However, buck and buck-boost regulators usually have a high-side switch. When driving an LED load,

a ground referenced load is often not necessary, therefore a ground referenced switch drives a floating load

instead. The controller can then be used to drive all three basic topologies as shown in the Basic Topology

Schematics section. Other topologies such as the SEPIC and flyback converter (both derivatives of the buck-

boost) can be implemented as well.

Looking at the buck-boost design, the basic operation of a current regulator can be analyzed. During the time

that the N-channel FET (Q1) is turned on (t_ON), the input voltage source stores energy in the inductor (L1) while

the output capacitor (C_O) provides energy to the LED load. When Q1 is turned off (t_OFF), the re-circulating diode

(D1) becomes forward biased and L1 provides energy to both C_Oand the LED load. Figure 12 shows the

inductor current (i_L(t)) waveform for a regulator operating in CCM.

The average output LED current (I_LED) is proportional to the average inductor current (I_L) , therefore if I_Lis tightly

controlled, I_LEDis well regulated. As the system changes input voltage or output voltage, the ideal duty cycle (D)

is varied to regulate I_Land ultimately I_LED. For any current regulator, D is a function of the conversion ratio:

Buck

V_O

D =

V

IN

(1)

Boost

V_O- V

IN

D =

V_O

(2)

Buck-boost

V_O

D

=

V_O+ V

IN

(3)

8.3.2 Predictive Off-Time (PRO) Control

PRO control is used by the device to control I_LED. It is a combination of average peak current control and a one-

shot off-timer that varies with input voltage. The LM3421-Q1 and LM3423-Q1 use peak current control to

regulate the average LED current through an array of HBLEDs. This method of control uses a series resistor in

the LED path to sense LED current and can use either a series resistor in the MOSFET path or the MOSFET

R_DS-ONfor both cycle-by-cycle current limit and input voltage feed forward. D is indirectly controlled by changes in

both t_OFFand t_ON, which vary depending on the operating point.

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Feature Description (continued)

Even though the off-time control is quasi-hysteretic, the input voltage proportionality in the off-timer creates an

essentially constant switching frequency over the entire operating range for boost and buck-boost topologies.

The buck topology can be designed to give constant ripple over either input voltage or output voltage, however

switching frequency is only constant at a specific operating point .

This type of control minimizes the control loop compensation necessary in many switching regulators, simplifying

the design process. The averaging mechanism in the peak detection control loop provides extremely accurate

LED current regulation over the entire operating range.

PRO control was designed to mitigate current mode instability (also called sub-harmonic oscillation) found in

standard peak current mode control when operating near or above 50% duty cycles. When using standard peak

current mode control with a fixed switching frequency, this condition is present, regardless of the topology.

However, using a constant off-time approach, current mode instability cannot occur, enabling easier design and

control.

Predictive off-time advantages:

•

There is no current mode instability at any duty cycle.

Higher duty cycles or voltage transformation ratios are possible, especially in the boost regulator.

The only disadvantage is that synchronization to an external reference frequency is generally not available.

8.3.3 Average LED Current

LM3421/23

I

LED

High-Side

Sense Amplifier

R

HSP

HSN

V

R

SNS

R

HSN

I

CSH

R

C

CSH

Error Amplifier

CSH

To PWM

Comparator

1.24V

CMP

COMP

Figure 13. LED Current Sense Circuitry

The LM3421-Q1 and LM3423-Q1 use an external current sense resistor (R_SNS) placed in series with the LED

load to convert the LED current (I_LED) into a voltage (V_SNS) as shown in Figure 13. The HSP and HSN pins are

the inputs to the high-side sense amplifier which are forced to be equal potential (V_HSP=V_HSN) through negative

feedback. Because of this, the V_SNSvoltage is forced across R_HSPto generate the signal current (I_CSH) which

flows out of the CSH pin and through the R_CSHresistor. The error amplifier regulates the CSH pin to 1.24 V,

therefore I_CSHcan be calculated using Equation 4.

V_SNS

R_HSP

I_CSH

=

(4)

(5)

This application regulates V_SNSas described in Equation 5.

R_HSP

V_SNS= 1.24V x

R_CSH

Calculate I_LEDusing Equation 6.

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Feature Description (continued)

V_SNS

R_SNS

1.24V R_HSP

x

I_LED

=

R_SNS

R_CSH

(6)

The selection of the three resistors (R_SNS, R_CSH, and R_HSP) is not arbitrary. For matching and noise performance,

the suggested signal current I_CSHis approximately 100 µA. This current does not flow in the LEDs and does not

affect either the off-state LED current or the regulated LED current. I_CSHcan be above or below this value, but

the high-side amplifier offset characteristics may be affected slightly. In addition, to minimize the effect of the

high-side amplifier voltage offset on LED current accuracy, the minimum V_SNSis suggested to be 50 mV. Place a

resistor (R_HSN= R_HSP) in series with the HSN pin to cancel out the effects of the input bias current (approximately

10 µA) of both inputs of the high-side sense amplifier.

The sense resistor (R_SNS) can be placed anywhere in the series string of LEDs as long as the voltage at the HSN

and HSP pins (V_HSPand V_HSN) satisfies the following conditions.

V_HSP< 76V

V_HSN> 3.5V

(7)

Typically, for a buck-boost configuration, R_SNSis placed at the bottom of the string (LED-) which allows for

greater flexibility of input and output voltage. However, if there is substantial input voltage ripple allowed, it can

help to place R_SNSat the top of the string (LED+) which limits the output voltage of the string to:

V_O= 76V - V_IN

(8)

The CSH pin can also be used as a low-side current sense input regulated to 1.24 V. The high-side sense

amplifier is disabled if HSP and HSN are tied to AGND (or V_HSN> V_HSP) .

8.3.4 Analog Dimming

The CSH pin can be used to analog dim the LED current by adjusting the current sense voltage (V_SNS). There

are several different methods to adjust V_SNSusing the CSH pin:

1. External variable resistance: Adjust a potentiometer placed in series with R_CSHto vary V_SNS

.

2. External variable current source: Source current (0 µA to I_CSH) into the CSH pin to adjust V_SNS

.

Variable Current Source

LM3421/23

V_CC

V

REF

Q8

Q7

R

MAX

Q6

R

CSH

R

CSH

R

ADJ

BIAS

Variable

Resistance

R

ADJ

Figure 14. Analog Dimming Circuitry

In general, analog dimming applications require a lower switching frequency to minimize the effect of the leading

edge blanking circuit. As the LED current is reduced, the output voltage and the duty cycle decreases.

Eventually, the minimum on-time is reached. The lower the switching frequency, the wider the linear dimming

range. Figure 14 shows how both CSH methods are physically implemented.

Method 1 uses an external potentiometer in the CSH path which is a simple addition to the existing circuitry.

However, the LEDs cannot dim completely because there is always some resistance causing signal current to

flow. This method is also susceptible to noise coupling at the CSH pin because the potentiometer increases the

size of the signal current loop.

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Feature Description (continued)

Method 2 provides a complete dimming range and better noise performance, though it is more complex. It

consists of a PNP current mirror and a bias network consisting of an NPN, 2 resistors and a potentiometer

(R_ADJ), where R_ADJcontrols the amount of current sourced into the CSH pin. A higher resistance value sources

more current into the CSH pin, causing less regulated signal current through R_HSP, effectively dimming the LEDs.

V_REFshould be a precise external voltage reference, while Q7 and Q8 should be a dual pair PNP for best

matching and performance. The additional current (I_ADD) sourced into the CSH pin can be calculated using

Equation 9.

≈

∆

«

’

÷

R_ADJx V_REF

R_ADJ+ R_MAX

- V_BE-Q6

◊

I_ADD

=

R_BIAS

(9)

The corresponding LED current ( I_LED) for a specific I_ADDis:

R

≈

∆

«

’

÷

◊

HSP

I_LED= (I_CSH- I_ADD) x

R_SNS

(10)

8.3.5 Current Sense and Current Limit

The LM3421-Q1 and LM3423-Q1 achieve peak current mode control using a comparator that monitors the main

MOSFET (Q1) transistor current, comparing it with the COMP pin voltage as shown in Figure 15. The controller

incorporates a cycle-by-cycle overcurrent protection function. Aredundant internal current sense comparator

provides the current limit functionality . If the voltage at the current sense comparator input (IS pin) exceeds 245

mV (typical), the on cycle is immediately terminated. The IS input pin has an internal N-channel MOSFET which

pulls it down at the conclusion of every cycle. The discharge device remains on for an additional 210 ns (typical)

after the beginning of a new cycle to blank the leading edge spike on the current sense signal. The leading edge

blanking (LEB) determines the minimum achievable on-time (t_ON-MIN).

R

DS-ON

Sensing

LM3421/23

COMP

Q1

GATE

IS

0.8V

PWM

R

LIM

Sensing

0.245V

I

T

R

LIM

LEB

PGND

Figure 15. Current Sense / Current Limit Circuitry

There are two possible methods to sense the transistor current. The R_DS-ONof the main power MOSFET can be

used as the current sense resistance because the IS pin was designed to withstand the high voltages present on

the drain when the MOSFET is in the off state. Alternatively, a sense resistor located in the source of the

MOSFET may be used for current sensing; however, TI suggests a low inductance (ESL) type. The cycle-by-

cycle current limit (I_LIM) can be calculated using either method as the limiting resistance (R_LIM):

245 mV

R_LIM

I_LIM

=

(11)

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Feature Description (continued)

8.3.6 Overcurrent Protection

The LM3421-Q1 and LM3423-Q1 controllers have a secondary method of overcurrent protection. Switching

action is disabled whenever the current in the LEDs is more than 30% above the regulation set point. The

dimming MOSFET switch driver (DDRV) is not disabled however as this would immediately remove the fault

condition and cause oscillatory behavior.

8.3.7 Zero Current Shutdown

The LM3421-Q1 and LM3423-Q1 controllers implement zero current shutdown through the EN and RPD pins.

When pulled low, the EN pin places the devices into near-zero current state, where only the leakage currents

occurs at the pins (typical 0.1 µA). The applications circuits frequently have resistor dividers to set UVLO, OVLO,

or other similar functions. The RPD pin is an open-drain N-channel MOSFET that is enabled only when the

device is enabled. Tying the bottom of all resistor dividers to the RPD pin as shown in Figure 16 allows them to

float during shutdown, thus removing their current paths and providing true application-wide zero current

shutdown.

L1

D1

V_IN

V_O

LM3421/23

Enable

EN

R

OV2

V_IN

OVP

RPD

R

OV1

UV2

nDIM

R

UV1

Figure 16. Zero Current Shutdown Circuit

8.3.8 Control Loop Compensation

The control loop is modeled as most typical current mode controllers. Using a first order approximation, the

uncompensated loop can be modeled as a single pole created by the output capacitor and, in the boost and

buck-boost topologies, a right half plane zero created by the inductor, where both have a dependence on the

LED string dynamic resistance. There is also a high-frequency pole in the model; however, it is near the

switching frequency and plays no part in the compensation design process. Therefore, it is neglected. Because

ceramic capacitance is recommended for use with LED drivers, due to long lifetimes and high ripple current

rating, the ESR of the output capacitor can also be neglected in the loop analysis. The DC gain of the

uncompensated loop depends on internal controller gains and the external sensing network.

This section describes a buck-boost regulator as an example case.

Use Equation 12 to calculate the uncompensated loop gain for a buck-boost regulator.

≈

’

÷

◊

s

w_Z1

∆ -

1

∆

«

T_U= T_U0

x

≈

’

÷

◊

s

w_P1

∆

1+

∆

«

(12)

(13)

Where the uncompensated DC loop gain of the system is calculated using Equation 13.

Å

D x 500Vx R_CSHx R_SNS

Å

D x 620V

T_U0

=

(

)

(

)

1+D x R_HSPx R_LIM

1+D xI_LEDx R_LIM

And the output pole (ω_P1) is approximated using Equation 14.

1+D

w_P1=

r_Dx C_O

(14)

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Feature Description (continued)

And the right half plane zero (ω_Z1) is:

Å²

r_DxD

w_Z1=

DxL1

(15)

135

90

100

80

60

40

20

0

ö

P1

ö

Z1

GAIN

45

0

PHASE

-45

-90

-135

-180

-225

0°Phase Margin

-20

-40

-60

1e-1

1e1

1e3

1e5

1e7

FREQUENCY (Hz)

Figure 17. Uncompensated Loop Gain Frequency Response

Figure 17 shows the uncompensated loop gain in a worst-case scenario when the RHP zero is below the output

pole. This occurs at high duty cycles when the regulator is trying to boost the output voltage significantly. The

RHP zero adds 20dB/decade of gain while losing 45°/decade of phase, which places the crossover frequency

(when the gain is zero dB) extremely high because the gain only starts falling again due to the high-frequency

pole (not shown in Figure 17). The phase is below –180° at the crossover frequency, which means there is no

phase margin (180° + phase at crossover frequency) causing system instability. Even if the output pole is below

the RHP zero, the phase reaches –180° before the crossover frequency in most cases yielding instability.

LM3421/23

I

LED

High-Side

Sense Amplifier

R

HSP

HSN

C

FS

V

SNS

R

SNS

R

HSN

R

FS

Error Amplifier

sets ö

P3

R

CSH

To PWM

Comparator

1.24V

R

O

C

CMP

sets ö

COMP

P2

Figure 18. Compensation Circuitry

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Feature Description (continued)

To mitigate this problem, a compensator should be designed to give adequate phase margin (above 45°) at the

crossover frequency. A simple compensator using a single capacitor at the COMP pin (C_CMP) adds a dominant

pole to the system, which ensures adequate phase margin if placed low enough. At high duty cycles (as shown

in Figure 17), the RHP zero places extreme limits on the achievable bandwidth with this type of compensation.

However, because an LED driver is essentially free of output transients (except catastrophic failures open or

short), the dominant pole approach, even with reduced bandwidth, is usually the best approach. The dominant

compensation pole (ω_P2) is determined by C_CMPand the output resistance (R_O) of the error amplifier (typically 5

MΩ) as demonstrated in Equation 16.

1

w_P2

=

5ì10⁶ìC_CMP

(16)

It may also be necessary to add one final pole at least one decade above the crossover frequency to attenuate

switching noise and, in some cases, provide better gain margin. This pole can be placed across R_SNSto filter the

ESL of the sense resistor at the same time. Figure 18 shows how the compensation is physically implemented in

the system.

The high-frequency pole (ω_P3) can be calculated using Equation 17.

1

w_P3

=

R_FSxC_FS

(17)

The total system transfer function becomes:

≈

’

÷

◊

s

w_Z1

∆

1-

∆

«

T = T_U0

x

≈

’

÷

◊

≈

∆

«

’

≈

∆

«

’

÷

◊

s

w_P1

s

w_P2

s

w_P3

∆

÷

∆

1+

x 1+

∆

÷

«

◊

(18)

The resulting compensated loop gain frequency response shown in Figure 19 indicates that the system has

adequate phase margin (above 45°) if the dominant compensation pole is placed low enough, ensuring stability.

90

80

60

ö

P2

45

0

40

GAIN

-45

-90

-135

-180

-225

-270

20

ö

Z1

P1

0

PHASE

ö

P3

-20

-40

-60

-80

60°Phase Margin

1e-1

1e1

1e3

1e5

1e7

FREQUENCY (Hz)

Figure 19. Compensated Loop Gain Frequency Response

8.3.9 Start-Up Regulator

The controller includes a high voltage, low dropout bias regulator. When power is applied, the regulator is

enabled and sources current into an external capacitor (C_BYP) connected to the V_CCpin. The recommended

bypass capacitance for the V_CCregulator is 2.2 µF to 3.3 µF. The output of the V_CCregulator is monitored by an

internal UVLO circuit that protects the device from attempting to operate with insufficient supply voltage and the

supply is also internally current limited. Figure 20 shows the typical start-up waveforms.

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Feature Description (continued)

V

CMP

0.9V

0

t

CO

VCC

CMP

Figure 20. Start-Up Waveforms

First, C_BYPis charged to be above V_CCUVLO threshold (approximately 4.2 V). The C_VCCcharging time (t_VCC) can

be estimated using Equation 19.

4.2V

25 mA

t_VCC

xC_BYP168W xC

=

BYP

=

(19)

C_CMPis then charged to 0.9 V over the charging time (t_CMP), which can be estimated using Equation 20.

0.9V

25 mA

t_CMP

x C_CMP36 kW xC

=

CMP

=

(20)

Once C_CMP= 0.9 V, the part starts switching to charge C_Ountil the LED current is in regulation. The C_Ocharging

time (t_CO) can be roughly estimated using Equation 21.

V_O

I_LED

t_CO

C

_Ox

=

(21)

The system start-up time (t_SU) is defined using Equation 22.

t_SU

t

+

CO

=

+

VCC

CMP

(22)

In some configurations, the start-up waveform overshoots the steady state COMP pin voltage. In this case, the

LED current and output voltage overshoots also, which can trip the overvoltage or protection, causing a race

condition. The easiest way to prevent this is to use a larger compensation capacitor (C_CMP), thereby slowing

down the control loop.

8.3.10 Overvoltage Lockout (OVLO)

The LM3421-Q1 and LM3423-Q1 can be configured to detect an output (or input) overvoltage condition through

the OVP pin. The pin features a precision 1.24-V threshold with 23 µA (typical) of hysteresis current as shown in

Figure 21. When the OVLO threshold is exceeded, the GATE pin is immediately pulled low and a 23-µA current

source provides hysteresis to the lower threshold of the OVLO hysteretic band.

If the LEDs are referenced to a potential other than ground (floating), as in the buck-boost and buck

configuration, the output voltage (V_O) should be sensed and translated to ground by using a single PNP as

shown in Figure 22.

The overvoltage turnoff threshold (V_TURN-OFF) is defined:

Ground Referenced

≈

’

R_OV+ R_OV2

1

∆

«

÷

◊

V_TURN-OFF= 1.24Vx

R_OV1

(23)

Floating

V_TURN-OFF= 1.24Vx

≈

’

+ R_OV2

R_OV1

0.5 x R_OV1

∆

«

÷

◊

(24)

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Feature Description (continued)

In the ground referenced configuration, the voltage across R_OV2is V_O– 1.24 V whereas in the floating

configuration it is V_O– 620 mV where 620 mV approximates V_BEof the PNP.

The overvoltage hysteresis (V_HYSO) is defined using Equation 25.

V_HYSO= 23 mA x R_OV2

(25)

LM3421/23

V_O

23 mA

R

OV2

OV1

OVP

OVLO

1.24V

Figure 21. Overvoltage Protection Circuitry

LED+

R

OV2

LM3421/23

LED-

OVP

R

OV1

Figure 22. Floating Output OVP Circuitry

The OVLO feature can cause some interesting results if the OVLO trip-point is set too close to V_O. At turnon, the

converter has a modest amount of voltage overshoot before the control loop gains control of I_LED. If the overshoot

exceeds the OVLO threshold, the controller shuts down, opening the dimming MOSFET. This isolates the LED

load from the converter and the output capacitance. The voltage then discharges very slowly through the HSP

and HSN pins until V_Odrops below the lower threshold, where the process repeats. This looks like the LEDs are

blinking at around 2 Hz. This mode can be escaped if the input voltage is reduced.

8.3.11 Input Undervoltage Lockout (UVLO)

The nDIM pin is a dual-function input that features an accurate 1.24-V threshold with programmable hysteresis

as shown in Figure 23. This pin functions as both the PWM dimming input for the LEDs and as a V_INUVLO.

When the pin voltage rises and exceeds the 1.24-V threshold, 23 µA (typical) of current is driven out of the nDIM

pin into the resistor divider providing programmable hysteresis.

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Feature Description (continued)

LM3421/23

V_IN

23 mA

R

UV2

UV1

nDIM

UVLO

1.24V

R

UVH

(optional)

Figure 23. UVLO Circuit

When using the nDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra series

resistor to set the hysteresis. This allows the standard resistor divider to have smaller resistor values minimizing

PWM delays due to a pulldown MOSFET at the nDIM pin (see PWM Dimming section). In general, at least 3 V of

hysteresis is preferable when PWM dimming, if operating near the UVLO threshold.

The turnon threshold (V_TURN-ON) is defined using Equation 26.

≈

’

÷

◊

R_UV+ R_UV2

1

∆

«

V_TURN_O-N= 1.24Vx

R_UV1

(26)

(27)

The hysteresis (V_HYS) is defined as follows:

8.3.11.1 UVLO Only

V_HYS23 mA xR

=

UV2

8.3.11.2 PWM Dimming and UVLO

≈

∆

«

(

)’

÷

◊

R_UVHx R_UV1+ R_UV2

∆

23mA x R

V_HYS

=

+

UV2

÷

R_UV1

(28)

When zero current shutdown and UVLO are implemented together, the EN pin can be used to escape UVLO.

The nDIM pin pulls up to V_INwhen EN is pulled low. Therefore, if V_INis within the UVLO hysteretic window when

EN is pulled high again, the controller starts-up even though V_TURN-ONis not exceeded.

8.3.12 PWM Dimming

The active low nDIM pin can be driven with a PWM signal which controls the main N-channel FET and the

dimming FET (dimFET). The brightness of the LEDs can be varied by modulating the duty cycle of this signal.

LED brightness is approximately proportional to the PWM signal duty cycle, (that is, 30% duty cycle equals

approximately 30% LED brightness). This function can be ignored if PWM dimming is not required by using nDIM

solely as a V_INUVLO input as described in Input Undervoltage Lockout (UVLO) or by tying it directly to V_CCor

V_IN.

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Feature Description (continued)

Inverted

PWM

V_IN

LM3421/23

nDIM

D

DIM

R

UV2

R

UVH

R

UV1

Q

DIM

Standard

PWM

Figure 24. PWM Dimming Circuit

STOPPED DD EDITING HERELM3421-Q1 and LM3423-Q1

Figure 24 shows how the PWM signal is applied to nDIM:

1. Connect the dimming MOSFET (Q_DIM) with the drain to the nDIM pin and the source to AGND. Apply an

external logic-level PWM signal to the gate of Q_DIM

.

2. Connect the anode of a Schottky diode (D_DIM) to the nDIM pin. Apply an inverted external logic-level PWM

signal to the cathode of the same diode.

The DDRV pin is a PWM output that follows the nDIM PWM input signal. When the nDIM pin rises, the DDRV pin

rises and the PWM latch reset signal is removed allowing the main MOSFET Q1 to turn on at the beginning of

the next clock set pulse. In boost and buck-boost topologies, the DDRV pin is used to control a N-channel

MOSFET placed in series with the LED load, while it would control a P-channel MOSFET in parallel with the load

for a buck topology.

The series dimFET opens the LED load, when nDIM is low, effectively speeding up the rise and fall times of the

LED current. Without any dimFET, the rise and fall times are limited by the inductor slew rate and dimming

frequencies above 1 kHz are impractical. Using the series dimFET, dimming frequencies up to 30 kHz are

achievable. With a parallel dimFET (buck topology), even higher dimming frequencies are achievable.

When using the PWM functionality in a boost regulator, the PWM signal can drive a ground referenced FET.

However, with buck-boost and buck topologies, level shifting circuitry is necessary to translate the PWM dim

signal to the floating dimFET as shown in Figure 25 and Figure 26. If high side dimming is necessary in a boost

regulator using the LM3423-Q1, level shifting can be added providing the polarity inverting DPOL pin is pulled

low (see LM3423-Q1 Only: DPOL, FLT, TIMR, and LRDY section) as shown in Figure 27.

When using a series dimFET to PWM dim the LED current, more output capacitance is always better. Typical

applications use a minimum of 40 µF for PWM dimming. For most applications, a capacitance of 40 µF provides

adequate energy storage at the output when the dimFET turns off and opens the LED load. Then when the

dimFET is turned back on, the capacitance helps source current into the load, improving the LED current rise

time.

A minimum on-time must be maintained in order for PWM dimming to operate in the linear region of its transfer

function. Because the controller is disabled during dimming, the PWM pulse must be long enough such that the

energy intercepted from the input is greater than or equal to the energy being put into the LEDs. For boost and

buck-boost regulators, the minimum dimming pulse length in seconds (t_PULSE) is:

2 x I_LEDx V_OX L1

t_PULSE

=

2

V_IN

(29)

Even maintaining a dimming pulse greater than t_PULSE, preserving linearity at low dimming duty cycles is difficult.

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Feature Description (continued)

The second helpful modification is to remove the C_FScapacitor and R_FSresistor, eliminating the high-frequency

compensation pole. Typically, this does not affect stability, but it speeds up the response of the CSH pin,

specifically at the rising edge of the LED current when PWM dimming, thus improving the achievable linearity at

low dimming duty cycles.

LED+

LM3421/23

10W

5 kW

Q7

Q4

100 nF

Q2

V_CC

Q6

R

SNS

100 pF

10V

V

IN

500W

DDRV

Figure 25. Buck-boost Level-Shifted PWM Circuit

LM3421/23

R

SNS

100

kW

10V

Q2

100 nF

DDRV

Figure 26. Buck Level-Shifted PWM Circuit

V

O

LM3421/23

DPOL

R

SNS

100

kW

10V

Q2

V_CC

Q6

100 pF

10 kW

DDRV

Figure 27. Boost Level-Shifted PWM Circuit

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Feature Description (continued)

8.3.13 LM3423-Q1 Only: DPOL, FLT, TIMR, and LRDY

The LM3423-Q1 has four additional pins: DPOL, FLT, TIMR, and LRDY. The DPOL pin is simply used to invert

the DDRV polarity . If DPOL is left open, then it is internally pulled high and the polarity is correct for driving a

series N-channel dimFET. If DPOL is pulled low then the polarity is correct for using a series P-channel dimFET

in high-side dimming applications. For a parallel P-channel dimFET, as used in the buck topology, leave DPOL

open for proper polarity.

The additional TIMR and FLT pins can be used in conjunction with an input disconnect MOSFET switch as

shown in Figure 28 to protect the module from various fault conditions.

A fault is detected and an 11.5 µA (typical) current is sourced from the TIMR pin whenever any one of the

following conditions exists.

•

LED current is above regulation by more than 30%.

OVLO has engaged.

Thermal shutdown has engaged.

An external capacitor (C_TMR) from TIMR to AGND programs the fault filter time as follows:

t_FLT11.5

x

m

A

C_TMR

=

1.24V

(30)

When the voltage on the TIMR pin reaches 1.24 V, the device is latched off and the N-channel MOSFET open-

drain FLT pin transitions to a high impedance state. The controller immediatly pulls the TIMR pin to ground

(resets) if the fault condition is removed at any point during the filter period. Otherwise, if the timer expires, the

fault remains latched until one of these situations occurs:

•

The EN pin is pulled low long enough for the V_CCpin to drop below 4.1 V (approximately 200 ms) or

the TIMR pin is pulled to ground or

a complete power cycle occurs

When using the EN and OVP pins in conjunction with the RPD pulldown pin, a race condition exists when exiting

the disabled (EN low) state. When disabled, controller pulls up the OVP pin to the output voltage because the

RPD pulldown is disabled, and this appears as if it is a real OVLO condition. The timer pin immediately rises and

latches the controller to the fault state. To protect against this behavior, a minimum timer capacitor (C_TMR= 220

pF) should be used. If fault latching is not required, short the TMR pin to AGND, which disables the FLT flag

function.

The LM3423-Q1 also includes an LED Ready (LRDY) flag to notify the system that the LEDs are in proper

regulation. The N-channel MOSFET open-drain LRDY pin is pulled low whenever any of the following conditions

are met:

1. V_CCUVLO has engaged.

2. LED current is below regulation by more than 20%.

3. LED current is above regulation by more than 30%.

4. Overvoltage protection has engaged

5. Thermal shutdown has engaged.

6. A fault has latched the device off.

The LRDY pin is pulled low during start-up of the device and remains low until the LED current is in regulation.

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Feature Description (continued)

V_IN

V_SW

LM3421/23

FLT

V_IN

High = LED in regulation

LRDY

TIMR

Figure 28. Fault Detection and LED Status Circuit

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Inductor

The inductor (L1) is the main energy storage device in a switching regulator. Depending on the topology, energy

is stored in the inductor and transfered to the load in different ways (as an example, buck-boost operation is

detailed in the Current Regulators section). The size of the inductor, the voltage across it, and the length of the

switching subinterval (t_ONor t_OFF) determines the inductor current ripple (Δi_L-PP). In the design process, L1 is

chosen to provide a desired Δi_L-PP. For a buck regulator the inductor has a direct connection to the load, which is

good for a current regulator. This requires little to no output capacitance therefore Δi_L-PPis basically equal to the

LED ripple current Δi_LED-PP. However, for boost and buck-boost regulators, there is always an output capacitor

which reduces Δi_LED-PP; therefore, the inductor ripple can be larger than in the buck regulator case where output

capacitance is minimal or completely absent.

In general, Δi_LED-PPis recommended by manufacturers to be less than 40% of the average LED current (I_LED).

Therefore, for the buck regulator with no output capacitance, Δi_L-PPshould also be less than 40% of I_LED. For the

boost and buck-boost topologies, Δi_L-PPcan be much higher depending on the output capacitance value.

However, Δi_L-PPis suggested to be less than 100% of the average inductor current (I_L) to limit the RMS inductor

current.

L1 is also suggested to have an RMS current rating at least 25% higher than the calculated minimum allowable

RMS inductor current (I_L-RMS).

9.1.2 LED Dynamic Resistance

When the load is a string of LEDs, the output load resistance is the LED string dynamic resistance plus R_SNS

.

LEDs are PN junction diodes, and their dynamic resistance shifts as their forward current changes. Dividing the

forward voltage of a single LED (V_LED) by the forward current (I_LED) leads to an incorrect calculation of the

dynamic resistance of a single LED (r_LED). The result can be 5 to 10 times higher than the true r_LEDvalue.

Figure 29. Dynamic Resistance

Obtaining r_LEDis accomplished by referring to the manufacturer's LED I-V characteristic. It can be calculated as

the slope at the nominal operating point as shown in Figure 29. For any application with more than 2 series

LEDs, R_SNScan be neglected allowing r_Dto be approximated as the number of LEDs multiplied by r_LED

.

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Application Information (continued)

9.1.3 Output Capacitor

For boost and buck-boost regulators, the output capacitor (C_O) provides energy to the load when the recirculating

diode (D1) is reverse biased during the first switching subinterval. An output capacitor in a buck topology simplys

reduce the LED current ripple (Δi_LED-PP) below the inductor current ripple (Δi_L-PP). In all cases, C_Ois sized to

provide a desired Δi_LED-PP. As mentioned in the Inductor section, Δi_LED-PPis recommended by manufacturers to be

less than 40% of the average LED current (I_LED).

C_Oshould be carefully chosen to account for derating due to temperature and operating voltage. It must also

have the necessary RMS current rating. Ceramic capacitors are the best choice due to their high ripple current

rating, long lifetime, and good temperature performance. An X7R dieletric rating is suggested.

9.1.4 Input Capacitors

The input capacitance (C_IN) provides energy during the discontinuous portions of the switching period. For buck

and buck-boost regulators, C_INprovides energy during t_ONand during t_OFF, the input voltage source charges up

C_INwith the average input current (I_IN). For boost regulators, C_INonly needs to provide the ripple current due to

the direct connection to the inductor. C_INis selected given the maximum input voltage ripple (Δv_IN-PP) which can

be tolerated. Δv_IN-PPis suggested to be less than 10% of the input voltage (V_IN).

An input capacitance at least 100% greater than the calculated C_INvalue is recommended to account for derating

due to temperature and operating voltage. When PWM dimming, even more capacitance can be helpful to

minimize the large current draw from the input voltage source during the rising transition of the LED current

waveform.

The chosen input capacitors must also have the necessary RMS current rating. Ceramic capacitors are again the

best choice due to their high ripple current rating, long lifetime, and good temperature performance. An X7R

dielectric rating is suggested.

For most applications, TI recommends bypassing the V_INpin with an 0.1 µF ceramic capacitor placed as close as

possible to the pin. In situations where the bulk input capacitance may be far from the controller, a 10-Ω series

resistor can be placed between the bulk input capacitance and the bypass capacitor, creating a 150-kHz filter to

eliminate undesired high-frequency noise.

9.1.5 Main MOSFET / Dimming MOSFET

The controller requires an external N-channel FET (Q1) as the main power MOSFET for the switching regulator.

TI recommends Q1 have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe

operation during the ringing of the switch node. In practice, all switching regulators have some ringing at the

switch node due to the diode parasitic capacitance and the lead inductance. TI recommends the current rating be

at least 10% higher than the average transistor current. The power rating is then verified by calculating the power

loss given the RMS transistor current and the N-channel FET on-resistance (R_DS-ON).

When PWM dimming, the controller requires another MOSFET (Q2) placed in series (or parallel for a buck

regulator) with the LED load. This MOSFET should have a voltage rating greater than the output voltage (V_O)

and a current rating at least 10% higher than the nominal LED current (I_LED) . The power rating is simply R_DS-ON

multiplied by I_LED, assuming 100% dimming duty cycle (continuous operation) occurs.

For most applications, choose an N-channel FET that minimizes total gate charge (Q_g) when f_SWis high. It that is

not possible. minimize the on-resistance R_DS(on)to minimize the dominant power losses in the system.

Frequently, higher current N-channel FETs in larger packages yield better thermal performance.

9.1.6 Re-Circulating Diode

The controller requires a recirculating diode (D1) to carry the inductor current during the off time (t_OFF). The most

efficient choice for D1 is a Schottky diode due to low forward voltage drop and near-zero reverse recovery time.

Similar to Q1, TI recommends D1 have a voltage rating at least 15% higher than the maximum transistor voltage

to ensure safe operation during the ringing of the switch node and a current rating at least 10% higher than the

average diode current. The power rating is verified by calculating the power loss through the diode. This is

accomplished by checking the typical diode forward voltage from the I-V curve on the product data sheet and

multiplying by the average diode current. In general, higher current diodes have a lower forward voltage and

come in better performing packages minimizing both power losses and temperature rise.

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Application Information (continued)

9.1.7 Boost Inrush Current

When configured as a boost converter, there is a phantom power path comprised of the inductor, the output

diode, and the output capacitor. This path causes two things to happen when power is applied:

1. a very large inrush of current to charge the output capacitor

2. the energy stored in the inductor during this inrush collects in the output capacitor, charging it to a higher

potential than the input voltage

Depending on the state of the EN pin, the output capacitor discharges by:

1. EN < 1.3 V: no discharge path (leakage only).

2. EN > 1.3 V, the OVP divider resistor path, if present, and 10 µA into each of the HSP & HSN pins.

In applications using the OVP divider and with EN > 1.3 V, the output capacitor voltage can charge higher than

V_TURN-OFF. In this situation, the FLT pin (LM3423-Q1 only) is open and the PWM dimming MOSFET is turned off.

This condition (the system appearing disabled) can persist for an undesirably long time. Possible solutions to this

condition include:

•

Add an inrush diode from V_INto the output as shown in Figure 30.

Add an NTC thermistor in series with the input to prevent the inrush from overcharging the output capacitor

too high.

•

Use a current limited source supply.

Raise the OVP threshold.

Boost Inrush Diode

L1

D1

V_IN

V_O

Q1

Figure 30. Boost Topology with Inrush Diode

9.1.8 Switching Frequency

An external resistor (R_T) connected between the RCT pin and the switch node (where D1, Q1, and L1 connect),

in combination with a capacitor (C_T) between the RCT and AGND pins, sets the off-time (t_OFF) as shown in

Figure 31. For boost and buck-boost topologies, the V_INproportionality ensures a virtually constant switching

frequency (f_SW).

For a buck topology, R_Tand C_Tare also used to set t_OFF, however the iinput voltage (V_IN) proportionality does

not ensure a constant switching frequency. Instead, constant ripple operation can be achieved. Changing the

connection of R_Tin Figure 31 from V_SWto V_INprovides a constant ripple over varying V_IN. Adding a PNP

transistor as shown in Figure 32 provides constant ripple over varying V_O.

The switching frequency is defined:

Buck (Constant Ripple vs. V_IN)

25 x

V_IN- V_O

(

)

f_SW

=

R_Tx C_TX V_IN

(31)

Buck (Constant Ripple vs. V_O)

2

(

)

25 x V x V_O- V_O

IN

f_SW

=

2

R_Tx C_TxV

IN

(32)

Boost and Buck-boost

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Application Information (continued)

25

R_Tx C_T

f_SW

=

(33)

For all topologies, the C_Tcapacitor is recommended to be 1 nF and should be located very close to the LM34xx-

Q1.

V

SW

IN

LM3421/23

R

SNS

V

/25

IN

Start t

ON

R

T

RCT

R

T

LM3421/23

C

T

V

IN

/25

Start t

ON

Reset timer

LED-

RCT

C

T

Reset timer

Figure 31. Off-timer Circuitry for Boost and Buck-

boost Regulators

Figure 32. Off-timer Circuitry for Buck Regulators

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9.2 Typical Applications

9.2.1 Basic Topology Schematics

L1

D1

V_IN

R

HSN

1

16

15

14

13

12

VIN

HSN

HSP

LM3421

C

R

SNS

FS

R

C

IN

R

HSP

2

3

4

5

6

7

8

EN

FS

R

T

C

CMP

COMP

CSH

RCT

RPD

IS

R

CSH

C

O

R

OV2

I_LED

VCC

GATE

PGND

DDRV

C

BYP

C

T

11

AGND

OVP

nDIM

Q1

R

UV2

10

9

R

LIM

DAP

R

UVH

Q2

R

UV1

Q3

PWM

R

C

OV

OV1

Figure 33. Boost Regulator (V_IN< V_O)

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Typical Applications (continued)

V_IN

R

HSN

1

16

15

14

13

12

VIN

HSN

HSP

LM3421

C

FS

R

SNS

C

IN

R

HSP

2

3

4

5

6

7

8

EN

R

FS

R

T

C

O

C

CMP

COMP

CSH

RCT

RPD

IS

R

PU

D2

R

CSH

R

OV2

Q2

I_LED

DIM

D1

VCC

GATE

PGND

DDRV

L1

C

BYP

Q5

C

T

11

AGND

OVP

nDIM

Q1

R

UV2

10

9

R

LIM

DAP

R

UVH

DIM

C

DIM

R

UV1

Q3

PWM

R

OV1

C

OV

Figure 34. Buck Regulator (V_IN> V_O)

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Typical Applications (continued)

L1

D1

V_IN

I_LED

DIM

C

O

Q2

R

HSN

1

16

15

14

13

12

VIN

HSN

HSP

LM3421

C

R

SNS

FS

R

C

R

IN

HSP

2

EN

V_IN

FS

R

T

C

CMP

3

4

5

6

7

8

COMP

CSH

RPD

IS

R

CSH

R

Q7

PU

R

OV2

DIM

RCT

VCC

GATE

PGND

DDRV

Q6

Q4

C

BYP

C

T

C

G

D2

11

Q5

AGND

OVP

Q1

V_IN

R

UV2

10

9

R

LIM

R

SER

DAP

R

UVH

nDIM

R

UV1

Q3

PWM

R

OV1

C

OV

Figure 35. Buck-Boost Regulator

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Typical Applications (continued)

9.2.1.1 Design Requirements

Number of series LEDs: N

Single LED forward voltage: V_LED

Single LED dynamic resistance: r_LED

Nominal input voltage: V_IN

Input voltage range: V_IN-MAX, V_IN-MIN

Switching frequency: f_SW

Current sense voltage: V_SNS

Average LED current: I_LED

Inductor current ripple: Δi_L-PP

LED current ripple: Δi_LED-PP

Peak current limit: I_LIM

Input voltage ripple: Δv_IN-PP

Output OVLO characteristics: V_TURN-OFF, V_HYSO

Input UVLO characteristics: V_TURN-ON, V_HYS

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Operating Point

Given the number of series LEDs (N), the forward voltage (V_LED) and dynamic resistance (r_LED) for a single LED,

solve for the nominal output voltage (V_O) and the nominal LED string dynamic resistance (r_D):

V_O= N x V_LED

(34)

r_D= N x r_LED

(35)

Solve for the ideal nominal duty cycle (D):

Buck:

V_O

D =

V

IN

(36)

Boost:

V_O- V

IN

D =

V_O

(37)

Buck-Boost:

V_O

D

=

V_O+ V

IN

(38)

Using the same equations, find the minimum duty cycle (D_MIN) using maximum input voltage (V_IN-MAX) and the

maximum duty cycle (D_MAX) using the minimum input voltage (V_IN-MIN). Also, remember that D' = 1 - D.

9.2.1.2.2 Switching Frequency

Set the switching frequency (f_SW) by assuming a C_Tvalue of 1 nF and solving for R_T:

Buck (Constant Ripple vs. V_IN)

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Typical Applications (continued)

25 x V_IN- V_O

(

)

R_T=

f_SWx C_TX V_IN

(39)

Buck (Constant Ripple vs. V_O)

2

O

x (V x V_OV )

25

-

IN

R_T

=

2

f_SWx C_Tx V

IN

(40)

(41)

Boost and Buck-Boost

25

R_T=

f_SWx C_T

9.2.1.2.3 Average LED Current

For all topologies, set the average LED current (I_LED) knowing the desired current sense voltage (V_SNS) and

solving for R_SNS

:

V_SNS

I_LED

R_SNS

=

(42)

If the calculated R_SNSis too far from a desired standard value, then V_SNSrequires adjustment to obtain a

standard value.

Setup the suggested signal current of 100 µA by assuming R_CSH= 12.4 kΩ and solving for R_HSP

:

I_LEDx R_CSHx R_SNS

R_HSP

=

1.24V

(43)

If the calculated R_HSPis too far from a desired standard value, then R_CSHcan be adjusted to obtain a standard

value.

9.2.1.2.4 Inductor Ripple Current

Set the nominal inductor ripple current (Δi_L-PP) by solving for the appropriate inductor (L1):

Buck

(V_IN- V_O)ìD

L1=

Di_L-PPì f_SW

(44)

(45)

Boost and Buck-Boost

V ìD

Di_L-PPì f_SW

IN

L1=

To set the worst case inductor ripple current, use V_IN-MAXand D_MINwhen solving for L1.

The minimum allowable inductor RMS current rating (I_L-RMS) can be calculated as:

Buck

2

DI_L-PP

≈

∆

«

’

1

12

I_L-RMS= I_LED

x

1 +

x

÷

I_LED

◊

(46)

Boost and Buck-Boost

2

DI_L-PPx D'

I_LED

≈

’

÷

1

12

x

1 +

x

I_L-RMS

=

∆

I_LED

D'

«

◊

(47)

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Typical Applications (continued)

9.2.1.2.5 LED Ripple Current

Set the nominal LED ripple current (Δi_LED-PP), by solving for the output capacitance (C_O):

Buck

Di_L-PP

8 x f_SWx r_Dx Di_LED-PP

C_O=

(48)

(49)

Boost and Buck-boost

I_LEDìD

C_O

=

r_Dì Di_LED-PPì f_SW

To set the worst case LED ripple current, use D_MAXwhen solving for C_O. Remember, when PWM dimming, TI

recommends using a minimum of 40 µF of output capacitance to improve performance.

The minimum allowable RMS output capacitor current rating (I_CO-RMS) can be approximated:

Buck

üi_LED-PP

I_{CO- RMS}

=

12

(50)

(51)

Boost and Buck-boost

D_MAX

I_CO-RMS= I_LED

x

1-D_MAX

9.2.1.2.6 Peak Current Limit

Set the peak current limit (I_LIM) by solving for the transistor path sense resistor (R_LIM):

245 mV

R_LIM

=

I_LIM

(52)

9.2.1.2.7 Loop Compensation

Using a simple first order peak current mode control model, neglecting any output capacitor ESR dynamics, the

necessary loop compensation can be determined.

First, the uncompensated loop gain (T_U) of the regulator can be approximated:

Buck

1

T_U= T_U0

x

≈

’

÷

◊

s

∆

1+

∆

w_P1

«

(53)

(54)

Boost and Buck-Boost

≈

’

s

∆ -

÷

◊

1

∆

w_Z1

«

T_U= T_U0

x

≈

’

÷

◊

s

∆

1+

∆

w_P1

«

Where the pole (ω_P1) is approximated:

Buck

1

w_P1=

r_Dx C_O

(55)

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Typical Applications (continued)

Boost

2

w_P1=

r_Dx C_O

(56)

(57)

Buck-Boost

1+D

w_P1=

r_Dx C_O

And the RHP zero (ω_Z1) is approximated:

Boost

Å²

r_DxD

L1

w_Z1=

(58)

(59)

Buck-Boost

Å²

r_DxD

w_Z1=

DxL1

And the uncompensated DC loop gain (T_U0) is approximated:

Buck

500Vx R_CSHx R_SNS

R_HSPx R_LIM

620V

I_LEDx R_LIM

T_U0

=

(60)

(61)

Boost

T_U0

Buck-Boost

Å

D x 500V x R_CSHx R_SNS

Å

D x 310V

=

2 x R_HSPx R_LIM

I_LEDx R_LIM

Å

D x 500Vx R_CSHx R_SNS

Å

D x 620V

T_U0

=

(

)

(

)

1+D x R_HSPx R_LIM

1+D xI_LEDx R_LIM

(62)

For all topologies, the primary method of compensation is to place a low frequency dominant pole (ω_P2), which

ensures that there is ample phase margin at the crossover frequency. This is accomplished by placing a

capacitor (C_CMP) from the COMP pin to AGND, which is calculated according to the lower value of the pole and

the RHP zero of the system (shown as a minimizing function):

min(w_P1,w_Z1)

w_P2

=

5 xT_U0

(63)

1

C_CMP

=

w_P2ì 5ì10⁶

(64)

If analog dimming is used, C_CMPshould be approximately 4× larger to maintain stability as the LEDs are dimmed

to zero.

A high-frequency compensation pole (ω_P3) can be used to attenuate switching noise and provide better gain

margin. Assuming R_FS= 10 Ω, C_FSis calculated according to the higher value of the pole and the RHP zero of

the system (shown as a maximizing function):

(

)

w_P3max w ,w x10

=

P1

Z1

(65)

(66)

1

C_FS

=

10ì w_P3

The total system loop gain (T) can then be written as:

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Typical Applications (continued)

Buck

1

T = T_U0

x

≈

’

÷

◊

≈

∆

«

’

÷

◊

≈

∆

«

’

÷

◊

s

w_P1

s

w_P3

∆

1+

x 1+

∆

w_P2

«

(67)

(68)

Boost and Buck-Boost

≈

’

÷

◊

s

w_Z1

∆

1-

∆

«

T = T_U0

x

≈

’

÷

◊

≈

∆

«

’

≈

’

÷

◊

s

w_P1

s

w_P2

s

w_P3

∆

÷

∆

1+

x 1+

∆

÷

∆

«

◊

9.2.1.2.8 Input Capacitance

Set the nominal input voltage ripple (Δv_IN-PP) by solving for the required capacitance (C_IN):

Buck

I_LEDx (1 - D) x D

C_IN

Boost

C_IN

=

DV_IN-PPx f_SW

(69)

(70)

(71)

Di_L-PP

=

8 x DV_IN-PPx f_SW

Buck-Boost

C_IN

I_LEDx D

=

DV_IN-PPx f_SW

Use D_MAXto set the worst case input voltage ripple, when solving for C_INin a buck-boost regulator and D_MID= 0.5

when solving for C_INin a buck regulator.

The minimum allowable RMS input current rating (I_CIN-RMS) can be approximated:

Buck

I

_{CIN- RMS}= I_LEDx D_MIDx(1-D_MID

)

(72)

(73)

(74)

Boost

Di_L-PP

I_CIN-RMS

Buck-Boost

I_CIN-RMS= I_LED

=

12

D_MAX

x

1-D_MAX

9.2.1.2.9 N-channel FET

The N-channel FET voltage rating should be at least 15% higher than the maximum N-channel FET drain-to-

source voltage (V_T-MAX):

Buck

V_{T- MAX}= V

IN- MAX

(75)

Boost

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Typical Applications (continued)

V

_{T- MAX}= V_O

(76)

(77)

Buck-Boost

_{T- MAX}= V_{IN- MAX}+ V_O

V

The current rating should be at least 10% higher than the maximum average N-channel FET current (I_T-MAX):

Buck

I_T-MAX= D_MAXx I_LED

(78)

(79)

(80)

Boost and Buck-Boost

D_MAX

I_T-MAX

=

x I_LED

1 - D_MAX

Approximate the nominal RMS transistor current (I_T-RMS) :

Buck

I

_{T- RMS}= I_LEDx D

9.2.1.2.9.1 Boost and Buck-Boost

I

^LEDx D

I_{T- RMS}

=

Å

D

(81)

(82)

Given an N-channel FET with on-resistance (R_DS-ON), solve for the nominal power dissipation (P_T):

P = I_{T- RMS}²x R_DSON

T

9.2.1.2.10 Diode

The Schottky diode voltage rating should be at least 15% higher than the maximum blocking voltage (V_RD-MAX):

Buck

V_RD-MAX= V_IN-MAX

(83)

Boost

V_RD-MAX= V_O

(84)

(85)

Buck-Boost

V_RD-MAX= V_IN-MAX+ V_O

The current rating should be at least 10% higher than the maximum average diode current (I_D-MAX):

Buck

I_D-MAX= (1 - D_MIN) x I_LED

(86)

(87)

Boost and Buck-Boost

I_D-MAX= I_LED

Replace D_MAXwith D in the I_D-MAXequation to solve for the average diode current (I_D). Given a diode with forward

voltage (V_FD), solve for the nominal power dissipation (P_D):

P_D= I_DxV_FD

(88)

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Typical Applications (continued)

9.2.1.2.11 Output OVLO

For boost and buck-boost regulators, output OVLO is programmed with the turn-off threshold voltage (V_TURN-OFF

)

and the desired hysteresis (V_HYSO). To set V_HYSO, solve for R_OV2

:

V_HYSO

R_OV2

=

23mA

(89)

To set V_TURN-OFF, solve for R_OV1

:

Boost

1.24V x R_OV2

R_OV1

Buck-Boost

R_OV1

=

V_TURN-OFF- 1.24V

(90)

(91)

1.24V x R_OV2

=

V_{TURN- OFF}- 620 mV

A small filter capacitor (C_OVP= 47 pF) should be added from the OVP pin to ground to reduce coupled switching

noise.

9.2.1.2.12 Input UVLO

For all topologies, input UVLO is programmed with the turnon threshold voltage (V_TURN-ON) and the desired

hysteresis (V_HYS).

Method 1: If no PWM dimming is required, a two resistor network can be used. To set V_HYS, solve for R_UV2

:

V_HYS

23 mA

R_UV2

=

(92)

To set V_TURN-ON, solve for R_UV1

:

1.24Vx R_UV2

R_UV1

=

V_{TURN- ON}- 1.24V

(93)

Method 2: If PWM dimming is required, a three resistor network is suggested. To set V_TURN-ON, assume R_UV2

10 kΩ and solve for R_UV1as in Method 1. To set V_HYS, solve for R_UVH

=

:

(

)

R_UV1x V_HYS- 23 mA x R_UV2

R_UVH

=

(

)

23 mA x R_UV1+ R_UV2

(94)

9.2.1.2.13 PWM Dimming Method

PWM dimming can be performed several ways:

Method 1: Connect the dimming MOSFET (Q₃) with the drain to the nDIM pin and the source to AGND. Apply an

external PWM signal to the gate of Q_DIM. A pulldown resistor may be necessary to properly turn off Q₃.

Method 2: Connect the anode of a Schottky diode to the nDIM pin. Apply an external inverted PWM signal to the

cathode of the same diode.

The DDRV pin should be connected to the gate of the dimFET with or without level-shifting circuitry as described

in the PWM Dimming section. The dimFET should be rated to handle the average LED current and the nominal

output voltage.

9.2.1.2.14 Analog Dimming Method

Analog dimming can be performed several ways:

Method 1: Place a potentiometer in series with the R_CSHresistor to dim the LED current from the nominal I_LEDto

near zero.

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Typical Applications (continued)

Method 2: Connect a controlled current source as detailed in the Analog Dimming section to the CSH pin.

Increasing the current sourced into the CSH node decreases the LEDs from the nominal I_LEDto zero current in

the same manner as the thermal foldback circuit.

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Typical Applications (continued)

9.2.2 LM3421 Buck-Boost Application

L1

10V œ 70V

D1

V_IN

R

HSN

1

16

15

14

13

12

VIN

HSN

HSP

LM3421

1A

C

IN

I_LED

R

HSP

2

EN

C

O

R

T

C

CMP

3

4

5

6

7

8

COMP

CSH

RPD

IS

R

CSH

C

FS

R

SNS

V_IN

R

FS

RCT

VCC

GATE

PGND

DDRV

C

BYP

C

T

11

AGND

OVP

Q1

R

UV2

R

10

9

OV2

R

LIM

DAP

Q2

nDIM

V_IN

R

UV1

R

C

OV

OV1

Figure 36. LM3421 Buck-Boost Application

9.2.2.1 Design Requirements

N = 6

V_LED= 3.5 V

r_LED= 325 mΩ

V_IN= 24 V

V_IN-MIN= 10 V

V_IN-MAX= 70 V

f_SW= 500 kHz

V_SNS= 100 mV

I_LED= 1 A

Δi_L-PP= 700 mA

Δi_LED-PP= 12 mA

Δv_IN-PP= 100 mV

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Typical Applications (continued)

I_LIM= 6 A

V_TURN-ON= 10 V

V_HYS= 3 V

V_TURN-OFF= 40 V

V_HYSO= 10 V

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Operating Point

Solve for V_Oand r_D:

V_ONx V

6x 3.5V 21V

=

LED

(95)

(96)

r_DN x r

6 x 325 mW 1.95W

=

LED

Solve for D, D', D_MAX, and D_MIN

:

V_O

21V

21V + 24V

D =

=

= 0.467

V_O+V

IN

(97)

(98)

D' 1- D 1- 0.467 0.533

=

V_O

21V

=

D_MIN

=

= 0.231

V_O+ V_IN-MAX

21V + 70V

(99)

V_O

=

21V

21V +10V

D_MAX

=

= 0.677

V_O+ V

IN-MIN

(100)

9.2.2.2.2 Switching Frequency

Assume C_T= 1 nF and solve for R_T:

25

f_SWx C_T

25

=

R_T=

= 50 kW

500 kHz x 1 nF

(101)

The closest standard resistor is 49.9 kΩ; therefore, f_SWis:

25

R_Tx C_T

25

=

f_SW

=

= 501 kHz

49.9 kW x 1 nF

(102)

(103)

The chosen component from step 2 is:

C_T= 1 nF

R_T= 49.9 kW

9.2.2.2.3 Average LED Current

Solve for R_SNS

:

V

I_LED

100 mV

1A

SNS

R_SNS

0.1W

=

(104)

Assume R_CSH= 12.4 kΩ and solve for R_HSP

:

I_LEDxR_CSHx R_SNS

1.24V

1Ax12.4 kW x 0.1W

R_HSP

=

=1.0 kW

1.24V

(105)

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Typical Applications (continued)

The closest standard resistor for R_SNSis actually 0.1 Ω and for R_HSPis actually 1 kΩ; therefore, I_LEDis:

1.24Vx R_HSP

R_SNSx R_CSH

1.24V x1.0 kW

0.1W x12.4 kW

I_LED

=

=1.0A

(106)

(107)

The chosen components from step 3 are:

R_SNS0.1W

=

R_CSH12.4 kW

=

R_HSP

R

1kW

=

HSN

9.2.2.2.4 Inductor Ripple Current

Solve for L1:

V x D

24Vx0.467

Di_L-PPx f_SW700 mA x501kHz

IN

32 mH

=

L1=

=

(108)

(109)

The closest standard inductor is 33 µH; therefore, Δi_L-PPis:

V x D

24Vx 0.467

L1x f_SW33 mHx501 kHz

IN

678 mA

=

Di_{L- PP}

=

Determine minimum allowable RMS current rating:

≈

∆

«

Å’²

Di_L-PPx D

I

1

12

^LEDx 1+

÷

x

I_L-RMS

=

÷

I_LED

Å

D

◊

2

678 mA x 0.533

1

≈

’

1A

1.89A

x

=

x 1+

∆

÷

I_L-RMS

12

1A

0.533

«

◊

(110)

(111)

The chosen component from step 4 is:

L1= 33 mH

9.2.2.2.5 Output Capacitance

Solve for C_O:

I_LEDx D

C_O=

r_Dx Di_LED-PPx f_SW

1A x 0.467

1.95W x 12 mA x501 kHz

=

= 39.8 mF

C_O

(112)

The closest capacitance totals 40 µF; therefore, Δi_LED-PPis:

I_LEDx D

Di_LED-PP

=

r_Dx C_Ox f_SW

1A x 0.467

1.95W x x 501 kHz

Di_LED-PP

12 mA

=

40 mF

(113)

Determine minimum allowable RMS current rating:

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Typical Applications (continued)

D_MAX

1- D_MAX

0.677

1- 0.677

x

I

_CO-RMS=I_LED

=1A

=1.45A

(114)

(115)

The chosen components from step 5 are:

C_O= 4 x 10 mF

9.2.2.2.6 Peak Current Limit

Solve for R_LIM

:

245 mV 245 mV

=

R_LIM

=

= 0.041W

I_LIM

6A

(116)

The closest standard resistor is 0.04 Ω; therefore, I_LIMis:

245 mV 245 mV

I_LIM

=

= 6.13A

R_LIM

0.04W

(117)

(118)

The chosen component from step 6 is:

R_LIM= 0.04W

9.2.2.2.7 Loop Compensation

ω_P1is approximated:

rad

sec

1+D

r_DxC_O

1.467

1.95W x 40 mF

w_P1=

=

=19k

(119)

(120)

ω_Z1is approximated:

Å²

1.95W x0.533²

DxL1 0.467x 33mH

rad

sec

r_Dx D

w_Z1=

=

= 36k

T_U0is approximated:

Å

0.533x620V

1.467x1A x 0.04W

D x 620V

T_U0=

=

= 5630

(

)

1 D xI_LEDx R_LIM

+

(121)

To ensure stability, calculate ω_P2:

rad

sec

19k

min(w_P1, w_Z1)

w_P1

rad

sec

=

= 0.675

w_P2

=

5 x T_U0

5 x 5630 5 x 5630

(122)

(123)

Solve for C_CMP

:

1

C_CMP

=

= 0.3 mF

w_P2ì5ì10⁶W

rad

0.675

ì5ì10⁶W

sec

To attenuate switching noise, calculate ω_P3:

w

_P3= (max w_P1, w_Z1) x 10 = w_Z1x 10

rad

sec

rad

sec

x 10 = 360k

_P3= 36k

(124)

Assume R_FS= 10 Ω and solve for C_FS

:

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Typical Applications (continued)

1

x w

1

C_FS=

=

= 0.28 mF

rad

sec

10W

P3

10W x

360k

(125)

(126)

The chosen components from step 7 are:

C_CMP= 0.33mF

R_FS=10W

C_FS= 0.27mF

9.2.2.2.8 Input Capacitance

Solve for the minimum C_IN:

I_LEDx D

Dv_IN-PPx f_SW

1A x 0.467

100 mV x 504kHz

C_IN=

=

= 9.27mF

(127)

To minimize power supply interaction a 200% larger capacitance of approximately 20 µF is used, therefore the

actual Δv_IN-PPis much lower. Because high voltage ceramic capacitor selection is limited, four 4.7-µF X7R

capacitors are chosen.

Determine minimum allowable RMS current rating:

D_MAX

1- D_MAX

0.677

1- 0.677

x

I

_IN-RMS=I_LED

=1A

=1.45A

(128)

(129)

The chosen components from step 8 are:

C_IN= 4 x 4.7 mF

9.2.2.2.9 N-channel FET

Determine minimum Q1 voltage rating and current rating:

V_T-MAX

V

70V 21V 91V

= + =

=

+

IN- MAX

O

(130)

(131)

0.677

1- 0.677

I_T-MAX

x1A 2.1A

=

A 100-V N-channel FET is chosen with a current rating of 32 A due to the low R_DS-ON= 50 mΩ. Determine I_T-RMS

and P_T:

I_LED

1A

0.533

I_T-RMS

D

0.467 1.28A

x

=

x

=

Å

D

(132)

(133)

P_T

I

²x R_DSON1.28A²x 50 mW 82 mW

= =

T- RMS

=

The chosen component from step 9 is:

Q1 ç 32A, 100V, DPAK

(134)

9.2.2.2.10 Diode

Determine minimum D1 voltage rating and current rating:

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Typical Applications (continued)

V

_RD-MAX= V_IN-MAX+ V_O= 70V +21V = 91V

(135)

(136)

I_D-MAX1A

I

=

LED

A 100-V diode is chosen with a current rating of 12 A and V_DF= 600 mV. Determine P_D:

I x V 1A x 600 mV 600 mW

P

=

FD

=

D

(137)

(138)

The chosen component from step 10 is:

D1 ç 12A, 100V, DPAK

9.2.2.2.11 Input UVLO

Solve for R_UV2

:

V_HYS

3V

m

R_UV2

=

=130kW

m

23 A 23 A

(139)

(140)

The closest standard resistor is 130 kΩ; therefore, V_HYSis:

V_HYS

R

x23mA 130 kW x23 mA 2.99V

=

UV2

Solve for R_UV1

:

1.24Vx R_UV2

V_{TURN- ON}-1.24V

1.24Vx130kW

10V -1.24V

R_UV1

=

= 18.4 kW

(141)

The closest standard resistor is 18.2 kΩ, making V_TURN-ON

:

(

)

1.24Vx R_UV1+ R_UV2

V_TURN-ON

=

R_UV1

(

)

1.24V x 18.2kW +130kW

V_TURN-ON

= 10.1V

18.2kW

(142)

(143)

The chosen components from step 11 are:

R_UV118.2kW

=

R_UV2130 kW

=

9.2.2.2.12 Output OVLO

Solve for R_OV2

:

V_HYSO

10V

m

R_OV2

=

= 435kW

m

23 A 23 A

(144)

(145)

The closest standard resistor is 432 kΩ; therefore, V_HYSOis:

m

V_HYSO

R

x 23 A 432 kW x 23 A 9.94V

=

OV2

Solve for R_OV1

:

1.24Vx R_OV2

V_TURN-OFF- 0.62V

1.24Vx 432kW

40V - 0.62V

R_OV1

=

= 13.6kW

(146)

The closest standard resistor is 13.7 kΩ, making V_TURN-OFF

:

48

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Typical Applications (continued)

(

)

1.24Vx 0.5 xR_OV1+ R_OV2

V_TURN-OFF

=

R_OV1

(

)

13.7 kW +432kW

1.24Vx

0.5 x

V_TURN-OFF

= 39.7V

13.7 kW

(147)

(148)

The chosen components from step 12 are:

R_OV1= 13.7 kW

R_OV2= 432 kW

Table 2. Bill of Materials

QTY

1

PART ID

LM3421

C_BYP

C_CMP

C_FS

PART VALUE

MANUFACTURER

PART NUMBER

Buck-boost controller

2.2-µF X7R 10% 16V

0.33-µF X7R 10% 25V

0.27-µF X7R 10% 25V

4.7-µF X7R 10% 100V

10-µF X7R 10% 50V

47-pF COG/NPO 5% 50V

1000-pF COG/NPO 5% 50V

Schottky 100 V 12 A

33 µH 20% 6.3 A

NMOS 100 V 32 A

PNP 150 V 600 mA

12.4 kΩ 1%

TI

LM3421MH

1

MURATA

TDK

GRM21BR71C225KA12L

GRM21BR71E334KA01L

GRM21BR71E274KA01L

C5750X7R2A475K

C4532X7R1H106K

08055A470JAT2A

1

4

C_IN

4

C_O

TDK

1

C_OV

AVX

1

C_T

MURATA

VISHAY

COILCRAFT

FAIRCHILD

VISHAY

GRM2165C1H102JA01D

12CWQ10FNPBF

1

D1

1

L1

MSS1278-333MLB

FDD3682

1

Q1

1

Q2

MMBT5401

1

R_CSH

R_FS

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW08051K00FKEA

WSL2512R0400FEA

CRCW080513K7FKEA

CRCW0805432KFKEA

WSL2512R1000FEA

CRCW080549K9FKEA

CRCW080518K2FKEA

CRCW0805130KFKEA

1

10 Ω 1%

2

R_HSP, R_HSN

R_LIM

R_OV1

R_OV2

R_SNS

R_T

1 kΩ 1%

1

0.04 Ω 1% 1 W

1

13.7 kΩ 1%

1

432 kΩ 1%

1

0.1 Ω 1% 1 W

1

49.9 kΩ 1%

1

R_UV1

R_UV2

18.2 kΩ 1%

1

130 kΩ 1%

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LM3421-Q1, LM3423-Q1

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9.2.2.3 Application Curve

V_OUT= 21 V

Figure 37. Sample Buck-Boost Efficiency vs Input Voltage.

50

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9.2.3 LM3421-Q1 BOOST Application

D2

L1

D1

8V œ 28V

V_IN

R

HSN

1

16

VIN

HSN

HSP

LM3421

C

R

SNS

FS

R

C

IN

R

HSP

2

15

14

13

12

EN

FS

R

T

C

CMP

3

4

5

6

7

8

COMP

CSH

RPD

IS

R

CSH

1A

C

O

I_LED

RCT

VCC

GATE

PGND

DDRV

C

BYP

C

T

11

AGND

OVP

Q1

R

UV2

10

9

R

LIM

DAP

R

UVH

nDIM

Q2

R

OV2

OV1

R

UV1

Q3

PWM

R

C

OV

Figure 38. LM3421-Q1 BOOST Application

9.2.3.1 Design Requirements

•

Input: 8 V to 28 V

Output: 9 LEDs at 1 A

PWM Dimming up to 30kHz

Switching Frequency: 700-kHz

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LM3421-Q1, LM3423-Q1

SNVSB95 –JULY 2019

www.ti.com

9.2.3.2 Detailed Design Procedure

Table 3. Bill of Materials

QTY

1

PART ID

LM3421

C_BYP

C_CMP

C_FS

PART VALUE

MANUFACTURER

PART NUMBER

Boost controller

2.2-µF X7R 10% 16 V

0.1-µF X7R 10% 25 V

DNP

TI

LM3421MH

1

MURATA

GRM21BR71C225KA12L

GRM21BR71E104KA01L

1

0

4

C_IN

4.7-µF X7R 10% 100 V

10-µF X7R 10% 50 V

47-pF COG/NPO 5% 50 V

1000-pF COG/NPO 5% 50 V

Schottky 60 V 5 A

33-µH 20% 6.3 A

NMOS 60 V 8 A

NMOS 60 V 115 mA

12.4 kΩ 1%

TDK

C5750X7R2A475K

C4532X7R1H106K

08055A470JAT2A

4

C_O

TDK

1

C_OV

AVX

1

C_T

MURATA

COMCHIP

COILCRAFT

VISHAY

ON-SEMI

VISHAY

GRM2165C1H102JA01D

CDBC560-G

2

D1, D2

L1

1

MSS1278-333MLB

SI4436DY

2

Q1, Q2

Q3

1

2N7002ET1G

2

R_CSH, R_OV1

R_FS

R_HSP, R_HSN

R_LIM

CRCW080512K4FKEA

CRCW08050000Z0EA

CRCW08051K00FKEA

WSL2512R0600FEA

CRCW0805499KFKEA

WSL2512R1000FEA

CRCW080510K0FKEA

CRCW080535K7FKEA

CRCW08051K82FKEA

CRCW080517K8FKEA

1

0 Ω 1%

2

1 kΩ 1%

1

0.06 Ω 1% 1 W

499 kΩ 1%

1

R_OV2

R_SNS

R_UV2

R_T

1

0.1 Ω 1% 1 W

1

10 kΩ 1%

1

35.7 kΩ 1%

1

R_UV1

R_UVH

1.82 kΩ 1%

1

17.8 kΩ 1%

52

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9.2.4 LM3421-Q1 Buck-Boost Application

L1

D1

10V ꢀ0V

V_IN

2A

R

HSN

1

16

15

14

1ꢀ

12

I_LED

VIN

HSN

HSP

LM3421

C

O

C

R

IN

HSP

2

ꢀ

4

5

6

7

8

EN

Q2

R

DIM

R

T

C

CMP

C

FS

COMP

CSH

RCT

RPD

IS

SNS

V_IN

R

CSH

POT

R

FS

R

F

R

Q7

PU

C

F

VCC

GATE

PGND

DDRV

R

OV2

C

DIM

BYP

C

T

11

Q6

Q4

AGND

OVP

nDIM

Q1

R

C

B

D2

UV2

10

9

Q5

R

LIM

R

SER

V_IN

DAP

R

UVH

R

UV1

Qꢀ

PWM

C

R

OV1

OV

Figure 39. LM3421-Q1 Buck-Boost Application

9.2.4.1 Design Requirements

•

Input: 10 V to 30 V

Output: 4 LEDs at 2 A

PWM Dimming: up to 10 kHz

Analog Dimming

Switching Frequency: 600-kHz

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LM3421-Q1, LM3423-Q1

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www.ti.com

9.2.4.2 Detailed Design Procedure

Table 4. Bill of Materials

QTY

1

3

1

0

4

1

2

1

2

1

PART ID

LM3421

C_B

PART VALUE

MANUFACTURER

PART NUMBER

Buck-boost controller

100-pF COG/NPO 5% 50 V

2.2-µF X7R 10% 16 V

1-µF X7R 10% 25 V

0.1-µF X7R 10% 25 V

DNP

TI

LM3421MH

MURATA

GRM2165C1H101JA01D

GRM21BR71C225KA12L

GRM21BR71E105KA01L

GRM21BR71E104KA01L

C_BYP

C_CMP, C_REF, C_SS

C_F

C_FS

C_IN

6.8-µF X7R 10% 50 V

10-µF X7R 10% 50 V

47-pF COG/NPO 5% 50 V

1000-pF COG/NPO 5% 50 V

Schottky 100 V 12 A

Zener 10 V 500 mA

22 µH 20% 7.2 A

NMOS 60 V 8 A

NMOS 60 V 260 mA

PNP 40 V 200 mA

PNP 150 V 600 mA

NPN 300 V 600 mA

NPN 40 V 200 mA

12.4 kΩ 1%

TDK

C5750X7R1H685K

C4532X7R1H106K

08055A470JAT2A

GRM2165C1H102JA01D

12CWQ10FNPBF

BZX84C10LT1G

C_O

TDK

C_OV

AVX

C_T

MURATA

VISHAY

ON-SEMI

COILCRAFT

VISHAY

ON-SEMI

FAIRCHILD

VISHAY

BOURNS

VISHAY

D1

D2

L1

MSS1278-223MLB

SI4436DY

Q1, Q2

Q3

2N7002ET1G

Q4

MMBT5087

Q5

MMBT5401

Q6

MMBTA42

Q7

MMBT6428

R_CSH

R_F

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW08050000Z0EA

CRCW080510K0FKEA

CRCW08051K00FKEA

WSL2512R0400FEA

CRCW080518K2FKEA

CRCW0805499KFKEA

3352P-1-105

10 Ω 1%

R_FS

0 Ω 1%

R_UV2

R_HSP, R_HSN

R_LIM

R_OV1

R_OV2

R_POT

R_PU

10 kΩ 1%

1 kΩ 1%

0.04 Ω 1% 1 W

18.2 kΩ 1%

499 kΩ 1%

1-MΩ potentiometer

4.99 kΩ 1%

CRCW08054K99FKEA

CRCW0805499RFKEA

WSL2512R0500FEA

CRCW080541K2FKEA

CRCW08051K43FKEA

CRCW080517K4FKEA

R_SER

R_SNS

R_T

499 Ω 1%

0.05 Ω 1% 1 W

41.2 kΩ 1%

R_UV1

R_UVH

1.43 kΩ 1%

17.4 kΩ 1%

54

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9.2.5 LM3423-Q1 Boost Application

D2

L1

D1

18V œ 38V

V_IN

R

HSN

1

2

20

V_CC

VIN

HSN

HSP

LM3423

External

Enable

C

FS

R

SNS

C

IN

R

HSP

19

18

17

16

EN

V_REF

R

FS

R

T

Q4

Q5

C

CMP

3

COMP

CSH

RCT

AGND

OVP

nDIM

FLT

RPD

D3

RPD

V_CC

PU

R

MAX

Q2

Q7

R

4

IS

R

ADJ

R

BIAS2

CSH

5

Q6

VCC

C

DIM

C

BYP

C

T

6

15

GATE

PGND

DDRV

DPOL

LRDY

Q1

R

SER

C

O

R

UV2

7

14

13

12

11

R

LIM

8

R

UVH

700 mA

I_LED

9

DAP

R

UV1

10

TIMR

R

OV2

OV1

Q3

PWM

C

OV

R

RPD

Figure 40. LM3423-Q1 Boost Application

9.2.5.1 Design Requirements

•

Input: 18 V to 38 V

Output: 12 LEDs at 700 mA

High-Side PWM Dimming: up to 30 kHz

Dimming: Analog

Zero Current Shutdown

Switching Frequency: 700-kHz

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LM3421-Q1, LM3423-Q1

SNVSB95 –JULY 2019

www.ti.com

9.2.5.2 Detailed Design Procedure

Table 5. Bill of Materials

QTY

1

4

1

2

1

2

1

3

1

PART ID

PART VALUE

MANUFACTURER

PART NUMBER

LM3423

Boost controller

2.2-µF X7R 10% 16 V

1-µF X7R 10% 25 V

0.1-µF X7R 10% 25 V

4.7-µF X7R 10% 100 V

10-µF X7R 10% 50 V

47-pF COG/NPO 5% 50 V

1000-pF COG/NPO 5% 50 V

Schottky 60 V 5 A

Zener 10 V 500 mA

47 µH 20% 5.3 A

NMOS 60 V 8 A

PMOS 70 V 5.7 A

NMOS 60 V 260 mA

Dual PNP 40 V 200 mA

NPN 300 V 600 mA

NPN 40 V 200 mA

100-kΩ potentiometer

17.4 kΩ 1%

TI

LM3423MH

C_BYP

MURATA

TDK

GRM21BR71C225KA12L

GRM21BR71E105KA01L

GRM21BR71E104KA01L

C5750X7R2A475K

C4532X7R1H106K

08055A470JAT2A

GRM2165C1H102JA01D

CDBC560-G

C_CMP

C_FS

C_IN

C_O

TDK

C_OV

AVX

C_T

MURATA

COMCHIP

ON-SEMI

COILCRAFT

VISHAY

ZETEX

D1, D2

D3

BZX84C10LT1G

L1

MSS1278-473MLB

SI4436DY

Q1

Q2

ZXMP7A17K

Q3

ON-SEMI

FAIRCHILD

BOURNS

VISHAY

2N7002ET1G

Q4, Q5 (dual pack)

FFB3906

Q6

MMBTA42

Q7

MMBT3904

R_ADJ

3352P-1-104

R_BIAS2

R_CSH, R_OV1

R_FS

CRCW080517K4FKEA

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW08051K00FKEA

WSL2512R0600FEA

CRCW0805499KFKEA

WSL2512R1500FEA

CRCW080535K7FKEA

CRCW08051K43FKEA

CRCW080510K0FKEA

CRCW080516K9FKEA

12.4 kΩ 1%

10 Ω 1%

R_HSP, R_HSN, R_MAX

R_LIM

1 kΩ 1%

0.06 Ω 1% 1W

R_OV2

499 kΩ 1%

R_SNS

0.15 Ω 1% 1W

R_T

35.7 kΩ 1%

R_UV1

1.43 kΩ 1%

R_UV2

10 kΩ 1%

R_UVH

16.9 kΩ 1%

56

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SNVSB95 –JULY 2019

9.2.6 LM3421 Buck-Boost Application

L1

D1

10V œ 70V

V_IN

R

T

C

IN

R

HSN

RCT

External

Enable

1

2

3

4

5

6

7

8

16

15

14

13

12

500 mA

I_LED

VIN

HSN

HSP

LM3421

C

O

Q9

R

HSP

EN

C

EN

Q2

DIM

COMP

CSH

RCT

AGND

OVP

nDIM

RPD

IS

C

R

CMP

CSH

C

FS

R

SNS

V_IN

C

Q8

CSH

R

FS

R

F

VCC

GATE

PGND

DDRV

RCT

C

BYP

C

T

Q7

R

PU

C

F

11

10

9

Q1

R

OV2

DIM

R

UV2

Q6

Q4

DAP

C

D2

B

R

SER

R

UVH

Q5

V_IN

Q3

R

UV1

PWM

R

OV1

C

OV

Figure 41. LM3421 Buck-Boost Application

9.2.6.1 Design Requirements

•

Input: 10 V to 70 V

Output: 6 LEDs at 500 mA

PWM Dimming up to 10 kHz

Slow Fade Out

MOSFET R_DS-ONSensing

700-kHz Switching Frequency

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LM3421-Q1, LM3423-Q1

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www.ti.com

9.2.6.2 Detailed Design Procedure

Table 6. Bill of Materials

QTY

1

0

4

1

2

1

2

1

2

1

2

1

PART ID

LM3421

C_B

PART VALUE

MANUFACTURER

PART NUMBER

Buck-boost controller

100-pF COG/NPO 5% 50 V

2.2-µF X7R 10% 16 V

1-µF X7R 10% 25 V

0.1-µF X7R 10% 25 V

DNP

TI

LM3421MH

MURATA

GRM2165C1H101JA01D

GRM21BR71C225KA12L

GRM21BR71E105KA01L

GRM21BR71E104KA01L

C_BYP

C_CMP

C_F

C_FS

C_IN

4.7-µF X7R 10% 100 V

10-µF X7R 10% 50 V

47-pF COG/NPO 5% 50 V

1000-pF COG/NPO 5% 50 V

Schottky 100 V 12 A

Zener 10 V 500 mA

68 µH 20% 4.3 A

NMOS 100 V 32 A

NMOS 60 V 260 mA

PNP 40 V 200 mA

PNP 150 V 600 mA

NPN 300 V 600 mA

NPN 40 V 200 mA

12.4 kΩ 1%

TDK

C5750X7R2A475K

C4532X7R1H106K

08055A470JAT2A

GRM2165C1H102JA01D

12CWQ10FNPBF

BZX84C10LT1G

C_O

TDK

C_OV

AVX

C_T

MURATA

VISHAY

ON-SEMI

COILCRAFT

FAIRCHILD

ON-SEMI

FAIRCHILD

VISHAY

D1

D2

L1

MSS1278-683MLB

FDD3682

Q1, Q2

Q3

2N7002ET1G

Q4, Q8

Q5

MMBT5087

MMBT5401

Q6

MMBTA42

Q7, Q9

R_CSH

R_FS

MMBT6428

CRCW080512K4FKEA

CRCW08050000Z0EA

CRCW080510K0FKEA

CRCW08051K00FKEA

CRCW080515K8FKEA

CRCW0805499KFKEA

CRCW08054K99FKEA

CRCW0805499RFKEA

WSL2512R2000FEA

CRCW080535K7FKEA

CRCW08051K43FKEA

CRCW080517K4FKEA

0 Ω 1%

R_UV2

R_HSP, R_HSN

R_OV1

R_OV2

R_PU

10 kΩ 1%

1 kΩ 1%

15.8 kΩ 1%

499 kΩ 1%

4.99 kΩ 1%

R_SER

R_SNS

R_T

499 Ω 1%

0.2 Ω 1% 1 W

35.7 kΩ 1%

R_UV1

R_UVH

1.43 kΩ 1%

17.4 kΩ 1%

58

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9.2.7 LM3423 Buck Application

15V œ 50V

V_IN

R

HSN

1

20

19

18

17

16

VIN

HSN

HSP

LM3423

C

R

SNS

FS

External

Enable

C

IN

R

HSP

2

3

EN

R

FS

R

T

C

O

C

CMP

COMP

CSH

RCT

AGND

OVP

nDIM

FLT

RPD

R

D2

PU

R

CSH

4

R

OV2

Q2

IS

1.25A

I_LED

D1

5

VCC

L1

C

BYP

Q4

C

T

6

15

GATE

PGND

DDRV

DPOL

LRDY

Q1

C

DIM

7

14

13

12

11

R

LIM

R

UV2

R

UVH

8

PWM

Q3

R

UV1

V_IN

9

DAP

R

PU2

LED

STATUS

LIGHT

10

TIMR

R

C

OV1

OV

RPD

Figure 42. LM3423 Buck Application

9.2.7.1 Design Requirements

•

Input: 15 V to 50 V

Output: 3 LEDs at 1.25 A

PWM Dimming up to 50 kHz

LED Status Indicator

Zero Current Shutdown

700-kHz Switching Frequency

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LM3421-Q1, LM3423-Q1

SNVSB95 –JULY 2019

www.ti.com

9.2.7.2 Detailed Design Procedure

Table 7. Bill of Materials

QTY

1

PART ID

LM3423

C_BYP

C_CMP, C_DIM

C_FS

PART VALUE

MANUFACTURER

PART NUMBER

Buck controller

2.2-µF X7R 10% 16 V

0.1 µF X7R 10% 25 V

DNP

TI

LM3423MH

1

MURATA

GRM21BR71C225KA12L

GRM21BR71E104KA01L

2

0

4

C_IN

4.7-µF X7R 10% 100 V

DNP

TDK

C5750X7R2A475K

0

C_O

1

C_OV

47-pF COG/NPO 5% 50 V

1000-pF COG/NPO 5% 50 V

Schottky 100 V 12 A

Zener 10 V 500 mA

22 µH 20% 7.3 A

NMOS 60 V 8 A

PMOS 30 V 6.2 A

NMOS 60 V 115 mA

PNP 150 V 600 mA

12.4 kΩ 1%

AVX

08055A470JAT2A

GRM2165C1H102JA01D

12CWQ10FNPBF

BZX84C10LT1G

1

C_T

MURATA

VISHAY

ON-SEMI

COILCRAFT

VISHAY

ON-SEMI

FAIRCHILD

VISHAY

1

D1

1

D2

1

L1

MSS1278-223MLB

SI4436DY

1

Q1

1

Q2

SI3483DV

1

Q3

2N7002ET1G

1

Q4

MMBT5401

1

R_CSH

R_FS

CRCW080512K4FKEA

CRCW08050000OZEA

CRCW08051K00FKEA

WSL2512R0400FEA

CRCW080521K5FKEA

CRCW0805499KFKEA

CRCW0805100KFKEA

CRCW080535K7FKEA

WSL2512R0800FEA

CRCW080511K5FKEA

1

0 Ω 1%

2

R_HSP, R_HSN

R_LIM

1 kΩ 1%

1

0.04 Ω 1% 1 W

21.5 kΩ 1%

1

R_OV1

R_OV2

R_PU, R_PU2, R_UV2

R_T

1

499 kΩ 1%

3

100 kΩ 1%

1

35.7 kΩ 1%

1

R_SNS

R_UV1

0.08 Ω 1% 1 W

11.5 kΩ 1%

1

60

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SNVSB95 –JULY 2019

9.2.8 LM3423 Buck-Boost Application

L1

D1

15V œ 60V

V_IN

Q2

R

D2

PU

R

HSN

1

2

20

19

18

17

16

VIN

HSN

HSP

2.5A

I_LED

LM3423

C

O

C

R

IN

HSP

External

Enable

EN

R

T

C

CMP

3

COMP

CSH

RCT

AGND

OVP

nDIM

FLT

RPD

R

CSH

4

C

FS

R

SNS

IS

V_IN

R

FS

5

VCC

R

FLT

C

BYP

C

T

6

15

GATE

PGND

DDRV

DPOL

LRDY

Q1

R

OV2

7

14

13

12

11

R

UV2

Q5

V_IN

8

R

UV1

9

DAP

10

TIMR

C

TMR

R

OV1

C

OV

RPD

Figure 43. LM3423 Buck-Boost Application

9.2.8.1 Design Requirements

•

Input: 15 V to 60 V

Output: 8 LEDs at 2.5 A

Fault Input Disconnect

Zero Current Shutdown

500-kHz Switching Frequency

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9.2.8.2 Detailed Design Procedure

Table 8. Bill of Materials

QTY

1

PART ID

LM3423

C_BYP

C_CMP

C_FS

PART VALUE

MANUFACTURER

PART NUMBER

Buck-boost controller

2.2-µF X7R 10% 16 V

0.33-µF X7R 10% 25 V

0.1-µF X7R 10% 25 V

4.7-µF X7R 10% 100 V

10-µF X7R 10% 50 V

47-pF COG/NPO 5% 50 V

1000-pF COG/NPO 5% 50 V

220-pF COG/NPO 5% 50 V

Schottky 100 V 12 A

Zener 10 V 500 mA

22 µH 20% 7.2 A

NMOS 100 V 32 A

PMOS 70 V 5.7 A

PNP 150 V 600 mA

12.4 kΩ 1%

TI

LM3423MH

1

MURATA

TDK

GRM21BR71C225KA12L

GRM21BR71E334KA01L

GRM21BR71E104KA01L

C5750X7R2A475K

C4532X7R1H106K

08055A470JAT2A

1

4

C_IN

4

C_O

TDK

1

C_OV

AVX

1

C_T

MURATA

VISHAY

ON-SEMI

COILCRAFT

FAIRCHILD

ZETEX

GRM2165C1H102JA01D

GRM2165C1H221JA01D

12CWQ10FNPBF

1

C_TMR

D1

1

D2

BZX84C10LT1G

1

L1

MSS1278-223MLB

FDD3682

1

Q1

1

Q2

ZXMP7A17K

1

Q5

FAIRCHILD

VISHAY

MMBT5401

2

R_CSH, R_OV1

R_FS

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW0805100KFKEA

CRCW08051K00FKEA

WSL2512R0400FEA

CRCW080515K8FKEA

CRCW0805499KFKEA

CRCW080549K9FKEA

CRCW080513K7FKEA

CRCW0805150KFKEA

1

10 Ω 1%

2

R_FLT, R_PU2

R_HSP, R_HSN

R_LIM, R_SNS

R_OV1

R_OV2

R_T

100 kΩ 1%

2

1 kΩ 1%

2

0.04 Ω 1% 1 W

1

15.8 kΩ 1%

1

499 kΩ 1%

1

49.9 kΩ 1%

1

R_UV1

R_UV2

13.7 kΩ 1%

1

150 kΩ 1%

62

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SNVSB95 –JULY 2019

9.2.9 LM3421 SEPIC Application

L1

D1

9V œ 36V

V_IN

C

SEP

L2

R

HSN

1

16

15

14

13

12

VIN

HSN

HSP

LM3421

C

FS

R

SNS

C

R

IN

HSP

2

3

4

5

6

7

8

EN

R

FS

R

T

C

CMP

COMP

CSH

RCT

RPD

IS

R

CSH

750 mA

I_LED

C

O

VCC

GATE

PGND

DDRV

C

BYP

C

T

11

AGND

OVP

nDIM

Q1

R

UV2

10

9

R

LIM

DAP

R

UVH

Q2

R

OV2

OV1

R

UV1

Q3

PWM

C

OV

Figure 44. LM3421 SEPIC Application

9.2.9.1 Design Procedure

•

Input: 9 V to 36 V

Output: 5 LEDs at 750 mA

PWM Dimming up to 30 kHz

500-kHz Switching Frequency

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www.ti.com

9.2.9.2 Detailed Design Procedure

Table 9. Bill of Materials

QTY

1

PART ID

LM3421

C_BYP

C_CMP

C_FS

PART VALUE

MANUFACTURER

PART NUMBER

SEPIC controller

2.2-µF X7R 10% 16 V

0.47-µF X7R 10% 25 V

DNP

TI

LM3421MH

1

MURATA

GRM21BR71C225KA12L

GRM21BR71E474KA01L

1

0

4

C_IN

4.7-µF X7R 10% 100 V

10-µF X7R 10% 50 V

1-µF X7R 10% 100 V

47-pF COG/NPO 5% 50 V

1000-pF COG/NPO 5% 50 V

Schottky 60 V 5 A

68 µH 20% 4.3 A

NMOS 60 V 8 A

NMOS 60 V 115 mA

12.4 kΩ 1%

TDK

C5750X7R2A475K

C4532X7R1H106K

C4532X7R2A105K

08055A470JAT2A

4

C_O

TDK

1

C_SEP

C_OV

TDK

1

AVX

1

C_T

MURATA

COMCHIP

COILCRAFT

VISHAY

ON-SEMI

VISHAY

GRM2165C1H102JA01D

CDBC560-G

1

D1

2

L1, L2

Q1, Q2

Q3

DO3340P-683

2

SI4436DY

1

2N7002ET1G

1

R_CSH

R_FS

CRCW080512K4FKEA

CRCW08050000OZEA

CRCW0805750RFKEA

WSL2512R0400FEA

CRCW080515K8FKEA

CRCW0805499KFKEA

CRCW080549K9FKEA

WSL2512R1000FEA

CRCW080549K9FKEA

CRCW08051K62FKEA

CRCW080510K0FKEA

CRCW080516K9FKEA

1

0 Ω 1%

2

R_HSP, R_HSN

R_LIM

750 Ω 1%

1

0.04 Ω 1% 1 W

15.8 kΩ 1%

1

R_OV1

R_OV2

R_REF1, R_REF2

R_SNS

R_T

1

499 kΩ 1%

2

49.9 kΩ 1%

1

0.1 Ω 1% 1 W

1

49.9 kΩ 1%

1

R_UV1

R_UV2

R_UVH

1.62 kΩ 1%

1

10 kΩ 1%

1

16.9 kΩ 1%

64

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SNVSB95 –JULY 2019

10 Power Supply Recommendations

10.1 General Recommendations

The device is designed to operate from an input voltage supply range from 4.5 V to 75 V. This input supply

should be well regulated. If the input supply is located more than a few inches from the EVM or PCB, additional

bulk capacitance may be required in addition to the ceramic bypass capacitors.

10.2 Input Supply Current Limit

It is important to set the output current limit of your input supply to an appropriate value to avoid delays in your

converter analysis and optimization. If not set high enough, current limit can be tripped during start-up or when

your converter output power is increased, causing a foldback or shutdown condition. It is a common oversight

when powering up a converter for the first time.

11 Layout

11.1 Layout Guidelines

•

The performance of any switching regulator depends as much upon the layout of the PCB as the component

selection. Following a few simple guidelines allows maximum noise rejection and minimal generation of EMI

within the circuit.

•

Discontinuous currents are the most likely to generate EMI, therefore care should be taken when routing

these paths. The main path for discontinuous current in the LM34xx-Q1 buck regulator contains the input

capacitor (C_IN), the recirculating diode (D1), the N-channel MOSFET (Q1), and the sense resistor (R_LIM). In

the LM34xx-Q1 boost regulator, the discontinuous current flows through the output capacitor (C_O), D1, Q1,

and R_LIM. In the buck-boost regulator, both loops are discontinuous and should be carefully layed out. These

loops should be kept as small as possible and the connections between all the components should be short

and thick to minimize parasitic inductance. In particular, the switch node (where L1, D1 and Q1 connect)

should be just large enough to connect the components. To minimize excessive heating, large copper pours

can be placed adjacent to the short current path of the switch node.

•

The RT, COMP, CSH, IS, HSP and HSN pins are all high-impedance inputs which couple external noise

easily; therefore, the loops containing these nodes should be minimized whenever possible.

In some applications the LED or LED array can be far away (several inches or more) from the controller or on

a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large

or separated from the rest of the regulator, the output capacitor should be placed close to the LEDs to reduce

the effects of parasitic inductance on the AC impedance of the capacitor.

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SNVSB95 –JULY 2019

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11.2 Layout Example

Note critical paths and component placement:

Minimize power loop containing discontinuous currents

Minimize signal current loops (components close to IC)

ñ

Ground plane under IC for signal routing helps minimize noise coupling

discontinuous switching

frequency currents

V_IN

Input

Power

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V_IN

LM3421

HSN

HSP

RPD

IS

GND

EN

COMP

CSH

I_LED

RCT

V_CC

AGND

OVP

GATE

PGND

DDRV

DAP

PWM

nDIM

STAR GROUND

Power Ground

Figure 45. LM3421 Boost Layout Guideline

66

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SNVSB95 –JULY 2019

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 10. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

LM3421

LM3421-Q1

LM3423

Click here

LM3423-Q1

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

9-Apr-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM3421Q0MHX/NOPB HTSSOP PWP

LM3421Q1MHX/NOPB HTSSOP PWP

LM3423Q0MHX/NOPB HTSSOP PWP

LM3423Q1MHX/NOPB HTSSOP PWP

16

20

2500

330.0

12.4

16.4

6.95

5.6

7.1

1.6

8.0

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Apr-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM3421Q0MHX/NOPB

LM3421Q1MHX/NOPB

LM3423Q0MHX/NOPB

LM3423Q1MHX/NOPB

HTSSOP

PWP

16

20

2500

367.0

356.0

367.0

356.0

35.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Apr-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

LM3421Q0MH/NOPB

LM3421Q1MH/NOPB

LM3423Q0MH/NOPB

LM3423Q1MH/NOPB

PWP

HTSSOP

16

20

92

73

495

8

2514.6

4.06

Pack Materials-Page 3

PACKAGE OUTLINE

PWP0016A

PowerPAD ^TMHTSSOP - 1.2 mm max height

S

C

A

L

E

2

.

4

0

PLASTIC SMALL OUTLINE

C

6.6

6.2

TYP

SEATING PLANE

PIN 1 ID

AREA

A

0.1 C

14X 0.65

16

1

2X

5.1

4.9

4.55

NOTE 3

8

9

0.30

16X

0.19

4.5

4.3

B

0.1

C A B

(0.15) TYP

SEE DETAIL A

4X 0.166 MAX

NOTE 5

2X 1.34 MAX

NOTE 5

THERMAL

PAD

0.25

GAGE PLANE

3.3

2.7

17

1.2 MAX

0.15

0.05

0 - 8

0.75

0.50

DETAIL A

TYPICAL

(1)

3.3

2.7

4214868/A 02/2017

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0016A

PowerPAD ^TMHTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.4)

NOTE 9

SOLDER MASK

DEFINED PAD

(3.3)

16X (1.5)

SYMM

SEE DETAILS

1

16

16X (0.45)

(1.1)

TYP

17

SYMM

(3.3)

(5)

NOTE 9

14X (0.65)

8

9

(

0.2) TYP

VIA

(1.1) TYP

METAL COVERED

BY SOLDER MASK

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-16

4214868/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0016A

PowerPAD ^TMHTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.3)

BASED ON

0.125 THICK

STENCIL

16X (1.5)

(R0.05) TYP

1

16

16X (0.45)

(3.3)

17

SYMM

BASED ON

0.125 THICK

STENCIL

14X (0.65)

9

8

SYMM

(5.8)

METAL COVERED

BY SOLDER MASK

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.69 X 3.69

3.3 X 3.3 (SHOWN)

3.01 X 3.01

0.125

0.15

0.175

2.79 X 2.79

4214868/A 02/2017

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

MECHANICAL DATA

PWP0020A

MXA20A (Rev C)

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM3421-Q1
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