LM3423MHX/NOPB [TI]
具有串联 DIM FET 驱动器和故障标志功能的 N 沟道恒流 LED 驱动器控制器 | PWP | 20 | -40 to 125;型号: | LM3423MHX/NOPB |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有串联 DIM FET 驱动器和故障标志功能的 N 沟道恒流 LED 驱动器控制器 | PWP | 20 | -40 to 125 驱动 控制器 光电二极管 接口集成电路 驱动器 |
文件: | 总77页 (文件大小:3137K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
用于恒流 LED 驱动器的 LM342x N 沟道控制器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
•
VIN 范围从 4.5V 至 75V
LM3421 和 LM3423 系列器件是适用于 LED 驱动器的
多功能高压 N 沟道 MOSFET 控制器。可以轻松为降
压、升压、降压/升压和 SEPIC 拓扑配置这些器件。这
一灵活性以及 75V 的输入电压额定值使得这些控制器
非常适合在多种应用中 点亮 LED。
高侧可调节电流感应
2Ω、1A 峰值 MOSFET 栅极驱动器
输入欠压和输出过压保护
PWM 和模拟调光
逐周期电流限制
可调节高侧电流感应电压允许以尽可能高的效率对
LED 电流进行严格稳压。LM3421 和 LM3423 器件采
用预测性关闭时间 (PRO) 控制,此控制集成了峰值电
流模式控制和预测性关闭计时器。这种控制方法简化了
环路补偿设计,并提供了固有的输入电压前馈补偿。
可编程开关频率
零电流关断和热关断
LED 输出状态标志(仅 LM3423 和 LM3423-Q0)
故障状态标志和计时器(仅 LM3423 和 LM3423-
Q0)
LM3421 和 LM3423 器件包含一个高电压启动稳压
器,此稳压器能够在 4.5V 至 75V 的宽输入范围内工
作。PWM 控制器专为高达 2MHz 的可调节开关频率而
设计,因此可实现紧凑的解决方案。
2 应用
•
•
•
•
•
LED 驱动器:降压、升压、降压/升压和 SEPIC
室内外空地 SSL
汽车
器件信息(1)
通用照明
器件型号
LM3421
LM3423
封装
HTSSOP (16)
HTSSOP (20)
封装尺寸(标称值)
5.00mm × 4.40mm
6.50mm × 4.40mm
恒流稳压器
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
典型升压应用
VIN
1
2
3
4
5
6
7
8
VIN
HSN 16
HSP 15
RPD 14
IS 13
EN
COMP
CSH
RCT
AGND
OVP
nDIM
ILED
VCC 12
GATE 11
PGND 10
PWM
DDRV
9
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNVS574
LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison ............................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ..................................... 5
7.2 ESD Ratings ............................................................ 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics .......................................... 7
7.6 Typical Characteristics ........................................... 11
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
9
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 Typical Applications ................................................ 32
10 Power Supply Recommendations ..................... 65
10.1 General Recommendations .................................. 65
10.2 Input Supply Current Limit .................................... 65
11 Layout................................................................... 65
11.1 Layout Guidelines ................................................. 65
11.2 Layout Example .................................................... 66
12 器件和文档支持 ..................................................... 67
12.1 器件支持................................................................ 67
12.2 相关链接................................................................ 67
12.3 社区资源................................................................ 67
12.4 商标....................................................................... 67
12.5 静电放电警告......................................................... 67
12.6 Glossary................................................................ 67
13 机械、封装和可订购信息....................................... 67
8
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision F (July 2015) to Revision G
Page
•
•
•
已删除 删除了对汽车级(LM342x-Q1 和 LM342x-Q0)器件的引用,现在在数据表 SNVSB95 中提供................................ 1
Corrected typographic error in Table 1................................................................................................................................... 3
Changed EN pulldown resistance specification minimum value from: 0.45 MΩ to: 0.245 MΩ Electrical
Characteristics table. ............................................................................................................................................................. 7
•
Changed EN pulldown resistance specification maximum value from: 1.3 MΩ to: 2.85 MΩ in Electrical
Characteristics table. ............................................................................................................................................................. 7
Changes from Revision E (April 2013) to Revision F
Page
•
已添加 ESD 额定值表, 特性 说明 部分、器件功能模式、应用和实施 部分、电源建议 部分、布局 部分、器件和文档
支持 部分以及机械、封装和可订购信息 部分 ......................................................................................................................... 1
Changes from Revision D (May 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 64
2
Copyright © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
5 Device Comparison
Table 1. Device Comparison
FLAG FEATURES
TEMPERATURE
RANGE, TA
DEVICE
QUALIFACTION
FAULT
LED OUTPUT
STATUS
LM3421-Q0
LM3421-Q1
LM3423-Q0
LM3423-Q1
LM3421
No
No
No
No
AEC-Q100 Grade 0
AEC-Q100 Grade 1
AEC-Q100 Grade 0
AEC-Q100 Grade 1
Commercial Grade
Commercial Grade
–40°C to +150°C
–40°C to +125°C
–40°C to +150°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Yes
Yes
No
Yes
Yes
No
LM3423
Yes
Yes
Copyright © 2008–2019, Texas Instruments Incorporated
3
LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
6 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
PWP Package
20-Pin HTSSOP
Top View
VIN
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
HSN
HSP
RPD
IS
VIN
EN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
HSN
HSP
RPD
IS
COMP
CSH
COMP
CSH
RCT
RCT
VCC
GATE
PGND
DDRV
VCC
GATE
AGND
OVP
AGND
OVP
nDIM
FLT
17 Thermal
Pad
14
PGND
DDRV
IADJ
nDIM
13
21 Thermal
Pad
12
11
TIMR
VREF
Pin Functions
PIN
I/O(1)
FUNCTION
NAME
LM3423
LM3421
Analog ground. Connect to PGND through the DAP copper pad to provide ground return
for CSH, COMP, RCT, and TIMR.
AGND
COMP
6
3
6
3
G
I
Compensation. Connect a capacitor to AGND to set the compensation.
Current sense high. Connect a resistor to AGND to set the signal current. For analog
dimming, connect a controlled current source or a potentiometer to AGND as detailed in
the Analog Dimming section.
CSH
4
4
I
DDRV
DPOL
13
12
9
O
I
Dim gate drive output. Connect to the gate of the dimming MOSFET.
Dim polarity. Connect to AGND if dimming with a series P-channel MOSFET or leave
open when dimming with series N-channel MOSFET.
—
Enable. Connect to AGND for zero current shutdown or apply more than 2.4 V to enable
device.
EN
2
2
I
Fault flag. Connect to pullup resistor from VIN and N-channel MOSFET open-drain
output is high when a fault condition is latched by the timer.
FLT
9
—
11
16
I
O
I
GATE
HSN
15
20
Main gate drive output. Connect to the gate of the main switching MOSFET.
LED current sense negative. Connect through a series resistor to the negative side of
the LED current sense resistor.
LED current sense positive. Connect through a series resistor to the positive side of the
LED current sense resistor.
HSP
IS
19
17
11
15
13
—
I
I
Main switch current sense. Connect to the drain of the main N-channel MOSFET switch
for RDS-ON sensing or to a sense resistor installed in the source of the same device.
LED ready flag. Connect to pullup resistor from VIN and N-channel MOSFET open-drain
output pulls down when the LED current is not in regulation.
LRDY
O
Dimming input and undervoltage protection. Connect a PWM signal for dimming as
detailed in the PWM Dimming section and/or a resistor divider from VIN to program input
undervoltage lockout (UVLO). Turnon threshold is 1.24 V and hysteresis for turnoff is
provided by a 23-µA current source.
nDIM
OVP
8
7
8
7
I
I
Overvoltage protection. Connect to a resistor divider from VO to program output
overvoltage lockout (OVLO). Turnoff threshold is 1.24 V and hysteresis for turnon is
provided by 23-µA current source.
Power ground. Connect to AGND through the DAP copper pad to provide ground return
for GATE and DDRV.
PGND
RCT
14
5
10
5
G
I
Resistor capacitor timing. External RC network sets the predictive off-time and thus the
switching frequency.
(1) G = Ground, I = Input, O = Output
4
Copyright © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
Pin Functions (continued)
PIN
I/O(1)
FUNCTION
NAME
LM3423
LM3421
Resistor pulldown. Connect the low side of all external resistor dividers (VIN UVLO,
OVP) to implement zero-current shutdown.
RPD
18
10
14
I
I
I
Fault timer. Connect a capacitor to AGND to set the time delay before a sensed fault
condition is latched.
TIMR
VIN
—
Input voltage. Bypass with 100-nF capacitor to AGND as close to the device as possible
in the printed-circuit-board layout.
1
1
VCC
16
12
I
Internal regulator output. Bypass with 2.2-µF to 3.3-µF ceramic capacitor to PGND.
Thermal PAD on bottom of IC. Star ground, connecting AGND and PGND.
Star ground, connecting AGND and PGND.
Thermal PAD
G
G
DAP
DAP (21)
DAP (17)
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
MAX
UNIT
V
76
VIN, EN, RPD, nDIM
OVP, HSP, HSN, LRDY, FLT, DPOL
RCT
–1 continuous
–0.3
mA
V
76
–100 continuous
–0.3
µA
V
76
5 continuous
76
–1 continuous
–0.3
mA
V
IS
–2 for 100 ns
–1 continuous
–0.3
mA
V
VCC
8
–0.3
7
100 continuous
6
V
TIMR
–100 continuous
–0.3
µA
V
COMP, CSH
GATE, DDRV
PGND
–200 continuous
–0.3
200 continuous
VCC
µA
V
mA
V
–2.5 for 100 ns
–1 continuous
–0.3
VCC+ 2.5 for 100 ns
1 continuous
0.3
–2.5 for 100 ns
2.5 for 100 ns
Continuous power dissipation
Maximum junction temperature
Internally Limited
Internally Limited
(3)
Maximum lead temperature (solder and reflow)
260
150
°C
°C
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Refer to http://www.ti.com/packaging for more detailed information and mounting techniques.
Copyright © 2008–2019, Texas Instruments Incorporated
5
LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-
001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification
JESD22-C101
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
MAX
UNIT
°C
Operating junction temperature, TJ
Input voltage, VIN
LM3421 , LM3423
−40
125
75
4.5
V
7.4 Thermal Information
LM3421
LM3423
THERMAL METRIC(1)
PWP (HTSSOP)
PWP (HTSSOP)
UNIT
16 PINS
38.9
23.1
16.8
0.6
20 PINS
36.7
21.5
18
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJB
16.6
1.7
17.8
1.9
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6
Copyright © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
7.5 Electrical Characteristics
VIN = 14, −40°C ≤ TJ ≤ 125°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
START-UP REGULATOR
TEST CONDITIONS
MIN
6.3
20
TYP
MAX
UNIT
ICC = 0 mA
7.35
VCCREG
ICCLIM
IQ
VCC regulation
V
ICC = 0 mA, TA = 25°C
VCC = 0 V
6.9
25
2
VCC current limit
Quiescent Current
Shutdown current
mA
mA
µA
VCC = 0 V, TA = 25°C
VEN = 3 V, Static
3
1
VEN = 3 V, Static, TA = 25°C
VEN = 0 V
ISD
VEN = 0 V, TA = 25°C
0.1
VCC SUPPLY
VCC Increasing
4.5
VCC Increasing, TA = 25°C
VCC Decreasing
4.17
VCCUV
VCC UVLO Threshold
VCC UVLO Hysteresis
V
V
V
3.7
VCC Decreasing, TA = 25°C
TA = 25°C
4.08
0.1
VCCHYS
ENABLE THRESHOLDS
VEN Increasing
2.4
ENST
EN start-up threshold
VEN Increasing, TA = 25°C
VEN Decreasing
1.75
0.8
ENST
EN start-up threshold
EN start-up hysteresis
EN pulldown resistance
V
V
VEN Decreasing, TA = 25°C
TA = 25°C
1.63
0.1
ENSTHYS
REN
VEN = 1 V
0.245
2.85
MΩ
VEN = 1 V, TA = 25°C
0.82
CSH THRESHOLDS
CSH high fault
CSH Increasing, TA = 25°C
CSH increasing, TA = 25°C
1.6
1
V
V
CSH low condition on LRDY
Pin
LM3423
OV THRESHOLDS
OVP Increasing
1.185
20
1.285
25
OVPCB
OVP OVLO threshold
V
OVP Increasing, TA = 25°C
OVP Active (high)
1.24
23
OVPHYS
OVP hysteresis source current
µA
OVP Active (high), TA = 25°C
Copyright © 2008–2019, Texas Instruments Incorporated
7
LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
Electrical Characteristics (continued)
VIN = 14, −40°C ≤ TJ ≤ 125°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
DPOL THRESHOLDS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DPOL Increasing
2
2.6
DPOLTHRSH DPOL logic threshold
V
DPOL Increasing, TA = 25°C
2.3
1200
RDPOL
DPOL pullup resistance
kΩ
TA = 25°C
500
FAULT TIMER
VFLTTH
1.185
10
1.29
13
Fault threshold
V
TA = 25°C
TA = 25°C
1.24
11.5
IFLT
FAULT pin source current
µA
ERROR AMPLIFIER
w/r/t to AGND
1.21
1.26
VREF
CSH reference voltage
V
w/r/t to AGND, TJ = 25°C
1.235
0
Error amplifier input bias
current
TJ = 25°C
–0.6
22
0.6
35
µA
µA
COMP sink or source current
TJ = 25°C
30
100
Transconductance
Linear input range
TJ = 25°C
(1), TJ = 25°C
µA/V
mV
±125
(1)
–6dB Unloaded Response
MIN = TJ = 25°C
,
Transconductance bandwidth
0.5
1
MHz
OFF TIMER
RCT = 1 V through 1 kΩ
75
120
585
tOFF(min)
Minimum OFF-time
ns
RCT = 1 V through 1 kΩ, TJ = 25°C
35
36
RRCT
RCT reset pulldown resistance
VIN/25 reference voltage
Ω
TJ = 25°C
VIN = 14 V
540
VRCT
f
mV
Hz
VIN = 14 V, TJ = 25°C
565
Continuous conduction
switching frequency
(2)
2.2 nF > CT > 470 pF, TJ = 25°C
(See
)
PWM COMPARATOR
COMP-to-PWM offset voltage
CURRENT LIMIT (IS)
700
215
900
mV
TJ = 25°C
800
275
75
ILIM
Current limit threshold
mV
ns
TJ = 25°C
TJ = 25°C
TJ = 25°C
245
35
Current limit delay-to-output
115
20
325
Leading edge blanking (LEB)
time
tLEB
ns
210
11.5
119
HIGH SIDE TRANSCONDUCTANCE AMPLIFIER
Input bias current
TJ = 25°C
µA
gM
Transconductance
mA/V
TJ = 25°C
(1) Specified by design. Not production tested.
(2) f = 25/(CT × RT
8
Copyright © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
Electrical Characteristics (continued)
VIN = 14, −40°C ≤ TJ ≤ 125°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–1.5
1.5
Input offset current
µA
TJ = 25°C
TJ = 25°C
0
–7
7
Input offset voltage
mV
0
gM(BW)
Transconductance bandwidth
ICSH = 100 µA(1), TJ = 25°C
250
500
kHz
GATE DRIVER (GATE)
GATE = High
6
RSRC(GATE) GATE sourcing resistance
Ω
Ω
GATE = High, TJ = 25°C
GATE = Low
2
4.5
RSNK(GATE)
GATE sinking resistance
GATE = Low, TJ = 25°C
1.3
DIM DRIVER (DIM, DDRV)
1.185
20
1.285
25
nDIMVTH
nDIM / UVLO threshold
V
µA
Ω
TJ = 25°C
1.24
23
nDIMHYS
nDIM hysteresis current
DDRV sourcing resistance
DDRV sinking resistance
TJ = 25°C
DDRV = High
30
RSRC(DDRV)
DDRV = High, TJ = 25°C
DDRV = Low
13.5
3.5
10
RSNK(DDRV)
Ω
DDRV = Low, TJ = 25°C
Copyright © 2008–2019, Texas Instruments Incorporated
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LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
Electrical Characteristics (continued)
VIN = 14, −40°C ≤ TJ ≤ 125°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
300
300
300
UNIT
PULLDOWN N-CHANNEL MOSFETS
RRPD
RPD pulldown resistance
FLT pulldown resistance
LRDY pulldown resistance
Ω
Ω
Ω
TJ = 25°C
TJ = 25°C
TJ = 25°C
145
145
135
RFLT
RLRDY
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold(1)
TJ = 25°C
TJ = 25°C
165
25
°C
°C
Thermal shutdown
hysteresis(1)
THYS
10
Copyright © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
7.6 Typical Characteristics
TA= 25°C, VIN = 14 V unless otherwise specified
VO = 32 V (9 LEDs)
VO = 21 V (6 LEDs)
Figure 2. Buck-Boost Efficiency vs. Input Voltage
Figure 1. Boost Efficiency vs. Input Voltage
VO = 21 V (6 LEDs)
Figure 4. Buck-Boost LED Current vs. Input Voltage
VO = 32V (9 LEDs)
Figure 3. Boost LED Current vs. Input Voltage
VO = 21 V (6 LEDs), VIN = 24 V
VO = 32 V (9 LEDs), VIN = 24 V
Figure 6. PWM Dimming
Figure 5. Analog Dimming
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Typical Characteristics (continued)
TA= 25°C, VIN = 14 V unless otherwise specified
Figure 8. VCC vs Junction Temperature
Figure 7. VCSH vs Junction Temperature
567
566
565
564
563
562
-50
-14
22
58
94
130
TEMPERATURE (°C)
Figure 9. VRCT vs Junction Temperature
Figure 10. VLIM vs Junction Temperature
225
220
215
210
205
200
195
-50
-14
22
58
94
130
TEMPERATURE (°C)
Figure 11. tON(min) vs Junction Temperature
12
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8 Detailed Description
8.1 Overview
The LM3421 and LM3423 are N-channel MOSFET ( N-channel FET ) controllers for buck, boost and buck-boost
current regulators which are ideal for driving LED loads. The controller has wide input voltage range allowing for
regulation of a variety of LED loads. The high-side differential current sense, with low adjustable threshold
voltage, provides an excellent method for regulating output current while maintaining high system efficiency.
The devices use a Predictive Off-time (PRO) control architecture that allows the regulator to be operated using
minimal external control loop compensation, while providing an inherent cycle-by-cycle current limit. The
adjustable current sense threshold provides the capability to amplitude (analog) dim the LED current and the
output enable and disable function with external dimming FET driver allows for fast PWM dimming of the LED
load. The maximum attainable LED current is not internally limited because the device is a controller. Instead,
current is a function of the system operating point, component choices, and switching frequency that allows the
device to easily provide constant currents up to 5 A. This controller contains all the features necessary to
implement a high-efficiency versatile LED driver.
8.2 Functional Block Diagram
VIN
6.9V LDO
Regulator
EN
VCC
V
UVLO
820k
CC
UVLO
(4.1V)
1.235V
REFERENCE
Standby
500k
V
IN
UVLO
HYSTERESIS
DPOL
DDRV
V
CC
23 mA
TLIM
Thermal
Limit
nDIM
Dimming
1.24V
OVLO
LatchOff
PGND
Reset
Dominant
Start new on time
V
CC
V
IN
/25
Q
S
R
RCT
LEB
GATE
PGND
t = 150 ns
COMP
CSH
RPD
PWM
23 mA
OVP
HYSTERESIS
1.235V
EN
OVLO
OVP
800 mV
1.24V
LOGIC
HSP
HSN
LRDY
CURRENT
LIMIT
IS
0.245V
11.5 mA
LED CURRENT LOW
LED CURRENT HIGH
LEB
1.0V
1.6V
LatchOff
TIMR
FLT
1.24V
AGND
TLIM
Grey pins are available in the LM3423 only.
In the LM3421, TIMR is internally shorted to AGND.
V
UVLO
CC
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8.3 Feature Description
8.3.1 Current Regulators
iL (t)
I
L-MAX
Âi
L-PP
I
L
I
L-MIN
t
= DT
t = (1-D)T
OFF S
ON
S
0
t
T
S
Figure 12. Ideal CCM Regulator Inductor Current iL(t)
Current regulators can create three basic topologies: buck, boost, or buck-boost. All three topologies in their
most basic form contain a main switching MOSFET, a recirculating diode, an inductor and capacitors. The
controller is designed to drive a ground referenced N-channel FET which is perfect for a standard boost
regulator. However, buck and buck-boost regulators usually have a high-side switch. When driving an LED load,
a ground referenced load is often not necessary, therefore a ground referenced switch drives a floating load
instead. The controller can then be used to drive all three basic topologies as shown in the Basic Topology
Schematics section. Other topologies such as the SEPIC and flyback converter (both derivatives of the buck-
boost) can be implemented as well.
Looking at the buck-boost design, the basic operation of a current regulator can be analyzed. During the time
that the N-channel FET (Q1) is turned on (tON), the input voltage source stores energy in the inductor (L1) while
the output capacitor (CO) provides energy to the LED load. When Q1 is turned off (tOFF), the re-circulating diode
(D1) becomes forward biased and L1 provides energy to both CO and the LED load. Figure 12 shows the
inductor current (iL(t)) waveform for a regulator operating in CCM.
The average output LED current (ILED) is proportional to the average inductor current (IL) , therefore if IL is tightly
controlled, ILED is well regulated. As the system changes input voltage or output voltage, the ideal duty cycle (D)
is varied to regulate IL and ultimately ILED. For any current regulator, D is a function of the conversion ratio:
Buck
VO
D =
V
IN
(1)
Boost
VO - V
IN
D =
VO
(2)
Buck-boost
VO
D
=
VO + V
IN
(3)
8.3.2 Predictive Off-Time (PRO) Control
PRO control is used by the device to control ILED. It is a combination of average peak current control and a one-
shot off-timer that varies with input voltage. The LM3421 and LM3423 use peak current control to regulate the
average LED current through an array of HBLEDs. This method of control uses a series resistor in the LED path
to sense LED current and can use either a series resistor in the MOSFET path or the MOSFET RDS-ON for both
cycle-by-cycle current limit and input voltage feed forward. D is indirectly controlled by changes in both tOFF and
tON, which vary depending on the operating point.
14
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Feature Description (continued)
Even though the off-time control is quasi-hysteretic, the input voltage proportionality in the off-timer creates an
essentially constant switching frequency over the entire operating range for boost and buck-boost topologies.
The buck topology can be designed to give constant ripple over either input voltage or output voltage, however
switching frequency is only constant at a specific operating point .
This type of control minimizes the control loop compensation necessary in many switching regulators, simplifying
the design process. The averaging mechanism in the peak detection control loop provides extremely accurate
LED current regulation over the entire operating range.
PRO control was designed to mitigate current mode instability (also called sub-harmonic oscillation) found in
standard peak current mode control when operating near or above 50% duty cycles. When using standard peak
current mode control with a fixed switching frequency, this condition is present, regardless of the topology.
However, using a constant off-time approach, current mode instability cannot occur, enabling easier design and
control.
Predictive off-time advantages:
•
•
There is no current mode instability at any duty cycle.
Higher duty cycles or voltage transformation ratios are possible, especially in the boost regulator.
The only disadvantage is that synchronization to an external reference frequency is generally not available.
8.3.3 Average LED Current
LM3421/23
I
LED
High-Side
Sense Amplifier
R
HSP
HSP
HSN
V
R
SNS
SNS
R
HSN
I
CSH
R
C
CSH
Error Amplifier
CSH
To PWM
Comparator
1.24V
CMP
COMP
Figure 13. LED Current Sense Circuitry
The LM3421 and LM3423 use an external current sense resistor (RSNS) placed in series with the LED load to
convert the LED current (ILED) into a voltage (VSNS) as shown in Figure 13. The HSP and HSN pins are the inputs
to the high-side sense amplifier which are forced to be equal potential (VHSP=VHSN) through negative feedback.
Because of this, the VSNS voltage is forced across RHSP to generate the signal current (ICSH) which flows out of
the CSH pin and through the RCSH resistor. The error amplifier regulates the CSH pin to 1.24 V, therefore ICSH
can be calculated using Equation 4.
VSNS
ICSH
=
RHSP
(4)
(5)
This application regulates VSNS as described in Equation 5.
RHSP
VSNS = 1.24V x
RCSH
Calculate ILED using Equation 6.
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Feature Description (continued)
VSNS
RSNS
1.24V RHSP
x
ILED
=
=
RSNS
RCSH
(6)
The selection of the three resistors (RSNS, RCSH, and RHSP) is not arbitrary. For matching and noise performance,
the suggested signal current ICSH is approximately 100 µA. This current does not flow in the LEDs and does not
affect either the off-state LED current or the regulated LED current. ICSH can be above or below this value, but
the high-side amplifier offset characteristics may be affected slightly. In addition, to minimize the effect of the
high-side amplifier voltage offset on LED current accuracy, the minimum VSNS is suggested to be 50 mV. Place a
resistor (RHSN = RHSP) in series with the HSN pin to cancel out the effects of the input bias current (approximately
10 µA) of both inputs of the high-side sense amplifier.
The sense resistor (RSNS) can be placed anywhere in the series string of LEDs as long as the voltage at the HSN
and HSP pins (VHSP and VHSN) satisfies the following conditions.
VHSP < 76V
VHSN > 3.5V
(7)
Typically, for a buck-boost configuration, RSNS is placed at the bottom of the string (LED-) which allows for
greater flexibility of input and output voltage. However, if there is substantial input voltage ripple allowed, it can
help to place RSNS at the top of the string (LED+) which limits the output voltage of the string to:
VO = 76V - VIN
(8)
The CSH pin can also be used as a low-side current sense input regulated to 1.24 V. The high-side sense
amplifier is disabled if HSP and HSN are tied to AGND (or VHSN > VHSP) .
8.3.4 Analog Dimming
The CSH pin can be used to analog dim the LED current by adjusting the current sense voltage (VSNS). There
are several different methods to adjust VSNS using the CSH pin:
1. External variable resistance: Adjust a potentiometer placed in series with RCSH to vary VSNS
.
2. External variable current source: Source current (0 µA to ICSH) into the CSH pin to adjust VSNS
.
Variable Current Source
LM3421/23
VCC
V
REF
Q8
Q7
R
MAX
Q6
R
CSH
R
CSH
R
ADJ
BIAS
Variable
Resistance
R
ADJ
Figure 14. Analog Dimming Circuitry
In general, analog dimming applications require a lower switching frequency to minimize the effect of the leading
edge blanking circuit. As the LED current is reduced, the output voltage and the duty cycle decreases.
Eventually, the minimum on-time is reached. The lower the switching frequency, the wider the linear dimming
range. Figure 14 shows how both CSH methods are physically implemented.
Method 1 uses an external potentiometer in the CSH path which is a simple addition to the existing circuitry.
However, the LEDs cannot dim completely because there is always some resistance causing signal current to
flow. This method is also susceptible to noise coupling at the CSH pin because the potentiometer increases the
size of the signal current loop.
16
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Feature Description (continued)
Method 2 provides a complete dimming range and better noise performance, though it is more complex. It
consists of a PNP current mirror and a bias network consisting of an NPN, 2 resistors and a potentiometer
(RADJ), where RADJ controls the amount of current sourced into the CSH pin. A higher resistance value sources
more current into the CSH pin, causing less regulated signal current through RHSP, effectively dimming the LEDs.
VREF should be a precise external voltage reference, while Q7 and Q8 should be a dual pair PNP for best
matching and performance. The additional current (IADD) sourced into the CSH pin can be calculated using
Equation 9.
≈
∆
«
’
÷
RADJ x VREF
RADJ + RMAX
- VBE-Q6
◊
IADD
=
RBIAS
(9)
The corresponding LED current ( ILED) for a specific IADD is:
R
≈
∆
«
’
÷
◊
HSP
ILED = (ICSH - IADD) x
RSNS
(10)
8.3.5 Current Sense and Current Limit
The LM3421 and LM3423 achieve peak current mode control using a comparator that monitors the main
MOSFET (Q1) transistor current, comparing it with the COMP pin voltage as shown in Figure 15. The controller
incorporates a cycle-by-cycle overcurrent protection function. Aredundant internal current sense comparator
provides the current limit functionality . If the voltage at the current sense comparator input (IS pin) exceeds 245
mV (typical), the on cycle is immediately terminated. The IS input pin has an internal N-channel MOSFET which
pulls it down at the conclusion of every cycle. The discharge device remains on for an additional 210 ns (typical)
after the beginning of a new cycle to blank the leading edge spike on the current sense signal. The leading edge
blanking (LEB) determines the minimum achievable on-time (tON-MIN).
R
DS-ON
Sensing
LM3421/23
COMP
Q1
GATE
0.8V
PWM
R
LIM
Sensing
IS
0.245V
I
T
R
LIM
LEB
PGND
Figure 15. Current Sense / Current Limit Circuitry
There are two possible methods to sense the transistor current. The RDS-ON of the main power MOSFET can be
used as the current sense resistance because the IS pin was designed to withstand the high voltages present on
the drain when the MOSFET is in the off state. Alternatively, a sense resistor located in the source of the
MOSFET may be used for current sensing; however, TI suggests a low inductance (ESL) type. The cycle-by-
cycle current limit (ILIM) can be calculated using either method as the limiting resistance (RLIM):
245 mV
ILIM
=
RLIM
(11)
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Feature Description (continued)
8.3.6 Overcurrent Protection
The LM3421 and LM3423 controllers have a secondary method of overcurrent protection. Switching action is
disabled whenever the current in the LEDs is more than 30% above the regulation set point. The dimming
MOSFET switch driver (DDRV) is not disabled however as this would immediately remove the fault condition and
cause oscillatory behavior.
8.3.7 Zero Current Shutdown
The LM3421 and LM3423 controllers implement zero current shutdown through the EN and RPD pins. When
pulled low, the EN pin places the devices into near-zero current state, where only the leakage currents occurs at
the pins (typical 0.1 µA). The applications circuits frequently have resistor dividers to set UVLO, OVLO, or other
similar functions. The RPD pin is an open-drain N-channel MOSFET that is enabled only when the device is
enabled. Tying the bottom of all resistor dividers to the RPD pin as shown in Figure 16 allows them to float
during shutdown, thus removing their current paths and providing true application-wide zero current shutdown.
L1
D1
VIN
VO
LM3421/23
Enable
EN
R
OV2
VIN
OVP
RPD
R
R
OV1
UV2
nDIM
R
UV1
Figure 16. Zero Current Shutdown Circuit
8.3.8 Control Loop Compensation
The control loop is modeled as most typical current mode controllers. Using a first order approximation, the
uncompensated loop can be modeled as a single pole created by the output capacitor and, in the boost and
buck-boost topologies, a right half plane zero created by the inductor, where both have a dependence on the
LED string dynamic resistance. There is also a high-frequency pole in the model; however, it is near the
switching frequency and plays no part in the compensation design process. Therefore, it is neglected. Because
ceramic capacitance is recommended for use with LED drivers, due to long lifetimes and high ripple current
rating, the ESR of the output capacitor can also be neglected in the loop analysis. The DC gain of the
uncompensated loop depends on internal controller gains and the external sensing network.
This section describes a buck-boost regulator as an example case.
Use Equation 12 to calculate the uncompensated loop gain for a buck-boost regulator.
≈
’
÷
÷
◊
s
∆ -
1
∆
w
Z1
«
TU = TU0
x
≈
∆
«
’
÷
÷
◊
s
∆
1+
w
P1
(12)
(13)
Where the uncompensated DC loop gain of the system is calculated using Equation 13.
Å
D x 500Vx RCSH x RSNS
Å
D x 620V
TU0
=
=
( )
1+D x RHSP x RLIM
( )
1+D xILED x RLIM
And the output pole (ωP1) is approximated using Equation 14.
1+D
w =
P1
rD x CO
(14)
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Feature Description (continued)
And the right half plane zero (ωZ1) is:
2
Å
rD xD
DxL1
w =
Z1
(15)
135
90
100
80
60
40
20
0
ö
P1
ö
Z1
GAIN
45
0
PHASE
-45
-90
-135
-180
-225
0° Phase Margin
-20
-40
-60
1e-1
1e1
1e3
1e5
1e7
FREQUENCY (Hz)
Figure 17. Uncompensated Loop Gain Frequency Response
Figure 17 shows the uncompensated loop gain in a worst-case scenario when the RHP zero is below the output
pole. This occurs at high duty cycles when the regulator is trying to boost the output voltage significantly. The
RHP zero adds 20dB/decade of gain while losing 45°/decade of phase, which places the crossover frequency
(when the gain is zero dB) extremely high because the gain only starts falling again due to the high-frequency
pole (not shown in Figure 17). The phase is below –180° at the crossover frequency, which means there is no
phase margin (180° + phase at crossover frequency) causing system instability. Even if the output pole is below
the RHP zero, the phase reaches –180° before the crossover frequency in most cases yielding instability.
LM3421/23
I
LED
High-Side
Sense Amplifier
R
HSP
HSP
HSN
C
FS
V
SNS
R
SNS
R
HSN
R
FS
Error Amplifier
sets ö
P3
R
CSH
CSH
To PWM
Comparator
1.24V
R
O
C
CMP
sets ö
COMP
P2
Figure 18. Compensation Circuitry
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Feature Description (continued)
To mitigate this problem, a compensator should be designed to give adequate phase margin (above 45°) at the
crossover frequency. A simple compensator using a single capacitor at the COMP pin (CCMP) adds a dominant
pole to the system, which ensures adequate phase margin if placed low enough. At high duty cycles (as shown
in Figure 17), the RHP zero places extreme limits on the achievable bandwidth with this type of compensation.
However, because an LED driver is essentially free of output transients (except catastrophic failures open or
short), the dominant pole approach, even with reduced bandwidth, is usually the best approach. The dominant
compensation pole (ωP2) is determined by CCMP and the output resistance (RO) of the error amplifier (typically 5
MΩ) as demonstrated in Equation 16.
1
wP2
=
5ì106 ìCCMP
(16)
It may also be necessary to add one final pole at least one decade above the crossover frequency to attenuate
switching noise and, in some cases, provide better gain margin. This pole can be placed across RSNS to filter the
ESL of the sense resistor at the same time. Figure 18 shows how the compensation is physically implemented in
the system.
The high-frequency pole (ωP3) can be calculated using Equation 17.
1
w
=
P3
RFS xCFS
(17)
The total system transfer function becomes:
≈
’
÷
÷
◊
s
∆
1-
∆
w
Z1
«
T = TU0
x
≈
’
÷
÷
◊
≈
∆
«
’
÷
÷
≈
∆
«
’
÷
÷
◊
s
s
s
∆
∆
∆
1+
x 1+
x 1+
∆
w
w
w
P1
P2
P3
«
◊
(18)
The resulting compensated loop gain frequency response shown in Figure 19 indicates that the system has
adequate phase margin (above 45°) if the dominant compensation pole is placed low enough, ensuring stability.
90
80
60
ö
P2
45
0
40
GAIN
-45
-90
-135
-180
-225
-270
20
ö
ö
Z1
P1
0
PHASE
ö
P3
-20
-40
-60
-80
60° Phase Margin
1e-1
1e1
1e3
1e5
1e7
FREQUENCY (Hz)
Figure 19. Compensated Loop Gain Frequency Response
8.3.9 Start-Up Regulator
The controller includes a high voltage, low dropout bias regulator. When power is applied, the regulator is
enabled and sources current into an external capacitor (CBYP) connected to the VCC pin. The recommended
bypass capacitance for the VCC regulator is 2.2 µF to 3.3 µF. The output of the VCC regulator is monitored by an
internal UVLO circuit that protects the device from attempting to operate with insufficient supply voltage and the
supply is also internally current limited. Figure 20 shows the typical start-up waveforms.
20
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Feature Description (continued)
V
CMP
0.9V
0
t
t
t
t
CO
VCC
CMP
Figure 20. Start-Up Waveforms
First, CBYP is charged to be above VCC UVLO threshold (approximately 4.2 V). The CVCC charging time (tVCC) can
be estimated using Equation 19.
4.2V
tVCC
xCBYP 168W xC
=
=
BYP
25 mA
(19)
CCMP is then charged to 0.9 V over the charging time (tCMP), which can be estimated using Equation 20.
0.9V
tCMP
x CCMP 36 kW xC
=
=
CMP
25 mA
(20)
Once CCMP = 0.9 V, the part starts switching to charge CO until the LED current is in regulation. The CO charging
time (tCO) can be roughly estimated using Equation 21.
VO
tCO
C
O x
=
ILED
(21)
The system start-up time (tSU) is defined using Equation 22.
tSU
t
t
t
+
CO
=
+
VCC
CMP
(22)
In some configurations, the start-up waveform overshoots the steady state COMP pin voltage. In this case, the
LED current and output voltage overshoots also, which can trip the overvoltage or protection, causing a race
condition. The easiest way to prevent this is to use a larger compensation capacitor (CCMP), thereby slowing
down the control loop.
8.3.10 Overvoltage Lockout (OVLO)
The LM3421 and LM3423 can be configured to detect an output (or input) overvoltage condition through the OVP
pin. The pin features a precision 1.24-V threshold with 23 µA (typical) of hysteresis current as shown in
Figure 21. When the OVLO threshold is exceeded, the GATE pin is immediately pulled low and a 23-µA current
source provides hysteresis to the lower threshold of the OVLO hysteretic band.
If the LEDs are referenced to a potential other than ground (floating), as in the buck-boost and buck
configuration, the output voltage (VO) should be sensed and translated to ground by using a single PNP as
shown in Figure 22.
The overvoltage turnoff threshold (VTURN-OFF) is defined:
Ground Referenced
≈
’
ROV + ROV2
1
∆
∆
«
÷
÷
◊
V
TURN-OFF = 1.24Vx
ROV1
(23)
Floating
TURN-OFF = 1.24Vx
≈
’
+ ROV2
0.5 x ROV1
∆
∆
«
÷
V
÷
ROV1
◊
(24)
21
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Feature Description (continued)
In the ground referenced configuration, the voltage across ROV2 is VO – 1.24 V whereas in the floating
configuration it is VO – 620 mV where 620 mV approximates VBE of the PNP.
The overvoltage hysteresis (VHYSO) is defined using Equation 25.
VHYSO = 23 mA x ROV2
(25)
LM3421/23
VO
23 mA
R
R
OV2
OV1
OVP
OVLO
1.24V
Figure 21. Overvoltage Protection Circuitry
LED+
R
OV2
LM3421/23
LED-
OVP
R
OV1
Figure 22. Floating Output OVP Circuitry
The OVLO feature can cause some interesting results if the OVLO trip-point is set too close to VO. At turnon, the
converter has a modest amount of voltage overshoot before the control loop gains control of ILED. If the overshoot
exceeds the OVLO threshold, the controller shuts down, opening the dimming MOSFET. This isolates the LED
load from the converter and the output capacitance. The voltage then discharges very slowly through the HSP
and HSN pins until VO drops below the lower threshold, where the process repeats. This looks like the LEDs are
blinking at around 2 Hz. This mode can be escaped if the input voltage is reduced.
8.3.11 Input Undervoltage Lockout (UVLO)
The nDIM pin is a dual-function input that features an accurate 1.24-V threshold with programmable hysteresis
as shown in Figure 23. This pin functions as both the PWM dimming input for the LEDs and as a VIN UVLO.
When the pin voltage rises and exceeds the 1.24-V threshold, 23 µA (typical) of current is driven out of the nDIM
pin into the resistor divider providing programmable hysteresis.
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Feature Description (continued)
LM3421/23
VIN
23 mA
R
R
UV2
UV1
nDIM
UVLO
1.24V
R
UVH
(optional)
Figure 23. UVLO Circuit
When using the nDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra series
resistor to set the hysteresis. This allows the standard resistor divider to have smaller resistor values minimizing
PWM delays due to a pulldown MOSFET at the nDIM pin (see PWM Dimming section). In general, at least 3 V of
hysteresis is preferable when PWM dimming, if operating near the UVLO threshold.
The turnon threshold (VTURN-ON) is defined using Equation 26.
≈
’
÷
÷
◊
RUV + RUV2
1
∆
∆
«
VTURN O-N = 1.24Vx
RUV1
(26)
(27)
The hysteresis (VHYS) is defined as follows:
8.3.11.1 UVLO Only
VHYS 23 mA xR
=
UV2
8.3.11.2 PWM Dimming and UVLO
≈
∆
«
(
)’
÷
◊
RUVH x RUV1 + RUV2
∆
23mA x R
VHYS
=
+
UV2
÷
RUV1
(28)
When zero current shutdown and UVLO are implemented together, the EN pin can be used to escape UVLO.
The nDIM pin pulls up to VIN when EN is pulled low. Therefore, if VIN is within the UVLO hysteretic window when
EN is pulled high again, the controller starts-up even though VTURN-ON is not exceeded.
8.3.12 PWM Dimming
The active low nDIM pin can be driven with a PWM signal which controls the main N-channel FET and the
dimming FET (dimFET). The brightness of the LEDs can be varied by modulating the duty cycle of this signal.
LED brightness is approximately proportional to the PWM signal duty cycle, (that is, 30% duty cycle equals
approximately 30% LED brightness). This function can be ignored if PWM dimming is not required by using nDIM
solely as a VIN UVLO input as described in Input Undervoltage Lockout (UVLO) or by tying it directly to VCC or
VIN.
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Feature Description (continued)
Inverted
PWM
VIN
LM3421/23
D
DIM
R
UV2
nDIM
R
UVH
R
UV1
Q
DIM
Standard
PWM
Figure 24. PWM Dimming Circuit
STOPPED DD EDITING HERELM3421 and LM3423
Figure 24 shows how the PWM signal is applied to nDIM:
1. Connect the dimming MOSFET (QDIM) with the drain to the nDIM pin and the source to AGND. Apply an
external logic-level PWM signal to the gate of QDIM
.
2. Connect the anode of a Schottky diode (DDIM) to the nDIM pin. Apply an inverted external logic-level PWM
signal to the cathode of the same diode.
The DDRV pin is a PWM output that follows the nDIM PWM input signal. When the nDIM pin rises, the DDRV pin
rises and the PWM latch reset signal is removed allowing the main MOSFET Q1 to turn on at the beginning of
the next clock set pulse. In boost and buck-boost topologies, the DDRV pin is used to control a N-channel
MOSFET placed in series with the LED load, while it would control a P-channel MOSFET in parallel with the load
for a buck topology.
The series dimFET opens the LED load, when nDIM is low, effectively speeding up the rise and fall times of the
LED current. Without any dimFET, the rise and fall times are limited by the inductor slew rate and dimming
frequencies above 1 kHz are impractical. Using the series dimFET, dimming frequencies up to 30 kHz are
achievable. With a parallel dimFET (buck topology), even higher dimming frequencies are achievable.
When using the PWM functionality in a boost regulator, the PWM signal can drive a ground referenced FET.
However, with buck-boost and buck topologies, level shifting circuitry is necessary to translate the PWM dim
signal to the floating dimFET as shown in Figure 25 and Figure 26. If high side dimming is necessary in a boost
regulator using the LM3423, level shifting can be added providing the polarity inverting DPOL pin is pulled low
(see LM3423 Only: DPOL, FLT, TIMR, and LRDY section) as shown in Figure 27.
When using a series dimFET to PWM dim the LED current, more output capacitance is always better. Typical
applications use a minimum of 40 µF for PWM dimming. For most applications, a capacitance of 40 µF provides
adequate energy storage at the output when the dimFET turns off and opens the LED load. Then when the
dimFET is turned back on, the capacitance helps source current into the load, improving the LED current rise
time.
A minimum on-time must be maintained in order for PWM dimming to operate in the linear region of its transfer
function. Because the controller is disabled during dimming, the PWM pulse must be long enough such that the
energy intercepted from the input is greater than or equal to the energy being put into the LEDs. For boost and
buck-boost regulators, the minimum dimming pulse length in seconds (tPULSE) is:
2 x ILED x VO X L1
tPULSE
=
2
VIN
(29)
Even maintaining a dimming pulse greater than tPULSE, preserving linearity at low dimming duty cycles is difficult.
24
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Feature Description (continued)
The second helpful modification is to remove the CFS capacitor and RFS resistor, eliminating the high-frequency
compensation pole. Typically, this does not affect stability, but it speeds up the response of the CSH pin,
specifically at the rising edge of the LED current when PWM dimming, thus improving the achievable linearity at
low dimming duty cycles.
LED+
LM3421/23
10W
5 kW
Q7
Q4
100 nF
Q2
VCC
Q6
R
SNS
100 pF
10V
V
IN
500W
DDRV
Figure 25. Buck-boost Level-Shifted PWM Circuit
LM3421/23
R
SNS
100
10V
kW
Q2
100 nF
DDRV
Figure 26. Buck Level-Shifted PWM Circuit
V
O
LM3421/23
DPOL
R
SNS
100
kW
10V
Q2
VCC
Q6
100 pF
10 kW
DDRV
Figure 27. Boost Level-Shifted PWM Circuit
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Feature Description (continued)
8.3.13 LM3423 Only: DPOL, FLT, TIMR, and LRDY
The LM3423 has four additional pins: DPOL, FLT, TIMR, and LRDY. The DPOL pin is simply used to invert the
DDRV polarity . If DPOL is left open, then it is internally pulled high and the polarity is correct for driving a series
N-channel dimFET. If DPOL is pulled low then the polarity is correct for using a series P-channel dimFET in high-
side dimming applications. For a parallel P-channel dimFET, as used in the buck topology, leave DPOL open for
proper polarity.
The additional TIMR and FLT pins can be used in conjunction with an input disconnect MOSFET switch as
shown in Figure 28 to protect the module from various fault conditions.
A fault is detected and an 11.5 µA (typical) current is sourced from the TIMR pin whenever any one of the
following conditions exists.
•
•
•
LED current is above regulation by more than 30%.
OVLO has engaged.
Thermal shutdown has engaged.
An external capacitor (CTMR) from TIMR to AGND programs the fault filter time as follows:
tFLT 11.5
x
m
A
CTMR
=
1.24V
(30)
When the voltage on the TIMR pin reaches 1.24 V, the device is latched off and the N-channel MOSFET open-
drain FLT pin transitions to a high impedance state. The controller immediatly pulls the TIMR pin to ground
(resets) if the fault condition is removed at any point during the filter period. Otherwise, if the timer expires, the
fault remains latched until one of these situations occurs:
•
•
•
The EN pin is pulled low long enough for the VCC pin to drop below 4.1 V (approximately 200 ms) or
the TIMR pin is pulled to ground or
a complete power cycle occurs
When using the EN and OVP pins in conjunction with the RPD pulldown pin, a race condition exists when exiting
the disabled (EN low) state. When disabled, controller pulls up the OVP pin to the output voltage because the
RPD pulldown is disabled, and this appears as if it is a real OVLO condition. The timer pin immediately rises and
latches the controller to the fault state. To protect against this behavior, a minimum timer capacitor (CTMR = 220
pF) should be used. If fault latching is not required, short the TMR pin to AGND, which disables the FLT flag
function.
The LM3423 also includes an LED Ready (LRDY) flag to notify the system that the LEDs are in proper
regulation. The N-channel MOSFET open-drain LRDY pin is pulled low whenever any of the following conditions
are met:
1. VCC UVLO has engaged.
2. LED current is below regulation by more than 20%.
3. LED current is above regulation by more than 30%.
4. Overvoltage protection has engaged
5. Thermal shutdown has engaged.
6. A fault has latched the device off.
The LRDY pin is pulled low during start-up of the device and remains low until the LED current is in regulation.
26
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Feature Description (continued)
VIN
VSW
LM3421/23
FLT
VIN
High = LED in regulation
LRDY
TIMR
Figure 28. Fault Detection and LED Status Circuit
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Inductor
The inductor (L1) is the main energy storage device in a switching regulator. Depending on the topology, energy
is stored in the inductor and transfered to the load in different ways (as an example, buck-boost operation is
detailed in the Current Regulators section). The size of the inductor, the voltage across it, and the length of the
switching subinterval (tON or tOFF) determines the inductor current ripple (ΔiL-PP). In the design process, L1 is
chosen to provide a desired ΔiL-PP. For a buck regulator the inductor has a direct connection to the load, which is
good for a current regulator. This requires little to no output capacitance therefore ΔiL-PP is basically equal to the
LED ripple current ΔiLED-PP. However, for boost and buck-boost regulators, there is always an output capacitor
which reduces ΔiLED-PP; therefore, the inductor ripple can be larger than in the buck regulator case where output
capacitance is minimal or completely absent.
In general, ΔiLED-PP is recommended by manufacturers to be less than 40% of the average LED current (ILED).
Therefore, for the buck regulator with no output capacitance, ΔiL-PP should also be less than 40% of ILED. For the
boost and buck-boost topologies, ΔiL-PP can be much higher depending on the output capacitance value.
However, ΔiL-PP is suggested to be less than 100% of the average inductor current (IL) to limit the RMS inductor
current.
L1 is also suggested to have an RMS current rating at least 25% higher than the calculated minimum allowable
RMS inductor current (IL-RMS).
9.1.2 LED Dynamic Resistance
When the load is a string of LEDs, the output load resistance is the LED string dynamic resistance plus RSNS
.
LEDs are PN junction diodes, and their dynamic resistance shifts as their forward current changes. Dividing the
forward voltage of a single LED (VLED) by the forward current (ILED) leads to an incorrect calculation of the
dynamic resistance of a single LED (rLED). The result can be 5 to 10 times higher than the true rLED value.
Figure 29. Dynamic Resistance
Obtaining rLED is accomplished by referring to the manufacturer's LED I-V characteristic. It can be calculated as
the slope at the nominal operating point as shown in Figure 29. For any application with more than 2 series
LEDs, RSNS can be neglected allowing rD to be approximated as the number of LEDs multiplied by rLED
.
28
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Application Information (continued)
9.1.3 Output Capacitor
For boost and buck-boost regulators, the output capacitor (CO) provides energy to the load when the recirculating
diode (D1) is reverse biased during the first switching subinterval. An output capacitor in a buck topology simplys
reduce the LED current ripple (ΔiLED-PP) below the inductor current ripple (ΔiL-PP). In all cases, CO is sized to
provide a desired ΔiLED-PP. As mentioned in the Inductor section, ΔiLED-PP is recommended by manufacturers to be
less than 40% of the average LED current (ILED).
CO should be carefully chosen to account for derating due to temperature and operating voltage. It must also
have the necessary RMS current rating. Ceramic capacitors are the best choice due to their high ripple current
rating, long lifetime, and good temperature performance. An X7R dieletric rating is suggested.
9.1.4 Input Capacitors
The input capacitance (CIN) provides energy during the discontinuous portions of the switching period. For buck
and buck-boost regulators, CIN provides energy during tON and during tOFF, the input voltage source charges up
CIN with the average input current (IIN). For boost regulators, CIN only needs to provide the ripple current due to
the direct connection to the inductor. CIN is selected given the maximum input voltage ripple (ΔvIN-PP) which can
be tolerated. ΔvIN-PP is suggested to be less than 10% of the input voltage (VIN).
An input capacitance at least 100% greater than the calculated CIN value is recommended to account for derating
due to temperature and operating voltage. When PWM dimming, even more capacitance can be helpful to
minimize the large current draw from the input voltage source during the rising transition of the LED current
waveform.
The chosen input capacitors must also have the necessary RMS current rating. Ceramic capacitors are again the
best choice due to their high ripple current rating, long lifetime, and good temperature performance. An X7R
dielectric rating is suggested.
For most applications, TI recommends bypassing the VIN pin with an 0.1 µF ceramic capacitor placed as close as
possible to the pin. In situations where the bulk input capacitance may be far from the controller, a 10-Ω series
resistor can be placed between the bulk input capacitance and the bypass capacitor, creating a 150-kHz filter to
eliminate undesired high-frequency noise.
9.1.5 Main MOSFET / Dimming MOSFET
The controller requires an external N-channel FET (Q1) as the main power MOSFET for the switching regulator.
TI recommends Q1 have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe
operation during the ringing of the switch node. In practice, all switching regulators have some ringing at the
switch node due to the diode parasitic capacitance and the lead inductance. TI recommends the current rating be
at least 10% higher than the average transistor current. The power rating is then verified by calculating the power
loss given the RMS transistor current and the N-channel FET on-resistance (RDS-ON).
When PWM dimming, the controller requires another MOSFET (Q2) placed in series (or parallel for a buck
regulator) with the LED load. This MOSFET should have a voltage rating greater than the output voltage (VO)
and a current rating at least 10% higher than the nominal LED current (ILED) . The power rating is simply RDS-ON
multiplied by ILED, assuming 100% dimming duty cycle (continuous operation) occurs.
For most applications, choose an N-channel FET that minimizes total gate charge (Qg) when fSW is high. It that is
not possible. minimize the on-resistance RDS(on) to minimize the dominant power losses in the system.
Frequently, higher current N-channel FETs in larger packages yield better thermal performance.
9.1.6 Re-Circulating Diode
The controller requires a recirculating diode (D1) to carry the inductor current during the off time (tOFF). The most
efficient choice for D1 is a Schottky diode due to low forward voltage drop and near-zero reverse recovery time.
Similar to Q1, TI recommends D1 have a voltage rating at least 15% higher than the maximum transistor voltage
to ensure safe operation during the ringing of the switch node and a current rating at least 10% higher than the
average diode current. The power rating is verified by calculating the power loss through the diode. This is
accomplished by checking the typical diode forward voltage from the I-V curve on the product data sheet and
multiplying by the average diode current. In general, higher current diodes have a lower forward voltage and
come in better performing packages minimizing both power losses and temperature rise.
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Application Information (continued)
9.1.7 Boost Inrush Current
When configured as a boost converter, there is a phantom power path comprised of the inductor, the output
diode, and the output capacitor. This path causes two things to happen when power is applied:
1. a very large inrush of current to charge the output capacitor
2. the energy stored in the inductor during this inrush collects in the output capacitor, charging it to a higher
potential than the input voltage
Depending on the state of the EN pin, the output capacitor discharges by:
1. EN < 1.3 V: no discharge path (leakage only).
2. EN > 1.3 V, the OVP divider resistor path, if present, and 10 µA into each of the HSP & HSN pins.
In applications using the OVP divider and with EN > 1.3 V, the output capacitor voltage can charge higher than
VTURN-OFF. In this situation, the FLT pin (LM3423 only) is open and the PWM dimming MOSFET is turned off.
This condition (the system appearing disabled) can persist for an undesirably long time. Possible solutions to this
condition include:
•
•
Add an inrush diode from VIN to the output as shown in Figure 30.
Add an NTC thermistor in series with the input to prevent the inrush from overcharging the output capacitor
too high.
•
•
Use a current limited source supply.
Raise the OVP threshold.
Boost Inrush Diode
L1
D1
VIN
VO
Q1
Figure 30. Boost Topology with Inrush Diode
9.1.8 Switching Frequency
An external resistor (RT) connected between the RCT pin and the switch node (where D1, Q1, and L1 connect),
in combination with a capacitor (CT) between the RCT and AGND pins, sets the off-time (tOFF) as shown in
Figure 31. For boost and buck-boost topologies, the VIN proportionality ensures a virtually constant switching
frequency (fSW).
For a buck topology, RT and CT are also used to set tOFF, however the iinput voltage (VIN) proportionality does
not ensure a constant switching frequency. Instead, constant ripple operation can be achieved. Changing the
connection of RT in Figure 31 from VSW to VIN provides a constant ripple over varying VIN. Adding a PNP
transistor as shown in Figure 32 provides constant ripple over varying VO.
The switching frequency is defined:
Buck (Constant Ripple vs. VIN)
25 x
VIN - VO
(
RT x CT X VIN
)
fSW
=
(31)
Buck (Constant Ripple vs. VO)
2
(
25 x V x VO - VO
)
IN
fSW
=
2
RT x CT xV
IN
(32)
Boost and Buck-boost
30
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ZHCSK33G –JULY 2008–REVISED JULY 2019
Application Information (continued)
25
fSW
=
RT x CT
(33)
For all topologies, the CT capacitor is recommended to be 1 nF and should be located very close to the LM34xx-
Q1.
V
V
SW
IN
LM3421/23
R
SNS
V
IN
/25
Start t
ON
R
T
RCT
R
T
LM3421/23
C
T
V
IN
/25
Start t
ON
Reset timer
LED-
RCT
C
T
Reset timer
Figure 31. Off-timer Circuitry for Boost and Buck-
boost Regulators
Figure 32. Off-timer Circuitry for Buck Regulators
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9.2 Typical Applications
9.2.1 Basic Topology Schematics
L1
D1
VIN
R
HSN
1
16
15
14
13
12
VIN
HSN
HSP
LM3421
C
R
SNS
FS
R
C
IN
R
HSP
2
3
4
5
6
7
8
EN
FS
R
T
C
CMP
COMP
CSH
RCT
RPD
IS
R
CSH
C
O
R
OV2
ILED
VCC
GATE
PGND
DDRV
C
BYP
C
T
11
AGND
OVP
nDIM
Q1
R
UV2
10
9
R
LIM
DAP
R
UVH
Q2
R
UV1
Q3
PWM
R
C
OV
OV1
Figure 33. Boost Regulator (VIN < VO)
32
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Typical Applications (continued)
VIN
R
HSN
1
16
15
14
13
12
VIN
HSN
HSP
LM3421
C
FS
R
SNS
C
IN
R
HSP
2
3
4
5
6
7
8
EN
R
FS
R
T
C
O
C
CMP
COMP
CSH
RCT
RPD
IS
R
PU
D2
R
CSH
R
OV2
Q2
ILED
DIM
D1
VCC
GATE
PGND
DDRV
L1
C
BYP
Q5
C
T
11
AGND
OVP
nDIM
Q1
R
UV2
10
9
R
LIM
DAP
R
UVH
DIM
C
DIM
R
UV1
Q3
PWM
R
C
OV
OV1
Figure 34. Buck Regulator (VIN > VO)
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Typical Applications (continued)
L1
D1
VIN
ILED
DIM
C
O
Q2
R
HSN
1
16
15
14
13
12
VIN
HSN
HSP
LM3421
C
R
SNS
FS
R
C
R
IN
HSP
2
EN
VIN
FS
R
T
C
CMP
3
4
5
6
7
8
COMP
CSH
RPD
IS
R
CSH
R
Q7
PU
R
OV2
DIM
RCT
VCC
GATE
PGND
DDRV
Q6
Q4
C
BYP
C
C
G
D2
T
11
Q5
AGND
OVP
Q1
VIN
R
UV2
10
9
R
LIM
R
SER
DAP
R
UVH
nDIM
R
UV1
Q3
PWM
R
C
OV
OV1
Figure 35. Buck-Boost Regulator
34
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Typical Applications (continued)
9.2.1.1 Design Requirements
Number of series LEDs: N
Single LED forward voltage: VLED
Single LED dynamic resistance: rLED
Nominal input voltage: VIN
Input voltage range: VIN-MAX, VIN-MIN
Switching frequency: fSW
Current sense voltage: VSNS
Average LED current: ILED
Inductor current ripple: ΔiL-PP
LED current ripple: ΔiLED-PP
Peak current limit: ILIM
Input voltage ripple: ΔvIN-PP
Output OVLO characteristics: VTURN-OFF, VHYSO
Input UVLO characteristics: VTURN-ON, VHYS
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Operating Point
Given the number of series LEDs (N), the forward voltage (VLED) and dynamic resistance (rLED) for a single LED,
solve for the nominal output voltage (VO) and the nominal LED string dynamic resistance (rD):
VO = N x VLED
(34)
rD = N x rLED
(35)
Solve for the ideal nominal duty cycle (D):
Buck:
VO
D =
V
IN
(36)
Boost:
VO - V
IN
D =
VO
(37)
Buck-Boost:
VO
D
=
VO + V
IN
(38)
Using the same equations, find the minimum duty cycle (DMIN) using maximum input voltage (VIN-MAX) and the
maximum duty cycle (DMAX) using the minimum input voltage (VIN-MIN). Also, remember that D' = 1 - D.
9.2.1.2.2 Switching Frequency
Set the switching frequency (fSW) by assuming a CT value of 1 nF and solving for RT:
Buck (Constant Ripple vs. VIN)
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Typical Applications (continued)
25 x VIN - VO
(
fSW x CT X VIN
)
RT =
(39)
Buck (Constant Ripple vs. VO)
2
x (V x VO V )
25
-
IN
O
2
RT
=
fSW x CT x V
IN
(40)
(41)
Boost and Buck-Boost
25
RT =
fSW x CT
9.2.1.2.3 Average LED Current
For all topologies, set the average LED current (ILED) knowing the desired current sense voltage (VSNS) and
solving for RSNS
VSNS
:
RSNS
=
ILED
(42)
If the calculated RSNS is too far from a desired standard value, then VSNS requires adjustment to obtain a
standard value.
Setup the suggested signal current of 100 µA by assuming RCSH = 12.4 kΩ and solving for RHSP
:
I
LED x RCSH x RSNS
RHSP
=
1.24V
(43)
If the calculated RHSP is too far from a desired standard value, then RCSH can be adjusted to obtain a standard
value.
9.2.1.2.4 Inductor Ripple Current
Set the nominal inductor ripple current (ΔiL-PP) by solving for the appropriate inductor (L1):
Buck
(VIN - VO )ìD
L1=
DiL-PP ì fSW
(44)
(45)
Boost and Buck-Boost
V ìD
DiL-PP ì fSW
IN
L1=
To set the worst case inductor ripple current, use VIN-MAX and DMIN when solving for L1.
The minimum allowable inductor RMS current rating (IL-RMS) can be calculated as:
Buck
2
DIL-PP
≈
∆
«
’
1
IL-RMS = ILED
x
1 +
x
÷
ILED
12
◊
(46)
Boost and Buck-Boost
2
DIL-PP x D'
ILED
≈
’
÷
1
x
1 +
x
IL-RMS
=
∆
ILED
D'
12
«
◊
(47)
36
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Typical Applications (continued)
9.2.1.2.5 LED Ripple Current
Set the nominal LED ripple current (ΔiLED-PP), by solving for the output capacitance (CO):
Buck
DiL-PP
8 x fSW x rD x DiLED-PP
CO =
(48)
(49)
Boost and Buck-boost
ILED ìD
CO
=
rD ì DiLED-PP ì fSW
To set the worst case LED ripple current, use DMAX when solving for CO. Remember, when PWM dimming, TI
recommends using a minimum of 40 µF of output capacitance to improve performance.
The minimum allowable RMS output capacitor current rating (ICO-RMS) can be approximated:
Buck
üiLED-PP
ICO- RMS
=
12
Boost and Buck-boost
ICO-RMS = ILED
(50)
(51)
DMAX
x
1-DMAX
9.2.1.2.6 Peak Current Limit
Set the peak current limit (ILIM) by solving for the transistor path sense resistor (RLIM):
245 mV
RLIM
=
ILIM
(52)
9.2.1.2.7 Loop Compensation
Using a simple first order peak current mode control model, neglecting any output capacitor ESR dynamics, the
necessary loop compensation can be determined.
First, the uncompensated loop gain (TU) of the regulator can be approximated:
Buck
1
TU = TU0
x
≈
’
÷
÷
◊
s
∆
1+
∆
w
P1
«
(53)
(54)
Boost and Buck-Boost
≈
’
s
∆ -
÷
÷
◊
1
∆
w
Z1
«
TU = TU0
x
≈
∆
’
÷
÷
◊
s
1+
∆
w
P1
«
Where the pole (ωP1) is approximated:
Buck
1
w =
P1
rD x CO
(55)
37
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Typical Applications (continued)
Boost
2
w =
P1
rD x CO
(56)
(57)
Buck-Boost
1+D
w =
P1
rD x CO
And the RHP zero (ωZ1) is approximated:
Boost
2
Å
rD xD
w =
Z1
L1
(58)
(59)
Buck-Boost
2
Å
rD xD
DxL1
w =
Z1
And the uncompensated DC loop gain (TU0) is approximated:
Buck
500Vx RCSH x RSNS
620V
TU0
=
=
R
HSP x RLIM
I
LED x RLIM
(60)
(61)
Boost
TU0
Buck-Boost
Å
D x 500V x RCSH x RSNS
Å
D x 310V
LED x RLIM
=
=
2 x RHSP x RLIM
I
Å
D x 500Vx RCSH x RSNS
Å
D x 620V
TU0
=
=
( )
1+D x RHSP x RLIM
(
)
1+D xILED x RLIM
(62)
For all topologies, the primary method of compensation is to place a low frequency dominant pole (ωP2), which
ensures that there is ample phase margin at the crossover frequency. This is accomplished by placing a
capacitor (CCMP) from the COMP pin to AGND, which is calculated according to the lower value of the pole and
the RHP zero of the system (shown as a minimizing function):
min(wP1,wZ1)
5 xTU0
wP2
=
(63)
1
CCMP
=
wP2 ì 5ì106
(64)
If analog dimming is used, CCMP should be approximately 4× larger to maintain stability as the LEDs are dimmed
to zero.
A high-frequency compensation pole (ωP3) can be used to attenuate switching noise and provide better gain
margin. Assuming RFS = 10 Ω, CFS is calculated according to the higher value of the pole and the RHP zero of
the system (shown as a maximizing function):
(
)
Z1
wP3 max w ,w x10
=
P1
(65)
(66)
1
CFS
=
10ì wP3
The total system loop gain (T) can then be written as:
38
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ZHCSK33G –JULY 2008–REVISED JULY 2019
Typical Applications (continued)
Buck
1
T = TU0
x
≈
’
÷
÷
◊
≈
∆
«
’
÷
÷
◊
≈
∆
«
’
÷
÷
◊
s
s
s
∆
∆
∆
1+
x 1+
x 1+
∆
w
w
w
P1
P2
P3
«
(67)
(68)
Boost and Buck-Boost
≈
’
÷
÷
◊
s
∆
1-
∆
w
Z1
«
T = TU0
x
≈
’
÷
÷
◊
≈
’
÷
÷
≈
∆
«
’
÷
÷
◊
s
s
s
∆
∆
∆
1+
x 1+
x 1+
∆
∆
«
w
w
w
P1
P2
P3
«
◊
9.2.1.2.8 Input Capacitance
Set the nominal input voltage ripple (ΔvIN-PP) by solving for the required capacitance (CIN):
Buck
ILED x (1 - D) x D
CIN
Boost
CIN
=
DVIN-PP x fSW
(69)
(70)
(71)
DiL-PP
=
8 x DVIN-PP x fSW
Buck-Boost
CIN
ILED x D
=
DVIN-PP x fSW
Use DMAX to set the worst case input voltage ripple, when solving for CIN in a buck-boost regulator and DMID = 0.5
when solving for CIN in a buck regulator.
The minimum allowable RMS input current rating (ICIN-RMS) can be approximated:
Buck
I
CIN- RMS = ILED x DMID x(1-DMID
)
(72)
(73)
(74)
Boost
DiL-PP
ICIN-RMS
=
12
Buck-Boost
ICIN-RMS = ILED
DMAX
x
1-DMAX
9.2.1.2.9 N-channel FET
The N-channel FET voltage rating should be at least 15% higher than the maximum N-channel FET drain-to-
source voltage (VT-MAX):
Buck
V
T- MAX = V
IN- MAX
(75)
39
Boost
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Typical Applications (continued)
VT- MAX = VO
(76)
(77)
Buck-Boost
VT- MAX = VIN- MAX + VO
The current rating should be at least 10% higher than the maximum average N-channel FET current (IT-MAX):
Buck
IT-MAX = DMAX x ILED
(78)
(79)
(80)
Boost and Buck-Boost
DMAX
IT-MAX
=
x ILED
1 - DMAX
Approximate the nominal RMS transistor current (IT-RMS) :
Buck
IT- RMS = ILED x D
9.2.1.2.9.1 Boost and Buck-Boost
I
LED x D
Å
D
IT- RMS
=
(81)
(82)
Given an N-channel FET with on-resistance (RDS-ON), solve for the nominal power dissipation (PT):
P = IT- RMS2 x RDSON
T
9.2.1.2.10 Diode
The Schottky diode voltage rating should be at least 15% higher than the maximum blocking voltage (VRD-MAX):
Buck
VRD-MAX = VIN-MAX
(83)
Boost
VRD-MAX = VO
(84)
(85)
Buck-Boost
VRD-MAX = VIN-MAX + VO
The current rating should be at least 10% higher than the maximum average diode current (ID-MAX):
Buck
ID-MAX = (1 - DMIN) x ILED
(86)
(87)
Boost and Buck-Boost
ID-MAX = ILED
Replace DMAX with D in the ID-MAX equation to solve for the average diode current (ID). Given a diode with forward
voltage (VFD), solve for the nominal power dissipation (PD):
PD = ID xVFD
(88)
40
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Typical Applications (continued)
9.2.1.2.11 Output OVLO
For boost and buck-boost regulators, output OVLO is programmed with the turn-off threshold voltage (VTURN-OFF
)
and the desired hysteresis (VHYSO). To set VHYSO, solve for ROV2
:
VHYSO
ROV2
=
23mA
(89)
To set VTURN-OFF, solve for ROV1
:
Boost
1.24V x ROV2
ROV1
=
VTURN-OFF - 1.24V
(90)
(91)
Buck-Boost
ROV1
1.24V x ROV2
=
VTURN- OFF - 620 mV
A small filter capacitor (COVP = 47 pF) should be added from the OVP pin to ground to reduce coupled switching
noise.
9.2.1.2.12 Input UVLO
For all topologies, input UVLO is programmed with the turnon threshold voltage (VTURN-ON) and the desired
hysteresis (VHYS).
Method 1: If no PWM dimming is required, a two resistor network can be used. To set VHYS, solve for RUV2
:
VHYS
RUV2
=
23 mA
(92)
To set VTURN-ON, solve for RUV1
:
1.24Vx RUV2
RUV1
=
VTURN- ON - 1.24V
(93)
Method 2: If PWM dimming is required, a three resistor network is suggested. To set VTURN-ON, assume RUV2
10 kΩ and solve for RUV1 as in Method 1. To set VHYS, solve for RUVH
=
:
(
)
RUV1 x VHYS - 23 mA x RUV2
RUVH
=
(
)
23 mA x RUV1 + RUV2
(94)
9.2.1.2.13 PWM Dimming Method
PWM dimming can be performed several ways:
Method 1: Connect the dimming MOSFET (Q3) with the drain to the nDIM pin and the source to AGND. Apply an
external PWM signal to the gate of QDIM. A pulldown resistor may be necessary to properly turn off Q3.
Method 2: Connect the anode of a Schottky diode to the nDIM pin. Apply an external inverted PWM signal to the
cathode of the same diode.
The DDRV pin should be connected to the gate of the dimFET with or without level-shifting circuitry as described
in the PWM Dimming section. The dimFET should be rated to handle the average LED current and the nominal
output voltage.
9.2.1.2.14 Analog Dimming Method
Analog dimming can be performed several ways:
Method 1: Place a potentiometer in series with the RCSH resistor to dim the LED current from the nominal ILED to
near zero.
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Typical Applications (continued)
Method 2: Connect a controlled current source as detailed in the Analog Dimming section to the CSH pin.
Increasing the current sourced into the CSH node decreases the LEDs from the nominal ILED to zero current in
the same manner as the thermal foldback circuit.
42
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Typical Applications (continued)
9.2.2 LM3421 Buck-Boost Application
L1
10V œ 70V
VIN
D1
R
HSN
1
16
15
14
13
12
VIN
HSN
HSP
LM3421
1A
C
IN
ILED
R
HSP
2
EN
C
O
R
T
C
CMP
3
4
5
6
7
8
COMP
CSH
RPD
IS
R
CSH
C
FS
R
SNS
VIN
R
FS
RCT
VCC
GATE
PGND
DDRV
C
BYP
C
T
11
AGND
OVP
Q1
R
UV2
R
10
9
OV2
R
LIM
DAP
Q2
nDIM
VIN
R
UV1
R
C
OV
OV1
Figure 36. LM3421 Buck-Boost Application
9.2.2.1 Design Requirements
N = 6
VLED = 3.5 V
rLED = 325 mΩ
VIN = 24 V
VIN-MIN = 10 V
VIN-MAX = 70 V
fSW = 500 kHz
VSNS = 100 mV
ILED = 1 A
ΔiL-PP = 700 mA
ΔiLED-PP = 12 mA
ΔvIN-PP = 100 mV
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Typical Applications (continued)
ILIM = 6 A
VTURN-ON = 10 V
VHYS = 3 V
VTURN-OFF = 40 V
VHYSO = 10 V
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Operating Point
Solve for VO and rD:
VO Nx V
=
6x 3.5V 21V
=
=
LED
(95)
(96)
rD N x r
=
6 x 325 mW 1.95W
=
=
LED
Solve for D, D', DMAX, and DMIN
:
VO
21V
21V + 24V
D =
=
= 0.467
VO +V
IN
(97)
(98)
D' 1- D 1- 0.467 0.533
= = =
VO
21V
=
DMIN
=
= 0.231
VO + VIN-MAX
21V + 70V
(99)
VO
21V
DMAX
=
=
= 0.677
VO + V
21V +10V
IN-MIN
(100)
9.2.2.2.2 Switching Frequency
Assume CT = 1 nF and solve for RT:
25
25
=
RT =
= 50 kW
fSW x CT
500 kHz x 1 nF
(101)
The closest standard resistor is 49.9 kΩ; therefore, fSW is:
25
25
=
fSW
=
= 501 kHz
RT x CT
49.9 kW x 1 nF
(102)
(103)
The chosen component from step 2 is:
CT = 1 nF
RT = 49.9 kW
9.2.2.2.3 Average LED Current
Solve for RSNS
:
V
100 mV
1A
SNS
RSNS
0.1W
=
=
=
ILED
(104)
Assume RCSH = 12.4 kΩ and solve for RHSP
:
I
LED xRCSH x RSNS
1Ax12.4 kW x 0.1W
1.24V
RHSP
=
=
=1.0 kW
1.24V
(105)
44
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ZHCSK33G –JULY 2008–REVISED JULY 2019
Typical Applications (continued)
The closest standard resistor for RSNS is actually 0.1 Ω and for RHSP is actually 1 kΩ; therefore, ILED is:
1.24Vx RHSP
1.24V x1.0 kW
0.1W x12.4 kW
ILED
=
=
=1.0A
RSNS x RCSH
(106)
(107)
The chosen components from step 3 are:
RSNS 0.1W
=
RCSH 12.4 kW
=
RHSP
R
1kW
=
=
HSN
9.2.2.2.4 Inductor Ripple Current
Solve for L1:
V x D
24Vx0.467
IN
32 mH
L1=
=
=
DiL-PP x fSW 700 mA x501kHz
(108)
(109)
The closest standard inductor is 33 µH; therefore, ΔiL-PP is:
V x D
24Vx 0.467
L1x fSW 33 mHx501 kHz
IN
678 mA
=
DiL- PP
=
=
Determine minimum allowable RMS current rating:
≈
∆
∆
«
Å’2
DiL-PP x D
ILED
I
1
LED x 1+
÷
x
IL-RMS
=
=
÷
Å
12
D
◊
2
678 mA x 0.533
1
≈
’
1A
1.89A
x
=
x 1+
∆
÷
IL-RMS
∆
÷
12
1A
0.533
«
◊
(110)
(111)
The chosen component from step 4 is:
L1= 33 mH
9.2.2.2.5 Output Capacitance
Solve for CO:
ILED x D
CO =
rD x DiLED-PP x fSW
1A x 0.467
=
= 39.8 mF
CO
1.95W x 12 mA x501 kHz
(112)
The closest capacitance totals 40 µF; therefore, ΔiLED-PP is:
ILED x D
DiLED-PP
=
rD x CO x fSW
1A x 0.467
DiLED-PP
12 mA
=
=
1.95W x
x 501 kHz
40 mF
(113)
Determine minimum allowable RMS current rating:
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Typical Applications (continued)
DMAX
0.677
x
x
ICO-RMS =ILED
=1A
=1.45A
1- DMAX
1- 0.677
(114)
(115)
The chosen components from step 5 are:
CO = 4 x 10 mF
9.2.2.2.6 Peak Current Limit
Solve for RLIM
:
245 mV 245 mV
=
RLIM
=
= 0.041W
ILIM
6A
(116)
The closest standard resistor is 0.04 Ω; therefore, ILIM is:
245 mV 245 mV
=
ILIM
=
= 6.13A
RLIM
0.04W
(117)
(118)
The chosen component from step 6 is:
RLIM = 0.04W
9.2.2.2.7 Loop Compensation
ωP1 is approximated:
rad
sec
1+D
1.467
w =
=
=19k
P1
1.95W x 40 mF
rD xCO
(119)
(120)
ωZ1 is approximated:
2
1.95W x0.5332
DxL1 0.467x 33mH
rad
sec
Å
rD x D
w =
=
= 36k
Z1
TU0 is approximated:
Å
D x 620V
0.533x620V
1.467x1A x 0.04W
TU0 =
=
= 5630
(
)
1 D xILED x RLIM
+
(121)
To ensure stability, calculate ωP2:
rad
sec
19k
min(wP1, wZ1)
wP1
rad
sec
=
=
= 0.675
wP2
=
5 x TU0
5 x 5630 5 x 5630
(122)
(123)
Solve for CCMP
:
1
1
CCMP
=
=
= 0.3 mF
wP2 ì5ì106 W
rad
0.675
ì5ì106 W
sec
To attenuate switching noise, calculate ωP3:
w
w
P3 = (max wP1, wZ1) x 10 = wZ1 x 10
rad
sec
rad
sec
x 10 = 360k
P3 = 36k
(124)
Assume RFS = 10 Ω and solve for CFS
:
46
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ZHCSK33G –JULY 2008–REVISED JULY 2019
Typical Applications (continued)
1
1
CFS =
=
= 0.28 mF
rad
10W
x w
P3
10W x
360k
sec
(125)
(126)
The chosen components from step 7 are:
CCMP = 0.33mF
RFS =10W
CFS = 0.27mF
9.2.2.2.8 Input Capacitance
Solve for the minimum CIN:
ILED x D
1A x 0.467
CIN =
=
= 9.27mF
DvIN-PP x fSW
100 mV x 504kHz
(127)
To minimize power supply interaction a 200% larger capacitance of approximately 20 µF is used, therefore the
actual ΔvIN-PP is much lower. Because high voltage ceramic capacitor selection is limited, four 4.7-µF X7R
capacitors are chosen.
Determine minimum allowable RMS current rating:
DMAX
0.677
x
x
IIN-RMS =ILED
=1A
=1.45A
1- DMAX
1- 0.677
(128)
(129)
The chosen components from step 8 are:
CIN = 4 x 4.7 mF
9.2.2.2.9 N-channel FET
Determine minimum Q1 voltage rating and current rating:
VT-MAX
V
V
70V 21V 91V
= + =
=
+
IN- MAX
O
(130)
(131)
0.677
IT-MAX
x1A 2.1A
=
=
1- 0.677
A 100-V N-channel FET is chosen with a current rating of 32 A due to the low RDS-ON = 50 mΩ. Determine IT-RMS
and PT:
ILED
1A
IT-RMS
D
0.467 1.28A
x
=
x
=
=
Å
D
0.533
(132)
(133)
PT
I
T- RMS
2 x RDSON 1.28A2 x 50 mW 82 mW
=
=
=
The chosen component from step 9 is:
Q1 ç 32A, 100V, DPAK
(134)
9.2.2.2.10 Diode
Determine minimum D1 voltage rating and current rating:
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Typical Applications (continued)
VRD-MAX = VIN-MAX + VO = 70V +21V = 91V
(135)
(136)
ID-MAX
I
1A
=
=
LED
A 100-V diode is chosen with a current rating of 12 A and VDF = 600 mV. Determine PD:
I x V 1A x 600 mV 600 mW
P
=
=
FD
=
D
D
(137)
(138)
The chosen component from step 10 is:
D1 ç 12A, 100V, DPAK
9.2.2.2.11 Input UVLO
Solve for RUV2
:
VHYS
3V
RUV2
=
=
23 A 23 A
=130kW
m
m
(139)
(140)
The closest standard resistor is 130 kΩ; therefore, VHYS is:
VHYS
R
x23mA 130 kW x23 mA 2.99V
=
=
=
UV2
Solve for RUV1
:
1.24Vx RUV2
VTURN- ON -1.24V
1.24Vx130kW
10V -1.24V
RUV1
=
=
= 18.4 kW
(141)
The closest standard resistor is 18.2 kΩ, making VTURN-ON
:
(
1.24Vx RUV1+ RUV2
)
VTURN-ON
=
=
RUV1
(
)
1.24V x 18.2kW +130kW
VTURN-ON
= 10.1V
18.2kW
(142)
(143)
The chosen components from step 11 are:
RUV1 18.2kW
=
RUV2 130 kW
=
9.2.2.2.12 Output OVLO
Solve for ROV2
:
VHYSO
10V
ROV2
=
=
23 A 23 A
= 435kW
m
m
(144)
(145)
The closest standard resistor is 432 kΩ; therefore, VHYSO is:
m
m
VHYSO
R
x 23 A 432 kW x 23 A 9.94V
=
=
=
OV2
Solve for ROV1
:
1.24Vx ROV2
VTURN-OFF - 0.62V
1.24Vx 432kW
ROV1
=
=
= 13.6kW
40V - 0.62V
(146)
The closest standard resistor is 13.7 kΩ, making VTURN-OFF
:
48
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Typical Applications (continued)
(
1.24Vx 0.5 xROV1+ ROV2
)
VTURN-OFF
=
=
ROV1
(
)
13.7 kW +432kW
1.24Vx
0.5 x
VTURN-OFF
= 39.7V
13.7 kW
(147)
(148)
The chosen components from step 12 are:
ROV1 = 13.7 kW
ROV2 = 432 kW
Table 2. Bill of Materials
QTY
1
PART ID
LM3421
CBYP
CCMP
CFS
PART VALUE
MANUFACTURER
PART NUMBER
Buck-boost controller
2.2-µF X7R 10% 16V
0.33-µF X7R 10% 25V
0.27-µF X7R 10% 25V
4.7-µF X7R 10% 100V
10-µF X7R 10% 50V
47-pF COG/NPO 5% 50V
1000-pF COG/NPO 5% 50V
Schottky 100 V 12 A
33 µH 20% 6.3 A
NMOS 100 V 32 A
PNP 150 V 600 mA
12.4 kΩ 1%
TI
LM3421MH
1
MURATA
MURATA
MURATA
TDK
GRM21BR71C225KA12L
GRM21BR71E334KA01L
GRM21BR71E274KA01L
C5750X7R2A475K
C4532X7R1H106K
08055A470JAT2A
1
1
4
CIN
4
CO
TDK
1
COV
AVX
1
CT
MURATA
VISHAY
COILCRAFT
FAIRCHILD
FAIRCHILD
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
GRM2165C1H102JA01D
12CWQ10FNPBF
1
D1
1
L1
MSS1278-333MLB
FDD3682
1
Q1
1
Q2
MMBT5401
1
RCSH
RFS
CRCW080512K4FKEA
CRCW080510R0FKEA
CRCW08051K00FKEA
WSL2512R0400FEA
CRCW080513K7FKEA
CRCW0805432KFKEA
WSL2512R1000FEA
CRCW080549K9FKEA
CRCW080518K2FKEA
CRCW0805130KFKEA
1
10 Ω 1%
2
RHSP, RHSN
RLIM
ROV1
ROV2
RSNS
RT
1 kΩ 1%
1
0.04 Ω 1% 1 W
1
13.7 kΩ 1%
1
432 kΩ 1%
1
0.1 Ω 1% 1 W
1
49.9 kΩ 1%
1
RUV1
RUV2
18.2 kΩ 1%
1
130 kΩ 1%
Copyright © 2008–2019, Texas Instruments Incorporated
49
LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
9.2.2.3 Application Curve
VOUT = 21 V
Figure 37. Sample Buck-Boost Efficiency vs Input Voltage.
50
Copyright © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
9.2.3 LM3421 BOOST Application
D2
L1
D1
8V œ 28V
VIN
R
HSN
1
16
VIN
HSN
HSP
LM3421
C
R
SNS
FS
R
C
IN
R
HSP
2
3
4
5
6
7
8
15
14
13
12
EN
FS
R
T
C
CMP
COMP
CSH
RCT
RPD
IS
R
CSH
1A
C
O
ILED
VCC
GATE
PGND
DDRV
C
BYP
C
T
11
AGND
OVP
nDIM
Q1
R
UV2
10
9
R
LIM
DAP
R
UVH
Q2
R
OV2
R
UV1
Q3
PWM
R
C
OV
OV1
Figure 38. LM3421 BOOST Application
9.2.3.1 Design Requirements
•
•
•
•
Input: 8 V to 28 V
Output: 9 LEDs at 1 A
PWM Dimming up to 30kHz
Switching Frequency: 700-kHz
Copyright © 2008–2019, Texas Instruments Incorporated
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ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
9.2.3.2 Detailed Design Procedure
Table 3. Bill of Materials
QTY
1
PART ID
LM3421
CBYP
CCMP
CFS
PART VALUE
MANUFACTURER
PART NUMBER
Boost controller
2.2-µF X7R 10% 16 V
0.1-µF X7R 10% 25 V
DNP
TI
LM3421MH
1
MURATA
MURATA
GRM21BR71C225KA12L
GRM21BR71E104KA01L
1
0
4
CIN
4.7-µF X7R 10% 100 V
10-µF X7R 10% 50 V
47-pF COG/NPO 5% 50 V
1000-pF COG/NPO 5% 50 V
Schottky 60 V 5 A
33-µH 20% 6.3 A
NMOS 60 V 8 A
NMOS 60 V 115 mA
12.4 kΩ 1%
TDK
C5750X7R2A475K
C4532X7R1H106K
08055A470JAT2A
4
CO
TDK
1
COV
AVX
1
CT
MURATA
COMCHIP
COILCRAFT
VISHAY
ON-SEMI
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
GRM2165C1H102JA01D
CDBC560-G
2
D1, D2
L1
1
MSS1278-333MLB
SI4436DY
2
Q1, Q2
Q3
1
2N7002ET1G
2
RCSH, ROV1
RFS
RHSP, RHSN
RLIM
CRCW080512K4FKEA
CRCW08050000Z0EA
CRCW08051K00FKEA
WSL2512R0600FEA
CRCW0805499KFKEA
WSL2512R1000FEA
CRCW080510K0FKEA
CRCW080535K7FKEA
CRCW08051K82FKEA
CRCW080517K8FKEA
1
0 Ω 1%
2
1 kΩ 1%
1
0.06 Ω 1% 1 W
499 kΩ 1%
1
ROV2
RSNS
RUV2
RT
1
0.1 Ω 1% 1 W
1
10 kΩ 1%
1
35.7 kΩ 1%
1
RUV1
RUVH
1.82 kΩ 1%
1
17.8 kΩ 1%
52
Copyright © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
9.2.4 LM3421 Buck-Boost Application
L1
D1
10V ꢀ0V
VIN
2A
R
HSN
1
16
15
14
1ꢀ
12
ILED
VIN
HSN
HSP
LM3421
C
O
C
R
IN
HSP
2
EN
Q2
R
DIM
R
T
C
CMP
ꢀ
4
5
6
7
8
C
FS
COMP
CSH
RPD
IS
SNS
VIN
R
R
CSH
POT
R
FS
R
F
R
Q7
PU
C
F
RCT
VCC
GATE
PGND
DDRV
R
OV2
C
DIM
BYP
C
T
11
Q6
Q4
AGND
OVP
Q1
R
C
B
D2
UV2
10
9
Q5
R
LIM
R
SER
VIN
DAP
R
UVH
nDIM
R
UV1
Qꢀ
PWM
C
R
OV1
OV
Figure 39. LM3421 Buck-Boost Application
9.2.4.1 Design Requirements
•
•
•
•
•
Input: 10 V to 30 V
Output: 4 LEDs at 2 A
PWM Dimming: up to 10 kHz
Analog Dimming
Switching Frequency: 600-kHz
Copyright © 2008–2019, Texas Instruments Incorporated
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LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
9.2.4.2 Detailed Design Procedure
Table 4. Bill of Materials
QTY
1
1
1
3
1
0
4
4
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
PART ID
LM3421
CB
PART VALUE
MANUFACTURER
PART NUMBER
Buck-boost controller
100-pF COG/NPO 5% 50 V
2.2-µF X7R 10% 16 V
1-µF X7R 10% 25 V
0.1-µF X7R 10% 25 V
DNP
TI
LM3421MH
MURATA
MURATA
MURATA
MURATA
GRM2165C1H101JA01D
GRM21BR71C225KA12L
GRM21BR71E105KA01L
GRM21BR71E104KA01L
CBYP
CCMP, CREF, CSS
CF
CFS
CIN
6.8-µF X7R 10% 50 V
10-µF X7R 10% 50 V
47-pF COG/NPO 5% 50 V
1000-pF COG/NPO 5% 50 V
Schottky 100 V 12 A
Zener 10 V 500 mA
22 µH 20% 7.2 A
NMOS 60 V 8 A
NMOS 60 V 260 mA
PNP 40 V 200 mA
PNP 150 V 600 mA
NPN 300 V 600 mA
NPN 40 V 200 mA
12.4 kΩ 1%
TDK
C5750X7R1H685K
C4532X7R1H106K
08055A470JAT2A
GRM2165C1H102JA01D
12CWQ10FNPBF
BZX84C10LT1G
CO
TDK
COV
AVX
CT
MURATA
VISHAY
ON-SEMI
COILCRAFT
VISHAY
ON-SEMI
FAIRCHILD
FAIRCHILD
FAIRCHILD
FAIRCHILD
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
BOURNS
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
D1
D2
L1
MSS1278-223MLB
SI4436DY
Q1, Q2
Q3
2N7002ET1G
Q4
MMBT5087
Q5
MMBT5401
Q6
MMBTA42
Q7
MMBT6428
RCSH
RF
CRCW080512K4FKEA
CRCW080510R0FKEA
CRCW08050000Z0EA
CRCW080510K0FKEA
CRCW08051K00FKEA
WSL2512R0400FEA
CRCW080518K2FKEA
CRCW0805499KFKEA
3352P-1-105
10 Ω 1%
RFS
0 Ω 1%
RUV2
RHSP, RHSN
RLIM
ROV1
ROV2
RPOT
RPU
10 kΩ 1%
1 kΩ 1%
0.04 Ω 1% 1 W
18.2 kΩ 1%
499 kΩ 1%
1-MΩ potentiometer
4.99 kΩ 1%
CRCW08054K99FKEA
CRCW0805499RFKEA
WSL2512R0500FEA
CRCW080541K2FKEA
CRCW08051K43FKEA
CRCW080517K4FKEA
RSER
RSNS
RT
499 Ω 1%
0.05 Ω 1% 1 W
41.2 kΩ 1%
RUV1
RUVH
1.43 kΩ 1%
17.4 kΩ 1%
54
Copyright © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
9.2.5 LM3423 Boost Application
D2
L1
D1
18V œ 38V
VIN
R
HSN
1
2
20
VCC
VIN
HSN
HSP
LM3423
External
Enable
C
FS
R
SNS
C
IN
R
HSP
19
18
17
16
EN
VREF
R
R
FS
R
T
Q4
Q5
C
CMP
3
COMP
CSH
RCT
AGND
OVP
nDIM
FLT
RPD
D3
RPD
PU
R
MAX
Q2
Q7
R
4
IS
VCC
R
ADJ
R
CSH
BIAS2
5
Q6
VCC
C
DIM
C
BYP
C
T
6
15
GATE
PGND
DDRV
DPOL
LRDY
Q1
R
SER
C
O
R
UV2
7
14
13
12
11
R
LIM
8
R
UVH
700 mA
ILED
9
DAP
R
UV1
10
TIMR
R
OV2
Q3
PWM
C
OV
R
OV1
RPD
Figure 40. LM3423 Boost Application
9.2.5.1 Design Requirements
•
•
•
•
•
•
Input: 18 V to 38 V
Output: 12 LEDs at 700 mA
High-Side PWM Dimming: up to 30 kHz
Dimming: Analog
Zero Current Shutdown
Switching Frequency: 700-kHz
Copyright © 2008–2019, Texas Instruments Incorporated
55
LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
9.2.5.2 Detailed Design Procedure
Table 5. Bill of Materials
QTY
1
1
1
1
4
4
1
1
2
1
1
1
1
1
1
1
1
1
1
2
1
3
1
1
1
1
1
1
1
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
LM3423
Boost controller
2.2-µF X7R 10% 16 V
1-µF X7R 10% 25 V
0.1-µF X7R 10% 25 V
4.7-µF X7R 10% 100 V
10-µF X7R 10% 50 V
47-pF COG/NPO 5% 50 V
1000-pF COG/NPO 5% 50 V
Schottky 60 V 5 A
Zener 10 V 500 mA
47 µH 20% 5.3 A
NMOS 60 V 8 A
PMOS 70 V 5.7 A
NMOS 60 V 260 mA
Dual PNP 40 V 200 mA
NPN 300 V 600 mA
NPN 40 V 200 mA
100-kΩ potentiometer
17.4 kΩ 1%
TI
LM3423MH
CBYP
MURATA
MURATA
MURATA
TDK
GRM21BR71C225KA12L
GRM21BR71E105KA01L
GRM21BR71E104KA01L
C5750X7R2A475K
C4532X7R1H106K
08055A470JAT2A
GRM2165C1H102JA01D
CDBC560-G
CCMP
CFS
CIN
CO
TDK
COV
AVX
CT
MURATA
COMCHIP
ON-SEMI
COILCRAFT
VISHAY
ZETEX
D1, D2
D3
BZX84C10LT1G
L1
MSS1278-473MLB
SI4436DY
Q1
Q2
ZXMP7A17K
Q3
ON-SEMI
FAIRCHILD
FAIRCHILD
FAIRCHILD
BOURNS
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
2N7002ET1G
Q4, Q5 (dual pack)
FFB3906
Q6
MMBTA42
Q7
MMBT3904
RADJ
3352P-1-104
RBIAS2
RCSH, ROV1
RFS
CRCW080517K4FKEA
CRCW080512K4FKEA
CRCW080510R0FKEA
CRCW08051K00FKEA
WSL2512R0600FEA
CRCW0805499KFKEA
WSL2512R1500FEA
CRCW080535K7FKEA
CRCW08051K43FKEA
CRCW080510K0FKEA
CRCW080516K9FKEA
12.4 kΩ 1%
10 Ω 1%
RHSP, RHSN, RMAX
RLIM
1 kΩ 1%
0.06 Ω 1% 1W
ROV2
499 kΩ 1%
RSNS
0.15 Ω 1% 1W
RT
35.7 kΩ 1%
RUV1
1.43 kΩ 1%
RUV2
10 kΩ 1%
RUVH
16.9 kΩ 1%
56
Copyright © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
9.2.6 LM3421 Buck-Boost Application
L1
D1
10V œ 70V
VIN
R
T
C
IN
R
HSN
RCT
External
Enable
1
2
3
4
5
6
7
8
16
15
14
13
12
500 mA
VIN
HSN
HSP
LM3421
C
O
ILED
Q9
R
HSP
EN
C
EN
Q2
R
DIM
COMP
CSH
RCT
AGND
OVP
nDIM
RPD
IS
C
R
CMP
CSH
C
FS
SNS
VIN
C
Q8
CSH
R
FS
R
F
VCC
GATE
PGND
DDRV
RCT
C
BYP
C
T
Q7
R
PU
C
F
11
10
9
Q1
R
OV2
DIM
R
UV2
Q6
Q4
DAP
C
D2
B
R
SER
R
UVH
Q5
VIN
Q3
R
UV1
PWM
R
OV1
C
OV
Figure 41. LM3421 Buck-Boost Application
9.2.6.1 Design Requirements
•
•
•
•
•
•
Input: 10 V to 70 V
Output: 6 LEDs at 500 mA
PWM Dimming up to 10 kHz
Slow Fade Out
MOSFET RDS-ON Sensing
700-kHz Switching Frequency
Copyright © 2008–2019, Texas Instruments Incorporated
57
LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
9.2.6.2 Detailed Design Procedure
Table 6. Bill of Materials
QTY
1
1
1
1
1
0
4
4
1
1
1
1
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
PART ID
LM3421
CB
PART VALUE
MANUFACTURER
PART NUMBER
Buck-boost controller
100-pF COG/NPO 5% 50 V
2.2-µF X7R 10% 16 V
1-µF X7R 10% 25 V
0.1-µF X7R 10% 25 V
DNP
TI
LM3421MH
MURATA
MURATA
MURATA
MURATA
GRM2165C1H101JA01D
GRM21BR71C225KA12L
GRM21BR71E105KA01L
GRM21BR71E104KA01L
CBYP
CCMP
CF
CFS
CIN
4.7-µF X7R 10% 100 V
10-µF X7R 10% 50 V
47-pF COG/NPO 5% 50 V
1000-pF COG/NPO 5% 50 V
Schottky 100 V 12 A
Zener 10 V 500 mA
68 µH 20% 4.3 A
NMOS 100 V 32 A
NMOS 60 V 260 mA
PNP 40 V 200 mA
PNP 150 V 600 mA
NPN 300 V 600 mA
NPN 40 V 200 mA
12.4 kΩ 1%
TDK
C5750X7R2A475K
C4532X7R1H106K
08055A470JAT2A
GRM2165C1H102JA01D
12CWQ10FNPBF
BZX84C10LT1G
CO
TDK
COV
AVX
CT
MURATA
VISHAY
ON-SEMI
COILCRAFT
FAIRCHILD
ON-SEMI
FAIRCHILD
FAIRCHILD
FAIRCHILD
FAIRCHILD
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
D1
D2
L1
MSS1278-683MLB
FDD3682
Q1, Q2
Q3
2N7002ET1G
Q4, Q8
Q5
MMBT5087
MMBT5401
Q6
MMBTA42
Q7, Q9
RCSH
RFS
MMBT6428
CRCW080512K4FKEA
CRCW08050000Z0EA
CRCW080510K0FKEA
CRCW08051K00FKEA
CRCW080515K8FKEA
CRCW0805499KFKEA
CRCW08054K99FKEA
CRCW0805499RFKEA
WSL2512R2000FEA
CRCW080535K7FKEA
CRCW08051K43FKEA
CRCW080517K4FKEA
0 Ω 1%
RUV2
RHSP, RHSN
ROV1
ROV2
RPU
10 kΩ 1%
1 kΩ 1%
15.8 kΩ 1%
499 kΩ 1%
4.99 kΩ 1%
RSER
RSNS
RT
499 Ω 1%
0.2 Ω 1% 1 W
35.7 kΩ 1%
RUV1
RUVH
1.43 kΩ 1%
17.4 kΩ 1%
58
Copyright © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
9.2.7 LM3423 Buck Application
15V œ 50V
VIN
R
HSN
1
20
19
18
17
16
VIN
HSN
HSP
LM3423
C
R
SNS
FS
External
Enable
C
R
IN
HSP
2
3
EN
R
FS
R
T
C
O
C
CMP
COMP
CSH
RCT
AGND
OVP
nDIM
FLT
RPD
RPD
R
D2
PU
R
CSH
4
R
OV2
Q2
IS
1.25A
ILED
D1
5
VCC
L1
C
BYP
Q4
C
T
6
15
GATE
PGND
DDRV
DPOL
LRDY
Q1
C
DIM
7
14
13
12
11
R
LIM
R
UV2
R
UVH
8
PWM
Q3
R
UV1
VIN
9
DAP
R
PU2
10
TIMR
LED
STATUS
LIGHT
R
C
OV1
OV
RPD
Figure 42. LM3423 Buck Application
9.2.7.1 Design Requirements
•
•
•
•
•
•
Input: 15 V to 50 V
Output: 3 LEDs at 1.25 A
PWM Dimming up to 50 kHz
LED Status Indicator
Zero Current Shutdown
700-kHz Switching Frequency
Copyright © 2008–2019, Texas Instruments Incorporated
59
LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
9.2.7.2 Detailed Design Procedure
Table 7. Bill of Materials
QTY
1
PART ID
LM3423
CBYP
CCMP, CDIM
CFS
PART VALUE
MANUFACTURER
PART NUMBER
Buck controller
2.2-µF X7R 10% 16 V
0.1 µF X7R 10% 25 V
DNP
TI
LM3423MH
1
MURATA
MURATA
GRM21BR71C225KA12L
GRM21BR71E104KA01L
2
0
4
CIN
4.7-µF X7R 10% 100 V
DNP
TDK
C5750X7R2A475K
0
CO
1
COV
47-pF COG/NPO 5% 50 V
1000-pF COG/NPO 5% 50 V
Schottky 100 V 12 A
Zener 10 V 500 mA
22 µH 20% 7.3 A
NMOS 60 V 8 A
PMOS 30 V 6.2 A
NMOS 60 V 115 mA
PNP 150 V 600 mA
12.4 kΩ 1%
AVX
08055A470JAT2A
GRM2165C1H102JA01D
12CWQ10FNPBF
BZX84C10LT1G
1
CT
MURATA
VISHAY
ON-SEMI
COILCRAFT
VISHAY
VISHAY
ON-SEMI
FAIRCHILD
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
1
D1
1
D2
1
L1
MSS1278-223MLB
SI4436DY
1
Q1
1
Q2
SI3483DV
1
Q3
2N7002ET1G
1
Q4
MMBT5401
1
RCSH
RFS
CRCW080512K4FKEA
CRCW08050000OZEA
CRCW08051K00FKEA
WSL2512R0400FEA
CRCW080521K5FKEA
CRCW0805499KFKEA
CRCW0805100KFKEA
CRCW080535K7FKEA
WSL2512R0800FEA
CRCW080511K5FKEA
1
0 Ω 1%
2
RHSP, RHSN
RLIM
1 kΩ 1%
1
0.04 Ω 1% 1 W
21.5 kΩ 1%
1
ROV1
ROV2
RPU, RPU2, RUV2
RT
1
499 kΩ 1%
3
100 kΩ 1%
1
35.7 kΩ 1%
1
RSNS
RUV1
0.08 Ω 1% 1 W
11.5 kΩ 1%
1
60
Copyright © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
9.2.8 LM3423 Buck-Boost Application
L1
D1
15V œ 60V
VIN
Q2
R
D2
PU
R
HSN
1
2
20
19
18
17
16
VIN
HSN
HSP
2.5A
LM3423
C
O
ILED
C
R
IN
HSP
External
Enable
EN
R
T
C
CMP
3
COMP
CSH
RCT
AGND
OVP
nDIM
FLT
RPD
RPD
R
CSH
4
C
FS
R
SNS
IS
VIN
R
FS
5
VCC
R
FLT
C
BYP
C
T
6
15
GATE
PGND
DDRV
DPOL
LRDY
Q1
R
OV2
7
14
13
12
11
R
UV2
Q5
VIN
8
R
UV1
9
DAP
10
TIMR
C
TMR
R
OV1
C
OV
RPD
Figure 43. LM3423 Buck-Boost Application
9.2.8.1 Design Requirements
•
•
•
•
•
Input: 15 V to 60 V
Output: 8 LEDs at 2.5 A
Fault Input Disconnect
Zero Current Shutdown
500-kHz Switching Frequency
Copyright © 2008–2019, Texas Instruments Incorporated
61
LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
9.2.8.2 Detailed Design Procedure
Table 8. Bill of Materials
QTY
1
PART ID
LM3423
CBYP
CCMP
CFS
PART VALUE
MANUFACTURER
PART NUMBER
Buck-boost controller
2.2-µF X7R 10% 16 V
0.33-µF X7R 10% 25 V
0.1-µF X7R 10% 25 V
4.7-µF X7R 10% 100 V
10-µF X7R 10% 50 V
47-pF COG/NPO 5% 50 V
1000-pF COG/NPO 5% 50 V
220-pF COG/NPO 5% 50 V
Schottky 100 V 12 A
Zener 10 V 500 mA
22 µH 20% 7.2 A
NMOS 100 V 32 A
PMOS 70 V 5.7 A
PNP 150 V 600 mA
12.4 kΩ 1%
TI
LM3423MH
1
MURATA
MURATA
MURATA
TDK
GRM21BR71C225KA12L
GRM21BR71E334KA01L
GRM21BR71E104KA01L
C5750X7R2A475K
C4532X7R1H106K
08055A470JAT2A
1
1
4
CIN
4
CO
TDK
1
COV
AVX
1
CT
MURATA
MURATA
VISHAY
ON-SEMI
COILCRAFT
FAIRCHILD
ZETEX
GRM2165C1H102JA01D
GRM2165C1H221JA01D
12CWQ10FNPBF
1
CTMR
D1
1
1
D2
BZX84C10LT1G
1
L1
MSS1278-223MLB
FDD3682
1
Q1
1
Q2
ZXMP7A17K
1
Q5
FAIRCHILD
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
MMBT5401
2
RCSH, ROV1
RFS
CRCW080512K4FKEA
CRCW080510R0FKEA
CRCW0805100KFKEA
CRCW08051K00FKEA
WSL2512R0400FEA
CRCW080515K8FKEA
CRCW0805499KFKEA
CRCW080549K9FKEA
CRCW080513K7FKEA
CRCW0805150KFKEA
1
10 Ω 1%
2
RFLT, RPU2
RHSP, RHSN
RLIM, RSNS
ROV1
ROV2
RT
100 kΩ 1%
2
1 kΩ 1%
2
0.04 Ω 1% 1 W
1
15.8 kΩ 1%
1
499 kΩ 1%
1
49.9 kΩ 1%
1
RUV1
RUV2
13.7 kΩ 1%
1
150 kΩ 1%
62
Copyright © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
9.2.9 LM3421 SEPIC Application
L1
D1
9V œ 36V
VIN
C
SEP
L2
R
HSN
1
16
15
14
13
12
VIN
HSN
HSP
LM3421
C
FS
R
SNS
C
R
IN
HSP
2
3
4
5
6
7
8
EN
R
FS
R
T
C
CMP
COMP
CSH
RCT
RPD
IS
R
CSH
750 mA
ILED
C
O
VCC
GATE
PGND
DDRV
C
BYP
C
T
11
AGND
OVP
nDIM
Q1
R
UV2
10
9
R
LIM
DAP
R
UVH
Q2
R
R
OV2
R
UV1
Q3
PWM
C
OV1
OV
Figure 44. LM3421 SEPIC Application
9.2.9.1 Design Procedure
•
•
•
•
Input: 9 V to 36 V
Output: 5 LEDs at 750 mA
PWM Dimming up to 30 kHz
500-kHz Switching Frequency
Copyright © 2008–2019, Texas Instruments Incorporated
63
LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
9.2.9.2 Detailed Design Procedure
Table 9. Bill of Materials
QTY
1
PART ID
LM3421
CBYP
CCMP
CFS
PART VALUE
MANUFACTURER
PART NUMBER
SEPIC controller
2.2-µF X7R 10% 16 V
0.47-µF X7R 10% 25 V
DNP
TI
LM3421MH
1
MURATA
MURATA
GRM21BR71C225KA12L
GRM21BR71E474KA01L
1
0
4
CIN
4.7-µF X7R 10% 100 V
10-µF X7R 10% 50 V
1-µF X7R 10% 100 V
47-pF COG/NPO 5% 50 V
1000-pF COG/NPO 5% 50 V
Schottky 60 V 5 A
68 µH 20% 4.3 A
NMOS 60 V 8 A
NMOS 60 V 115 mA
12.4 kΩ 1%
TDK
C5750X7R2A475K
C4532X7R1H106K
C4532X7R2A105K
08055A470JAT2A
4
CO
TDK
1
CSEP
COV
TDK
1
AVX
1
CT
MURATA
COMCHIP
COILCRAFT
VISHAY
ON-SEMI
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
VISHAY
GRM2165C1H102JA01D
CDBC560-G
1
D1
2
L1, L2
Q1, Q2
Q3
DO3340P-683
2
SI4436DY
1
2N7002ET1G
1
RCSH
RFS
CRCW080512K4FKEA
CRCW08050000OZEA
CRCW0805750RFKEA
WSL2512R0400FEA
CRCW080515K8FKEA
CRCW0805499KFKEA
CRCW080549K9FKEA
WSL2512R1000FEA
CRCW080549K9FKEA
CRCW08051K62FKEA
CRCW080510K0FKEA
CRCW080516K9FKEA
1
0 Ω 1%
2
RHSP, RHSN
RLIM
750 Ω 1%
1
0.04 Ω 1% 1 W
15.8 kΩ 1%
1
ROV1
ROV2
RREF1, RREF2
RSNS
RT
1
499 kΩ 1%
2
49.9 kΩ 1%
1
0.1 Ω 1% 1 W
1
49.9 kΩ 1%
1
RUV1
RUV2
RUVH
1.62 kΩ 1%
1
10 kΩ 1%
1
16.9 kΩ 1%
64
Copyright © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
10 Power Supply Recommendations
10.1 General Recommendations
The device is designed to operate from an input voltage supply range from 4.5 V to 75 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the EVM or PCB, additional
bulk capacitance may be required in addition to the ceramic bypass capacitors.
10.2 Input Supply Current Limit
It is important to set the output current limit of your input supply to an appropriate value to avoid delays in your
converter analysis and optimization. If not set high enough, current limit can be tripped during start-up or when
your converter output power is increased, causing a foldback or shutdown condition. It is a common oversight
when powering up a converter for the first time.
11 Layout
11.1 Layout Guidelines
•
The performance of any switching regulator depends as much upon the layout of the PCB as the component
selection. Following a few simple guidelines allows maximum noise rejection and minimal generation of EMI
within the circuit.
•
Discontinuous currents are the most likely to generate EMI, therefore care should be taken when routing
these paths. The main path for discontinuous current in the LM34xx-Q1 buck regulator contains the input
capacitor (CIN), the recirculating diode (D1), the N-channel MOSFET (Q1), and the sense resistor (RLIM). In
the LM34xx-Q1 boost regulator, the discontinuous current flows through the output capacitor (CO), D1, Q1,
and RLIM. In the buck-boost regulator, both loops are discontinuous and should be carefully layed out. These
loops should be kept as small as possible and the connections between all the components should be short
and thick to minimize parasitic inductance. In particular, the switch node (where L1, D1 and Q1 connect)
should be just large enough to connect the components. To minimize excessive heating, large copper pours
can be placed adjacent to the short current path of the switch node.
•
•
The RT, COMP, CSH, IS, HSP and HSN pins are all high-impedance inputs which couple external noise
easily; therefore, the loops containing these nodes should be minimized whenever possible.
In some applications the LED or LED array can be far away (several inches or more) from the controller or on
a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large
or separated from the rest of the regulator, the output capacitor should be placed close to the LEDs to reduce
the effects of parasitic inductance on the AC impedance of the capacitor.
Copyright © 2008–2019, Texas Instruments Incorporated
65
LM3421, LM3423
ZHCSK33G –JULY 2008–REVISED JULY 2019
www.ti.com.cn
11.2 Layout Example
Note critical paths and component placement:
Minimize power loop containing discontinuous currents
Minimize signal current loops (components close to IC)
ñ
Ground plane under IC for signal routing helps minimize noise coupling
discontinuous switching
frequency currents
VIN
Input
Power
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN
LM3421
HSN
HSP
RPD
IS
GND
EN
COMP
CSH
ILED
RCT
VCC
AGND
OVP
GATE
PGND
DDRV
DAP
PWM
nDIM
STAR GROUND
Power Ground
Figure 45. LM3421 Boost Layout Guideline
66
版权 © 2008–2019, Texas Instruments Incorporated
LM3421, LM3423
www.ti.com.cn
ZHCSK33G –JULY 2008–REVISED JULY 2019
12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件,以及申请样片或购买产品的快速链
接。
表 10. 相关链接
器件
产品文件夹
单击此处
单击此处
单击此处
单击此处
样片与购买
单击此处
单击此处
单击此处
单击此处
技术文档
单击此处
单击此处
单击此处
单击此处
工具与软件
单击此处
单击此处
单击此处
单击此处
支持和社区
单击此处
单击此处
单击此处
单击此处
LM3421
LM3421-Q1
LM3423
LM3423-Q1
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2008–2019, Texas Instruments Incorporated
67
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM3421MH/NOPB
LM3421MHX/NOPB
LM3423MH/NOPB
LM3423MHX/NOPB
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
16
16
20
20
92
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LM3421
MH
ACTIVE
ACTIVE
ACTIVE
PWP
2500 RoHS & Green
73 RoHS & Green
2500 RoHS & Green
SN
SN
SN
LM3421
MH
PWP
LM3423
MH
PWP
LM3423
MH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3421MHX/NOPB
LM3423MHX/NOPB
HTSSOP PWP
HTSSOP PWP
16
20
2500
2500
330.0
330.0
12.4
16.4
6.95
6.95
5.6
7.1
1.6
1.6
8.0
8.0
12.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM3421MHX/NOPB
LM3423MHX/NOPB
HTSSOP
HTSSOP
PWP
PWP
16
20
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM3421MH/NOPB
LM3423MH/NOPB
PWP
PWP
HTSSOP
HTSSOP
16
20
92
73
495
495
8
8
2514.6
2514.6
4.06
4.06
Pack Materials-Page 3
PACKAGE OUTLINE
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
0.19
4.5
4.3
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
4X 0.166 MAX
NOTE 5
2X 1.34 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
3.3
2.7
17
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
3.3
2.7
4214868/A 02/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3.3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
17
SYMM
(3.3)
(5)
NOTE 9
14X (0.65)
8
9
(
0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4214868/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016A
PowerPAD TM HTSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3.3)
17
SYMM
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.69 X 3.69
3.3 X 3.3 (SHOWN)
3.01 X 3.01
0.125
0.15
0.175
2.79 X 2.79
4214868/A 02/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
PWP0020A
MXA20A (Rev C)
www.ti.com
重要声明和免责声明
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