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LM3429, LM3429-Q1

SNVS616H –APRIL 2009–REVISED JULY 2015

LM3429/-Q1 N-Channel Controller for Constant Current LED Drivers

1 Features

3 Description

The LM3429 is a versatile high voltage N-channel

MosFET controller for LED drivers. It can be easily

configured in buck, boost, buck-boost and SEPIC

topologies. This flexibility, along with an input voltage

rating of 75V, makes the LM3429 ideal for

illuminating LEDs in a very diverse, large family of

applications.

1

•

LM3429-Q1 is AEC-Q100 Grade 1 Qualified for

Automotive Applications

•

V_INRange From 4.5 V to 75 V

Adjustable Current Sense Voltage

High-Side Current Sensing

2-Ω, 1-A Peak MosFET Gate Driver

Input Undervoltage Protection

Overvoltage Protection

Adjustable high-side current sense voltage allows for

tight regulation of the LED current with the highest

efficiency possible. The LM3429 uses Predictive Off-

time (PRO) control, which is a combination of peak

current-mode control and a predictive off-timer. This

method of control eases the design of loop

compensation while providing inherent input voltage

feed-forward compensation.

PWM Dimming

Analog Dimming

Cycle-by-Cycle Current Limit

Programmable Switching Frequency

Low Profile 14-lead HTSSOP Package

Thermal Shutdown

The LM3429 includes a high-voltage startup regulator

that operates over a wide input range of 4.5 V to 75

V. The internal PWM controller is designed for

adjustable switching frequencies of up to 2 MHz, thus

enabling compact solutions. Additional features

include analog dimming, PWM dimming, overvoltage

protection, undervoltage lock-out, cycle-by-cycle

current limit, and thermal shutdown.

2 Applications

•

LED Drivers - Buck, Boost, Buck-Boost, SEPIC

Indoor and Outdoor SSL

Automotive

General Illumination

Device Information⁽¹⁾

Constant-Current Regulators

PART NUMBER

LM3429

LM3429-Q1

PACKAGE

BODY SIZE (NOM)

HTSSOP (14)

5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Boost Application Circuit

V_IN

LM3429

1

2

3

4

5

6

7

V_IN

14

HSN

13

COMP

CSH

HSP

12

IS

I_LED

11

RCT

V_CC

10

AGND

OVP

GATE

9

PGND

DAP

8

PWM

nDIM

NC

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM3429, LM3429-Q1

SNVS616H –APRIL 2009–REVISED JULY 2015

www.ti.com

Table of Contents

1

2

3

4

5

6

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics .......................................... 5

6.6 Typical Characteristics ............................................. 7

Detailed Description .............................................. 9

7.1 Overview ................................................................... 9

7.2 Functional Block Diagram ......................................... 9

7.3 Feature Description................................................. 10

7.4 Device Functional Modes........................................ 21

8

Application and Implementation ........................ 22

8.1 Application Information............................................ 22

8.2 Typical Applications ................................................ 24

Power Supply Recommendations...................... 53

9.1 Input Supply Current Limit ...................................... 53

9

10 Layout................................................................... 53

10.1 Layout Guidelines ................................................. 53

10.2 Layout Example .................................................... 54

11 Device and Documentation Support ................. 55

11.1 Device Support...................................................... 55

11.2 Documentation Support ........................................ 55

11.3 Related Links ........................................................ 55

11.4 Community Resources.......................................... 55

11.5 Trademarks........................................................... 55

11.6 Electrostatic Discharge Caution............................ 56

11.7 Glossary................................................................ 56

7

12 Mechanical, Packaging, and Orderable

Information ........................................................... 56

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (April 2013) to Revision H

Page

•

Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device

Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout

section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information

section ................................................................................................................................................................................... 1

Changes from Revision F (May 2013) to Revision G

Page

•

Changed layout of National Data Sheet to TI format ........................................................................................................... 51

Changed layout of National Data Sheet to TI format ........................................................................................................... 52

2

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SNVS616H –APRIL 2009–REVISED JULY 2015

5 Pin Configuration and Functions

PWP Package

14- Pin HTSSOP

Top View

1

14 HSN

13 HSP

12 IS

V

IN

COMP

CSH

2

3

4

5

6

7

DAP

15

RCT

11

V

CC

AGND

OVP

10 GATE

9

8

PGND

NC

nDIM

Pin Functions

NAME

I/O

DESCRIPTION

APPLICATION INFORMATION

NO.

1

Bypass with 100 nF capacitor to AGND as close to the device as

possible in the circuit board layout.

V_IN

I

Input Voltage

Compensation

2

COMP

Connect a capacitor to AGND to set compensation.

Connect a resistor to AGND to set signal current. For analog

dimming, connect current source or potentiometer to AGND (see

Analog Dimming section).

3

CSH

I

Current Sense High

Connect a resistor from the switch node and a capacitor to AGND to

set the switching frequency.

4

5

RCT

I

Resistor Capacitor Timing

Analog Ground

Connect to PGND through the DAP copper circuit board pad to

provide proper ground return for CSH, COMP, and RCT.

AGND

GND

Connect to a resistor divider from the output (V_O) or the input to

program output overvoltage lockout (OVLO). Turn-off threshold is

1.24 V and hysteresis for turn-on is provided by 20 µA current

source.

6

7

OVP

I

Overvoltage Protection

Not DIM input

Connect a PWM signal for dimming as detailed in the PWM Dimming

section and/or a resistor divider from V_INto program input

undervoltage lockout (UVLO). Turn-on threshold is 1.24 V and

hysteresis for turn-off is provided by 20 µA current source.

nDIM

8

9

NC

No Connection

Power Ground

Leave open.

Connect to AGND through DAP copper pad to provide ground return

for GATE.

PGND

GND

10

11

GATE

V_CC

O

I

Gate Drive Output

Connect to the gate of the external NFET.

Internal Regulator Output

Bypass with a 2.2 µF–3.3 µF, ceramic capacitor to PGND.

Connect to the drain of the main N-channel MosFET switch for R_DS-

12

IS

I

Main Switch Current Sense

sensing or to a sense resistor installed in the source of the same

ON

device.

Connect through a series resistor to LED current sense resistor

(positive).

13

14

HSP

HSN

DAP

I

LED Current Sense Positive

LED Current Sense Negative

Thermal pad on bottom of IC

Connect through a series resistor to LED current sense resistor

(negative).

DAP

(15)

GND

Connect to AGND and PGND.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

MAX

UNIT

V_IN, nDIM

OVP, HSP, HSN

RCT

76

3

76

IS

–2 for 100 ns

V

Voltage

V_CC

–0.3

8

COMP, CSH

6

–0.3

V_CC

GATE

PGND

–2.5 for 100 ns

–0.3

V_CC+2.5 for 100 ns

0.3

–2.5

2.5 for 100 ns

V_IN, nDIM

OVP, HSP, HSN

RCT

–1

–100

5

mA

µA

–1

Continuous Current

mA

IS

–1

COMP, CSH

GATE

–200

–1

200

1

µA

mA

Maximum Junction Temperature

Maximum Lead Temperature (Reflow and Solder)

Continuous Power Dissipation

Internally Limited

(3)

260

150

°C

Internally Limited

Storage Temperature, T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) Refer to http://www.ti.com/packaging for more detailed information and mounting techniques.

6.2 ESD Ratings

VALUE

UNIT

LM3429 IN PWP PACKAGE

V_(ESD)Electrostatic discharge

LM3429-Q1 IN PWP PACKAGE

V_(ESD)Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

±1000

V

Charged device model (CDM), per JEDEC specification JESD22-C101, all

pins⁽²⁾

Human body model (HBM), per AEC Q100-002⁽³⁾

Charged device model (CDM), per AEC Q100-011

±2000

±1000

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN

MAX UNIT

Operating Junction Temperature Range

Input Voltage V_IN

–40

4.5

125

75

°C

V

4

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6.4 Thermal Information

LM3429-Q1

LM3429

THERMAL METRIC⁽¹⁾

PWP (HTSSOP) PWP (HTSSOP) UNIT

14 PINS

47.8

26.5

22.3

0.7

14 PINS

47.8

26.5

22.3

0.7

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

22.1

3.3

22.1

3.3

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

MIN and MAX limits apply T_J= (−40°C to 125°C) unless specified otherwise. Unless otherwise stated the following condition

applies: V_IN= 14 V.

PARAMETER

STARTUP REGULATOR (V_CC

TEST CONDITIONS

MIN⁽¹⁾

TYP⁽²⁾

MAX⁽¹⁾

UNIT

)

V_CC-REG

I_CC-LIM

I_Q

V_CCRegulation

I_CC= 0 mA

6.3

20

6.9

27

7.35

V

V_CCCurrent Limit

Quiescent Current

V_CCUVLO Threshold

V_CC= 0V

mA

Static

1.6

3

V_CC-UVLO

V_CCIncreasing

V_CCDecreasing

4.17

4.08

0.1

4.5

3.7

V

V_CC-HYS

V_CCUVLO Hysteresis

OVERVOLTAGE PROTECTION (OVP)

V_TH-OVP

I_HYS-OVP

OVP OVLO Threshold

OVP Increasing

1.18

10

1.24

20

1.28

30

V

OVP Hysteresis Source Current

OVP Active (high)

µA

ERROR AMPLIFIER

V_CSHCSH Reference Voltage

With Respect to AGND

MIN, MAX: T_J= 25°C

1.21

–0.6

10

1.235

0

1.26

0.6

40

V

Error Amplifier Input Bias Current

COMP Sink / Source Current

Transconductance

µA

26

100

±125

µA/V

mV

(3)

Linear Input Range

Transconductance Bandwidth

-6dB Unloaded

Response⁽³⁾, MIN: T_J=

25°C

0.5

1

MHz

OFF TIMER (RCT)

t_OFF-MINMinimum Off-time

R_RCT

RCT = 1V through 1 kΩ

35

36

75

120

585

ns

Ω

RCT Reset Pulldown Resistance

V_IN/25 Reference Voltage

V_RCT

V_IN= 14V

540

700

215

75

565

mV

PWM COMPARATOR

COMP to PWM Offset

CURRENT LIMIT (IS)

800

900

mV

V_LIM

Current Limit Threshold

245

35

275

75

mV

ns

V_LIMDelay to Output

t_ON-MIN

Leading Edge Blanking Time

250

450

(1) All limits specified at room temperature (TYP) and at temperature extremes (MIN/MAX). All room temperature limits are 100%

production tested. All limits at temperature extremes are specified through correlation using standard Statistical Quality Control (SQC)

methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) Typical numbers are at 25°C and represent the most likely norm.

(3) These electrical parameters are specified by design, and are not verified by test.

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Electrical Characteristics (continued)

MIN and MAX limits apply T_J= (−40°C to 125°C) unless specified otherwise. Unless otherwise stated the following condition

applies: V_IN= 14 V.

PARAMETER

HIGH SIDE TRANSCONDUCTANCE AMPLIFIER

Input Bias Current

TEST CONDITIONS

MIN⁽¹⁾

TYP⁽²⁾

MAX⁽¹⁾

UNIT

10

119

0

µA

mA/V

µA

Transconductance

20

–1.5

–7

Input Offset Current

1.5

7

Input Offset Voltage

0

mV

Transconductance Bandwidth

I_CSH= 100 µA⁽³⁾, MIN: T_J

= 25°C

250

500

kHz

GATE DRIVER (GATE)

R_SRC(GATE)

R_SNK(GATE)

GATE Sourcing Resistance

GATE Sinking Resistance

GATE = High

GATE = Low

2

6

Ω

1.3

4.5

UNDERVOLTAGE LOCKOUT and DIM INPUT (nDIM)

V_TH-nDIM

I_HYS-nDIM

nDIM / UVLO Threshold

nDIM Hysteresis Current

1.18

10

1.24

20

1.28

30

V

µA

THERMAL SHUTDOWN

(3)

T_SD

Thermal Shutdown Threshold

165

25

°C

T_HYS

Thermal Shutdown Hysteresis

6

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6.6 Typical Characteristics

T_A= 25°C and V_IN= 14 V unless otherwise specified. The measurements for Figure 1 and Figure 3 were made using the

standard boost evaluation board from AN-1986 (SNVA404). The measurements for Figure 2, Figure 4, and Figure 5, Figure 6

were made using the standard buck-boost evaluation board from AN-1985 (SNVA403).

100

95

90

85

80

100

95

90

85

80

75

70

0

16

32

48

(V)

64

80

10

15

20

(V)

25

30

V

IN

V

IN

Figure 2. Buck-Boost Efficiency vs Input Voltage

V_O= 20 V (6 LEDs)

Figure 1. Boost Efficiency vs Input Voltage

V_O= 32 V (9 LEDs)

1.05

1.03

1.01

0.99

0.97

1.00

0.99

0.98

0.97

0.96

0

16

32

48

64

80

5

10

15

V

20

25

30

(V)

V

(V)

IN

Figure 3. Boost LED Current vs Input Voltage

Figure 4. Buck-boost LED Current vs Input Voltage

V_O= 32 V (9 LEDs)

V_O= 20 V (6 LEDs)

1.0

0.8

0.6

0.4

0.2

0.0

0.8

0.6

500 Hz

0.4

100 Hz

0.2

0.0

0

20

40

60

(éA)

80

100

20

40

60

80

100

I

CSH

DUTY CYCLE (%)

Figure 5. Analog Dimming

V_O= 20 V (6 LEDs)

Figure 6. PWM Dimming

V_O= 20V (6 LEDs)

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Typical Characteristics (continued)

T_A= 25°C and V_IN= 14 V unless otherwise specified. The measurements for Figure 1 and Figure 3 were made using the

standard boost evaluation board from AN-1986 (SNVA404). The measurements for Figure 2, Figure 4, and Figure 5, Figure 6

were made using the standard buck-boost evaluation board from AN-1985 (SNVA403).

1.250

1.245

1.240

1.235

1.230

1.225

1.220

7.10

7.05

7.00

6.95

6.90

6.85

6.80

-50

-14

22

58

94

130

-50

-14

22

58

94

130

TEMPERATURE (°C)

Figure 7. V_CSHvs. Junction Temperature

569

Figure 8. V_CCvs. Junction Temperature

246

568

567

566

565

564

244

242

240

238

-50

-14

22

58

94

130

-50

-14

22

58

94

130

TEMPERATURE (°C)

Figure 10. V_LIMvs. Junction Temperature

Figure 9. V_RCTvs. Junction Temperature

280

275

270

265

260

255

250

-50

-14

22

58

94

130

TEMPERATURE (°C)

Figure 11. t_ON-MINvs. Junction Temperature

8

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7 Detailed Description

7.1 Overview

The LM3429 is an N-channel MosFET (NFET) controller for buck, boost and buck-boost current regulators which

are ideal for driving LED loads. The controller has wide input voltage range allowing for regulation of a variety of

LED loads. The high-side differential current sense, with low adjustable threshold voltage, provides an excellent

method for regulating output current while maintaining high system efficiency. The LM3429 uses a Predictive Off-

time (PRO) control architecture that allows the regulator to be operated using minimal external control loop

compensation, while providing an inherent cycle-by-cycle current limit. The adjustable current sense threshold

provides the capability to amplitude (analog) dim the LED current and the output enable/disable function allows

for PWM dimming using no external components. When designing, the maximum attainable LED current is not

internally limited because the LM3429 is a controller. Instead it is a function of the system operating point,

component choices, and switching frequency allowing the LM3429 to easily provide constant currents up to 5A.

This simple controller contains all the features necessary to implement a high-efficiency versatile LED driver.

7.2 Functional Block Diagram

V

IN

6.9V LDO

Regulator

V

CC

VccUVLO

UVLO

Standby

UVLO

HYSTERESIS

1.24V

REFERENCE

TLIM

20 PA

Thermal

nDIM

RCT

Limit

Dimming

1.24V

V

/25

IN

Reset

Dominant

V

CC

Start new on time

GATE

PGND

S

R

Q

QB

COMP

CSH

OVP

HYSTERESIS

PWM

1.24V

20 PA

OVP

1.24V

800 mV

HSP

HSN

LOGIC

AGND

CURRENT

LIMIT

IS

245 mV

LEB

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7.3 Feature Description

7.3.1 Current Regulators

Current regulators can be designed to accomplish three basic functions: buck, boost, and buck-boost. All three

topologies in their most basic form contain a main switching MosFET, a recirculating diode, an inductor and

capacitors. The LM3429 is designed to drive a ground referenced NFET which is perfect for a standard boost

regulator. Buck and buck-boost regulators, on the other hand, usually have a high-side switch. When driving an

LED load, a ground referenced load is often not necessary, therefore a ground referenced switch can be used to

drive a floating load instead. The LM3429 can then be used to drive all three basic topologies as shown in the

Typical Applications section.

Looking at the buck-boost design, the basic operation of a current regulator can be analyzed. During the time

that the NFET (Q1) is turned on (t_ON), the input voltage source stores energy in the inductor (L1) while the output

capacitor (C_O) provides energy to the LED load. When Q1 is turned off (t_OFF), the re-circulating diode (D1)

becomes forward biased and L1 provides energy to both C_Oand the LED load. Figure 12 shows the inductor

current (i_L(t)) waveform for a regulator operating in CCM.

i_L(t)

I

L-MAX

Âi

L-PP

I

L

I

L-MIN

t

= DT

t

= (1-D)T

OFF S

ON

S

0

t

T

S

Figure 12. Ideal CCM Regulator Inductor Current i_L(t)

The average output LED current (I_LED) is proportional to the average inductor current (I_L) , therefore if I_Lis tightly

controlled, I_LEDwill be well regulated. As the system changes input voltage or output voltage, the ideal duty cycle

(D) is varied to regulate I_Land ultimately I_LED. For any current regulator, D is a function of the conversion ratio:

Buck

V_O

D =

V

IN

(1)

Boost

V_O- V

IN

D =

V_O

(2)

Buck-Boost

V_O

D

=

V_O+ V

IN

(3)

7.3.2 Predictive Off-Time (PRO) Control

PRO control is used by the LM3429 to control I_LED. It is a combination of average peak current control and a one-

shot off-timer that varies with input voltage. The LM3429 uses peak current control to regulate the average LED

current through an array of HBLEDs. This method of control uses a series resistor in the LED path to sense LED

current and can use either a series resistor in the MosFET path or the MosFET R_DS-ONfor both cycle-by-cycle

current limit and input voltage feed forward. D is indirectly controlled by changes in both t_OFFand t_ON, which vary

depending on the operating point.

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Feature Description (continued)

Even though the off-time control is quasi-hysteretic, the input voltage proportionality in the off-timer creates an

essentially constant switching frequency over the entire operating range for boost and buck-boost topologies.

The buck topology can be designed to give constant ripple over either input voltage or output voltage, however

switching frequency is only constant at a specific operating point .

This type of control minimizes the control loop compensation necessary in many switching regulators, simplifying

the design process. The averaging mechanism in the peak detection control loop provides extremely accurate

LED current regulation over the entire operating range.

PRO control was designed to mitigate “current mode instability” (also called “sub-harmonic oscillation”) found in

standard peak current mode control when operating near or above 50% duty cycles. When using standard peak

current mode control with a fixed switching frequency, this condition is present, regardless of the topology.

However, using a constant off-time approach, current mode instability cannot occur, enabling easier design and

control.

Predictive off-time advantages:

•

There is no current mode instability at any duty cycle.

Higher duty cycles / voltage transformation ratios are possible, especially in the boost regulator.

The only disadvantage is that synchronization to an external reference frequency is generally not available.

7.3.3 Switching Frequency

An external resistor (R_T) connected between the RCT pin and the switch node (where D1, Q1, and L1 connect),

in combination with a capacitor (C_T) between the RCT and AGND pins, sets the off-time (t_OFF) as shown in

Figure 13. For boost and buck-boost topologies, the V_INproportionality ensures a virtually constant switching

frequency (f_SW).

V

SW

LM3429

V

IN

/25

Start t_ON

R

T

RCT

C

T

Reset timer

Figure 13. Off-timer Circuitry for Boost and Buck-boost Regulators

For a buck topology, R_Tand C_Tare also used to set t_OFF, however the V_INproportionality will not ensure a

constant switching frequency. Instead, constant ripple operation can be achieved. Changing the connection of R_T

in Figure 13 from V_SWto V_INwill provide a constant ripple over varying V_IN. Adding a PNP transistor as shown in

Figure 14 will provide constant ripple over varying V_O.

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Feature Description (continued)

V

IN

R

SNS

R

T

LM3429

V

IN

/25

Start t_ON

LED-

RCT

C

T

Reset timer

Figure 14. Off-timer Circuitry for Buck Regulators

The switching frequency is defined:

Buck (Constant Ripple vs. V_IN)

25 x V - V

(

)

IN

O

f_SW

=

R_Tx C_TX V_IN

(4)

Buck (Constant Ripple vs. V_O)

2

(

)

25 x V x V_O- V_O

IN

f_SW

=

2

R_Tx C_TxV

IN

(5)

(6)

Boost and Buck-Boost

25

f_SW

=

R_Tx C_T

For all topologies, the C_Tcapacitor is recommended to be 1 nF and should be located very close to the LM3429.

7.3.4 Average LED Current

The LM3429 uses an external current sense resistor (R_SNS) placed in series with the LED load to convert the

LED current (I_LED) into a voltage (V_SNS) as shown in Figure 15. The HSP and HSN pins are the inputs to the

high-side sense amplifier which are forced to be equal potential (V_HSP=V_HSN) through negative feedback.

Because of this, the V_SNSvoltage is forced across R_HSPto generate the signal current (I_CSH) which flows out of

the CSH pin and through the R_CSHresistor. The error amplifier will regulate the CSH pin to 1.24 V, therefore I_CSH

can be calculated:

V_SNS

R_HSP

I_CSH

=

(7)

This means V_SNSwill be regulated as follows:

R_HSP

V_SNS= 1.24V x

R_CSH

(8)

I_LEDcan then be calculated:

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Feature Description (continued)

V_SNS

R_SNS

1.24V R_HSP

x

I_LED

=

R_SNS

R_CSH

(9)

The selection of the three resistors (R_SNS, R_CSH, and R_HSP) is not arbitrary. For matching and noise performance,

the suggested signal current I_CSHis approximately 100 µA. This current does not flow in the LEDs and will not

affect either the off state LED current or the regulated LED current. I_CSHcan be above or below this value, but

the high-side amplifier offset characteristics may be affected slightly. In addition, to minimize the effect of the

high-side amplifier voltage offset on LED current accuracy, the minimum V_SNSis suggested to be 50 mV. Finally,

a resistor (R_HSN= R_HSP) should be placed in series with the HSN pin to cancel out the effects of the input bias

current (~10 µA) of both inputs of the high-side sense amplifier. The CSH pin can also be used as a low-side

current sense input regulated to 1.24 V. The high-side sense amplifier is disabled if HSP and HSN are tied to

GND.

LM3429

I

LED

High-Side

R

Sense Amplifier

HSP

HSN

I

CSH

R

SNS

V

SNS

R

HSN

Error Amplifier

R

C

CSH

To PWM

Comparator

1.24V

CMP

COMP

Figure 15. LED Current Sense Circuitry

7.3.5 Analog Dimming

The CSH pin can be used to analog dim the LED current by adjusting the current sense voltage (V_SNS). There

are several different methods to adjust V_SNSusing the CSH pin:

1. External variable resistance : Adjust a potentiometer placed in series with R_CSHto vary V_SNS

.

2. External variable current source: Source current (0 µA to I_CSH) into the CSH pin to adjust V_SNS

.

In general, analog dimming applications require a lower switching frequency to minimize the effect of the leading

edge blanking circuit. As the LED current is reduced, the output voltage and the duty cycle decreases.

Eventually, the minimum on-time is reached. The lower the switching frequency, the wider the linear dimming

range. Figure 16 shows how both methods are physically implemented.

Method 1 uses an external potentiometer in the CSH path which is a simple addition to the existing circuitry.

However, the LEDs cannot dim completely because there is always some resistance causing signal current to

flow. This method is also susceptible to noise coupling at the CSH pin because the potentiometer increases the

size of the signal current loop.

Method 2 provides a complete dimming range and better noise performance, though it is more complex. It

consists of a PNP current mirror and a bias network consisting of an NPN, 2 resistors and a potentiometer

(R_ADJ), where R_ADJcontrols the amount of current sourced into the CSH pin. A higher resistance value will source

more current into the CSH pin causing less regulated signal current through R_HSP, effectively dimming the LEDs.

V_REFshould be a precise external voltage reference, while Q7 and Q8 should be a dual pair PNP for best

matching and performance. The additional current (I_ADD) sourced into the CSH pin can be calculated:

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Feature Description (continued)

§

¨

©

·

¸

R_ADJx V_REF

R_ADJ+ R_MAX

- V_BE-Q6

¹

I_ADD

=

R_BIAS

(10)

(11)

The corresponding I_LEDfor a specific I_ADDis:

R_HSP

§

·

¸

I_LED= I_CSH- I_ADD

x

(

)

¨

R_SNS

©

¹

Variable Current Source

LM3429

V_CC

V_REF

Q8

Q7

R

MAX

Q6

R

CSH

R

CSH

R

BIAS

ADJ

Variable

Resistance

R

ADJ

Figure 16. Analog Dimming Circuitry

7.3.6 Current Sense and Current Limit

The LM3429 achieves peak current mode control using a comparator that monitors the MosFET transistor

current, comparing it with the COMP pin voltage as shown in Figure 17. Further, it incorporates a cycle-by-cycle

overcurrent protection function. Current limit is accomplished by a redundant internal current sense comparator.

If the voltage at the current sense comparator input (IS) exceeds 245 mV (typical), the on cycle is immediately

terminated. The IS input pin has an internal N-channel MosFET which pulls it down at the conclusion of every

cycle. The discharge device remains on an additional 250 ns (typical) after the beginning of a new cycle to blank

the leading edge spike on the current sense signal. The leading edge blanking (LEB) determines the minimum

achievable on-time (t_ON-MIN).

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Feature Description (continued)

LM3429

COMP

Q1

GATE

PWM

800 mV

IS

245 mV

I

T

R

LIM

LEB

PGND

Figure 17. Current Sense / Current Limit Circuitry

There are two possible methods to sense the transistor current. The R_DS-ONof the main power MosFET can be

used as the current sense resistance because the IS pin was designed to withstand the high voltages present on

the drain when the MosFET is in the off state. Alternatively, a sense resistor located in the source of the MosFET

may be used for current sensing, however a low inductance (ESL) type is suggested. The cycle-by-cycle current

limit (I_LIM) can be calulated using either method as the limiting resistance (R_LIM):

245 mV

R_LIM

I_LIM

=

(12)

In general, the external series resistor allows for more design flexibility, however it is important to ensure all of

the noise sensitive low power ground connections are connected together local to the controller and a single

connection is made to the high current PGND (sense resistor ground point).

7.3.7 Control Loop Compensation

The LM3429 control loop is modeled like any current mode controller. Using a first order approximation, the

uncompensated loop can be modeled as a single pole created by the output capacitor and, in the boost and

buck-boost topologies, a right half plane zero created by the inductor, where both have a dependence on the

LED string dynamic resistance. There is also a high frequency pole in the model, however it is above the

switching frequency and plays no part in the compensation design process therefore it will be neglected.

Because ceramic capacitance is recommended for use with LED drivers due to long lifetimes and high ripple

current rating, the ESR of the output capacitor can also be neglected in the loop analysis. Finally, there is a DC

gain of the uncompensated loop which is dependent on internal controller gains and the external sensing

network.

A buck-boost regulator will be used as an example case. See the Typical Applications section for compensation

of all topologies.

The uncompensated loop gain for a buck-boost regulator is given by the following equation:

§

·

¸

¹

s

Z_Z1

¨ -

1

¨

©

T_U= T_U0

x

§

·

¸

¹

s

Z_P1

¨

1+

¨

©

(13)

15

Where the uncompensated DC loop gain of the system is described as:

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Feature Description (continued)

c

D x 500Vx R_CSHx R_SNS

c

D x 620V

T_U0

=

(

)

(

)

1+D x R_HSPx R_LIM

And the output pole (ω_P1) is approximated:

1+

1+D xI_LEDx R_LIM

(14)

ꢀ

D

Z_P1=

r_Dx C_O

(15)

(16)

And the right half plane zero (ω_Z1) is:

c²

r_DxD

Z_Z1=

DxL1

135

90

100

ö

P1

ö

Z1

80

60

40

20

0

GAIN

45

0

PHASE

-45

-90

-135

-180

-225

0°Phase Margin

-20

-40

-60

1e-1

1e1

1e3

1e5

1e7

FREQUENCY (Hz)

Figure 18. Uncompensated Loop Gain Frequency Response

Figure 18 shows the uncompensated loop gain in a worst-case scenario when the RHP zero is below the output

pole. This occurs at high duty cycles when the regulator is trying to boost the output voltage significantly. The

RHP zero adds 20dB/decade of gain while loosing 45°/decade of phase which places the crossover frequency

(when the gain is zero dB) extremely high because the gain only starts falling again due to the high frequency

pole (not modeled or shown in figure). The phase will be below -180° at the crossover frequency which means

there is no phase margin (180° + phase at crossover frequency) causing system instability. Even if the output

pole is below the RHP zero, the phase will still reach -180° before the crossover frequency in most cases yielding

instability.

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Feature Description (continued)

LM3429

I

LED

High-Side

Sense Amplifier

R

HSP

HSN

C

FS

R

V

SNS

R

HSN

R

FS

Error Amplifier

sets ö

R

CSH

P3

CSH

To PWM

Comparator

1.24V

R

O

C

CMP

sets ö

COMP

P2

Figure 19. Compensation Circuitry

To mitigate this problem, a compensator should be designed to give adequate phase margin (above 45°) at the

crossover frequency. A simple compensator using a single capacitor at the COMP pin (C_CMP) will add a dominant

pole to the system, which will ensure adequate phase margin if placed low enough. At high duty cycles (as

shown in Figure 18), the RHP zero places extreme limits on the achievable bandwidth with this type of

compensation. However, because an LED driver is essentially free of output transients (except catastrophic

failures open or short), the dominant pole approach, even with reduced bandwidth, is usually the best approach.

The dominant compensation pole (ω_P2) is determined by C_CMPand the output resistance (R_O) of the error

amplifier (typically 5 MΩ):

1

Z_P2

5x10⁶: x C_CMP

(17)

It may also be necessary to add one final pole at least one decade above the crossover frequency to attenuate

switching noise and, in some cases, provide better gain margin. This pole can be placed across R_SNSto filter the

ESL of the sense resistor at the same time. Figure 19 shows how the compensation is physically implemented in

the system.

The high frequency pole (ω_P3) can be calculated:

1

Z_P3=

R_FSxC_FS

(18)

The total system transfer function becomes:

§

·

¸

¹

s

Z_Z1

¨

1-

¨

©

T = T_U0

x

§

·

¸

¹

§

¨

©

·

§

¨

©

·

¸

¹

s

Z_P1

s

Z_P2

s

Z_P3

¨

¸

¨

1+

x 1+

¨

¸

©

¹

(19)

The resulting compensated loop gain frequency response shown in Figure 20 indicates that the system has

adequate phase margin (above 45°) if the dominant compensation pole is placed low enough, ensuring stability:

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Feature Description (continued)

90

80

60

40

20

0

ö

P2

45

0

GAIN

-45

-90

-135

-180

-225

-270

ö

Z1

P1

PHASE

ö

P3

-20

-40

-60

-80

60°Phase Margin

1e-1

1e1

1e3

1e5

1e7

FREQUENCY (Hz)

Figure 20. Compensated Loop Gain Frequency Response

7.3.8 Output Overvoltage Lockout (OVLO)

The LM3429 can be configured to detect an output (or input) overvoltage condition through the OVP pin. The pin

features a precision 1.24-V threshold with 20 µA (typical) of hysteresis current as shown in Figure 21. When the

OVLO threshold is exceeded, the GATE pin is immediately pulled low and a 20 µA current source provides

hysteresis to the lower threshold of the OVLO hysteretic band.

LM3429

V_O

20 PA

R

OV2

OV1

OVP

OVLO

1.24V

Figure 21. Overvoltage Protection Circuitry

If the LEDs are referenced to a potential other than ground (floating), as in the buck-boost and buck

configuration, the output voltage (V_O) should be sensed and translated to ground by using a single PNP as

shown in Figure 22.

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Feature Description (continued)

LED+

R

OV2

LM3429

LED-

OVP

R

OV1

Figure 22. Floating Output OVP Circuitry

The overvoltage turnoff threshold (V_TURN-OFF) is defined as follows:

Ground Referenced

§

·

R_OV+ R_OV2

1

¨

©

¸

¹

V_TURN-OFF= 1.24Vx

Floating

V_TURN-OFF= 1.24Vx

R_OV1

(20)

(21)

§

·

+ R_OV2

0.5 x R_OV1

¨

©

¸

R_OV1

¹

In the ground referenced configuration, the voltage across R_OV2is V_O- 1.24 V whereas in the floating

configuration it is V_O- 620 mV where 620 mV approximates the V_BEof the PNP transistor.

The overvoltage hysteresis (V_HYSO) is defined as follows:

V_HYSO= 20 PA x R_OV2

(22)

7.3.9 Input Undervoltage Lockout (UVLO)

The nDIM pin is a dual-function input that features an accurate 1.24 V threshold with programmable hysteresis

as shown in Figure 23. This pin functions as both the PWM dimming input for the LEDs and as a V_INUVLO.

When the pin voltage rises and exceeds the 1.24 V threshold, 20 µA (typical) of current is driven out of the nDIM

pin into the resistor divider providing programmable hysteresis.

LM3429

V_IN

20 PA

R

UV2

UV1

nDIM

UVLO

1.24V

R

UVH

(optional)

Figure 23. UVLO Circuit

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Feature Description (continued)

When using the nDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra series

resistor to set the hysteresis. This allows the standard resistor divider to have smaller resistor values minimizing

PWM delays due to a pulldown MosFET at the nDIM pin (see PWM Dimming section). In general, at least 3V of

hysteresis is necessary when PWM dimming if operating near the UVLO threshold.

The turn-on threshold (V_TURN-ON) is defined as follows:

§

·

¸

¹

R_UV+ R_UV2

1

¨

©

V_TURN_O-N= 1.24Vx

R_UV1

(23)

(24)

The hysteresis (V_HYS) is defined as follows:

UVLO Only

V_HYS20 PA xR

=

UV2

PWM Dimming and UVLO

§

¨

©

(

)·

¸

¹

R_UVHx R_UV1+ R_UV2

¨

20PA x R

V_HYS

=

+

UV2

¸

R_UV1

(25)

7.3.10 PWM Dimming

The active low nDIM pin can be driven with a PWM signal which controls the main NFET (Q1). The brightness of

the LEDs can be varied by modulating the duty cycle of this signal. LED brightness is approximately proportional

to the PWM signal duty cycle, so 30% duty cycle equals approximately 30% LED brightness. This function can

be ignored if PWM dimming is not required by using nDIM solely as a V_INUVLO input as described in the Input

Undervoltage Lockout (UVLO) section or by tying it directly to V_CCor V_IN(if less than 76VDC).

Inverted

PWM

V_IN

LM3429

D

DIM

R

UV2

nDIM

R

UVH

R

UV1

Q

DIM

Standard

PWM

Figure 24. PWM Dimming Circuit

Figure 24 shows two ways the PWM signal can be applied to the nDIM pin:

1. Connect the dimming MosFET (Q_DIM) with the drain to the nDIM pin and the source to GND. Apply an

external logic-level PWM signal to the gate of Q_DIM. A pull down resistor may be necessary to properly turn

off Q_DIMif no signal is present.

2. Connect the anode of a Schottky diode (D_DIM) to the nDIM pin. Apply an external inverted logic-level PWM

signal to the cathode of the same diode.

A minimum on-time must be maintained in order for PWM dimming to operate in the linear region of its transfer

function. Because the controller is disabled during dimming, the PWM pulse must be long enough such that the

energy intercepted from the input is greater than or equal to the energy being put into the LEDs. For boost and

buck-boost regulators, the following condition must be maintained:

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Feature Description (continued)

2 x I_LEDx V_OX L1

t_PULSE

=

2

V_IN

(26)

In the previous equation, t_PULSEis the length of the PWM pulse in seconds.

7.3.11 Startup Regulator (V_CCLDO)

The LM3429 includes a high voltage, low dropout (LDO) bias regulator. When power is applied, the regulator is

enabled and sources current into an external capacitor connected to the V_CCpin. The V_CCoutput voltage is 6.9V

nominally and the supply is internally current limited to 20 mA (minimum). The recommended bypass

capacitance range for the V_CCregulator is 2.2 µF to 3.3 µF. The output of the V_CCregulator is monitored by an

internal UVLO circuit that protects the device during startup, normal operation, and shutdown from attempting to

operate with insufficient supply voltage.

7.3.12 Thermal Shutdown

The LM3429 includes thermal shutdown. If the die temperature reaches approximately 165°C the device will shut

down (GATE pin low), until it reaches approximately 140°C where it turns on again.

7.4 Device Functional Modes

This device has no functional modes.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Inductor

The inductor (L1) is the main energy storage device in a switching regulator. Depending on the topology, energy

is stored in the inductor and transfered to the load in different ways (as an example, buck-boost operation is

detailed in the Current Regulators section). The size of the inductor, the voltage across it, and the length of the

switching subinterval (t_ONor t_OFF) determines the inductor current ripple (Δi_L-PP). In the design process, L1 is

chosen to provide a desired Δi_L-PP. For a buck regulator the inductor has a direct connection to the load, which is

good for a current regulator. This requires little to no output capacitance therefore Δi_L-PPis basically equal to the

LED ripple current Δi_LED-PP. However, for boost and buck-boost regulators, there is always an output capacitor

which reduces Δi_LED-PP, therefore the inductor ripple can be larger than in the buck regulator case where output

capacitance is minimal or completely absent.

In general, Δi_LED-PPis recommended by manufacturers to be less than 40% of the average LED current (I_LED).

Therefore, for the buck regulator with no output capacitance, Δi_L-PPshould also be less than 40% of I_LED. For the

boost and buck-boost topologies, Δi_L-PPcan be much higher depending on the output capacitance value.

However, Δi_L-PPis suggested to be less than 100% of the average inductor current (I_L) to limit the RMS inductor

current.

L1 is also suggested to have an RMS current rating at least 25% higher than the calculated minimum allowable

RMS inductor current (I_L-RMS).

8.1.2 LED Dynamic Resistance (r_D)

When the load is a string of LEDs, the output load resistance is the LED string dynamic resistance plus R_SNS

.

LEDs are PN junction diodes, and their dynamic resistance shifts as their forward current changes. Dividing the

forward voltage of a single LED (V_LED) by the forward current (I_LED) leads to an incorrect calculation of the

dynamic resistance of a single LED (r_LED). The result can be 5 to 10 times higher than the true r_LEDvalue.

Figure 25. Dynamic Resistance

Obtaining r_LEDis accomplished by referring to the manufacturer's LED I-V characteristic. It can be calculated as

the slope at the nominal operating point as shown in Figure 25. For any application with more than 2 series

LEDs, R_SNScan be neglected allowing r_Dto be approximated as the number of LEDs multiplied by r_LED

.

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Application Information (continued)

8.1.3 Output Capacitor

For boost and buck-boost regulators, the output capacitor (C_O) provides energy to the load when the recirculating

diode (D1) is reverse biased during the first switching subinterval. An output capacitor in a buck topology will

simply reduce the LED current ripple (Δi_LED-PP) below the inductor current ripple (Δi_L-PP). In all cases, C_Ois sized

to provide a desired Δi_LED-PP. As mentioned in the Inductor section, Δi_LED-PPis recommended by manufacturers to

be less than 40% of the average LED current (I_LED).

C_Oshould be carefully chosen to account for derating due to temperature and operating voltage. It must also

have the necessary RMS current rating. Ceramic capacitors are the best choice due to their high ripple current

rating, long lifetime, and good temperature performance. An X7R dieletric rating is suggested.

8.1.4 Input Capacitors

The input capacitance (C_IN) provides energy during the discontinuous portions of the switching period. For buck

and buck-boost regulators, C_INprovides energy during t_ONand during t_OFF, the input voltage source charges up

C_INwith the average input current (I_IN). For boost regulators, C_INonly needs to provide the ripple current due to

the direct connection to the inductor. C_INis selected given the maximum input voltage ripple (Δv_IN-PP) which can

be tolerated. Δv_IN-PPis suggested to be less than 10% of the input voltage (V_IN).

An input capacitance at least 100% greater than the calculated C_INvalue is recommended to account for derating

due to temperature and operating voltage. When PWM dimming, even more capacitance can be helpful to

minimize the large current draw from the input voltage source during the rising transition of the LED current

waveform.

The chosen input capacitors must also have the necessary RMS current rating. Ceramic capacitors are again the

best choice due to their high ripple current rating, long lifetime, and good temperature performance. An X7R

dieletric rating is suggested.

For most applications, TI recommends bypassing the V_INpin with an 0.1-µF ceramic capacitor placed as close as

possible to the pin. In situations where the bulk input capacitance may be far from the LM3429 device, a 10-Ω

series resistor can be placed between the bulk input capacitance and the bypass capacitor, creating a 150 kHz

filter to eliminate undesired high frequency noise coupling.

8.1.5 N-Channel MosFET (NFET)

The LM3429 requires an external NFET (Q1) as the main power MosFET for the switching regulator. Q1 is

recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe

operation during the ringing of the switch node. In practice, all switching regulators have some ringing at the

switch node due to the diode parasitic capacitance and the lead inductance. The current rating is recommended

to be at least 10% higher than the average transistor current. The power rating is then verified by calculating the

power loss given the RMS transistor current and the NFET on-resistance (R_DS-ON).

In general, the NFET should be chosen to minimize total gate charge (Q_g) whenever switching frequencies are

high and minimize R_DS-ONotherwise. This will minimize the dominant power losses in the system. Frequently,

higher current NFETs in larger packages are chosen for better thermal performance.

8.1.6 Re-Circulating Diode

A re-circulating diode (D1) is required to carry the inductor current during t_OFF. The most efficient choice for D1 is

a Schottky diode due to low forward voltage drop and near-zero reverse recovery time. Similar to Q1, D1 is

recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe

operation during the ringing of the switch node and a current rating at least 10% higher than the average diode

current. The power rating is verified by calculating the power loss through the diode. This is accomplished by

checking the typical diode forward voltage from the I-V curve on the product data sheet and multiplying by the

average diode current. In general, higher current diodes have a lower forward voltage and come in better

performing packages minimizing both power losses and temperature rise.

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8.2 Typical Applications

8.2.1 Basic Topology Schematics

L1

D1

V_IN

C

IN

R

T

R

HSN

1

2

3

4

5

6

7

14

13

12

11

HSN

HSP

IS

V

LM3429

IN

C

FS

R

SNS

C

CMP

R

HSP

C

O

COMP

CSH

R

FS

R

CSH

I_LED

C

T

RCT

V

CC

C

BYP

10

AGND

OVP

GATE

PGND

NC

Q1

9

R

LIM

UV2

R

OV2

OV1

DAP

R

UVH

8

nDIM

C

OV

UV1

Q3

PWM

Figure 26. Boost Regulator (V_IN< V_O)

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Typical Applications (continued)

V_IN

C

IN

R

HSN

1

2

3

4

5

6

7

14

13

12

11

HSN

HSP

IS

V

LM3429

IN

C

R

T

FS

R

SNS

R

HSP

C

O

COMP

CSH

C

CMP

FS

D1

I_LED

L1

R

CSH

RCT

V

CC

C

T

C

BYP

10

9

AGND

OVP

GATE

PGND

NC

Q1

R

OV2

R

LIM

UV2

Q2

DAP

R

UVH

8

nDIM

R

OV1

C

OV

UV1

Q3

PWM

Figure 27. Buck Regulator (V_IN> V_O)

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Typical Applications (continued)

L1

D1

V_IN

C

IN

R

T

I_LED

R

HSN

1

2

3

4

5

6

7

14

13

12

11

C

O

V

HSN

HSP

IS

IN

LM3429

C

FS

R

SNS

C

R

HSP

CMP

COMP

CSH

V_IN

R

FS

R

CSH

C

T

RCT

V

CC

C

BYP

10

AGND

OVP

GATE

PGND

NC

Q1

R

OV2

9

R

UV2

LIM

Q2

V_IN

DAP

R

UVH

8

nDIM

R

C

OV

OV1

UV1

Q3

PWM

Figure 28. Buck-Boost Regulator

8.2.1.1 Design Requirements

Number of series LEDs: N

Single LED forward voltage: V_LED

Single LED dynamic resistance: r_LED

Nominal input voltage: V_IN

Input voltage range: V_IN-MAX, V_IN-MIN

Switching frequency: f_SW

Current sense voltage: V_SNS

Average LED current: I_LED

Inductor current ripple: Δi_L-PP

LED current ripple: Δi_LED-PP

Peak current limit: I_LIM

Input voltage ripple: Δv_IN-PP

Output OVLO characteristics: V_TURN-OFF, V_HYSO

Input UVLO characteristics: V_TURN-ON, V_HYS

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Typical Applications (continued)

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Operating Point

Given the number of series LEDs (N), the forward voltage (V_LED) and dynamic resistance (r_LED) for a single LED,

solve for the nominal output voltage (V_O) and the nominal LED string dynamic resistance (r_D):

V_O= N x V_LED

(27)

r_D= N x r_LED

(28)

Solve for the ideal nominal duty cycle (D):

Buck

V_O

D =

V

IN

(29)

Boost

V_O- V

IN

D =

V_O

(30)

Buck-boost

V_O

D

=

V_O+ V

IN

(31)

Using the same equations, find the minimum duty cycle (D_MIN) using maximum input voltage (V_IN-MAX) and the

maximum duty cycle (D_MAX) using the minimum input voltage (V_IN-MIN). Also, remember that D' = 1 - D.

8.2.1.2.2 Switching Frequency

Set the switching frequency (f_SW) by assuming a C_Tvalue of 1 nF and solving for R_T:

Buck (Constant Ripple vs. V_IN)

25 x V - V

(

)

IN

O

R_T=

f_SWx C_TX V_IN

(32)

Buck (Constant Ripple vs. V_O)

2

O

x (V x V_OV )

25

-

IN

R_T

=

2

f_SWx C_Tx V

IN

(33)

(34)

Boost and Buck-Boost

25

R_T=

f_SWx C_T

8.2.1.2.3 Average LED Current

For all topologies, set the average LED current (I_LED) knowing the desired current sense voltage (V_SNS) and

solving for R_SNS

:

V_SNS

I_LED

R_SNS

=

(35)

If the calculated R_SNSis too far from a desired standard value, then V_SNSmust be adjusted to obtain a standard

value.

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Typical Applications (continued)

Setup the suggested signal current of 100 µA by assuming R_CSH= 12.4 kΩ and solving for R_HSP

:

I_LEDx R_CSHx R_SNS

R_HSP

=

1.24V

(36)

If the calculated R_HSPis too far from a desired standard value, then R_CSHcan be adjusted to obtain a standard

value.

8.2.1.2.4 Inductor Ripple Current

Set the nominal inductor ripple current (Δi_L-PP) by solving for the appropriate inductor (L1):

Buck

(V_INꢀ V_O)xD

L1

'i_LꢀPPx f_SW

(37)

(38)

Boost and Buck-Boost

V x D

IN

L1

'i_LꢀPPx f_SW

To set the worst case inductor ripple current, use V_IN-MAXand D_MINwhen solving for L1.

The minimum allowable inductor RMS current rating (I_L-RMS) can be calculated as:

Buck

2

'I_L-PP

§

¨

©

·

1

12

I_L-RMS= I_LED

x

1 +

x

¸

I_LED

¹

(39)

(40)

Boost and Buck-Boost

2

'I_L-PPx D'

¨

I_LED

§

·

¸

1

12

x 1 +

x

I_L-RMS

=

I_LED

D'

©

¹

8.2.1.2.5 LED Ripple Current

Set the nominal LED ripple current (Δi_LED-PP), by solving for the output capacitance (C_O):

Buck

'i_L-PP

8 x f_SWx r_Dx 'i_LED-PP

C_O=

(41)

(42)

Boost and Buck-Boost

I_LEDx D

C_o

r_Dx 'i_LEDꢀPP

To set the worst case LED ripple current, use D_MAXwhen solving for C_O.

The minimum allowable RMS output capacitor current rating (I_CO-RMS) can be approximated:

Buck

üi_LED-PP

I_{CO- RMS}

=

12

(43)

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Typical Applications (continued)

Boost and Buck-boost

D_MAX

I_CO-RMS= I_LED

x

1-D_MAX

(44)

8.2.1.2.6 Peak Current Limit

Set the peak current limit (I_LIM) by solving for the transistor path sense resistor (R_LIM):

245 mV

R_LIM

=

I_LIM

(45)

8.2.1.2.7 Loop Compensation

Using a simple first order peak current mode control model, neglecting any output capacitor ESR dynamics, the

necessary loop compensation can be determined.

First, the uncompensated loop gain (T_U) of the regulator can be approximated:

Buck

1

T_U= T_U0

x

§

·

¸

¹

s

¨

1+

¨

Z_P1

©

(46)

(47)

Boost and Buck-Boost

§

·

¸

¹

·

¸

¹

s

Z_Z1

¨ -

1

¨

©

T_U= T_U0

x

§

s

Z_P1

¨

1+

¨

©

Where the pole (ω_P1) is approximated:

Buck

1

Z_P1=

r_Dx C_O

(48)

(49)

(50)

Boost

2

Z_P1=

r_Dx C_O

Buck-Boost

1+D

r_Dx C_O

ꢀ

Z_P1=

And the RHP zero (ω_Z1) is approximated:

Boost

c²

r_DxD

L1

Z_Z1=

(51)

Buck-Boost

c²

r_DxD

Z_Z1=

DxL1

(52)

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Typical Applications (continued)

And the uncompensated DC loop gain (T_U0) is approximated:

Buck

500Vx R_CSHx R_SNS

R_HSPx R_LIM

620V

I_LEDx R_LIM

T_U0

=

(53)

(54)

Boost

T_U0

Buck-Boost

c

D x 500V x R_CSHx R_SNS

c

D x 310V

=

2 x R_HSPx R_LIM

I_LEDx R_LIM

c

D x 500Vx R_CSHx R_SNS

c

D x 620V

T_U0

=

(

)

(

)

1+D x R_HSPx R_LIM

1+D xI_LEDx R_LIM

(55)

For all topologies, the primary method of compensation is to place a low-frequency dominant pole (ω_P2) which

will ensure that there is ample phase margin at the crossover frequency. This is accomplished by placing a

capacitor (C_CMP) from the COMP pin to GND, which is calculated according to the lower value of the pole and the

RHP zero of the system (shown as a minimizing function):

min(Z_P1,Z_Z1)

Z_P2

=

5 xT_U0

(56)

(57)

1

C_CMP

=

Ѡ_P2

×

5×10⁶

If analog dimming is used, C_CMPshould be approximately 4x larger to maintain stability as the LEDs are dimmed

to zero.

A high frequency compensation pole (ω_P3) can be used to attenuate switching noise and provide better gain

margin. Assuming R_FS= 10 Ω, C_FSis calculated according to the higher value of the pole and the RHP zero of

the system (shown as a maximizing function):

(

)

Z_P3max Z ,Z x10

=

P1

Z1

(58)

(59)

1

C_FS

=

10 xZ_P3

The total system loop gain (T) can then be written as:

Buck

1

T = T_U0

x

§

·

¸

¹

§

¨

©

·

¸

¹

§

¨

©

·

¸

¹

s

Z_P1

s

Z_P3

¨

1+

x 1+

¨

Z_P2

©

(60)

(61)

Boost and Buck-boost

§

·

¸

¹

s

Z_Z1

¨

1-

¨

©

T = T_U0

x

§

·

¸

¹

§

¨

©

·

§

·

¸

¹

s

Z_P1

s

Z_P2

s

Z_P3

¨

¸

¨

1+

x 1+

¨

¸

¨

©

¹

8.2.1.2.8 Input Capacitance

Set the nominal input voltage ripple (Δv_IN-PP) by solving for the required capacitance (C_IN):

Buck

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Typical Applications (continued)

I_LEDx (1 - D) x D

C_IN

Boost

C_IN

=

'V_IN-PPx f_SW

(62)

(63)

(64)

'i_L-PP

=

8 x 'V_IN-PPx f_SW

Buck-Boost

C_IN

I_LEDx D

=

'V_IN-PPx f_SW

Use D_MAXto set the worst case input voltage ripple, when solving for C_INin a buck-boost regulator and D_MID= 0.5

when solving for C_INin a buck regulator.

The minimum allowable RMS input current rating (I_CIN-RMS) can be approximated:

Buck

I

_{CIN- RMS}= I_LEDx D_MIDx(1-D_MID

)

(65)

(66)

(67)

Boost

'i_L-PP

I_CIN-RMS

Buck-Boost

I_CIN-RMS= I_LED

=

12

D_MAX

x

1-D_MAX

8.2.1.2.9 NFET

The NFET voltage rating should be at least 15% higher than the maximum NFET drain-to-source voltage (V_T-

_MAX):

Buck

V_{T- MAX}= V

IN- MAX

(68)

Boost

V

_{T- MAX}= V_O

(69)

(70)

Buck-Boost

V

_{T- MAX}= V_{IN- MAX}+ V_O

The current rating should be at least 10% higher than the maximum average NFET current (I_T-MAX):

Buck

I_T-MAX= D_MAXx I_LED

(71)

Boost and Buck-Boost

D_MAX

I_T-MAX

=

x I_LED

1 - D_MAX

(72)

31

Approximate the nominal RMS transistor current (I_T-RMS) :

Buck

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Typical Applications (continued)

I

_{T- RMS}= I_LEDx D

(73)

Boost and Buck-Boost

I

^LEDx D

I_{T- RMS}

=

c

D

(74)

(75)

Given an NFET with on-resistance (R_DS-ON), solve for the nominal power dissipation (P_T):

P = I_{T- RMS}²x R_DSON

T

8.2.1.2.10 Diode

The Schottky diode voltage rating should be at least 15% higher than the maximum blocking voltage (V_RD-MAX):

Buck

V_RD-MAX= V_IN-MAX

(76)

Boost

V_RD-MAX= V_O

(77)

(78)

Buck-Boost

V_RD-MAX= V_IN-MAX+ V_O

The current rating should be at least 10% higher than the maximum average diode current (I_D-MAX):

Buck

I_D-MAX= (1 - D_MIN) x I_LED

(79)

(80)

Boost and Buck-Boost

I_D-MAX= I_LED

Replace D_MAXwith D in the I_D-MAXequation to solve for the average diode current (I_D). Given a diode with forward

voltage (V_FD), solve for the nominal power dissipation (P_D):

P_D= I_DxV_FD

(81)

8.2.1.2.11 Output OVLO

For boost and buck-boost regulators, output OVLO is programmed with the turn-off threshold voltage (V_TURN-OFF

)

and the desired hysteresis (V_HYSO). To set V_HYSO, solve for R_OV2

:

V_HYSO

R_OV2

=

20PA

(82)

To set V_TURN-OFF, solve for R_OV1

:

Boost

1.24V x R_OV2

R_OV1

Buck-Boost

R_OV1

=

V_TURN-OFF- 1.24V

(83)

1.24V x R_OV2

=

V_{TURN- OFF}- 620 mV

(84)

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Typical Applications (continued)

A small filter capacitor (C_OVP= 47 pF) should be added from the OVP pin to ground to reduce coupled switching

noise.

8.2.1.2.12 Input UVLO

For all topologies, input UVLO is programmed with the turn-on threshold voltage (V_TURN-ON) and the desired

hysteresis (V_HYS).

Method #1: If no PWM dimming is required, a two resistor network can be used. To set V_HYS, solve for R_UV2

:

V_HYS

20 PA

R_UV2

=

(85)

To set V_TURN-ON, solve for R_UV1

:

1.24Vx R_UV2

R_UV1

=

V_{TURN- ON}- 1.24V

(86)

Method #2: If PWM dimming is required, a three resistor network is suggested. To set V_TURN-ON, assume R_UV2

10 kΩ and solve for R_UV1as in Method #1. To set V_HYS, solve for R_UVH

=

:

(

)

R_UV1x V_HYS- 20 PA x R_UV2

R_UVH

=

(

)

20 PA x R_UV1+ R_UV2

(87)

8.2.1.2.13 PWM Dimming Method

PWM dimming can be performed several ways:

Method #1: Connect the dimming MosFET (Q₃) with the drain to the nDIM pin and the source to GND. Apply an

external PWM signal to the gate of Q_DIM. A pull down resistor may be necessary to properly turn off Q₃.

Method #2: Connect the anode of a Schottky diode to the nDIM pin. Apply an external inverted PWM signal to

the cathode of the same diode.

8.2.1.2.14 Analog Dimming Method

Analog dimming can be performed several ways:

Method #1: Place a potentiometer in series with the R_CSHresistor to dim the LED current from the nominal I_LED

to near zero.

Method #2: Connect a controlled current source as detailed in the Analog Dimming section to the CSH pin.

Increasing the current sourced into the CSH node will decrease the LEDs from the nominal I_LEDto zero current.

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Typical Applications (continued)

8.2.2 Buck-Boost Application - 6 LEDs at 1 A

L1

D1

10V ± 70V

V_IN

C

IN

R

T

R

HSN

1

2

3

4

5

6

7

14

13

12

11

HSN

HSP

IS

V

LM3429

IN

1A

I_LED

C

CMP

R

HSP

C

O

COMP

CSH

R

CSH

C

FS

R

SNS

C

T

RCT

V

CC

V_IN

C

BYP

R

FS

10

9

AGND

OVP

GATE

PGND

NC

Q1

R

OV2

R

UV2

R

LIM

Q2

V_IN

DAP

8

nDIM

C

R

OV1

OV

R

UV1

Figure 29. Buck-Boost Application - 6 LEDs at 1 A Schematic

8.2.2.1 Design Requirements

N = 6

V_LED= 3.5 V

r_LED= 325 mΩ

V_IN= 24 V

V_IN-MIN= 10 V

V_IN-MAX= 70 V

f_SW= 700 kHz

V_SNS= 100 mV

I_LED= 1A

Δi_L-PP= 500 mA

Δi_LED-PP= 50 mA

Δv_IN-PP= 100 mV

I_LIM= 6A

V_TURN-ON= 10 V

V_HYS= 3 V

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Typical Applications (continued)

V_TURN-OFF= 40 V

V_HYSO= 10 V

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Operating Point

Solve for V_Oand r_D:

V_ONx V

6x 3.5V 21V

=

LED

(88)

(89)

r_DN x r

6 x 325 m: 1.95:

=

LED

Solve for D, D', D_MAX, and D_MIN

:

V_O

21V

21V + 24V

D =

=

= 0.467

V_O+V

IN

(90)

(91)

D' 1- D 1- 0.467 0.533

=

V_O

21V

=

D_MIN

=

= 0.231

V_O+ V_IN-MAX

21V + 70V

(92)

(93)

V_O

=

21V

21V +10V

D_MAX

=

= 0.677

V_O+ V

IN-MIN

8.2.2.2.2 Switching Frequency

Assume C_T= 1 nF and solve for R_T:

25

f_SWx C_T

25

=

R_T=

= 35.7 k:

700 kHz x 1 nF

(94)

(95)

(96)

The closest standard resistor is actually 35.7 kΩ therefore the f_SWis:

25

R_Tx C_T

25

=

f_SW

=

= 700 kHz

35.7 k: x 1 nF

The chosen components from step 2 are:

C_T= 1 nF

R_T= 35.7 k:

8.2.2.2.3 Average LED Current

Solve for R_SNS

:

V

I_LED

100 mV

1A

SNS

R_SNS

0.1:

=

(97)

(98)

Assume R_CSH= 12.4 kΩ and solve for R_HSP

:

I_LEDxR_CSHx R_SNS

1.24V

1Ax12.4 k: x 0.1:

R_HSP

=

=1.0 k:

1.24V

The closest standard resistor for R_SNSis actually 0.1Ω and for R_HSPis actually 1 kΩ therefore I_LEDis:

1.24Vx R_HSP

R_SNSx R_CSH

1.24V x1.0 k:

0.1: x12.4 k:

I_LED

=

=1.0A

(99)

35

The chosen components from step 3 are:

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Typical Applications (continued)

R_SNS0.1:

=

R_CSH12.4 k:

=

R_HSP

R

1k:

=

HSN

(100)

8.2.2.2.4 Inductor Ripple Current

Solve for L1:

V x D

24Vx0.467

'i_L-PPx f_SW500 mA x700kHz

IN

32 PH

=

L1=

=

(101)

(102)

The closest standard inductor is 33 µH therefore the actual Δi_L-PPis:

V x D

24Vx 0.467

L1x f_SW33 PHx700 kHz

IN

485 mA

=

'i_{L- PP}

=

Determine minimum allowable RMS current rating:

§

¨

©

c·²

'i_L-PPx D

I

1

12

x

^LEDx 1+

¸

I_L-RMS

=

¸

I_LED

c

D

¹

2

1

12

x

485 mA x 0.533

1A

0.533

§

·

x 1+

¨

¸

I_L-RMS

=

1A

©

¹

1.88A

I_L-RMS

(103)

(104)

The chosen component from step 4 is:

L1= 33 PH

8.2.2.2.5 Output Capacitance

Solve for C_O:

I_LEDx D

C_O=

r_Dx 'i_LED-PPx f_SW

1A x 0.467

1.95: x 50 mA x700 kHz

=

= 6.84PF

C_O

(105)

The closest standard capacitor is 6.8 µF therefore the actual Δi_LED-PPis:

I_LEDx D

'i_LED-PP

=

r_Dx C_Ox f_SW

1A x 0.467

1.95: x x 700 kHz

'i_LED-PP

50 mA

=

6.8PF

(106)

(107)

Determine minimum allowable RMS current rating:

D_MAX

0.677

x

I

_CO-RMS=I_LED

=1A

=1.45A

1- D_MAX

1- 0.677

The chosen components from step 5 are:

C_O= 6.8PF

(108)

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Typical Applications (continued)

8.2.2.2.6 Peak Current Limit

Solve for R_LIM

:

245 mV 245 mV

R_LIM

=

= 0.041:

I_LIM

6A

(109)

The closest standard resistor is 0.04 Ω therefore I_LIMis:

245 mV 245 mV

I_LIM

=

= 6.13A

R_LIM

0.04:

(110)

(111)

The chosen component from step 6 is:

R_LIM= 0.04:

8.2.2.2.7 Loop Compensation

ω_P1is approximated:

1.467

r_Dx C_O1.95: x 6.8 PF

1 + D

rad

sec

=

= 110k

Z_P1

=

(112)

(113)

ω_Z1is approximated:

c²

1.95: x0.533²

rad

sec

r_Dx D

Z_Z1=

=

= 37k

DxL1 0.467x 33PH

T_U0is approximated:

c

0.533x620V

1.467x1A x 0.04:

D x 620V

T_U0=

=

= 5630

(

)

1 D xI_LEDx R_LIM

+

(114)

To ensure stability, calculate ω_P2:

rad

sec

37k

min(Z_P1,Z_Z1)

Z_Z1

rad

sec

Z_P2=

=

=1.173

5 xT_U0

5 x5630 5 x 5630

(115)

(116)

Solve for C_CMP

:

1

C_CMP

=

= 0.17µF

rad

Ѡ_P2×5×10⁶Ω

1.173

×5×10⁶Ω

sec

To attenuate switching noise, calculate ω_P3:

Z_P3max Z ,Z x10

Z_P1x10

=

P1

Z1

rad

sec

rad

sec

Z_P3110k

x10 1.1M

=

(117)

(118)

Assume R_FS= 10 Ω and solve for C_FS

:

1

C_FS

=

= 0.091PF

rad

sec

10:

x Z

P3

10: x

1.1M

The chosen components from step 7 are:

C_COMP= 0.22PF

R_FS=10:

C_FS= 0.1PF

(119)

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LM3429, LM3429-Q1

SNVS616H –APRIL 2009–REVISED JULY 2015

www.ti.com

Typical Applications (continued)

8.2.2.2.8 Input Capacitance

Solve for the minimum C_IN:

I_LEDx D

'v_IN-PPx f_SW

1A x 0.467

100 mV x 700kHz

C_IN=

=

= 6.66 PF

(120)

To minimize power supply interaction a 200% larger capacitance of approximately 14 µF is used, therefore the

actual Δv_IN-PPis much lower. Because high voltage ceramic capacitor selection is limited, three 4.7 µF X7R

capacitors are chosen.

Determine minimum allowable RMS current rating:

D_MAX

1- D_MAX

0.677

1- 0.677

x

I

_IN-RMS=I_LED

=1A

=1.45A

(121)

(122)

The chosen components from step 8 are:

C_IN= 3 x 4.7 PF

8.2.2.2.9 NFET

Determine minimum Q1 voltage rating and current rating:

V_T-MAX

V

70V 21V 91V

= + =

=

+

IN- MAX

O

(123)

(124)

0.677

1- 0.677

I_T-MAX

x1A 2.1A

=

A 100-V NFET is chosen with a current rating of 32A due to the low R_DS-ON= 50 mΩ. Determine I_T-RMSand P_T:

I_LED

1A

0.533

I_T-RMS

D

0.467 1.28A

x

=

x

=

c

D

(125)

(126)

P_T

I

²x R_DSON1.28A²x 50 m: 82 mW

= =

T- RMS

=

The chosen component from step 9 is:

Q1 o 32A, 100V, DPAK

(127)

8.2.2.2.10 Diode

Determine minimum D1 voltage rating and current rating:

_RD-MAX= V_IN-MAX+ V_O= 70V +21V = 91V

V

(128)

(129)

I_D-MAX

I

1A

=

LED

A 100-V diode is chosen with a current rating of 12 A and V_DF= 600 mV. Determine P_D:

I x V 1A x 600 mV 600 mW

P

=

FD

=

D

(130)

(131)

The chosen component from step 10 is:

D1 o 12A, 100V, DPAK

8.2.2.2.11 Input UVLO

Solve for R_UV2

:

38

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SNVS616H –APRIL 2009–REVISED JULY 2015

Typical Applications (continued)

V_HYS

3V

P

R_UV2

=

=150k:

P

20 A 20 A

(132)

(133)

The closest standard resistor is 150 kΩ therefore V_HYSis:

V_HYS

R

x20PA 150 k: x20 PA 3V

=

UV2

Solve for R_UV1

:

1.24Vx R_UV2

1.24Vx150k:

10V -1.24V

R_UV1

=

= 21.2 k:

V_{TURN- ON}-1.24V

(134)

The closest standard resistor is 21 kΩ making V_TURN-ON

:

(

)

1.24Vx R_UV1+ R_UV2

V_TURN-ON

=

R_UV1

(

)

1.24Vx 21k: +150k:

V_TURN-ON

= 10.1V

21k:

(135)

(136)

The chosen components from step 11 are:

R_UV121k:

=

R_UV2150 k:

=

8.2.2.2.12 Output OVLO

Solve for R_OV2

:

V_HYSO

10V

P

R_OV2

=

= 500k:

P

20 A 20 A

(137)

(138)

The closest standard resistor is 499 kΩ therefore V_HYSOis:

P

V_HYSO

R

x 20 A 499 k: x 20 A 9.98V

=

OV2

Solve for R_OV1

:

1.24Vx R_OV2

1.24Vx 499k:

40V - 0.62V

R_OV1

=

=15.7k:

V_TURN-OFF- 0.62V

(139)

The closest standard resistor is 15.8 kΩ making V_TURN-OFF

:

1.24V x (0.5 x R_OV1+ R_OV2

R_OV1

)

V_TURN-OFF

=

1.24V x (0.5 x 15.8 k: + 499 k:)

15.8 k:

= 39.8V

V_TURN-OFF

(140)

(141)

The chosen components from step 12 are:

R_OV1= 15.8 k:

R_OV2= 499 k:

Submit Documentation Feedback

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LM3429, LM3429-Q1

SNVS616H –APRIL 2009–REVISED JULY 2015

www.ti.com

Typical Applications (continued)

Table 1. Design 1 Bill of Materials

QTY

1

PART ID

LM3429

C_CMP

C_F

PART VALUE

MANUFACTURER

TI

PART NUMBER

Boost controller

0.22 µF X7R 10% 25 V

2.2 µF X7R 10% 16 V

0.1 µF X7R 10% 25 V

4.7 µF X7R 10% 100 V

6.8 µF X7R 10% 50 V

47 pF COG/NPO 5% 50 V

1000 pF COG/NPO 5% 50 V

Schottky 100 V 12 A

33 µH 20% 6.3 A

NMOS 100 V 32 A

PNP 150 V 600 m A

12.4 kΩ 1%

LM3429MH

1

MURATA

TDK

GRM21BR71E224KA01L

GRM21BR71C225KA12L

GRM21BR71E104KA01L

C5750X7R2A475K

C4532X7R1H685K

08055A470JAT2A

1

C_FS

3

C_IN

1

C_O

TDK

1

C_OV

AVX

1

C_T

MURATA

VISHAY

COILCRAFT

FAIRCHILD

VISHAY

GRM2165C1H102JA01D

12CWQ10FNPBF

1

D1

1

L1

MSS1278-333MLB

FDD3682

1

Q1

1

Q2

MMBT5401

1

R_CSH

R_FS

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW08051K00FKEA

WSL2512R0400FEA

CRCW080515K8FKEA

CRCW0805499KFKEA

WSL2512R1000FEA

CRCW080535K7FKEA

CRCW080521K0FKEA

CRCW0805150KFKEA

1

10 Ω 1%

2

R_HSP, R_HSN

R_LIM

R_OV1

R_OV2

R_SNS

R_T

1 kΩ 1%

1

0.04 Ω 1% 1W

1

15.8 kΩ 1%

1

499 kΩ 1%

1

0.1 Ω 1% 1W

1

35.7 kΩ 1%

1

R_UV1

R_UV2

21 kΩ 1%

1

150 kΩ 1%

8.2.2.3 Application Curve

100

95

90

85

80

75

70

0

16

32

48

(V)

64

80

V

IN

Figure 30. Buck-Boost Efficiency vs Input Voltage, V_O= 6 LEDs

40

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SNVS616H –APRIL 2009–REVISED JULY 2015

8.2.3 Boost PWM Dimming Application - 9 LEDs at 1 A

L1

D1

8V - 28V

V_IN

C

IN

R

T

R

HSN

1

2

3

4

5

6

7

14

13

12

11

HSN

HSP

IS

V

LM3429

IN

C

FS

R

SNS

C

R

HSP

CMP

COMP

CSH

R

FS

C

O

R

CSH

C

T

1A

I_LED

RCT

V

CC

C

BYP

10

9

AGND

OVP

GATE

PGND

NC

Q1

R

LIM

UV2

R

OV2

DAP

R

UVH

8

nDIM

R

C

OV

OV1

UV1

Q2

PWM

Figure 31. Boost PWM Dimming Application - 9 LEDs at 1 A Schematic

8.2.3.1 Detailed Design Procedure

Table 2. Design 2 Bill of Materials

QTY

1

PART ID

LM3429

C_CMP, C_FS

C_F

PART VALUE

MANUFACTURER

TI

PART NUMBER

Boost controller

0.1 µF X7R 10% 25 V

2.2 µF X7R 10% 16 V

6.8 µF X7R 10% 50 V

47 pF COG/NPO 5% 50 V

1000 pF COG/NPO 5% 50 V

Schottky 60 V 5 A

33 µH 20% 6.3 A

NMOS 60 V 8 A

NMOS 60 V 115 mA

12.4 kΩ 1%

LM3429MH

2

MURATA

TDK

GRM21BR71E104KA01L

GRM21BR71C225KA12L

C4532X7R1H685K

08055A470JAT2A

1

2, 1

1

C_IN, C_O

C_OV

AVX

1

C_T

MURATA

COMCHIP

COILCRAFT

VISHAY

ON SEMI

VISHAY

GRM2165C1H102JA01D

CDBC560-G

1

D1

1

L1

MSS1278-333MLB

SI4436DY

1

Q1

1

Q2

2N7002ET1G

2

R_CSH, R_OV1

R_FS

R_HSP, R_HSN

R_LIM

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW08051K00FKEA

WSL2512R0600FEA

CRCW0805499KFKEA

WSL2512R1000FEA

CRCW080535K7FKEA

CRCW08051K82FKEA

CRCW080510KFKEA

CRCW080517K8FKEA

1

10 Ω 1%

2

1 kΩ 1%

1

0.06 Ω 1% 1 W

499 kΩ 1%

1

R_OV2

R_SNS

R_T

1

0.1 Ω 1% 1 W

1

35.7 kΩ 1%

1

R_UV1

1.82 kΩ 1%

1

R_UV2

10 kΩ 1%

1

R_UVH

17.8 kΩ 1%

Submit Documentation Feedback

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SNVS616H –APRIL 2009–REVISED JULY 2015

www.ti.com

8.2.4 Buck-Boost Analog Dimming Application - 4 LEDs at 2A

L1

D1

10V ± 30V

V_IN

C

IN

R

T

2A

I_LED

R

HSN

1

2

3

4

5

6

7

14

13

12

11

HSN

HSP

IS

V

LM3429

IN

C

O

C

CMP

R

HSP

COMP

CSH

C

FS

R

SNS

R

CSH

V_IN

R

ADJ

R

FS

C

T

RCT

V

CC

C

BYP

10

AGND

OVP

GATE

PGND

NC

Q1

R

OV2

9

R

LIM

UV2

Q2

V_IN

DAP

8

nDIM

C

OV

R

OV1

UV1

Figure 32. Buck-Boost Analog Dimming Application - 4 LEDs at 2 A Schematic

8.2.4.1 Detailed Design Procedure

Table 3. Bill of Materials

QTY

1

PART ID

LM3429

C_CMP

C_F

PART VALUE

MANUFACTURER

PART NUMBER

Boost controller

1 µF X7R 10% 10 V

2.2 µF X7R 10% 16 V

0.1 µF X7R 10% 50 V

6.8 µF X7R 10% 50 V

47 pF COG/NPO 5% 50 V

1000 pF COG/NPO 5% 50 V

Schottky 60 V 5 A

22 µH 20% 7.2 A

NMOS 60 V 8 A

PNP 150 V 600 mA

1-MΩ potentiometer

12.4 kΩ 1%

TI

LM3429MH

1

MURATA

TDK

GRM21BR71A105KA01L

GRM21BR71C225KA12L

GRM21BR71E104KA01L

C4532X7R1H685K

08055A470JAT2A

GRM2165C1H102JA01D

CDBC560-G

1

C_FS

2, 1

1

C_IN, C_O

C_OV

AVX

1

C_T

MURATA

VISHAY

COILCRAFT

VISHAY

FAIRCHILD

BOURNS

VISHAY

1

D1

1

L1

MSS1278-223MLB

SI4436DY

1

Q1

1

Q2

MMBT5401

1

R_ADJ

R_CSH

R_FS

3352P-1-105

1

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW08051K00FKEA

WSL2512R0400FEA

CRCW080518K2FKEA

CRCW0805499KFKEA

WSL2512R0500FEA

CRCW080541K2FKEA

1

10 Ω 1%

2

R_HSP, R_HSN

R_LIM

R_OV1

R_OV2

R_SNS

R_T

1 kΩ 1%

1

0.04 Ω 1% 1 W

1

18.2 kΩ 1%

1

499 kΩ 1%

1

0.05 Ω 1% 1 W

1

41.2 kΩ 1%

42

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SNVS616H –APRIL 2009–REVISED JULY 2015

Table 3. Bill of Materials (continued)

QTY

PART ID

R_UV1

PART VALUE

MANUFACTURER

VISHAY

PART NUMBER

1

21 kΩ 1%

CRCW080521K0FKEA

CRCW0805150KFKEA

R_UV2

150 kΩ 1%

VISHAY

Submit Documentation Feedback

43

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LM3429, LM3429-Q1

SNVS616H –APRIL 2009–REVISED JULY 2015

www.ti.com

8.2.5 Boost Analog Dimming Application - 12 LEDs at 700 mA

L1

D1

18V - 38V

V_IN

C

IN

R

T

R

HSN

1

2

3

4

5

6

7

14

13

12

11

HSN

HSP

IS

V

LM3429

IN

C

R

FS

R

SNS

C

R

HSP

CMP

COMP

CSH

V_REF

FS

Q4

Q3

R

MAX

C

O

C

T

Q2

R

RCT

V

CC

C

700 mA

I_LED

BYP

R

CSH

R

ADJ

BIAS

10

9

AGND

OVP

GATE

PGND

NC

Q1

V_IN

R

LIM

R

OV2

R

UV2

R

UV1

DAP

8

nDIM

C

OV

OV1

Figure 33. Boost Analog Dimming Application - 12 LEDs at 700 mA Schematic

8.2.5.1 Detailed Design Procedure

Table 4. Bill of Materials

QTY

1

PART ID

PART VALUE

MANUFACTURER

PART NUMBER

LM3429

Boost controller

TI

LM3429MH

1

C_CMP

1 µF X7R 10% 10 V

2.2 µF X7R 10% 16 V

0.1 µF X7R 10% 50 V

6.8 µF X7R 10% 50 V

47 pF COG/NPO 5% 50 V

1000 pF COG/NPO 5% 50 V

Schottky 100 V 12 A

47 µH 20% 5.3 A

NMOS 100 V 32 A

NPN 40 V 200 mA

Dual PNP 40 V 200 mA

100 kΩ potentiometer

40.2 kΩ 1%

MURATA

TDK

GRM21BR71A105KA01L

GRM21BR71C225KA12L

GRM21BR71E104KA01L

C4532X7R1H685K

08055A470JAT2A

GRM2165C1H102JA01D

12CWQ10FNPBF

1

C_F

1

C_FS

2, 1

1

C_IN, C_O

C_OV

AVX

1

C_T

MURATA

VISHAY

COILCRAFT

FAIRCHILD

BOURNS

VISHAY

1

D1

1

L1

MSS1278-473MLB

FDD3682

1

Q1

1

Q2

MMBT3904

1

Q3, Q4 (dual pack)

FFB3906

1

R_ADJ

3352P-1-104

1

R_BIAS

CRCW080540K2FKEA

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW08051K05FKEA

WSL2512R0600FEA

CRCW08054K99FKEA

CRCW0805499KFKEA

WSL2512R1500FEA

1

R_CSH, R_OV1, R_UV1

R_FS

R_HSP, R_HSN

R_LIM

12.4 kΩ 1%

1

10 Ω 1%

2

1.05 kΩ 1%

1

0.06 Ω 1% 1 W

1

R_MAX

4.99 kΩ 1%

1

R_OV2

499 kΩ 1%

1

R_SNS

0.15 Ω 1% 1 W

44

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SNVS616H –APRIL 2009–REVISED JULY 2015

Table 4. Bill of Materials (continued)

QTY

PART ID

R_T

PART VALUE

MANUFACTURER

PART NUMBER

CRCW080535K7FKEA

CRCW0805100KFKEA

LM4040

1

35.7 kΩ 1%

VISHAY

TI

R_UV2

V_REF

100 kΩ 1%

5 V precision reference

Submit Documentation Feedback

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LM3429, LM3429-Q1

SNVS616H –APRIL 2009–REVISED JULY 2015

www.ti.com

8.2.6 Buck-Boost PWM Dimming Application - 6 LEDs at 500 mA

L1

D1

10V ± 70V

V_IN

C

IN

R

T

R

HSN

1

2

3

4

5

6

7

14

13

12

11

HSN

HSP

IS

V

LM3429

IN

500 mA

I_LED

C

CMP

R

HSP

C

O

COMP

CSH

R

CSH

C

FS

R

SNS

C

T

RCT

V

CC

V_IN

C

BYP

R

FS

10

9

AGND

OVP

GATE

PGND

NC

Q1

R

OV2

R

UV2

Q2

V_IN

DAP

R

UVH

8

nDIM

D2

C

R

OV1

OV

R

UV1

PWM

Figure 34. Buck-Boost PWM Dimming Application - 6 LEDs at 500 mA

8.2.6.1 Detailed Design Procedure

Table 5. Bill of Materials

QTY

1

PART ID

LM3429

C_CMP

C_F

PART VALUE

MANUFACTURER

PART NUMBER

LM3429MH

Boost controller

TI

1

0.68 µF X7R 10% 25 V

2.2 µF X7R 10% 16 V

0.1 µF X7R 10% 25 V

4.7 µF X7R 10% 100 V

6.8 µF X7R 10% 50 V

47 pF COG/NPO 5% 50 V

1000 pF COG/NPO 5% 50 V

Schottky 100 V 12 A

Schottky 30 V 500 mA

68 µH 20% 4.3 A

NMOS 100 V 32 A

PNP 150 V 600 mA

12.4 kΩ 1%

MURATA

TDK

GRM21BR71E684KA88L

GRM21BR71C225KA12L

GRM21BR71E104KA01L

C5750X7R2A475K

C4532X7R1H685K

08055A470JAT2A

1

C_FS

3

C_IN

1

C_O

TDK

1

C_OV

AVX

1

C_T

MURATA

VISHAY

ON SEMI

COILCRAFT

VISHAY

FAIRCHILD

VISHAY

GRM2165C1H102JA01D

12CWQ10FNPBF

1

D1

1

D2

BAT54T1G

1

L1

MSS1278-683MLB

FDD3682

1

Q1

1

Q2

MMBT5401

1

R_CSH

R_FS

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW08051K00FKEA

CRCW080515K8FKEA

CRCW0805499KFKEA

WSL2512R2000FEA

CRCW080535K7FKEA

CRCW08051K43FKEA

CRCW080510K0FKEA

1

10 Ω 1%

2

R_HSP, R_HSN

R_OV1

R_OV2

R_SNS

R_T

1 kΩ 1%

1

15.8 kΩ 1%

1

499 kΩ 1%

1

0.2 Ω 1% 1 W

1

35.7 kΩ 1%

1

R_UV1

R_UV2

1.43 kΩ 1%

1

10 kΩ 1%

46

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LM3429, LM3429-Q1

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SNVS616H –APRIL 2009–REVISED JULY 2015

Table 5. Bill of Materials (continued)

QTY

PART ID

PART VALUE

17.4 kΩ 1%

MANUFACTURER

PART NUMBER

1

R_UVH

VISHAY

CRCW080517K4FKEA

Submit Documentation Feedback

47

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LM3429, LM3429-Q1

SNVS616H –APRIL 2009–REVISED JULY 2015

www.ti.com

8.2.7 Buck Application - 3 LEDS at 1.25 A

15V ± 50V

V_IN

C

IN

R

HSN

1

2

3

4

5

6

7

14

13

12

11

HSN

HSP

IS

V

LM3429

IN

C

R

T

FS

R

SNS

R

HSP

C

O

COMP

CSH

C

CMP

FS

D1

1.25A

I_LED

R

CSH

RCT

V

CC

L1

C

T

C

BYP

10

9

AGND

OVP

GATE

PGND

NC

Q1

R

OV2

R

LIM

UV2

Q2

DAP

8

nDIM

C

R

OV

OV1

UV1

Figure 35. Buck Application - 3 LEDS at 1.25 A Schematic

8.2.7.1 Detailed Design Procedure

Table 6. Bill of Materials

QTY

1

PART ID

LM3429

C_CMP

C_F

PART VALUE

MANUFACTURER

PART NUMBER

Boost controller

TI

LM3429MH

1

0.015 µF X7R 10% 50 V

2.2 µF X7R 10% 16 V

0.01 µF X7R 10% 50 V

6.8 µF X7R 10% 50 V

1 µF X7R 10% 50 V

47 pF COG/NPO 5% 50 V

1000 pF COG/NPO 5% 50 V

Schottky 60V 5 A

22 µH 20% 7.3 A

NMOS 60 V 8 A

PNP 150 V 600 mA

12.4 kΩ 1%

MURATA

TDK

GRM21BR71H153KA01L

GRM21BR71C225KA12L

GRM21BR71H103KA01L

C4532X7R1H685K

C4532X7R1H105K

08055A470JAT2A

1

C_FS

2

C_IN

1

C_O

TDK

1

C_OV

AVX

1

C_T

MURATA

COMCHIP

COILCRAFT

VISHAY

FAIRCHILD

VISHAY

GRM2165C1H102JA01D

CDBC560-G

1

D1

1

L1

MSS1278-223MLB

SI4436DY

1

Q1

1

Q2

MMBT5401

1

R_CSH

R_T

CRCW080512K4FKEA

CRCW080549K9FKEA

CRCW080510R0FKEA

CRCW08051K00FKEA

WSL2512R0400FEA

CRCW080521K5FKEA

CRCW0805499KFKEA

WSL2512R0800FEA

1

49.9 kΩ 1%

1

R_FS

10 Ω 1%

2

R_HSP, R_HSN

R_LIM

R_OV1

R_OV2

R_SNS

1 kΩ 1%

1

0.04 Ω 1% 1 W

1

21.5 kΩ 1%

1

499 kΩ 1%

1

0.08 Ω 1% 1 W

48

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SNVS616H –APRIL 2009–REVISED JULY 2015

Table 6. Bill of Materials (continued)

QTY

PART ID

R_UV1

PART VALUE

MANUFACTURER

VISHAY

PART NUMBER

1

11.5 kΩ 1%

100 kΩ 1%

CRCW080511K5FKEA

CRCW0805100KFKEA

R_UV2

VISHAY

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8.2.8 Buck-Boost Thermal Foldback Application - 8 LEDs at 2.5 A

L1

D1

15V ± 60V

V_IN

V_REF

C

IN

R

T

R

HSN

1

2

3

4

5

6

7

14

13

12

11

R

GAIN

HSN

HSP

IS

V

LM3429

IN

2.5A

I_LED

C

R

HSP

CMP

R

NTC

COMP

CSH

C

O

D2

R

BIAS

C

T

CSH

RCT

V

CC

C

BYP

R

SNS

C

FS

10

9

AGND

OVP

GATE

PGND

NC

Q1

R

V_IN

R

FS

R

OV2

LIM

R

UV2

Q2

V_IN

DAP

8

nDIM

C

OV

OV1

R

UV1

Figure 36. Buck-Boost Thermal Foldback Application - 8 LEDs at 2.5 A Schematic

8.2.8.1 Detailed Design Procedure

Table 7. Bill of Materials

QTY

1

PART ID

LM3429

C_CMP

C_F

PART VALUE

MANUFACTURER

PART NUMBER

Boost controller

TI

LM3429MH

1

0.1 µF X7R 10% 25 V

2.2 µF X7R 10% 16 V

0.1 µF X7R 10% 25 V

4.7 µF X7R 10% 100 V

6.8 µF X7R 10% 50 V

47 pF COG/NPO 5% 50 V

1000 pF COG/NPO 5% 50 V

Schottky 100 V 12 A

22 µH 20% 7.2 A

NMOS 100 V 32 A

PNP 150 V 600 mA

12.4 kΩ 1%

MURATA

TDK

GRM21BR71E104KA01L

GRM21BR71C225KA12L

GRM21BR71E104KA01L

C5750X7R2A475K

1

C_FS

3

C_IN

1

C_O

TDK

C4532X7R1H685K

08055A470JAT2A

1

C_OV

AVX

1

C_T

MURATA

VISHAY

COILCRAFT

FAIRCHILD

VISHAY

GRM2165C1H102JA01D

12CWQ10FNPBF

1

D1

1

L1

MSS1278-223MLB

1

Q1

FDD3682

1

Q2

MMBT5401

2

R_CSH, R_OV1

R_FS

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW08051K00FKEA

WSL2512R0400FEA

CRCW0805499KFKEA

CRCW080549K9FKEA

CRCW080513K7FKEA

CRCW0805150KFKEA

1

10 Ω 1%

2

R_HSP, R_HSN

R_LIM, R_SNS

R_OV2

R_T

1 kΩ 1%

2

0.04 Ω 1% 1 W

1

499 kΩ 1%

1

49.9 kΩ 1%

1

R_UV1

R_UV2

13.7 kΩ 1%

1

150 kΩ 1%

50

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SNVS616H –APRIL 2009–REVISED JULY 2015

8.2.9 SEPIC Application - 5 LEDs at 750 mA

L1

9V - 36V

C

SEP

D1

V_IN

L2

C

IN

R

T

R

HSN

1

2

3

4

5

6

7

14

13

12

11

HSN

HSP

IS

V

LM3429

IN

C

FS

R

SNS

C

R

HSP

CMP

COMP

CSH

R

FS

C

O

R

CSH

C

T

RCT

V

CC

750 mA

I_LED

C

BYP

10

9

AGND

OVP

GATE

PGND

NC

Q1

R

UV2

R

OV2

DAP

8

nDIM

C

OV

OV1

UV1

Figure 37. 5 LEDs at 750 mA

Table 8. Bill of Materials

8.2.9.1 Detailed Design Procedure

QTY

1

PART ID

LM3429

C_CMP

C_F

PART VALUE

MANUFACTURER

TI

PART NUMBER

Boost controller

LM3429MH

1

0.47 µF X7R 10% 25 V

2.2 µF X7R 10% 16 V

0.1 µF X7R 10% 25 V

6.8 µF X7R 10% 50 V

47 pF COG/NPO 5% 50 V

1 µF X7R 10% 100 V

1000 pF COG/NPO 5% 50 V

Schottky 60 V 5 A

68 µH 20% 4.3 A

NMOS 60 V 8 A

NMOS 60 V 115 mA

12.4 kΩ 1%

MURATA

TDK

GRM21BR71E474KA01L

GRM21BR71C225KA12L

GRM21BR71E104KA01L

C4532X7R1H685K

08055A470JAT2A

1

C_FS

2, 1

1

C_IN, C_O

C_OV

AVX

1

C_SEP

C_T

TDK

C4532X7R2A105K

GRM2165C1H102JA01D

CDBC560-G

1

MURATA

COMCHIP

COILCRAFT

VISHAY

ON SEMI

VISHAY

1

D1

1

L1, L2

Q1

DO3340P-683

1

SI4436DY

1

Q2

2N7002ET1G

1

R_CSH

R_FS

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW0805750RFKEA

WSL2512R0400FEA

CRCW080515K8FKEA

CRCW0805499KFKEA

WSL2512R1000FEA

CRCW080549K9FKEA

1

10 Ω 1%

2

R_HSP, R_HSN

R_LIM

750 Ω 1%

1

0.04 Ω 1% 1 W

2

R_OV1, R_UV1

R_OV2

R_SNS

R_T

15.8 kΩ 1%

1

499 kΩ 1%

1

0.1 Ω 1% 1 W

1

49.9 kΩ 1%

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www.ti.com

Table 8. Bill of Materials (continued)

QTY

PART ID

PART VALUE

100 kΩ 1%

MANUFACTURER

PART NUMBER

1

R_UV2

VISHAY

CRCW0805100KFKEA

52

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SNVS616H –APRIL 2009–REVISED JULY 2015

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 4.5 V to 75 V. This input supply

should be well regulated. If the input supply is located more than a few inches from the EVM or PCB, additional

bulk capacitance may be required in addition to the ceramic bypass capacitors.

9.1 Input Supply Current Limit

It is important to set the output current limit of your input supply to an appropriate value to avoid delays in your

converter analysis and optimization. If not set high enough, current limit can be tripped during start-up or when

your converter output power is increased, causing a foldback or shut-down condition. It is a common oversight

when powering up a converter for the first time.

10 Layout

10.1 Layout Guidelines

The performance of any switching regulator depends as much upon the layout of the PCB as the component

selection. Following a few simple guidelines will maximimize noise rejection and minimize the generation of EMI

within the circuit.

Discontinuous currents are the most likely to generate EMI; therefore, take care when routing these paths. The

main path for discontinuous current in the LM3429 buck regulator contains the input capacitor (C_IN), the

recirculating diode (D1), the N-channel MosFET (Q1), and the switch sense resistor (R_LIM). In the LM3429 boost

and buck-boost regulators, the discontinuous current flows through the output capacitor (C_O), D1, Q1, and R_LIM

.

In either case, this loop should be kept as small as possible and the connections between all the components

should be short and thick to minimize parasitic inductance. In particular, the switch node (where L1, D1 and Q1

connect) should be just large enough to connect the components. To minimize excessive heating, large copper

pours can be placed adjacent to the short current path of the switch node.

The RCT, COMP, CSH, IS, HSP and HSN pins are all high-impedance inputs which couple external noise easily,

therefore the loops containing these nodes should be minimized whenever possible.

In some applications the LED or LED array can be far away (several inches or more) from the LM3429, or on a

separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large or

separated from the rest of the regulator, the output capacitor should be placed close to the LEDs to reduce the

effects of parasitic inductance on the AC impedance of the capacitor.

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10.2 Layout Example

Note critical paths and component placement:

Minimize power loop containing discontinuous currents

Minimize signal current loops (components close to IC)

xꢀ Ground plane under IC for signal routing helps minimize noise coupling

discontinuous switching

frequency currents

L1

D1

V_IN

Input

C_IN

R_T

Power

R_HSN

1

2

3

4

5

6

7

14

13

12

11

V_IN

LM3429

HSN

HSP

IS

GND

R_SNS

C_FS

C_CMP

R_CSH

C_T

R_HSP

C_O

COMP

R_FS

I_LED

CSH

RCT

V_CC

C_BYP

10

STAR GROUND

AGND

OVP

nDIM

GATE

PGND

NC

Q1

R_UV2

9

R_LIM

R_OV2

DAP

R_UVH

8

C_OV

R_OV1

R_UV1

PWM

Q3

Power Ground

Figure 38. LM3429 Layout Guideline

54

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SNVS616H –APRIL 2009–REVISED JULY 2015

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

•

AN-1986 LM3429 Boost Evaluation Board, SNVA404

AN-1985 LM3429 Buck-Boost Evaluation Board, SNVA403

11.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 9. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

LM3429

Click here

LM3429-Q1

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

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11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

56

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PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM3429MHX/NOPB

HTSSOP PWP

14

2500

330.0

12.4

6.95

5.6

1.6

8.0

12.0

Q1

LM3429Q1MHX/NOPB HTSSOP PWP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM3429MHX/NOPB

HTSSOP

PWP

14

2500

367.0

35.0

LM3429Q1MHX/NOPB

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

LM3429MH/NOPB

PWP

HTSSOP

14

94

495

8

2514.6

4.06

LM3429Q1MH/NOPB

Pack Materials-Page 3

PACKAGE OUTLINE

PWP0014A

PowerPAD^TMTSSOP - 1.2 mm max height

S

C

A

L

E

2

.

4

0

PLASTIC SMALL OUTLINE

C

6.6

6.2

TYP

SEATING PLANE

PIN 1 ID

AREA

A

0.1 C

12X 0.65

14

1

2X

5.1

4.9

3.9

NOTE 3

7

8

0.30

14X

0.19

4.5

4.3

B

0.1

C A B

SEE DETAIL A

(0.15) TYP

4X (0.2)

NOTE 5

4X (0.05)

NOTE 5

8

7

THERMAL

PAD

0.25

GAGE PLANE

3.255

3.205

15

1.2 MAX

0.15

0.05

0 - 8

14

1

0.75

0.50

DETAIL A

(1)

TYPICAL

3.155

3.105

4214867/A 09/2016

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ and may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0014A

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.4)

NOTE 9

(3.155)

SYMM

SOLDER MASK

DEFINED PAD

SEE DETAILS

14X (1.5)

1

14

14X (0.45)

(1.1)

TYP

15

SYMM

(3.255)

(5)

NOTE 9

12X (0.65)

8

7

(

0.2) TYP

VIA

(R0.05) TYP

(1.1) TYP

METAL COVERED

BY SOLDER MASK

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-14

4214867/A 09/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0014A

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.155)

BASED ON

0.125 THICK

STENCIL

14X (1.5)

(R0.05) TYP

1

14

14X (0.45)

15

(3.255)

BASED ON

0.125 THICK

STENCIL

SYMM

12X (0.65)

8

7

SEE TABLE FOR

METAL COVERED

BY SOLDER MASK

SYMM

(5.8)

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.53 X 3.64

3.155 X 3.255 (SHOWN)

2.88 X 2.97

0.125

0.15

0.175

2.67 X 2.75

4214867/A 09/2016

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM3429MHX/NOPB
厂家：	TEXAS INSTRUMENTS
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