LM34919 [TI]
Ultra-Small 40-V 600-mA Constant On-Time Buck Switching Regulator;
| 型号： | LM34919 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Ultra-Small 40-V 600-mA Constant On-Time Buck Switching Regulator |
| 文件： | 总29页 (文件大小：1296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM34919C-Q1
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SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
LM34919C-Q1 Ultra Small 50V, 600 mA Constant On-Time Buck Switching Regulator
Check for Samples: LM34919C-Q1
1
FEATURES
APPLICATIONS
2
•
AEC-Q100 qualified (Tj = -40°C to 125°C)
Maximum Switching Frequency: 2.6 MHz
Input Voltage Range: 4.5 V to 50 V
Integrated N-Channel buck switch
Integrated Start-Up Regulator
•
•
•
•
Automotive Safety and Infotainment
High Efficiency Point-of-Load (POL) Regulator
Telecommunication Buck Regulator
Secondary Side Post Regulator
•
•
•
•
•
•
•
DESCRIPTION
No Loop Compensation Required
Ultra-Fast Transient Response
The LM34919C Step Down Switching Regulator
features all of the functions needed to implement a
low-cost, efficient, buck bias regulator capable of
supplying 0.6 A to the load. This buck regulator
contains an N-Channel Buck Switch and is available
in DSBGA and WSON packages. The constant on-
time feedback regulation scheme requires no loop
compensation, results in fast load transient response,
and simplifies circuit implementation. The operating
frequency remains constant with line and load
variations due to the inverse relationship between the
input voltage and the on-time. The valley current limit
results in a smooth transition from constant voltage to
constant current mode when current limit is detected,
reducing the frequency and output voltage, without
the use of foldback. Additional features include:
Power Good, enable, VCC undervoltage lockout,
thermal shutdown, gate drive undervoltage lockout,
and maximum duty cycle limiter.
Operating Frequency Remains Constant with
Load Current and Input Voltage
•
•
•
•
•
•
•
•
•
Adjustable Output Voltage
Power Good Output
Enable Input
Valley Current Limit at 0.64 A Typical
Precision Internal Voltage Reference
Low IQ Shutdown (<10 µA)
Highly Efficient Operation
Thermal Shutdown
12-Bump 2 mm x 2 mm DSBGA and 12-pin 4
mm x 4 mm WSON Packages
4.5V - 50V
Input
VIN
VCC
C3
C1
C5
REN
RON
LM34919C
BST
RON
EN
VOUT
C4
L1
RPGD
PGD
VOUT
SW
PGD
SS
D1
R1
R2
R3
C2
ISEN
FB
C6
RTN
SGND
Figure 1. Basic Step Down Regulator
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
LM34919C-Q1
SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
VALUE
65
UNIT
V
VIN, EN , RON to RTN
BST to RTN
79
V
SW to RTN (Steady State)
SW to VIN
–1.5 to 65
+0.3
V
V
BST to VCC
65
V
BST to SW
14
V
VCC to RTN
14
V
PGD
14
V
SGND to RTN
SS to RTN
–0.3 to 0.3
–0.3 to 4
–0.3 to 7
–65 to 150
2
V
V
FB to RTN
V
Storage Temperature Range
ESD Rating HBM
Junction Temperature
ºC
kV
ºC
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the devices at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1)
Recommended Operating Conditions
VALUE
4.5 to 50
−40 to 125
UNIT
V
VIN
Junction Temperature
°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which the
device is intended to be fully functional. For verified specifications and test conditions, see Electrical Characteristics.
2
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Electrical Characteristics
Unless otherwise specified, these specifications apply for –40°C ≤ TJ ≤ +125°C, VIN = 12 V, RON = 100 kΩ. Typical values
represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
Symbol
Parameter
Conditions
Min Typ Max
Units
EN Power Up Feature (EN Pin)
EN
ISD
EN Threshold
EN rising
2.1
1.3
10
3.0
V
V
EN Disable Threshold EN falling
0.5
6.1
EN Input Current
EN = VIN = 12 V
EN = 0 V
50
8
µA
VIN Shutdown
Current
1
µA
Start-Up Regulator, VCC
VCCReg
VCC Regulated Output VIN = 12 V
VIN =4.5 V, ICC = 3 mA
7
7.6
V
V
4.43
VIN – VCC Dropout
Voltage
ICC = 0 mA, Non-Switching
VCC = UVLOVCC + 250 mV
20
mV
VCC Output
Impedance
0 mA ≤ ICC ≤ 5 mA, VIN = 4.5 V
0 mA ≤ ICC ≤ 5 mA, VIN = 8 V
VCC = 0 V
16
8
Ω
VCC Current Limit
27
mA
UVLOVCC
VCC Under-Voltage
Lockout Threshold
Measured at VCC
VCC Increasing
3.4 3.75 4.1
3.25 3.6 3.95
V
VCC Decreasing
UVLOVCC Hysteresis,
at VCC
150
mV
VCC Under-Voltage
Lock-Out Threshold
Measured at VIN
VIN Increasing, ICC = 3 mA
VIN Decreasing, ICC = 3 mA
3.90 4.50
V
VCC Under-Voltage
Lock-Out Threshold
Measured at VIN
3.80 4.25
3
UVLOVCC Filter Delay 100 mV Overdrive
µs
IQ
IIN Operating Current Non-Switching, FB = 3 V, SW = Open
2.2
3.8
mA
Switch Characteristics
Rds(on)
Buck Switch Rds(on) ITEST = 200 mA
(DSBGA)
0.35 0.9
0.45
Ω
Buck Switch Rds(on) ITEST = 200 mA
(WSON-12)
1
UVLOGD
Gate Drive UVLO
UVLOGD Hysteresis
Pull-Up Voltage
VBST - VSW Increasing
VBST - VSW Decreasing
2.40 2.95 3.60
V
2.82
130
mV
Soft-start Pin
VSS
2.52
10.5
V
Internal Current
Source
VSS = 1V
µA
Current Limit
ILIM
Threshold
Current out of ISEN
0.52 0.64 0.76
A
Resistance from ISEN
to SGND
190
50
mΩ
ns
Response Time
On Timer
tON - 1
On-Time
On-Time
On-Time
VIN = 12 V, RON = 100 kΩ
VIN = 24 V, RON = 100 kΩ
VIN = 4.5 V, RON = 100 kΩ
300
175
760
tON - 2
ns
ns
tON - 3
Off Timer
tOFF
Minimum Off-time
100 120 150
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Electrical Characteristics (continued)
Unless otherwise specified, these specifications apply for –40°C ≤ TJ ≤ +125°C, VIN = 12 V, RON = 100 kΩ. Typical values
represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
Symbol
Parameter
Conditions
Min Typ Max
Units
Regulation and Over-Voltage Comparators (FB Pin)
VREF
FB Regulation
Threshold
SS pin = Steady State
2.47 2.52 2.57
V
FB Over-Voltage
Threshold
3.0
1
FB Bias Current
FB = 3 V
nA
Power Good Feature (PGD Pin)
PGDUV PGD UV Threshold
FB Increasing
Rising, With Respect
to VREF
87
92
97
PGD UV Threshold
Falling
FB Decreasing
FB Increasing
FB Decreasing
90
%
PGDOV
PGD OV Threshold
Rising
120
PGD OV Threshold
Falling
110
10
Td, PGD
PGD Delay
Falling Edge
us
IPGD
PGD Pulldown
Vin = 4.5 V, FB = 3 V, Vpg = 0.1 V
1
mA
Thermal Shutdown
TSD
Thermal Shutdown
Temperature
175
20
°C
Thermal Shutdown
Hysteresis
Thermal Resistance
θJA
Junction to Ambient
0 LFPM Air Flow
61
50
(DSBGA Packages)
°C/W
For WSON Package
(Exposed Pad)
4
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SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
PIN DESCRIPTIONS
D1
C1
B1
A1
D2
C2
B2
A2
D3
C3
B3
A3
Figure 2. DSBGA Package Bump View
BST
VCC
SS
SW
EN
VIN
ISEN
SGND
RON
PGD
RTN
FB
Figure 3. DSBGA Package Top View
VIN
ISEN
EN
1
2
3
4
5
6
12 SW
11
BST
10 VCC
WSON-12
Exposed
Pad
SGND
RTN
9
8
7
PGD
SS
RON
FB
Figure 4. WSON Top View
Pin Descriptions
DESCRIPTION
PIN
NUMBER
PIN NUMBER
(WSON-12)
NAME
APPLICATION INFORMATION
A1
A2
A3
6
5
7
RON
On-time control and shutdown
An external resistor from VIN to this pin sets the
buck switch on-time.
RTN
FB
Circuit Ground
Ground for all internal circuitry other than the current
limit detection.
Feedback input from the
regulated output
Internally connected to the regulation and
overvoltage comparators. The regulation level is
2.52 V (typ.).
B1
4
SGND
Sense Ground
Re-circulating current flows into this pin to the
current sense resistor.
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Pin Descriptions (continued)
PIN
NUMBER
PIN NUMBER
(WSON-12)
NAME
DESCRIPTION
APPLICATION INFORMATION
B2
9
PGD
Power Good
Open drain. Logic output indicates when the voltage
at the FB pin has increased above 92% of the
internal reference. The falling threshold for PGD is
90% of the internal reference. An external pull-up
resistor connecting PGD pin to a voltage less than
14 V is required.
B3
C1
8
2
SS
Soft-start
An internal current source charges an external
capacitor to 2.52 V, providing the soft-start function.
ISEN
Current sense
The re-circulating current flows through the internal
sense resistor and out of this pin to the free-
wheeling diode. Valley current limit is nominally set
at 0.64 A.
C2
C3
3
EN
Enable Pin
Pull low to disable the part for low shutdown current.
Shutdown threshold is 1.3 V (typ).
10
VCC
Output from the startup regulator Nominally regulated at 7.0 V. An external voltage (7
V - 14 V) can be applied to this pin to reduce
internal dissipation. An internal diode connects VCC
to VIN.
D1
D2
1
VIN
SW
Input supply voltage
Switching Node
Nominal input range is 4.5 V to 50 V.
12
Internally connected to the buck switch source.
Connects to the inductor, free-wheeling diode, and
bootstrap capacitor.
D3
11
BST
Boost pin for bootstrap capacitor Connect a 0.022 µF capacitor from SW to this pin.
The capacitor is charged from VCC via an internal
diode during each off-time.
EP (WSON Only)
Exposed pad should be connected to RTN pin and
system ground for proper cooling.
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SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
4.5V to 50V
Input
LM34919C
7V SERIES
REGULATOR
VIN
VCC
C5
C1
VCC
UVLO
C3
RON
GND
ON TIMER
OFF TIMER
RON
RON
START
FINISH
START
FINISH
2.1V
BST
SD
Gate Drive
UVLO
EN
SS
VIN
2.52V
10.5 µA
C4
LOGIC
Driver
C6
LEVEL
SHIFT
L1
SW
FB
VOUT
THERMAL
SHUTDOWN
REGULATION
D1
COMPARATOR
CURRENT LIMIT
COMPARATOR
R1
R3
C2
0.92VREF
+
-
ISEN
RSENSE
-
+
100 mꢀ
R2
64 mV
SGND
RTN
UNDER-VOLTAGE
COMPARATOR
1.2VREF
GND
RPGD
Power
Good
OVER-VOLTAGE
COMPARATOR
PGD
Figure 5. Functional Block Diagram
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Typical Performance Characteristics
Efficiency at 2.1 MHz, VOUT = 3.3 V
Efficiency at 250 kHz, VOUT = 3.3 V
90
80
70
95
90
85
80
75
70
Vin = 4.5V
Vin = 6V
Vin = 9V
Vin = 12V
Vin = 18V
Vin = 24V
Vin = 6V
Vin = 9V
Vin = 12V
Vin = 18V
60
0.2
0.2
0
0.3
0.4
0.5
0.6
0.2
0.3
0.4
0.5
0.6
LOAD CURRENT (A)
LOAD CURRENT (A)
VCC vs. VIN
C002
C002
Efficiency at 2.1 MHz, VOUT = 5 V
95
10
8
85
75
65
6
4
Vin = 9V
2
Vin = 12V
Vin = 18V
Vin = 24V
0
0.3
0.4
0.5
0.6
0
5
10
15
20
25
30
35
40
45
50
LOAD CURRENT (A)
VCC vs. ICC
INPUT VOLTAGE (V)
C003
C004
ICC vs. Externally Applied VCC
10
8
8
7
6
5
4
3
2
1
0
Vin = 4.5V
Vin = 12V
6
4
2
Vcc Externally Loaded
Fsw = 2 MHz
Fsw = 2 MHz
8
0
5
10
15
20
25
30
7
9
10
11
12
13
14
ICC (mA)
APPLIED VCC (V)
C005
C006
8
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Typical Performance Characteristics (continued)
ON-TIME vs. VIN and RON
Voltage at the RON Pin
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1000
Ron = 100k
Ron = 61.9k
Ron = 35.7K
Ron = 46.4k
Ron = 100kꢀ
Ron = 61.9kꢀ
Ron = 46.4kꢀ
100
10
0
10
20
30
40
50
0
10
20
30
40
50
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
C007
C001
Operating Current into VIN
Shutdown Current into VIN
6.00
5.00
4.00
3.00
2.00
1.00
0.00
0.20
0.15
0.10
0.05
0.00
No Load
FB = 3V
EN = 0V
5
0
5
10
15
20
25
30
35
40
45
50
0
10
15
20
25
30
35
40
45
50
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
C002
C006
Gate Drive UVLO vs. Temperature
Reference Voltage vs. Temperature
4.0
3.5
3.0
2.5
2.0
2.57
2.56
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
Driver On
Driver Off
Vin = 12V
0
25
50
75
100
125
150
0
25
50
75
100
125
150
±50
±25
±50
±25
JUNCTION TEMPERATURE (|C)
JUNCTION TEMPERATURE (|C)
C004
C007
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Typical Performance Characteristics (continued)
Soft-Start Current vs. Temperature
Operating Current vs. Temperature
11.5
11.0
10.5
10.0
9.5
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
VIN = 12V
Vin = 12V
±50 ±25
9.0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
±50
±25
JUNCTION TEMPERATURE (|C)
JUNCTION TEMPERATURE (|C)
C001
C008
VCC UVLO at Vin vs. Temperature
VCC Voltage vs. Temperature
4.50
4.25
4.00
3.75
3.50
3.25
3.00
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
Vin Increasing
Vin Decreasing
Vin = 12V
Vin = 4.5V
100 125 150
0
25
50
75
100
125
150
0
25
50
75
±50
±25
±50
±25
JUNCTION TEMPERATURE (|C)
JUNCTION TEMPERATURE (|C)
C003
C005
VCC Current Limit vs. Temperature
VCC Output Impedence vs. Temperature
40
35
30
25
20
15
30
25
20
15
10
5
Vin = 8V
Vin = 4.5V
Vin = 12V
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
±50
±25
±50
±25
JUNCTION TEMPERATURE (|C)
JUNCTION TEMPERATURE (|C)
C006
C009
10
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Typical Performance Characteristics (continued)
Minimum Off-Time vs. Temperature
On-Time vs. Temperature
150
145
140
135
130
125
120
115
110
105
100
400
300
200
100
0
RON = 100k
VIN = 12V
Vin = 12V
0
25
50
75
100
125
150
0
25
50
75
100
125
150
±50
±25
±50
±25
JUNCTION TEMPERATURE (|C)
JUNCTION TEMPERATURE (|C)
C007
C002
Current Limit Threshold vs. Temperature
EN Pin Threshold vs. Temperature
0.80
0.75
0.70
0.65
0.60
0.55
0.50
3.0
2.5
2.0
1.5
1.0
0.5
0.0
EN Rising
EN Falling
VIN = 12V
0
25
50
75
100
125
150
0
25
50
75
100
125
150
±50
±25
±50
±25
JUNCTION TEMPERATURE (|C)
JUNCTION TEMPERATURE (|C)
C003
C004
PGD vs. Sink Current
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0
2
4
6
8
10
PGD SINK CURRENT (mA)
C005
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VIN
EN
UVLO
VCC
PGD
SS
SW
FB
VOUT
tt1t
tt2t
Figure 6. Start-Up Sequence
Functional Description
Device Information
The LM34919C Step Down Switching Regulator features all the functions needed to implement a low cost,
efficient buck bias power converter capable of supplying 600 mA to the load. This high voltage regulator is easy
to implement and is available in DSBGA and WSON packages. The regulator’s operation is based on a constant
on-time control scheme, where the on-time is determined by VIN. This feature allows the operating frequency to
remain relatively constant with load and input voltage variations. The feedback control requires no loop
compensation resulting in fast load transient response. The valley current limit detection circuit, internally set at
0.64 A, holds the buck switch off until the high current level subsides. This scheme protects against excessively
high current if the output is short-circuited when VIN is high.
The LM34919C can be applied in numerous applications to efficiently step down higher voltages. Additional
features include: Thermal shutdown, VCC undervoltage lockout, gate drive undervoltage lockout, maximum duty
cycle limiter, power good, and enable.
Control Circuit Overview
The LM34919C buck DC-DC regulator employs a control scheme based on a comparator and a one-shot on-
timer, with the output voltage feedback (FB) compared to an internal reference (2.52 V). If the FB voltage is
below the reference the N-channel buck switch is turned on for a time period determined by the input voltage and
a programming resistor RON. Following the on-time the switch remains off until the FB voltage falls below the
reference but not less than the minimum off-time. The buck switch then turns on for another on-time period.
Typically, during start-up, or when the load current increases suddenly, the off-times are at the minimum. Once
regulation is established, in steady state operations, the off-times are longer and automatically adjust to produce
the SW pin duty cycle required for output regulation.
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When in regulation, the LM34919C operates in continuous conduction mode at heavy load currents and
discontinuous conduction mode at light load currents. In continuous conduction mode current always flows
through the inductor, never reaching zero during the off-time. In this mode the operating frequency remains
relatively constant with load and line variations. The minimum load current for continuous conduction mode is
one-half the inductor’s ripple current amplitude. The operating frequency is approximately:
VOUT
RON u35.5u10-12
FS
Hz
(1)
The buck switch duty cycle is approximately equal to:
tON
VOUT
VIN
=
DC =
tON + tOFF
(2)
In discontinuous conduction mode, current through the inductor ramps up from zero to a peak during the on-time,
then ramps back to zero before the end of the off-time. The next on-time period starts when the voltage at FB
falls below the reference. Until then the inductor current remains zero, and the load current is supplied by the
output capacitor. In this mode the operating frequency is lower than in continuous conduction mode, and varies
with load current. Conversion efficiency is maintained at light loads since the switching losses decrease with the
reduction in load and frequency.
The output voltage is set by two external resistors (R1, R2). The regulated output voltage is calculated as
follows:
VOUT = 2.52 x (R1 + R2) / R2
(3)
Output voltage regulation is based on ripple voltage at the feedback input, normally obtained from the output
voltage ripple through the feedback resistors. The LM34919C requires a minimum of 25 mV of ripple voltage at
the FB pin. In cases where the output capacitor’s ESR is insufficient additional series resistance may be required
(R3).
Start-Up Regulator, VCC
The start-up regulator is integral to the LM34919C. The input pin (VIN) can be connected directly to line voltage
up to 50 V with transient capability to 65 V. The VCC output regulates at 7.0 V and is current limited at 27 mA.
Upon power up, the regulator sources current into the external capacitor at VCC (C3). When the voltage on the
VCC pin reaches the undervoltage lockout rising threshold of 3.75 V, the buck switch is enabled and the soft-
start pin is released to allow the soft-start capacitor (C6) to charge up.
The minimum input voltage is determined by the VCC UVLO falling threshold (≊3.6 V). When VCC falls below the
falling threshold the VCC UVLO activates to shut off the output. If VCC is externally loaded, the minimum input
voltage increases.
To reduce power dissipation in the start-up regulator, an auxiliary bias voltage can be diode connected to the VCC
pin (see Figure 7). Setting the auxiliary bias voltage between 7.6 V and 14 V shuts off the internal regulator
reducing internal power dissipation. The sum of the auxiliary voltage and the input voltage (VCC + VIN) cannot
exceed 79 V. An internal diode connects VCC to VIN. (See Figure 5).
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VCC
BST
C3
C4
L1
D2
LM34919C
SW
V
OUT
D1
R3
R1
R2
ISEN
SGND
FB
C2
Figure 7. Self Biased Configuration
Regulation Comparator
The feedback voltage at FB is compared to the voltage at the soft-start pin. In normal operation (the output
voltage is regulated), an on-time period is initiated when the voltage at FB falls below 2.52 V. The buck switch
stays on for the programmed on-time causing the FB voltage to rise above 2.52 V. After the on-time period, the
buck switch stays off until the FB voltage falls below 2.52 V. Input bias current at the FB pin is less than 100 nA
over temperature.
Overvoltage Comparator and Undervoltage Comparator
The voltage at FB is compared to an internal overvoltage comparator reference (120% of internal reference
voltage). If the voltage at FB rises above this reference, the on-time pulse is immediately terminated. This
condition can occur if the input voltage or the output load changes suddenly, or if the inductor (L1) saturates. The
buck switch remains off until the voltage at FB falls below 2.52 V.
When the FB pin voltage rises above the undervoltage comparator voltage reference (92% of the internal
reference voltage), the PGD pin is released and is pulled high by the external pull-up resistor. When the FB pin
voltage measures less than 90% of the internal reference voltage, the PGD pin switches low.
ON-Time Timer
The on-time is determined by the RON resistor and the input voltage (VIN), and is calculated from:
RON u35.5u10-12
TON
s
V
IN
(4)
The inverse relationship with VIN results in a nearly constant frequency as VIN is varied. To set a specific
continuous conduction mode switching frequency (fS), the RON resistor is determined from the following:
VOUT
FS u 35.5u10-12
RON
:
(5)
The minimum off-time limits the maximum duty cycle achievable with a low voltage at VIN. The minimum on-time
is limited to ≊ 90 ns.
Enable
The LM34919C can be remotely shut down by forcing the Enable (EN) pin low. The bias and control circuits are
turned off when EN is pulled below the enable shutdown falling threshold of 1.3 V (typ). In the shutdown mode
the input current falls below 10 µA. If remote shutdown feature is not needed the EN pin can be connected to the
input voltage or any voltage greater than 3 V. In this case the device is enabled and disabled based on the VCC
UVLO threshold.
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Current Limit
Current limit detection occurs during the off-time by monitoring the recirculating current through the free-wheeling
diode (D1). Referring to Figure 5, when the buck switch is turned off the inductor current flows out of ISEN and
through D1. If the valley point of that current exceeds 0.64 A the current limit comparator output switches to
delay the start of the next on-time period. The next on-time starts when the valley point of the current out of ISEN
is below 0.64 A and the voltage at FB is below 2.52 V. If the overload condition persists causing the inductor
current valley point to exceed 0.64 A during each cycle the operating frequency is lower due to longer-than-
normal off-times.
Figure 8 illustrates the inductor current waveform. During normal operation the load current is Io, the average of
the ripple waveform. When the load resistance decreases the current ratchets up until the lower peak reaches
0.64 A. During the Current Limited portion of Figure 8, the current ramps down to 0.64 A during each off-time,
initiating the next on-time (assuming the voltage at FB is <2.52 V). During each on-time the current ramps up an
amount equal to:
ΔI = (VIN - VOUT) x tON / L1
(6)
During this time the LM34919C operates in a constant current mode with an average load current (IOCL) equal to
0.64 A + ΔI/2.
Generally, in applications where the switching frequency is higher than ≊300 kHz and a relatively small value
inductor is used, the higher dl/dt of the inductor's ripple current results in an effectively lower valley current limit
threshold due to the response time of the current limit detection circuit. However, since the small value inductor
results in a relatively high ripple current amplitude (ΔI in Figure 8), the load current (IOCL) at current limit typically
exceeds 640 mA.
I
PK
'I
I
OCL
0.64A
I
O
Load Current
Increases
Normal Operation
Current Limited
Figure 8. Inductor Current - Current Limit Operation
N - Channel Buck Switch and Driver
The LM34919C integrates an N-Channel buck switch and associated floating high side gate driver. The peak
current allowed through the buck switch is 1.5 A, and the maximum allowed average current is 1 A. The gate
driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A 0.022
µF capacitor (C4) connected between BST and SW provides the voltage to the driver during the on-time. During
each off-time, the SW pin is at approximately -1 V, and C4 charges from VCC through the internal diode. The
minimum off-time of LM34919C ensures sufficient time each cycle to recharge the bootstrap capacitor.
Soft-Start
The soft-start feature allows the converter to gradually reach a steady state operating point, thereby reducing
start-up stresses and current surges. Upon turn-on, after VCC reaches the undervoltage threshold, an internal
10.5 µA current source charges up the external capacitor at the SS pin to 2.52 V. The ramping voltage at SS
(and the inverting input of the regulation comparator) ramps up the output voltage in a controlled manner.
An internal switch grounds the SS pin if VCC is below the undervoltage lockout threshold, or if the EN pin is
grounded.
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Power Good Output
The Power Good Output (PGD) indicates when the voltage at the FB pin is close to the internal 2.52 V reference
voltage. The PGD pin remains low inside the device when the FB pin voltage is outside the range set by the
PGDUV and PGDOV thresholds (see Electrical Characteristics). The PGD pin is internally connected to the drain
of an N-channel MOSFET switch. An external pull-up resistor (RPGD), connected to an appropriate voltage not
exceeding 14 V, is required at PGD to indicate the status of LM34919C to other circuitry. For best results, pull up
the PGD pin to the output voltage. When PGD is low, the voltage at the pin is determined by the current into the
pin. See the graph "PGD Low Voltage vs. Sink Current." Upon powering, as VIN is increased, PGD stays low
until the output voltage takes the voltage at the FB pin above 92% of the internal reference voltage, at which time
PGD switches high. As VIN is decreased (e.g., during shutdown), PGD remains high until the voltage at the FB
pin falls below 90% (typ.) of the internal reference. PGD then switches low and remains low.
Thermal Shutdown
The LM34919C should be operated such that the junction temperature does not exceed 125°C. If the junction
temperature increases to 175°C (typical), an internal Thermal Shutdown circuit forces the controller to a low-
power reset state by disabling the buck switch. This feature helps prevent catastrophic failures from accidental
device overheating. When the junction temperature reduces below 155°C (hysteresis = 20°C) normal operation
resumes.
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APPLICATION INFORMATION
External Components
The procedure for calculating the external components is illustrated with the following design example. Referring
to Figure 5, the circuit is to be configured for the following specifications:
- VOUT = 3.3 V
- VIN = 4.5 V to 24 V
- Minimum load current = 200 mA
- Maximum load current = 600 mA
- Switching Frequency = 1.5 MHz
- Soft-start time = 5 ms
R1 and R2: These resistors set the output voltage. The ratio of the feedback resistors is calculated from:
R1/R2 = (VOUT/2.52 V) - 1
(7)
For this example, R1/R2 = 0.32. R1 and R2 should be chosen from standard value resistors in the range of 1.0
kΩ - 10 kΩ which satisfy the above ratio. For this example, 2.49 kΩ is chosen for R2 and 787 Ω for R1.
RON: This resistor sets the on-time and the switching frequency. The switching frequency must be less than 1.53
MHz to ensure the minimum forced on-time does not cause cycle skipping when operating at the maximum input
voltage. The RON resistor is calculated from Equation 8:
VOUT
FSW x35.5x10ꢀ12
RON
61.9k:
(8)
Check that this value resistor does not set an on-time less than 90 ns at maximum VIN.
A standard value 61.9 kΩ resistor is used, resulting in a nominal frequency of 1.50 MHz. The minimum on-time is
calculated ≊92 ns at Vin = 24 V, and the maximum on-time is ≊488 ns at Vin = 4.5 V. Alternately, RON can be
determined using Equation 4 if a specific on-time is required.
L1: The main parameter affected by the inductor is the inductor current ripple amplitude (IOR). The minimum load
current is used to determine the maximum allowable ripple in order to maintain continuous conduction mode,
where the lower peak does not reach 0 mA. This is not a requirement of the LM34919C, but serves as a
guideline for selecting L1. For this case the maximum ripple current is:
IOR(MAX) = 2 x IOUT(min) = 400 mA
(9)
If the minimum load current is zero, use 20% of IOUT(max) for IOUT(min) in Equation 9. The ripple calculated in
Equation 9 is then used in Equation 10:
V
- V OUT x t on (min )
(
)
(
)
IN m ax
L1 =
= 4.76 µH
IOR (MAX
)
(10)
A standard value 8.2 µH inductor is selected. The maximum ripple amplitude, which occurs at maximum VIN,
calculates to 232 mA p-p, and the peak current is 716 mA at maximum load current. Ensure the selected inductor
is rated for this peak current.
C2 and R3: Since the LM34919C requires a minimum of 25 mVp-p ripple at the FB pin for proper operation, the
required ripple at VOUT is increased by R1 and R2. This necessary ripple is created by the inductor ripple current
flowing through R3, and to a lesser extent by the ESR of C2. The minimum inductor ripple current is calculated
using Equation 6, rearranged to solve for IOR at minimum VIN.
kV
; F VOUT o x ton(max )
:
IN min
IOR (MIN )
=
= 71.4 mA
(11)
(12)
17
The minimum value for R3 is equal to:
R3(min ?)
=
25mV x (R1+ R2) = 0.47 3
R2 x IOR (MI N )
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A standard value 0.47 Ω resistor is used for R3 to allow for tolerances. C2 should generally be no smaller than
3.3 µF, although that is dependent on the frequency and the desired output characteristics. C2 should be a low
ESR, good quality ceramic capacitor. Experimentation is usually necessary to determine the minimum value for
C2, as the nature of the load may require a larger value. A load which creates significant transients requires a
larger value for C2 than a non-varying load.
C1 and C5: C1’s purpose is to supply most of the switch current during the on-time and limit the voltage ripple at
VIN.
At maximum load current, when the buck switch turns on, the current into VIN suddenly increases to the lower
peak of the inductor’s ripple current, ramps up to the upper peak, then drops to zero at turn-off. The average
current during the on-time is the load current. For a worst case calculation, C1 must supply this average load
current during the maximum on-time, without letting the voltage at VIN drop more than 0.5 V. The minimum value
for C1 is calculated from:
IOUT (max) x tON
C1 =
= 0.5 PF
'V
(13)
where tON is the maximum on-time, and ΔV is the allowable ripple voltage. Input ripple of 0.5 V is acceptable in
typical applications. C5’s purpose is to minimize transients and ringing due to long lead inductance leading to the
VIN pin. A low ESR, 0.1 µF ceramic chip capacitor must be located close to the VIN and RTN pins.
C3: The capacitor at the VCC pin provides noise filtering and stability for the Vcc regulator. C3 should be no
smaller than 0.1 µF, and should be a good quality, low ESR, ceramic capacitor. C3’s value, and the VCC current
limit, determine a portion of the turn-on-time (t1 in (Figure 6).
C4: The recommended value for C4 is 0.022 µF. A high quality ceramic capacitor with low ESR is recommended
as C4 supplies a surge current to charge the buck switch gate at each turn-on. A low ESR also helps ensure a
complete recharge during each off-time.
C6: The capacitor at the SS pin determines the soft-start time, i.e. the time for the output voltage to reach its final
value (t2 in Figure 6). The capacitor value is determined from the following:
t2 x 10.5 PA
= 0.021 PF
C6 =
2.5V
(14)
D1: A Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high speed
transitions at the SW pin may inadvertently affect the device's operation through external or internal EMI. The
diode should be rated for the maximum input voltage, the maximum load current, and the peak current which
occurs in current limiting. The diode’s average power dissipation is calculated from:
PD1 = VF x IOUT x (1-D)
(15)
where VF is the diode forward voltage drop, and D is the duty cycle at the SW pin.
Final Circuit
The final circuit is shown in Figure 9, and its performance is shown in Figure 10 and Figure 11.
4.5V - 24V
Input
VCC
C3
0.1 µF
VIN
C5
0.1 µF
R4
C1
2.2 µF
100 kꢀ
L1
8.2 µH
EN
C4
0.022 µF
BST
SW
RON
VOUT
61.9 kꢀ
LM34919C
VOUT
3.3V
RON
PGD
SS
D1
R5 10 kꢀ
R1
787ꢀ
R3
0.47ꢀ
ISEN
FB
C6
0.022 µF
C2
22 µF
R2
2.49 kꢀ
SGND
RTN
Figure 9. Example Circuit
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95
90
85
80
75
70
65
60
55
4.5V
9V
12V
18V
24V
0.2
0.3
LOAD CURRENT (A)
Figure 10. Efficiency (1.5 MHz, VOUT = 3.3 V)
0.4
0.5
0.6
3
2.5
2
1.5
1
Ron=61.9k
0.5
4
8
12
INPUT VOLTAGE (V)
Figure 11. Frequency vs. VIN (VOUT = 3.3 V)
16
20
24
28
Low Output Ripple Configurations
For applications where lower ripple at VOUT is required, the following options can be used to reduce or nearly
eliminate the ripple.
a) Reduced ripple configuration: In Figure 12, Cff is added across R1 to AC-couple the ripple at VOUT directly
to the FB pin. This allows the ripple at VOUT to be reduced to a minimum of 25 mVp-p by reducing R3, since the
ripple at VOUT is not attenuated by the feedback resistors. The minimum value for Cff is determined from:
tON (max) x 3
Cff =
(R1//R2)
(16)
where tON(max) is the maximum on-time, which occurs at VIN(min). The next larger standard value capacitor should
be used for Cff. R1 and R2 should each be towards the upper end of the 2 kΩ to 10 kΩ range.
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L1
SW
FB
V
OUT
Cff
LM34919C
R1
R3
R2
C2
Figure 12. Reduced Ripple Configuration
b) Minimum ripple configuration: The circuit of Figure 13 provides minimum ripple at VOUT, determined
primarily by characteristics of C2 and the inductor’s ripple current since R3 is removed. RA and CA are chosen to
generate a sawtooth waveform at their junction and that voltage is AC-coupled to the FB pin via CB. To
determine the values for RA, CA and CB, use the following procedure:
Calculate VA = VOUT - (VSW x (1 - (VOUT/VIN(min))))
(17)
where VSW is the absolute value of the voltage at the SW pin during the off-time (typically 1 V). VA is the DC
voltage at the RA/CA junction. Calculate the RA-CA product in Equation 18.
(VIN(min) - VA) x tON
RA x CA =
'V
(18)
where tON is the maximum on-time (at minimum input voltage), and ΔV is the desired ripple amplitude at the
RA/CA junction, typically 50 mV. RA and CA are then chosen from standard value components to achieve the
above product. Typically CA is 3000 pF to 5000 pF and RA is 10 kΩ to 300 kΩ. CB is then chosen large
compared to CA, typically 0.1 µF. R1 and R2 should each be towards the upper end of the 2 kΩ to 10 kΩ range.
L1
SW
V
OUT
CA
C2
LM34919C
RA
CB
R1
R2
FB
Figure 13. Minimum Output Ripple Using Ripple Injection
c) Alternate minimum ripple configuration: The circuit in Figure 14 is the same as that in Figure 9, except the
output voltage is taken from the junction of R3 and C2. The ripple at VOUT is determined by the inductor ripple
current and C2’s characteristics. R3 slightly degrades the load regulation because the feedback resistors are not
directly connected to VOUT. This circuit may be suitable if the load current is fairly constant.
L1
SW
LM34919C
R1
R2
R3
FB
V
OUT
C2
Figure 14. Alternate Minimum Output Ripple Configuration
Minimum Load Current
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The LM34919C requires a minimum load current of 1 mA. If the load current falls below that level, the bootstrap
capacitor (C4) may discharge during the long off-time, and the circuit will either shutdown or cycle on and off at a
low frequency. If the load current is expected to drop below 1 mA in the application, R1 and R2 should be
chosen low enough in value so they provide the minimum required current at nominal VOUT
.
PC Board Layout
Refer to application note AN-1112 for PC board guidelines for the DSBGA package.
The LM34919C regulation, overvoltage, and current limit comparators are very fast, and respond to short
duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout should
be as compact as possible, and all of the components must be as close as possible to their associated pins. The
two major current loops have currents which switch very fast, and so these loops should be as small as possible
to minimize conducted and radiated EMI. The first loop is that formed by C1, through the VIN to SW pins, L1, C2,
and back to C1.The second current loop is formed by D1, L1, C2 and the SGND and ISEN pins.
The power dissipation within the LM34919C can be approximated by determining the total conversion loss (PIN
-
POUT), and then subtracting the power losses in the free-wheeling diode and the inductor. The power loss in the
diode is approximately:
PD1 = IOUT x VF x (1-D)
(19)
where IOUT is the load current, VF is the diode’s forward voltage drop, and D is the on-time duty cycle. The power
loss in the inductor is approximately:
PL1 = IOUT2 x RL x 1.1
(20)
where RL is the inductor’s DC resistance, and the 1.1 factor is an approximation for the AC losses. If it is
expected that the internal dissipation of the LM34919C will produce excessive junction temperatures during
normal operation, good use of the PC board ground plane can help to dissipate heat. Additionally the use of wide
PC board traces, where possible, can help conduct heat away from the device. Judicious positioning of the PC
board within the end product, along with the use of any available air flow (forced or natural convection) will help
reduce the junction temperatures.
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Changes from Revision splat (September 2013) to Revision A
Page
•
Added value of the integrated high side switch for WSON package .................................................................................... 3
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PACKAGE OPTION ADDENDUM
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11-Dec-2013
PACKAGING INFORMATION
Orderable Device
LM34919CQSD/NOPB
LM34919CQSDX/NOPB
LM34919CQTL/NOPB
LM34919CQTLX/NOPB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
WSON
WSON
DSBGA
DSBGA
DNT
12
12
12
12
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
L34919C
ACTIVE
ACTIVE
ACTIVE
DNT
YZR
YZR
4500
250
Green (RoHS
& no Sb/Br)
CU SN
L34919C
SL9C
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
3000
Green (RoHS
& no Sb/Br)
SL9C
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Dec-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM34919CQSD/NOPB
WSON
DNT
DNT
YZR
YZR
12
12
12
12
1000
4500
250
178.0
330.0
178.0
178.0
12.4
12.4
8.4
4.3
4.3
4.3
4.3
1.3
1.3
8.0
8.0
4.0
4.0
12.0
12.0
8.0
Q1
Q1
Q1
Q1
LM34919CQSDX/NOPB WSON
LM34919CQTL/NOPB DSBGA
LM34919CQTLX/NOPB DSBGA
2.03
2.03
2.21
2.21
0.76
0.76
3000
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Dec-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM34919CQSD/NOPB
LM34919CQSDX/NOPB
LM34919CQTL/NOPB
LM34919CQTLX/NOPB
WSON
WSON
DSBGA
DSBGA
DNT
DNT
YZR
YZR
12
12
12
12
1000
4500
250
210.0
367.0
210.0
210.0
185.0
367.0
185.0
185.0
35.0
35.0
35.0
35.0
3000
Pack Materials-Page 2
MECHANICAL DATA
DNT0012B
WSON - 0.8mm max height
SON (PLASTIC SMALL OUTLINE - NO LEAD)
SDA12B (Rev A)
4214928/A 03/2013
NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is designed to be soldered to a thermal pad on the board for thermal and mechanical performance.
For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271).
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MECHANICAL DATA
YZR0012xxx
0.600±0.075
D
E
TLA12XXX (Rev C)
D: Max = 2.055 mm, Min =1.995 mm
E: Max = 1.844 mm, Min =1.784 mm
4215049/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
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