LM34923 [TI]
80V、600mA 恒定导通时间降压开关稳压器;
| 型号： | LM34923 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 80V、600mA 恒定导通时间降压开关稳压器 开关 稳压器 |
| 文件： | 总29页 (文件大小：1615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM34923
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SNVS695A –MARCH 2011–REVISED FEBRUARY 2013
80-V 600-mA Constant On-Time Buck Switching Regulator
Check for Samples: LM34923
1
FEATURES
DESCRIPTION
The LM34923 Step Down Switching Regulator
features all of the functions needed to implement a
low cost, efficient Buck bias regulator. This high
voltage regulator contains an 80V N-Channel
MOSFET Switch and a startup regulator. The device
is easy to implement and is provided in an 10-pin
VSSOP package. The regulator’s control scheme
uses an on-time inversely proportional to VIN. This
feature results in the operating frequency remaining
relatively constant with line and load variations. The
control scheme requires no loop compensation,
resulting in fast transient response. An intelligent
current limit is implemented with a forced off-time
which is inversely proportional to VOUT. This scheme
ensures short circuit control while providing minimum
foldback. Other features include: Thermal Shutdown,
VCC Under Voltage Lock-out, Max Duty Cycle
Limiter, a Pre-charge Switch, and a programmable
Under Voltage Detector with a status flag output.
2
•
•
•
•
•
•
Operating Input Voltage Range: 6V to 75V
Integrated 80V, N-Channel Buck Switch
Internal Start-up Regulator
No Loop Compensation Required
Ultra-Fast Transient Response
Operating Frequency Remains Constant with
Line and Load Variations
•
•
•
•
Adjustable Output voltage From 2.5V
Precision Internal Reference, ±2.5%
Intelligent Current Limit Reduces Foldback
Programmable Input UV Detector with Status
Flag Output
•
Pre-charge Switch Enables Bootstrap Gate
Drive with No Load
•
•
Thermal Shutdown
10-Pin VSSOP Package
APPLICATIONS
•
Non-Isolated Telecommunication Buck
Regulator
•
•
Secondary High Voltage Post Regulator
+42V Automotive Systems
Typical Application, Basic Step-Down Regulator
6V - 75V
Input
V
VIN
VCC
C3
IN
LM34923
C1
R
T
GND
BST
C4
L1
RT/SD
UV
SW
SHUTDOWN
V
OUT
R
UV2
D1
R3
C2
R
FB2
R
UV1
FB
R
UVO
GND
R
FB1
UVO
RTN
UV STATUS
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LM34923
SNVS695A –MARCH 2011–REVISED FEBRUARY 2013
www.ti.com
Connection Diagram
1
10
SW
VIN
VCC
RT
BST
2
3
9
8
7
6
N/C
RTN
UV
4
5
FB
UVO
Figure 1. Top View
10-Lead VSSOP
Table 1. Pin Descriptions
Pin
No.
Name
SW
Description
Switching Node
Application Information
1
Power switching node. Connect to the output inductor, re-circulating diode or synchronous
FET, and bootstrap capacitor.
2
BST
Boost Pin
An external capacitor is required between the BST and the SW pins (0.01uF or greater
ceramic). The BST pin capacitor is charged from VCC through an internal diode when SW is
low.
3
4
5
N/C
RTN
UV
Do not connect
Ground pin
Ground for the entire circuit.
Input pin for the under
voltage indicator
A resistor divider from VIN, or some other system voltage, programs the under-voltage
detection threshold. An internal current sink is enabled when UV is below 2.5V to provide
hysteresis.
6
7
8
UVO
FB
Under voltage status
indicator
This open drain output is high when the UV pin voltage is below 2.5V, or when the VCCUVLO
function or the shutdown function is invoked.
Feedback Input from
Regulated Output
This pin is connected to the inverting input of the internal regulation comparator. The
regulation level is 2.5V.
RT/SD On-time set pin and
shutdown input
A resistor between this pin and Vin sets the switch on-time as a function of Vin, and the
frequency. The minimum recommended on-time is 200 ns at max input voltage. Taking this
pin to ground shuts off the regulator.
9
VCC
Output from the internal
high voltage series pass
regulator. Regulated at
7.5V.
The internal regulator provides bias supply for the Buck switch gate driver and other internal
circuitry. A 1uF ceramic capacitor to ground is required. The regulator is current limited to
≈30 mA.
10
VIN
Input Voltage
The operating input range is 6V to 75V
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
VIN, UV to RTN
-0.3V to 80V
-0.3V to 88V
-1V to VIN + 0.3V
80V
BST to RTN
SW to RTN (Steady State)
BST to VCC
BST to SW
10V
VCC, UVO, RT to RTN
FB, RT, to RTN
ESD Rating, Human Body Model(3)
For soldering specifications see: Application Note SNOA549.
Junction Temperature
Storage Temperature Range
–0.3V to 10V
-0.3 to 5V
2kV
150°C
-55°C to +150°C
(1) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(2) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
(3) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Operating Ratings(1)
VIN
6V to 75V
−40°C to + 125°C
Operating Junction Temperature
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
Electrical Characteristics
Specifications with standard type are for TJ = 25°C only; limits in boldface type apply over the full Operating Junction
Temperature (TJ) range. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical
values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 48V(1)
.
Symbol
VCC Supply
Vcc Reg
Parameter
Conditions
Min
7.1
Typ
Max
7.9
Unit
Vcc Regulator Output
Vin – Vcc
Vin = 48V
7.5
240
45
30
4
V
VIN = 6V, ICC = 5mA
Vin =6V
mV
Ω
Vcc Output Impedance
Vcc Current Limit
Vcc UVLO
Vin = 48V(2)
20
mA
V
Vcc Increasing
4.8
Vcc UVLO hysteresis
Iin Operating current
Iin Shutdown Current
450
1
mV
mA
µA
FB = 3V, Vin = 48V
RT/SD = 0V
1.32
70
20
Switch Characteristics
Buck switch Rds(on)
Itest = 200 mA
0.56
3
1.1
3.8
Ω
V
Gate Drive UVLO
Vbst – Vsw Rising
2.15
Gate Drive UVLO hysteresis
Pre-charge switch voltage
Pre-charge switch on-time
250
0.8
150
mV
V
At 1 mA
ns
(1) All electrical characteristics having room temperature limits are tested during production with TA = TJ = 25°C. All hot and cold limits are
specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) The VCC output is intended as a self bias for the internal gate drive power and control circuits. Device thermal limitations limit external
loading.
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Electrical Characteristics (continued)
Specifications with standard type are for TJ = 25°C only; limits in boldface type apply over the full Operating Junction
Temperature (TJ) range. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical
values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 48V(1)
.
Symbol
Parameter
Conditions
Min
700
Typ
Max
Unit
Current Limit
Current Limit Threshold
1175
190
37
1500
mA
ns
µs
µs
µs
µs
Current Limit Response Time
OFF time generator (test 1)
OFF time generator (test 2)
OFF time generator (test 3)
OFF time generator (test 4)
Iswitch = 1.24A, Time to Switch Off
FB=0V, VIN = 75V
TOFF-1
TOFF-2
TOFF-3
TOFF-4
FB=2.3V, VIN = 75V
FB=0V, VIN = 10V
7.2
5.7
FB=2.3V, VIN = 10V
1.25
On Time Generator
TON - 1
On-Time
Vin = 10V
Ron = 250K
2.2
300
0.46
3.3
4.51
565
1.4
µs
ns
TON - 2
On-Time
Vin = 75V
Ron = 250K
450
Remote Shutdown Threshold
Remote Shutdown Hysteresis
Voltage at RT/SD rising
0.9
60
V
mV
Minimum Off Time
Minimum Off Time
VIN = 6V
260
2.5
347
ns
V
Regulation and OV Comparators
FB Reference Threshold
Internal reference
2.4365
2.5625
Trip point for switch ON
FB Over-Voltage Threshold
FB Bias Current
Trip point for switch OFF
2.85
1
V
nA
Under Voltage Sensing
UVTH
UV Threshold
2.4
2.7
2.5
5
2.6
7.3
V
UVHYS
UVBIAS
UVOVOL
UVOIOH
UV Hysteresis Current
UV Bias Current
UV = 2V
µA
nA
mV
nA
UV = 3V
1
UVO Output Low Voltage
UVO Leakage Current
UV = 3V, IUVO = 5mA
UV = 2V, VUVO = 7.8V
360
1
600
Thermal Shutdown
Tsd Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
Thermal Resistance
θJA Junction to Ambient
165
20
°C
°C
VSSOP Package
200
°C/W
4
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Typical Performance Characteristics
Efficiency at 300 kHz, 10V
Efficiency Comparison at 200 kHz
100
90
80
70
60
50
6V, D1
24V, D1
7.5V, D1
V
=5V, D1=DFLS1100
OUT
0
100 200 300 400 500 600
LOAD CURRENT (mA)
Figure 2.
Figure 3.
VCC
vs.
VIN
VCC
vs.
ICC
Figure 4.
Figure 5.
ICC
vs.
On-Time
vs.
VIN and RT
Externally Applied VCC
5
4
3
2
1
0
900 kHz, D1
200 kHz, D1
DCM
7.5
8.0
8.5
9.0
9.5
10.0
APPLIED VCC (V)
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
Current Limit Off-Time
vs.
VFB
Maximum Switching Frequency
Figure 8.
Figure 9.
Voltage at the RT Pin
Operating Current into VIN
4.5
77 kW
34 kW
4.0
3.5
200 kW
300 kW
3.0
2.5
2.0
1.5
1.0
RT = 500 kW
5
15
25
35
45
55
65
75
VIN (V)
Figure 10.
Figure 11.
UVO Pin Low Voltage
vs.
Shutdown Current into VIN
Sink Current
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
VCC UVLO
vs.
Temperature
Gate Drive UVLO
vs.
Temperature
Figure 14.
Figure 15.
VCC
vs.
Temperature
VCC Dropout
vs.
Temperature
Figure 16.
Figure 17.
VCC Output Impedance
vs.
VCC Current Limit
vs.
Temperature
Temperature
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
Reference Voltage
vs.
On-time
vs.
Temperature
Temperature
Figure 20.
Figure 21.
Minimum Off-time
vs.
Temperature
Current Limit Threshold
vs.
Temperature
Figure 22.
Figure 23.
Current Limit Off-Time
vs.
Operating Current
vs.
Temperature
Temperature
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
Shutdown Current
vs.
RT Pin Shutdown Threshold
vs.
Temperature
Temperature
Figure 26.
Figure 27.
UV Pin Threshold
vs.
Temperature
UV Hysteresis Current
vs.
Temperature
Figure 28.
Figure 29.
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BLOCK DIAGRAM
LM34923
Input
VIN
VCC
START-UP
REGULATOR
C5
C1
C3
VCC UVLO
THERMAL
SHUTDOWN
R
T
0.9V
ON/OFF
BST
TIMERS
RT/SD
V
IN
2.5V
C4
FEEDBACK
FB
L1
Delay
SW
DRIVER
LOGIC
OVER-VOLTAGE
2.85V
V
OUT
-
PRE
D1
R3
CHARGE
C2
CURRENT
LIMIT
R
FB2
+
-
Current
Limit
One-Shot
Vth
R
FB1
R
R
UV2
UV1
2.5V
UVO
UV
5 mA
RTN
FUNCTIONAL DESCRIPTION
The LM34923 Step Down Switching Regulator features all the functions needed to implement a low cost,
efficient, Buck bias power converter. This high voltage regulator contains an 80 V N-Channel Buck Switch, is
easy to implement and is provided in the VSSOP-10 package. The regulator is based on a control scheme using
an on-time inversely proportional to VIN. The control scheme requires no loop compensation. Current limit is
implemented with forced off-time, which is inversely proportional to VOUT. This scheme ensures short circuit
control while providing minimum foldback.
The LM34923 can be applied in numerous applications to efficiently regulate down higher voltages. This
regulator is well suited for 48 Volt Telecom and the new 42V Automotive power bus ranges. Features include:
Thermal Shutdown, VCC under-voltage lockout, Gate drive under-voltage lockout, Max Duty Cycle limit timer,
intelligent current limit off timer, a pre-charge switch, and a programmable under voltage detector with status flag.
Control Circuit Overview
The LM34923 is a Buck DC-DC regulator that uses a control scheme in which the on-time varies inversely with
line voltage (VIN). Control is based on a comparator and the on-time one-shot, with the output voltage feedback
(FB) compared to an internal reference (2.5V). If the FB level is below the reference the buck switch is turned on
for a fixed time determined by the line voltage and a programming resistor (RT). Following the ON period the
switch remains off for at least the minimum off-timer period of 260 ns. If FB is still below the reference at that
time the switch turns on again for another on-time period. This continues until regulation is achieved.
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The LM34923 operates in discontinuous conduction mode at light load currents, and continuous conduction
mode at heavy load current. In discontinuous conduction mode, current through the output inductor starts at zero
and ramps up to a peak during the on-time, then ramps back to zero before the end of the off-time. The next on-
time period starts when the voltage at FB falls below the internal reference - until then the inductor current
remains zero. In this mode the operating frequency is lower than in continuous conduction mode, and varies with
load current. Therefore at light loads the conversion efficiency is maintained, since the switching losses reduce
with the reduction in load and frequency. The discontinuous operating frequency can be calculated as follows:
VOUT2 x L x 1.28 x 1020
F =
RL x (RT)2
(1)
where RL = the load resistance
In continuous conduction mode, current flows continuously through the inductor and never ramps down to zero.
In this mode the operating frequency is greater than the discontinuous mode frequency and remains relatively
constant with load and line variations. The approximate continuous mode operating frequency can be calculated
as follows:
VOUT x (Vin - 0.5V)
F =
1.25 x 10-10 x VIN x (RT + 500W)
(2)
The buck switch duty cycle is approximately equal to:
tON
VOUT
VIN
DC =
=
t
ON + tOFF
(3)
The output voltage (VOUT) is programmed by two external resistors as shown in the Block Diagram. The
regulation point can be calculated as follows:
VOUT = 2.5 x (RFB1 + RFB2) / RFB1
(4)
The LM34923 regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum
amount of ESR for the output capacitor C2. A minimum of 25mV to 50mV of ripple voltage at the feedback pin
(FB) is required for the LM34923. In cases where the capacitor ESR is too small, additional series resistance
may be required (R3 in the Block Diagram).
For applications where lower output voltage ripple is required the output can be taken directly from a low ESR
output capacitor, as shown in Figure 30. However, R3 slightly degrades the load regulation.
L1
SW
R
FB2
LM34923
R3
C2
FB
V
OUT
R
FB1
Figure 30. Low Ripple Output Configuration
Start-Up Regulator (VCC)
The high voltage bias regulator is integrated within the LM34923. The input pin (VIN) can be connected directly
to line voltages between 6V and 75V, with transient capability to 80V. The VCC output is regulated at 7.5V. The
VCC regulator output current is limited at approximately 30 mA.
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C3 must be located as close as possible to the VCC and RTN pins. In applications with a relatively high input
voltage, power dissipation in the bias regulator is a concern. An auxiliary voltage of between 7.5V and 10V can
be diode connected to the VCC pin to shut off the VCC regulator, thereby reducing internal power dissipation. The
current required into the VCC pin depends on the voltage applied to VCC and the switching frequency. See the
graph “ICC vs. Externally Applied VCC.” Internally a diode connects VCC to VIN requiring that the auxiliary voltage
be less than VIN.
The turn-on sequence is shown in Figure 31. During the initial delay (t1) VCC ramps up at a rate determined by
its current limit and C3 while internal circuitry stabilizes. When VCC reaches the upper threshold of its under-
voltage lock-out, the buck switch is enabled. The inductor current increases to the current limit threshold (ILIM
)
and during t2 VOUT increases as the output capacitor charges up. When VOUT reaches the intended voltage the
average inductor current decreases (t3) to the nominal load current (IO).
V
IN
t1
UVLO
V
CC
Vin
0V
SW Pin
I
LIM
Inductor
Current
I
O
t3
t2
V
OUT
Figure 31. Startup Sequence
Regulation Comparator
The feedback voltage at FB is compared to an internal 2.5V reference. In normal operation (the output voltage is
regulated), an on-time period is initiated when the voltage at FB falls below 2.5V. The buck switch stays on for
the on-time, causing the FB voltage to rise above 2.5V. After the on-time period, the buck switch stays off until
the FB voltage again falls below 2.5V. During start-up, the FB voltage will be below 2.5V at the end of each on-
time, resulting in the minimum off-time of 260 ns.
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Over-Voltage Comparator
The feedback voltage at FB is compared to an internal 2.85V reference. If the voltage at FB rises above 2.85V
the on-time pulse is immediately terminated. This condition can occur if the input voltage, or the output load,
change suddenly. The buck switch will not turn on again until the voltage at FB falls below 2.5V.
On-Time Generator and Shutdown
The on-time for the LM34923 is determined by the RT resistor, and is inversely proportional to the input voltage
(Vin), resulting in a nearly constant frequency as Vin is varied over its range. The on-time equation for the
LM34923 is:
1.25 x 10-10 x (RT + 500W) + 30 ns
TON
=
(VIN - 0.5V)
(5)
RT should be selected for a minimum on-time (at maximum VIN) greater than 200 ns, for proper current limit
operation. This requirement limits the maximum frequency for each application, depending on VIN and VOUT
.
The LM34923 can be remotely disabled by taking the RT/SD pin to ground. See Figure 32. The voltage at the
RT/SD pin is between 1.5 and 5.0 volts, depending on Vin and the value of the RT resistor.
Input
Voltage
VIN
LM34923
R
T
R /SD
T
STOP
RUN
Figure 32. Shutdown Implementation
Current Limit
The LM34923 contains an intelligent current limit OFF timer. If the current in the Buck switch reaches the current
limit threshold, the present cycle is immediately terminated, and a non-resetable OFF timer is triggered. The
length of off-time is controlled by the FB voltage and VIN (see the graph Current Limit Off-Time vs. VFB). When
FB = 0V, a maximum off-time is required. This condition occurs when the output is shorted, and during the initial
part of start-up. This amount of time ensures safe short circuit operation up to the maximum input voltage of 75V.
In cases of overload where the FB voltage is above zero volts (not a short circuit) the required current limit off-
time is less. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time,
and the start-up time. The off-time in microseconds is calculated from the following equation:
(VIN + 1.83V) x 0.28
TOFF
=
(VFB x 1.05) + 0.58
(6)
The current limit sensing circuit is blanked for the first 50-70 ns of each on-time so it is not falsely tripped by the
current surge which occurs at turn-on. The current surge is required by the re-circulating diode (D1) for its turn-
off recovery.
N-Channel Buck Switch and Driver
The LM34923 integrates an N-Channel Buck switch and associated floating high voltage gate driver. The gate
driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A 0.01
µF ceramic capacitor (C4) connected between the BST pin and SW pin provides the voltage to the driver during
the on-time.
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During each off-time, the SW pin is at approximately 0V, and the bootstrap capacitor charges from Vcc through
the internal diode. The minimum OFF timer, set to 260 ns, ensures a minimum time each cycle to recharge the
bootstrap capacitor.
The internal pre-charge switch at the SW pin is turned on for ≊150 ns during the minimum off-time period,
ensuring sufficient voltage exists across the bootstrap capacitor for the on-time. This feature helps prevent
operating problems which can occur during very light load conditions, involving a long off-time, during which the
voltage across the bootstrap capacitor could otherwise reduce below the Gate Drive UVLO threshold. The pre-
charge switch also helps prevent startup problems which can occur if the output voltage is pre-charged prior to
turn-on. After current limit detection, the pre-charge switch is turned on for the entire duration of the forced off-
time .
Under Voltage Detector
The Under Voltage Detector can be used to monitor the input voltage, or any other system voltage as long as the
voltage at the UV pin does not exceed its maximum rating.
The Under Voltage Output indicator pin (UVO) is connected to the drain of an internal N-channel MOSFET
capable of sustaining 10V in the off-state. An external pull-up resistor is required at UVO to an appropriate
voltage to indicate the status to downstream circuitry. The off-state voltage at the UVO pin can be higher or lower
than the voltage at VIN, but must not exceed 10V.
The UVO pin switches low when the voltage at the UV input pin is above its threshold. Typically the monitored
voltage threshold is set with a resistor divider (RUV1, RUV2) as shown in the Block Diagram. When the voltage at
the UV pin is below its threshold, the internal 5 µA current source at UV is enabled. As the input voltage
increases, taking UV above its threshold, the current source is disabled, raising the voltage at UV to provide
threshold hysteresis.
The UVO output is high when the VCC voltage is below its UVLO threshold, or when the LM34923 is shutdown
using the RT/SD pin (see Figure 32), regardless of the voltage at the UV pin.
Thermal Protection
The LM34923 should be operated so the junction temperature does not exceed 125°C during normal operation.
An internal Thermal Shutdown circuit is provided to shutdown the LM34923 in the event of a higher than normal
junction temperature. When activated, typically at 165°C, the controller is forced into a low power reset state by
disabling the buck switch. This feature prevents catastrophic failures from accidental device overheating. When
the junction temperature reduces below 145°C (typical hysteresis = 20°C) normal operation is resumed.
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SNVS695A –MARCH 2011–REVISED FEBRUARY 2013
APPLICATIONS INFORMATION
SELECTION OF EXTERNAL COMPONENTS
A guide for determining the component values is illustrated with a design example. Refer to the Block Diagram.
The following steps will configure the LM34923 for:
•
•
•
•
Input voltage range (Vin): 15V to 75V
Output voltage (VOUT): 10V
Load current (for continuous conduction mode): 100 mA to 400 mA
Switching Frequency: 300 kHz
RFB1, RFB2: VOUT = VFB x (RFB1 + RFB2) / RFB1, and since VFB = 2.5V, the ratio of RFB2 to RFB1 calculates as 3:1.
Standard values of 3.01 kΩ and 1.00 kΩ are chosen. Other values could be used as long as the 3:1 ratio is
maintained.
Fs and RT: Unless the application requires a specific frequency, the choice of frequency is generally a
compromise. A higher frequency allows for a smaller inductor, input capacitor, and output capacitor (both in value
and physical size), while providing a lower conversion efficiency. A lower frequency provides higher efficiency,
but generally requires higher values for the inductor, input capacitor and output capacitor. The maximum allowed
switching frequency for the LM34923 is limited by the minimum on-time (200 ns) at the maximum input voltage,
and by the minimum off-time (260 ns) at the minimum input voltage. The maximum frequency limit for each
application is defined by the following two calculations:
VOUT
FS(max)1
=
VIN(max) x 200 ns
(7)
VIN(min) - VOUT
FS(max)2
=
VIN(min) x 260 ns
(8)
The maximum allowed frequency is the lesser of the two above calculations. See the graph “Maximum Switching
Frequency”. For this exercise, Fs(max)1 calculates to 667 kHz, and Fs(max)2 calculates to 1.28 MHz. Therefore the
maximum allowed frequency for this example is 667 kHz, which is greater than the 300 kHz specified for this
design. Using Equation 1, RT calculates to 258 kΩ. A standard value 261 kΩ resistor is used. The minimum on-
time calculates to 469 ns, and the maximum on-time calculates to 2.28 µs.
L1: The main parameter affected by the inductor is the output current ripple amplitude. The choice of inductor
value therefore depends on both the minimum and maximum load currents, keeping in mind that the maximum
ripple current occurs at maximum Vin.
a) Minimum load current: To maintain continuous conduction at minimum Io (100 mA) if a flyback diode is
used, the ripple amplitude (IOR) must be less than 200 mA p-p so the lower peak of the waveform does not reach
zero. L1 is calculated using the following equation:
VOUT x (VIN - VOUT
)
L1 =
IOR x Fs x VIN
(9)
At Vin = 75V, L1(min) calculates to 146µH. The next larger standard value (150 µH) is chosen and with this value
IOR calculates to 195 mA p-p at Vin = 75V, and 75 mA p-p at Vin = 15V.
b) Maximum load current: At a load current of 400 mA, the peak of the ripple waveform must not reach the
minimum specified value of the LM34923’s current limit threshold (700 mA). Therefore the ripple amplitude must
be less than 600 mA p-p, which is already satisfied in the above calculation. With L1 = 150 µH, at maximum Vin
and Io, the peak of the ripple is 498 mA. While L1 must carry this peak current without saturating or exceeding its
temperature rating, it also must be capable of carrying the maximum specified value of the LM34923’s current
limit threshold without saturating, since the current limit is reached during startup.
The DC resistance of the inductor should be as low as possible. For example, if the inductor’s DCR is 0.5 ohm,
the power dissipated at maximum load current is 0.08W. While small, it is not insignificant compared to the load
power of 4W.
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C3: The capacitor on the VCC output provides not only noise filtering and stability, but its primary purpose is to
prevent false triggering of the VCC UVLO at the buck switch on/off transitions. C3 should be no smaller than 1 µF.
C2 and R3: When selecting the output filter capacitor C2, the items to consider are ripple voltage due to its ESR,
ripple voltage due to its capacitance, and the nature of the load.
A low ESR for C2 is generally desirable so as to minimize power losses and heating within the capacitor.
However, the regulator requires a minimum amount of ripple voltage at the feedback input for proper loop
operation. For the LM34923 the minimum ripple required at pin 7 is 25 mV p-p, requiring a minimum ripple at
VOUT of 100 mV for this example. Since the minimum ripple current (at minimum Vin) is 75 mA p-p, the minimum
ESR required at VOUT is 100 mV/75 mA = 1.33Ω. Since quality capacitors for SMPS applications have an ESR
considerably less than this, R3 is inserted as shown in the Block Diagram. R3’s value, along with C2’s ESR,
must result in at least 25 mV p-p ripple at pin 7. See LOW OUTPUT RIPPLE CONFIGURATIONS for techniques
to reduce the output ripple voltage.
D1: A power Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high
speed transitions at the SW pin may inadvertently affect the IC’s operation through external or internal EMI. The
important parameters are reverse recovery time and forward voltage. The reverse recovery time determines how
long the reverse current surge lasts with each turn-on of the internal buck switch. The forward voltage drop
affects efficiency. The diode’s reverse voltage rating must be at least as great as the maximum input voltage,
plus ripple and transients, and its current rating must be at least as great as the maximum current limit
specification. The diode’s average power dissipation is calculated from:
PD1 = VF x IOUT x (1–D)
(10)
Where VF is the diode’s forward voltage drop, and D is the on-time duty cycle.
C1: This capacitor’s purpose is to supply most of the switch current during the on-time, and limit the voltage
ripple at Vin, on the assumption that the voltage source feeding Vin has an output impedance greater than zero.
At maximum load current, when the buck switch turns on, the current into the VIN pin suddenly increases to the
lower peak of the output current waveform, ramp up to the peak value, then drop to zero at turn-off. The average
input current during this on-time is the load current (400 mA). For a worst case calculation, C1 must supply this
average load current during the maximum on-time. To keep the input voltage ripple to less than 1V (for this
exercise), C1 calculates to:
I x tON
0.4A x 2.28 ms
= 0.91 mF
C1 =
=
DV
1V
(11)
Quality ceramic capacitors in this value have a low ESR which adds only a few millivolts to the ripple. It is the
capacitance which is dominant in this case. To allow for the capacitor’s tolerance, temperature effects, and
voltage effects, a 1.0 µF, 100V, X7R capacitor is used.
C4: The recommended value is 0.01µF for C4, as this is appropriate in the majority of applications. A high quality
ceramic capacitor, with low ESR is recommended as C4 supplies the surge current to charge the buck switch
gate at turn-on. A low ESR also ensures a quick recharge during each off-time.
C5: This capacitor helps avoid supply voltage transients and ringing due to long lead inductance at VIN. A low
ESR, 0.1µF ceramic chip capacitor is recommended, located close to the LM34923.
UV and UVO pins: The Under Voltage Detector function is used to monitor a system voltage, such as the input
voltage at VIN, by connecting the UV pin to two resistors (RUV1, RUV2) as shown in the Block Diagram. When the
voltage at the UV pin increases above its threshold the UVO pin switches low. The UVO pin is high when the
voltage at the UV input pin is below its threshold. Hysteresis is provided by the internal 5µA current source which
is enabled when the voltage at the UV pin is below its threshold. The resistor values are calculated using the
following procedure:
Choose the upper and lower thresholds (VUVH and VUVL) at VIN.
VUV(HYS)
VUVH - VUVL
=
RUV2
=
5 mA
5 mA
(12)
RUV2 x 2.5V
VUVL - 2.5V
RUV1
=
(13)
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As an example, assume the application requires the following thresholds: VUVH = 15V and VUVL = 14V. Therefore
VUV(HYS) = 1V. The resistor values calculate to:
(14)
RUV2 = 200kΩ, RUV1 = 43.5kΩ
(15)
Capacitor C6 is added to filter noise and ripple, which may be present on the VIN line. Where the resistor values
are known, the threshold voltages and hysteresis are calculated from the following:
VUVH = 2.5V + [RUV2 x (2.5V+ 5 mA)]
RUV1
(16)
(RUV1 + RUV2
RUV1
)
VUVL = 2.5V x
(17)
(18)
VUV(HYS) = RUV2 x 5 µA
The pull-up voltage for the UVO output can be any voltage under 10V. The maximum continuous current into the
UVO output pin should not exceed 5 mA.
FINAL CIRCUIT
The final circuit is shown in Figure 33. The circuit was tested, and the resulting performance is shown in
Figure 34 and Figure 35.
15V - 75V
Input
VIN
VIN
VCC
BST
SW
C3
1 mF
C5
0.1 mF
C1
LM34923
1 mF
R
T
GND
261 kW
0.01 mF
C4
150 mH
VOUT
10V
L1
RT/SD
UV
SHUT
DOWN
R
UV2
200 kW
R3
1.4W
D1
R
FB2
R
UV1
C6
1000 pF
43.2 kW
3.01 kW
C2
10 mF
FB
R
UVO
100 kW
GND
R
FB1
1 kW
UVO
RTN
UV
STATUS
Figure 33. LM34923 Example Circuit
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Figure 34. Efficiency vs. Load Current and VIN
LOW OUTPUT RIPPLE CONFIGURATIONS
Figure 35. Efficiency vs. VIN
For applications where low output ripple is required, the following options can be used to reduce or nearly
eliminate the ripple.
a) Reduced ripple configuration: In Figure 36, Cff is added across RFB2 to AC-couple the ripple at VOUT directly
to the FB pin. This allows the ripple at VOUT to be reduced to a minimum of 25 mVp-p by reducing R3, since the
ripple at VOUT is not attenuated by the feedback resistors. The minimum value for Cff is determined from:
3 x tON (max)
Cff =
(RFB1//RFB2
)
(19)
where tON(max) is the maximum on-time, which occurs at the minimum input voltage. The next larger standard
value capacitor should be used for Cff.
L1
SW
V
OUT
Cff
R
R3
LM34923
FB2
FB
R
FB1
C2
Figure 36. Reduced Ripple Configuration
b) Minimum ripple configuration: If the application requires a lower value of ripple (<10 mVp-p), the circuit of
Figure 37 can be used. R3 is removed, and the resulting output ripple voltage is determined by the inductor’s
ripple current and C2’s characteristics. RA and CA are chosen to generate a sawtooth waveform at their junction,
and that voltage is AC-coupled to the FB pin via CB. To determine the values for RA, CA and CB, use the
following procedure:
Calculate VA = VOUT - (VSW x (1 - (VOUT/VIN(min))))
(20)
where VSW is the absolute value of the voltage at the SW pin during the off-time. If a Schottky diode is used for
the flyback function, the off-time voltage is in the range of 0.5V to 1V, depending on the specific diode used, and
the maximum load current. VA is the DC voltage at the RA/CA junction, and is used in the next equation.
- Calculate RA x CA = (VIN(min) - VA) x tON/ΔV
(21)
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where tON is the maximum on-time (at minimum input voltage), and ΔV is the desired ripple amplitude at the
RA/CA junction (typically 40-50 mV). RA and CA are then chosen from standard value components to satisfy the
above product. Typically CA is 1000 pF to 5000 pF, and RA is 10 kΩ to 300 kΩ. CB is then chosen large
compared to CA, typically 0.1 µF.
L1
SW
V
OUT
CA
C2
RA
CB
LM34923
R
FB2
FB
R
FB1
Figure 37. Minimum Output Ripple Using Ripple Injection
c) Alternate minimum ripple configuration: The circuit in Figure 38 is the same as that in the Block Diagram,
except the output voltage is taken from the junction of R3 and C2. The ripple at VOUT is determined by the
inductor’s ripple current and C2’s characteristics. However, R3 slightly degrades the load regulation. This circuit
may be suitable if the load current is fairly constant.
L1
SW
LM34923
R
R
FB2
R3
FB
V
OUT
FB1
C2
Figure 38. Alternate Minimum Output Ripple
PC Board Layout
The LM34923 regulation, over-voltage, and current limit comparators are very fast, and respond to short duration
noise pulses. Layout considerations are therefore critical for optimum performance. The layout must be as neat
and compact as possible, and all of the components must be as close as possible to the associated pins. The
two major current loops have currents which switch very fast, and so the loops should be as small as possible to
minimize conducted and radiated EMI. The first loop is formed by C1, through VIN to the SW pin, L1, C2, and
back to C1. The second loop is formed by L1, C2, D1, and back to L1. Since a current equal to the load current
switches between these two loops with each transition from on-time to off-time and back to on-time, it is
imperative that the ground end of C1 have a short and direct connection to D1’s anode, without going through
vias or a lengthy route. The power dissipation in the LM34923 can be approximated by determining the total
conversion loss (PIN – POUT), and then subtracting the power losses in D1, and in the inductor. The power loss in
the diode is approximately:
PD1 = IOUT x VF x (1–D)
(22)
where VF is the diode’s forward voltage drop, and D is the on-time duty cycle.
PL1 = IOUT2 x RL x 1.1
(23)
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where RL is the inductor’s DC resistance, and the 1.1 factor is an approximation for the AC losses. If it is
expected that the internal dissipation of the LM34923 will produce excessive junction temperatures during normal
operation, good use of the PC board’s ground plane can help to dissipate heat. Additionally the use of wide PC
board traces, where possible, can help conduct heat away from the IC. Judicious positioning of the PC board
within the end product, along with the use of any available air flow (forced or natural convection) can help reduce
the junction temperature.
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SNVS695A –MARCH 2011–REVISED FEBRUARY 2013
REVISION HISTORY
Changes from Original (February 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM34923MM/NOPB
LM34923MMX/NOPB
ACTIVE
ACTIVE
VSSOP
VSSOP
DGS
DGS
10
10
1000 RoHS & Green
3500 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
SB5B
SB5B
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM34923MM/NOPB
LM34923MMX/NOPB
VSSOP
VSSOP
DGS
DGS
10
10
1000
3500
178.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM34923MM/NOPB
LM34923MMX/NOPB
VSSOP
VSSOP
DGS
DGS
10
10
1000
3500
208.0
367.0
191.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
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EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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