LM3524D [TI]
40V、0.2A 350KHz PWM 控制器;
| 型号： | LM3524D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 40V、0.2A 350KHz PWM 控制器 控制器 |
| 文件： | 总29页 (文件大小：1464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM2524D, LM3524D
www.ti.com
SNVS766E –JUNE 2009–REVISED MAY 2013
LM2524D/LM3524D Regulating Pulse Width Modulator
Check for Samples: LM2524D, LM3524D
The LM3524D has a ±1% precision 5V reference.
1
FEATURES
The current carrying capability of the output drive
transistors has been raised to 200 mA while reducing
VCEsat and increasing VCE breakdown to 60V. The
common mode voltage range of the error-amp has
been raised to 5.5V to eliminate the need for a
resistive divider from the 5V reference.
2
•
Fully Interchangeable With Standard LM3524
Family
•
±1% Precision 5V Reference With Thermal
Shut-Down
•
•
•
Output Current to 200 mA DC
60V Output Capability
In the LM3524D the circuit bias line has been isolated
from the shut-down pin. This prevents the oscillator
pulse amplitude and frequency from being disturbed
by shut-down. Also at high frequencies (≃300 kHz)
the max. duty cycle per output has been improved to
44% compared to 35% max. duty cycle in other
3524s.
Wide Common Mode Input Range for Error-
Amp
•
•
•
•
One Pulse per Period (Noise Suppression)
Improved Max. Duty Cycle at High Frequencies
Double Pulse Suppression
In addition, the LM3524D can now be synchronized
externally, through pin 3. Also a latch has been
added to insure one pulse per period even in noisy
environments. The LM3524D includes double pulse
suppression logic that insures when a shut-down
condition is removed the state of the T-flip-flop will
change only after the first clock pulse has arrived.
This feature prevents the same output from being
pulsed twice in a row, thus reducing the possibility of
core saturation in push-pull designs.
Synchronize Through Pin 3
DESCRIPTION
The LM3524D family is an improved version of the
industry standard LM3524. It has improved
specifications and additional features yet is pin for pin
compatible with existing 3524 families. New features
reduce the need for additional external circuitry often
required in the original version.
Connection Diagram
Figure 1. Top View
See Package Number NFG
See Package Number D
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
LM2524D, LM3524D
SNVS766E –JUNE 2009–REVISED MAY 2013
www.ti.com
Block Diagram
2
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
www.ti.com
SNVS766E –JUNE 2009–REVISED MAY 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage
40V
55V
Collector Supply Voltage
LM2524D
LM3524D
40V
Output Current DC (each)
200 mA
Oscillator Charging Current (Pin 7)
Internal Power Dissipation
5 mA
1W
(3)
Operating Junction Temperature Range
LM2524D
LM3524D
−40°C to +125°C
0°C to +125°C
150°
Maximum Junction Temperature
Storage Temperature Range
−65°C to +150°C
260°C
Lead Temperature (Soldering 4 sec.)
NFG, D Pkg.
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its rated operating conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) For operation at elevated temperatures, devices in the NFG package must be derated based on a thermal resistance of 86°C/W,
junction to ambient. Devices in the D package must be derated at 125°C/W, junction to ambient.
Electrical Characteristics(1)
Symbol
Parameter
Conditions
LM2524D
LM3524D
Units
Typ
Tested Design
Limit(2) Limit(3)
Typ
Tested Design
Limit(2) Limit(3)
REFERENCE SECTION
VREF
Output Voltage
5
4.85
5.15
15
4.80
5.20
30
5
4.75
5.25
VMin
VMax
VRLine
VRLoad
Line Regulation
Load Regulation
VIN = 8V to 40V
10
10
66
10
10
66
25
25
50
50
mVMax
mVMax
dB
IL = 0 mA to 20 mA
f = 120 Hz
15
25
ΔVIN/ΔVREF Ripple Rejection
IOS
Short Circuit Current
VREF = 0
25
25
mA Min
50
50
180
200
mA Max
NO
Output Noise
10 Hz ≤ f ≤ 10 kHz
40
20
100
500
40
20
100
μVrms
Max
Long Term Stability
TA = 125°C
mV/kHr
OSCILLATOR SECTION
fOSC
fOSC
Max. Freq.
RT = 1k, CT = 0.001 μF(4)
RT = 5.6k, CT = 0.01 μF(4)
550
20
350
20
kHzMin
kHzMin
Initial Accuracy
17.5
17.5
22.5
34
22.5
30
kHzMax
kHzMin
RT = 2.7k, CT = 0.01 μF(4)
38
38
42
46
kHzMax
(1) Unless otherwise stated, these specifications apply for TA = TJ = 25°C. Boldface numbers apply over the rated temperature range:
LM2524D is −40° to 85°C and LM3524D is 0°C to 70°C. VIN = 20V and fOSC = 20 kHz.
(2) Tested limits are ensured and 100% tested in production.
(3) Design limits are ensured (but not 100% production tested) over the indicated temperature and supply voltage range. These limits are
not used to calculate outgoing quality level.
(4) The value of a Ct capacitor can vary with frequency. Careful selection of this capacitor must be made for high frequency operation.
Polystyrene was used in this test. NPO ceramic or polypropylene can also be used.
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
SNVS766E –JUNE 2009–REVISED MAY 2013
www.ti.com
Electrical Characteristics(1) (continued)
Symbol
Parameter
Conditions
LM2524D
LM3524D
Units
Typ
Tested Design
Limit(2) Limit(3)
Typ
Tested Design
Limit(2) Limit(3)
ΔfOSC
Freq. Change with VIN
VIN = 8 to 40V
0.5
5
1
0.5
5
1.0
%
Max
ΔfOSC
Freq. Change with Temp. TA = −55°C to +125°C
at 20 kHz RT = 5.6k,
%
CT = 0.01 μF
VOSC
tPW
Output Amplitude (Pin 3)
RT = 5.6k, CT = 0.01 μF
3
2.4
1.5
3
2.4
VMin
(5)
Output Pulse Width (Pin 3) RT = 5.6k, CT = 0.01 μF
0.5
3.4
1.1
0.5
1.5
3.8
0.6
μsMax
VMax
VMin
Sawtooth Peak Voltage
Sawtooth Valley Voltage
RT = 5.6k, CT = 0.01 μF
RT = 5.6k, CT = 0.01 μF
3.6
0.8
3.8
0.6
ERROR-AMP SECTION
VIO
IIB
Input Offset Voltage
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
2
1
8
8
10
10
1
2
1
10
10
1
mVMax
μAMax
μAMax
μAMin
Input Bias Current
Input Offset Current
IIO
0.5
1.0
65
0.5
ICOSI
Compensation Current
(Sink)
VIN(I) − VIN(NI) = 150 mV
65
95
95
125
125
μAMax
μAMin
ICOSO
Compensation Current
(Source)
VIN(NI) − VIN(I) = 150 mV
−125
−125
−95
−95
−65
74
−65
μAMax
dBMin
VMin
AVOL
Open Loop Gain
RL = ∞, VCM = 2.5 V
80
60
1.4
5.4
80
70
1.5
5.5
60
VCMR
Common Mode Input
Voltage Range
1.5
5.5
VMax
CMRR
Common Mode Rejection
Ratio
90
3
80
90
2
80
dBMin
GBW
VO
Unity Gain Bandwidth
Output Voltage Swing
AVOL = 0 dB, VCM = 2.5V
MHz
VMin
VMax
RL = ∞
0.5
5.5
0.5
5.5
PSRR
Power Supply Rejection
Ratio
VIN = 8 to 40V
80
70
80
65
dbMin
COMPARATOR SECTION
Minimum Duty Cycle
Pin 9 = 0.8V,
[RT = 5.6k, CT = 0.01 μF]
tON/tOSC
tON/tOSC
tON/tOSC
VCOMPZ
0
0
0
0
%
Max
Maximum Duty Cycle
Maximum Duty Cycle
Pin 9 = 3.9V,
[RT = 5.6k, CT = 0.01 μF]
49
45
35
49
45
35
%
%
Min
Pin 9 = 3.9V,
[RT = 1k, CT = 0.001 μF]
44
1
44
1
Min
Input Threshold
(Pin 9)
Zero Duty Cycle
V
VCOMPM
IIB
Input Threshold (Pin 9)
Input Bias Current
Maximum Duty Cycle
3.5
3.5
V
−1
−1
μA
CURRENT LIMIT SECTION
VSEN
Sense Voltage
V
(Pin 2) − V(Pin 1) ≥ 150 mV
180
220
180
220
mVMin
200
200
mVMax
mV/°C
VMin
TC-Vsense
Sense Voltage T.C.
0.2
−0.7
1
0.2
−0.7
1
Common Mode Voltage
Range
V5 − V4 = 300 mV
VMax
(5) OSC amplitude is measured open circuit. Available current is limited to 1 mA so care must be exercised to limit capacitive loading of fast
pulses.
4
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
www.ti.com
SNVS766E –JUNE 2009–REVISED MAY 2013
Electrical Characteristics(1) (continued)
Symbol
Parameter
Conditions
LM2524D
LM3524D
Units
Typ
Tested Design
Limit(2) Limit(3)
Typ
Tested Design
Limit(2) Limit(3)
SHUT DOWN SECTION
VSD High Input Voltage
V
(Pin 2) − V(Pin 1) ≥ 150 mV
1
1
0.5
1.5
1
1
0.5
1.5
VMin
VMax
mA
ISD
High Input Current
I(pin 10)
OUTPUT SECTION (EACH OUTPUT)
VCES
ICES
Collector Emitter Voltage
Breakdown
IC ≤ 100 μA
55
50
40
VMin
Collector Leakage Current VCE = 60V
VCE = 55V
VCE = 40V
0.1
μAMax
0.1
0.2
1.5
18
50
0.7
2.5
17
VCESAT
Saturation Voltage
IE = 20 mA
IE = 200 mA
IE = 50 mA
0.2
1.5
18
0.5
2.2
17
VMax
VEO
tR
Emitter Output Voltage
Rise Time
VMin
ns
VIN = 20V,
IE = −250 μA
RC = 2k
200
200
tF
Fall Time
RC = 2k
100
100
ns
SUPPLY CHARACTERISTICS SECTION
VIN
Input Voltage Range
After Turn-on
8
8
VMin
VMax
°C
40
40
(6)
T
Thermal Shutdown Temp.
Stand By Current
160
5
160
5
IIN
VIN = 40V(7)
10
10
mA
(6) For operation at elevated temperatures, devices in the NFG package must be derated based on a thermal resistance of 86°C/W,
junction to ambient. Devices in the D package must be derated at 125°C/W, junction to ambient.
(7) Pins 1, 4, 7, 8, 11, and 14 are grounded; Pin 2 = 2V. All other inputs and outputs open.
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
SNVS766E –JUNE 2009–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics
Switching Transistor Peak Output Current
vs Temperature
Maximum Average Power Dissipation (NFG, D Packages)
Figure 2.
Figure 3.
Maximum & Minimum
Duty Cycle Threshold Voltage
Output Transistor
Saturation Voltage
Figure 4.
Figure 5.
Output Transistor Emitter
Voltage
Reference Transistor
Peak Output Current
Figure 6.
Figure 7.
6
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
www.ti.com
SNVS766E –JUNE 2009–REVISED MAY 2013
Typical Performance Characteristics (continued)
Standby Current
vs Voltage
Standby Current
vs Temperature
Figure 8.
Figure 9.
Current Limit Sense Voltage
Figure 10.
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
SNVS766E –JUNE 2009–REVISED MAY 2013
www.ti.com
TEST CIRCUIT
8
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
www.ti.com
SNVS766E –JUNE 2009–REVISED MAY 2013
Functional Description
Internal Voltage Regulator
The LM3524D has an on-chip 5V, 50 mA, short circuit protected voltage regulator. This voltage regulator
provides a supply for all internal circuitry of the device and can be used as an external reference.
For input voltages of less than 8V the 5V output should be shorted to pin 15, VIN, which disables the 5V
regulator. With these pins shorted the input voltage must be limited to a maximum of 6V. If input voltages of
6V–8V are to be used, a pre-regulator, as shown in Figure 11, must be added.
*Minimum CO of 10 μF required for stability.
Figure 11.
Oscillator
The LM3524D provides a stable on-board oscillator. Its frequency is set by an external resistor, RT and capacitor,
CT. A graph of RT, CT vs oscillator frequency is shown is Figure 12. The oscillator's output provides the signals
for triggering an internal flip-flop, which directs the PWM information to the outputs, and a blanking pulse to turn
off both outputs during transitions to ensure that cross conduction does not occur. The width of the blanking
pulse, or dead time, is controlled by the value of CT, as shown in Figure 13. The recommended values of RT are
1.8 kΩ to 100 kΩ, and for CT, 0.001 μF to 0.1 μF.
If two or more LM3524D's must be synchronized together, the easiest method is to interconnect all pin 3
terminals, tie all pin 7's (together) to a single CT, and leave all pin 6's open except one which is connected to a
single RT. This method works well unless the LM3524D's are more than 6″ apart.
A second synchronization method is appropriate for any circuit layout. One LM3524D, designated as master,
must have its RTCT set for the correct period. The other slave LM3524D(s) should each have an RTCT set for a
10% longer period. All pin 3's must then be interconnected to allow the master to properly reset the slave units.
The oscillator may be synchronized to an external clock source by setting the internal free-running oscillator
frequency 10% slower than the external clock and driving pin 3 with a pulse train (approx. 3V) from the clock.
Pulse width should be greater than 50 ns to insure full synchronization.
Figure 12.
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
SNVS766E –JUNE 2009–REVISED MAY 2013
www.ti.com
Figure 13.
Error Amplifier
The error amplifier is a differential input, transconductance amplifier. Its gain, nominally 86 dB, is set by either
feedback or output loading. This output loading can be done with either purely resistive or a combination of
resistive and reactive components. A graph of the amplifier's gain vs output load resistance is shown in
Figure 14.
Figure 14.
The output of the amplifier, or input to the pulse width modulator, can be overridden easily as its output
impedance is very high (ZO ≃ 5 MΩ). For this reason a DC voltage can be applied to pin 9 which will override the
error amplifier and force a particular duty cycle to the outputs. An example of this could be a non-regulating
motor speed control where a variable voltage was applied to pin 9 to control motor speed. A graph of the output
duty cycle vs the voltage on pin 9 is shown in Figure 15.
The duty cycle is calculated as the percentage ratio of each output's ON-time to the oscillator period. Paralleling
the outputs doubles the observed duty cycle.
10
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
www.ti.com
SNVS766E –JUNE 2009–REVISED MAY 2013
Figure 15.
The amplifier's inputs have a common-mode input range of 1.5V–5.5V. The on board regulator is useful for
biasing the inputs to within this range.
Current Limiting
The function of the current limit amplifier is to override the error amplifier's output and take control of the pulse
width. The output duty cycle drops to about 25% when a current limit sense voltage of 200 mV is applied
between the +CL and −CLsense terminals. Increasing the sense voltage approximately 5% results in a 0% output
duty cycle. Care should be taken to ensure the −0.7V to +1.0V input common-mode range is not exceeded.
In most applications, the current limit sense voltage is produced by a current through a sense resistor. The
accuracy of this measurement is limited by the accuracy of the sense resistor, and by a small offset current,
typically 100 μA, flowing from +CL to −CL.
Output Stages
The outputs of the LM3524D are NPN transistors, capable of a maximum current of 200 mA. These transistors
are driven 180° out of phase and have non-committed open collectors and emitters as shown in Figure 16.
Figure 16.
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
SNVS766E –JUNE 2009–REVISED MAY 2013
www.ti.com
Typical Applications
Figure 17. Positive Regulator, Step-Up Basic Configuration (IIN(MAX) = 80 mA)
(1)
Figure 18. Positive Regulator, Step-Up Boosted Current Configuration
12
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
www.ti.com
SNVS766E –JUNE 2009–REVISED MAY 2013
Figure 19. Positive Regulator, Step-Down Basic Configuration (IIN(MAX) = 80 mA)
(2)
Figure 20. Positive Regulator, Step-Down Boosted Current Configuration
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
SNVS766E –JUNE 2009–REVISED MAY 2013
www.ti.com
Figure 21. Boosted Current Polarity Inverter
(3)
Basic Switching Regulator Theory and Applications
The basic circuit of a step-down switching regulator circuit is shown in Figure 22, along with a practical circuit
design using the LM3524D in Figure 25.
Figure 22. Basic Step-Down Switching Regulator
The circuit works as follows: Q1 is used as a switch, which has ON and OFF times controlled by the pulse width
modulator. When Q1 is ON, power is drawn from VIN and supplied to the load through L1; VA is at approximately
VIN, D1 is reverse biased, and Co is charging. When Q1 turns OFF the inductor L1 will force VA negative to keep
the current flowing in it, D1 will start conducting and the load current will flow through D1 and L1. The voltage at
VAis smoothed by the L1, Co filter giving a clean DC output. The current flowing through L1 is equal to the
nominal DC load current plus some ΔIL which is due to the changing voltage across it. A good rule of thumb is to
set ΔILP-P ≃ 40% × Io.
14
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
www.ti.com
SNVS766E –JUNE 2009–REVISED MAY 2013
Figure 23. Relation of Switch Timing to Inductor Current in Step-Down Regulator
(4)
(5)
−
Neglecting VSAT, VD, and settling ΔIL+ = ΔIL ;
where T = Total Period
The above shows the relation between VIN, Vo and duty cycle.
(6)
(7)
as Q1 only conducts during tON
.
The efficiency, η, of the circuit is:
(8)
ηMAX will be further decreased due to switching losses in Q1. For this reason Q1 should be selected to have the
maximum possible fT, which implies very fast rise and fall times.
Calculating Inductor L1
(9)
Since ΔIL+ = ΔIL− = 0.4Io
Solving the above for L1
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
SNVS766E –JUNE 2009–REVISED MAY 2013
www.ti.com
(10)
where: L1 is in Henrys
f is switching frequency in Hz
Also, see LM1578 data sheet for graphical methods of inductor selection.
Calculating Output Filter Capacitor Co
Figure 23 shows L1's current with respect to Q1's tON and tOFF times (VA is at the collector of Q1). This curent
must flow to the load and Co. Co's current will then be the difference between IL, and Io.
Ico = IL − Io
(11)
From Figure 23 it can be seen that current will be flowing into Co for the second half of tON through the first half of
tOFF, or a time, tON/2 + tOFF/2. The current flowing for this time is ΔIL/4. The resulting ΔVc or ΔVo is described by:
(12)
For best regulation, the inductor's current cannot be allowed to fall to zero. Some minimum load current Io, and
thus inductor current, is required as shown below:
(13)
Figure 24. Inductor Current Slope in Step-Down Regulator
A complete step-down switching regulator schematic, using the LM3524D, is illustrated in Figure 25. Transistors
Q1 and Q2 have been added to boost the output to 1A. The 5V regulator of the LM3524D has been divided in
half to bias the error amplifier's non-inverting input to within its common-mode range. Since each output
transistor is on for half the period, actually 45%, they have been paralleled to allow longer possible duty cycle, up
to 90%. This makes a lower possible input voltage. The output voltage is set by:
(14)
where VNI is the voltage at the error amplifier's non-inverting input.
16
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
www.ti.com
SNVS766E –JUNE 2009–REVISED MAY 2013
Resistor R3 sets the current limit to:
(15)
Figure 26 and Figure 27 show a PC board layout and stuffing diagram for the 5V, 1A regulator of Figure 25. The
regulator's performance is listed in Table 1.
*Mounted to Staver Heatsink No. V5-1.
Q1 = BD344
Q2 = 2N5023
L1 = >40 turns No. 22 wire on Ferroxcube No. K300502 Torroid core.
Figure 25. 5V, 1 Amp Step-Down Switching Regulator
Table 1.
Parameter
Conditions
VIN = 10V, Io = 1A
Typical Characteristics
Output Voltage
5V
Switching Frequency
Short Circuit Current Limit
Load Regulation
VIN = 10V, Io = 1A
VIN = 10V
20 kHz
1.3A
VIN = 10V
Io = 0.2 − 1A
3 mV
Line Regulation
ΔVIN = 10 − 20V,
Io = 1A
6 mV
80%
Efficiency
VIN = 10V, Io = 1A
VIN = 10V, Io = 1A
Output Ripple
10 mVp-p
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
SNVS766E –JUNE 2009–REVISED MAY 2013
www.ti.com
Figure 26. 5V, 1 Amp Switching Regulator, Foil Side
Figure 27. Stuffing Diagram, Component Side
The Step-Up Switching Regulator
Figure 28 shows the basic circuit for a step-up switching regulator. In this circuit Q1 is used as a switch to
alternately apply VIN across inductor L1. During the time, tON, Q1 is ON and energy is drawn from VIN and stored
in L1; D1 is reverse biased and Io is supplied from the charge stored in Co. When Q1 opens, tOFF, voltage V1 will
rise positively to the point where D1 turns ON. The output current is now supplied through L1, D1 to the load and
any charge lost from Co during tON is replenished. Here also, as in the step-down regulator, the current through
L1 has a DC component plus some ΔIL. ΔIL is again selected to be approximately 40% of IL. Figure 29 shows the
inductor's current in relation to Q1's ON and OFF times.
18
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
www.ti.com
SNVS766E –JUNE 2009–REVISED MAY 2013
Figure 28. Basic Step-Up Switching Regulator
Figure 29. Relation of Switch Timing to Inductor Current in Step-Up Regulator
(16)
(17)
Since ΔIL+ = ΔIL−, VINtON = VotOFF − VINtOFF
,
and neglecting VSAT and VD1
The above equation shows the relationship between VIN, Vo and duty cycle.
In calculating input current IIN(DC), which equals the inductor's DC current, assume first 100% efficiency:
(18)
(19)
for η = 100%, POUT = PIN
This equation shows that the input, or inductor, current is larger than the output current by the factor (1 +
tON/tOFF). Since this factor is the same as the relation between Vo and VIN, IIN(DC) can also be expressed as:
(20)
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
SNVS766E –JUNE 2009–REVISED MAY 2013
www.ti.com
So far it is assumed η = 100%, where the actual efficiency or ηMAX will be somewhat less due to the saturation
voltage of Q1 and forward on voltage of D1. The internal power loss due to these voltages is the average IL
current flowing, or IIN, through either VSAT or VD1. For VSAT = VD1 = 1V this power loss becomes IIN(DC) (1V). ηMAX
is then:
(21)
(22)
This equation assumes only DC losses, however ηMAX is further decreased because of the switching time of Q1
and D1.
In calculating the output capacitor Co it can be seen that Co supplies Io during tON. The voltage change on Co
during this time will be some ΔVc = ΔVo or the output ripple of the regulator. Calculation of Co is:
(23)
where: Co is in farads, f is the switching frequency,
ΔVo is the p-p output ripple
Calculation of inductor L1 is as follows:
(24)
VIN is applied across L1
(25)
where: L1 is in henrys, f is the switching frequency in Hz
To apply the above theory, a complete step-up switching regulator is shown in Figure 30. Since VIN is 5V, VREF is
tied to VIN. The input voltage is divided by 2 to bias the error amplifier's inverting input. The output voltage is:
(26)
The network D1, C1 forms a slow start circuit.
20
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
www.ti.com
SNVS766E –JUNE 2009–REVISED MAY 2013
This holds the output of the error amplifier initially low thus reducing the duty-cycle to a minimum. Without the
slow start circuit the inductor may saturate at turn-on because it has to supply high peak currents to charge the
output capacitor from 0V. It should also be noted that this circuit has no supply rejection. By adding a reference
voltage at the non-inverting input to the error amplifier, see Figure 31, the input voltage variations are rejected.
The LM3524D can also be used in inductorless switching regulators. Figure 32 shows a polarity inverter which if
connected to Figure 30 provides a −15V unregulated output.
L1 = > 25 turns No. 24 wire on Ferroxcube No. K300502 Toroid core.
Figure 30. 15V, 0.5A Step-Up Switching Regulator
Figure 31. Replacing R3/R4 Divider in Figure 30 with Reference Circuit Improves Line Regulation
Figure 32. Polarity Inverter Provides Auxiliary −15V Unregulated Output from Circuit of Figure 30
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: LM2524D LM3524D
LM2524D, LM3524D
SNVS766E –JUNE 2009–REVISED MAY 2013
www.ti.com
REVISION HISTORY
Changes from Revision D (May 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
22
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM2524D LM3524D
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM3524DM/NOPB
LM3524DMX/NOPB
ACTIVE
ACTIVE
SOIC
SOIC
D
D
16
16
48
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 125
0 to 125
LM3524DM
LM3524DM
Samples
Samples
2500 RoHS & Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3524DMX/NOPB
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.3
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 16
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
LM3524DMX/NOPB
D
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM3524DM/NOPB
D
16
48
495
8
4064
3.05
Pack Materials-Page 3
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
LM3524DMWC
IC 0.2 A SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, UUC, WAFER, Switching Regulator or Controller
NSC
LM3524DMX
IC 0.2 A SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PDSO16, PLASTIC, SMT-16, Switching Regulator or Controller
NSC
LM3524DMX/NOPB
IC 0.2 A SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PDSO16, LEAD FREE, PLASTIC, SMT-16, Switching Regulator or Controller
NSC
LM3524DN/NOPB
IC 0.2 A SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PDIP16, PLASTIC, DIP-16, Switching Regulator or Controller
NSC
©2020 ICPDF网 联系我们和版权申明