LM3549SQE/NOPB [TI]

高功率顺序驱动 LED 驱动器 | RTW | 24 | -30 to 85;


型号：	LM3549SQE/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	高功率顺序驱动 LED 驱动器 \| RTW \| 24 \| -30 to 85 驱动接口集成电路驱动器
文件：	总28页 (文件大小：1328K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM3549

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SNVS640A –AUGUST 2010–REVISED MAY 2013

LM3549 High Power Sequential LED Driver

Check for Samples: LM3549

FEATURES

DESCRIPTION

The LM3549 is a high power LED driver with up to

700mA output current. It has three constant current

LED drivers and a buck boost SMPS for driving RGB

LEDs with high efficiency. LED drivers are designed

for sequential drive so only one driver can be enabled

at a time.

•

Over-Current Protection

Over-Temperature Protection

I²C Compatible Interface

Under-Voltage Lockout

LED Open and Short Protection and Detection

95% Peak Efficiency Buck-Boost Converter

LED driver output current settings can be stored to

integrated non-volatile memory which allows stand-

alone operation without I²C interface. Non-volatile

memory is rewritable so current setting can be

changed if needed.

NVM Memory for Calibration Data and

Standalone Usage without I²C Control

•

Soft Start

The LM3549 has a fault detection feature that can

detect several different fault conditions. In case of a

fault error flags are set and FAULT output sends

interrupt to control logic. Error flags can be read

through I²C interface.

APPLICATIONS

•

Portable Video Projectors

High Power LED Driving

Total brightness can be controlled with PWM input or

with master fader register if I²C interface is used.

KEY SPECIFICATIONS

•

Integrated buck-boost Converter

Programmable LED Drivers

700 mA Maximum Drive Current

±6% Current Accuracy Over Temperature

24-pin WQFN Package

L1 2.2 mH

2.7V to 5.5V

VDD

VOUT

OUT

10 mF

4.7 mF

SDA

SCL

LM3549

R_OUT

G_OUT

B_OUT

RED LED

CONTROL

LOGIC

R_EN

G_EN

B_EN

PWM

GREEN LED

BLUE LED

FAULT

GND

Figure 1. Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM3549

SNVS640A –AUGUST 2010–REVISED MAY 2013

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PIN 1 ID

BOTTOM VIEW

TOP VIEW

Figure 2. 24–Pin WQFN Package, No Pullback

See package number RTW0024A

Pin Descriptions

Name

Pin No.

Type

Description

Inductor positive terminal 1

Inductor positive terminal 2

SMPS ground

GND_SW

Inductor negative terminal 1

Inductor negative terminal 2

Buck boost output terminal 1

VOUT

R_EN

VDDS

G_EN

B_EN

PWM

GND

R_OUT

G_OUT

B_OUT

FAULT

SDA

Buck boost output terminal 2

Red output enable

Supply voltage

Green output enable

Blue output enable

Master fader input

Ground

R output

G output

B output

DI/O

Fault detection interrupts output. Active LOW open drain output.

I2C Data

SCL

I2C Clock

Enable and IO reference level

SMPS supply voltage

VDDP

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

(1) (2)(3)

Absolute Maximum Ratings

VDD and VOUT pins

−0.3V to 6.0V

Voltage on all other pins

−0.3V (V_IN+0.3V)

w/6.0V max

(4)

Continuous Power Dissipation

Internally Limited

+150°C

Junction Temperature (T_J-MAX

Storage Temperature Range

)

-65°C to +150°C

(5)

Maximum Lead Temperature (Soldering)

(6)

ESD Rating

Human Body Model

2.0kV

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test

conditions, see the Electrical Characteristics tables.

(2) All voltages are with respect to the potential at the GND pin.

(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(4) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J=+150°C (typ.) and

disengages at T_J=+140°C (typ.).

(5) For detailed soldering specifications and information, please refer to Application Note AN-1187: Leadless Leadframe Package

(LLP).(SNOA401)

(6) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7)

(1) (2)

Operating Ratings

Input Voltage Range

2.7V to 5.5V

−30°C to +125°C

−30°C to +85°C

Junction Temperature (T_J) Range

Ambient Temperature (T_A) Range

(3)

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test

conditions, see the Electrical Characteristics tables.

(2) All voltages are with respect to the potential at the GND pin.

(3) In applications where high-power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

+125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (θ_JA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (θ_JA× P_D-MAX).

Thermal Properties

Junction-to-Ambient Thermal Resistance (θ_JA), WQFN-24 Package

(1)

35 - 50°C/W

(1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

Electrical Characteristics^{(1) (2)}

Limits in standard type face are for T_A= 25°C. Limits in boldface type apply over the full operating ambient temperature

range (−30°C ≤ T_A≤ +85°C). Unless otherwise noted, specifications apply to Figure 1 with: V_IN= 3.6V, C_IN= 10 µF, C_OUT

4.7µF and L1 = 2.2 µH.

(3)

Parameter

Test Conditions

Minimum voltage for startup

Full output power

Min

2.7

3.1

Typ

Max

Units

V_IN

Supply voltage

5.5

I_IN

Shutdown supply current

Standby supply current

Active mode supply current

EN low

µA

(IVDDP + IVDDS)

EN High, x_EN low

0.4

1.6

I_IN

(IVDDS)

EN High, x_EN high, RGB outputs

open

(1) All voltages are with respect to the potential at the GND pin.

(2) Min and Max limits are specified by design, test, or statistical analysis. Typical (Typ) numbers represent the most likely norm.

(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

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Electrical Characteristics^{(1) (2)}(continued)

Limits in standard type face are for T_A= 25°C. Limits in boldface type apply over the full operating ambient temperature

range (−30°C ≤ T_A≤ +85°C). Unless otherwise noted, specifications apply to Figure 1 with: V_IN= 3.6V, C_IN= 10 µF, C_OUT

4.7µF and L1 = 2.2 µH.

(3)

Parameter

Test Conditions

Min

Typ

Max

Units

Drivers (R_OUT, G_OUT, B_OUT)

I_{OUT MIN}

I_{OUT MAX}

I_LIM

Minimum output current

107

705

118

720

Maximum output current

Current limit

690

R_OUT

Driver on resistance

I_OUT= 500 mA

0.2

±1

Ω

Driver System Characteristics

I_OUTCurrent accuracy

t_r

After settling, 500 mA (ISET = 276h)

−6

µs

Current rise time

Current fall time

Current step

t_f

µs

I_STEP

0.64

Buck or Boost Converter

Positive current limit range

Positive current limit accuracy Set to 1000 mA

Programmable

500

-20

550

-20

2000

+20

Negative current limit range

Programmable

Set to 550 mA

2200

+20

Negative current limit

accuracy

V_{OUT MAX}

f_SW

Maximum output voltage

Switching frequency

4.6

2.25

2.4

2.55

MHz

mΩ

r_{DSON P1S}

P1 on resistance in buck

mode (small)

100

r_{DSON P1L}

P1 on resistance in boost

mode (large)

mΩ

r_{DSON N1}

r_{DSON N3}

N1 on resistance

160

mΩ

N3 on resistance in buck

mode

VOUT = 0.8V

VOUT = 3.6V

r_{DSON P2}

r_{DSON N2}

P2 on resistance in boost

mode

mΩ

N2 on resistance

150

PWM Input (Global brightness control)

f_PWM

PWM frequency

7-bit resolution

8-bit resolution

9-bit resolution

For PWM zero

kHz

t_TO

Timeout

260

300

340

µs

t_ON

Minimum on time

Minimum off time

t_OFF

Logic Input EN

VIL

Logic input low level

Logic input high level

0.5

0.2* VEN

0.5

VIH

1.2

Logic Inputs SDA, SCL, R_EN, G_EN, B_EN, PWM

VIL

Logic input low level

Logic input high level

VEN = 1.65 to VDD

VIH

0.8* VEN

Logic Outputs SDA, FAULT

VOL Output low level

I_OUT= 3 mA

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BLOCK DIAGRAM

VDDP

VOUT

VDDS

SWITCHER

CONTROL

EEPROM

GND_SW

REGISTERS

I2C SLAVE

R_OUT

R SENS

SCL

SDA

DRIVER

CONTROL,

GND

G SENS

G_OUT

VOLTAGE

CONTROL,

CURRENT

LIMIT AND

R_EN

G_EN

B_EN

PWM

FAULT

DETECTION

GND

CONTROL

LOGIC

B SENS

B_OUT

ENABLES

FAULT

GND

VREF

IREF

OSC

TSD

UVLO

GND

GND_SW

Figure 3. LM3549 Block Diagram

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Modes of Operation

SHUTDOWN

EN = H

EN = L

STARTUP

STANDBY

TSD = H

UVLO = H

X_EN = H

TIME OUT

BOOST STARTUP

NORMAL MODE

1) TSD = L

Figure 4. Modes of Operation

SHUTDOWN: Shutdown mode is entered always if EN is low or internal Power On Reset (POR) is active. Power

on reset will activate during the chip startup or when the supply voltage VDD falls below 1.5V. This is the

low power consumption mode, when all circuit functions are disabled.

STARTUP: When EN input is pulled high, the internal startup sequence powers up all the needed internal blocks

(VREF, Oscillator, etc.). EEPROM values are also read to registers during Startup.

STANDBY: After Startup device enters Standby mode. In standby mode all support blocks are active but buck-

boost converter and the drivers are disabled. Control registers can be written in this mode and the control

bits are effective immediately. EEPROM writing is allowed only in standby mode.

BOOST STARTUP:Soft start for boost output is generated in the boost startup mode. The boost output is raised

in a low current mode. Soft start time can be set with registers. The boost startup is entered from Standby

if any of the X_EN inputs is pulled high.

NORMAL: During normal mode user controls the chip using the X_EN inputs. In normal mode buck-boost

converter and drivers are active. Device returns to standby mode if all X_EN inputs are low for time period

set by Time out register. If EN input is pulled low device goes to shutdown mode.

TSD: If the chip temperature rises too high, the thermal shutdown (TSD) disables the chip operation and

Standby mode is entered until no thermal shutdown event is present.

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Typical Performance Characteristics

Standby Supply Current

vs.

Active Mode Supply Current

Input Voltage (LED Open)

Input Voltage

Figure 5.

Figure 6.

LED Current

Current Setting

V_IN= 3.8V

Driver Current

vs.

Input Voltage

(I_OUT= 500 mA)

Figure 7.

Figure 8.

Driver Resistance

LED Driver Resistance

VIN

Output Current

(V_IN= 3.8V)

(I_OUT= 500 mA)

Figure 9.

Figure 10.

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Typical Performance Characteristics (continued)

LED Drive Efficiency

Output Current

(V_OUT= 3.4V)

Input Voltage

(I_OUT= 300 mA)

Figure 11.

Figure 12.

PWM Output Current Control

Master Fader Register Current Control

Figure 13.

Figure 14.

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OPERATION DESCRIPTION

LM3549 is a sequential LED driver for portable video projectors. It has three high current low side drivers and a

buck-boost DC-DC converter. Only single LED can be enabled at any given time. DC-DC converter quickly

adjusts the output voltage to a suitable level based on each LED’s forward voltage. This minimizes the power

dissipation at the drivers and maximizes the system efficiency.

Figure 15 shows a typical timing of a portable video projector light source. Each frame is divided into 10

individual color sequences. White balance is achieved by adjusting the driver currents.

Timing of LM3549 depends solely on the R_EN, G_EN and B_EN inputs. Each driver’s current is set with I²C

registers and current levels can be stored to internal EEPROM. After correct current values are stored to

EEPROM LM3549 can be used in application without I²C interface.

Full frame

Red

1/60Hz

16.66 ms

1.25 ms

1.822 ms

2.08 ms

Full frame x 7.5%

Full frame x 11%

Full frame x 12.5%

Green

Blue

60 Hz

RED

7.5%

GREEN

12.5%

BLUE

11%

RED

7.5%

GREEN

12.5%

RED

7.5%

GREEN

12.5%

BLUE

11%

RED

7.5%

GREEN

12.5%

R_EN

G_EN

B_EN

Figure 15. Timing Chart

CONTROL INTERFACE

Even though each driver has its own control input only one driver can be enabled at any given time. If second

control is pulled high while previous color is active second output won’t be enabled until the first input is pulled

low. This can be seen on Figure 16. G_EN is pulled high while R_EN is still high. G_OUT is not activated until

R_EN is pulled low. Next B_EN and R_EN are both pulled high while G_EN is high. When G_EN is pulled low

R_OUT is enabled because R_EN has higher priority (Priority order: RGB).

R_EN

G_EN

B_EN

R_OUT

G_OUT

B_OUT

Figure 16. Control Signals

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CONTROL REGISTERS

Figure 17 shows the structure of the control registers. Control registers consists of volatile dynamic registers and

non volatile EEPROM.

EEPROM

I²C bus

DYNAMIC REGISTERS

CONTROL

LOGIC

Figure 17. Register Structure

All I²C register read write commands are done to volatile dynamic registers. Dynamic registers are also used to

set the device parameters. All registers except FAULT and EEPROM CONTROL register can be stored to

EEPROM. EEPROM values are automatically read to dynamic registers during startup. This makes device use

very versatile. After calibration device can be used even without I²C control. If system has I²C bus, control

registers can be written to adjust parameters on the fly. If registers need to be set back to default values this can

be done by first writing 04h to register 40h (EE init bit to “1”) followed by 01h to register 40h (EE read bit to “1”).

EEPROM PROGRAMMING

EEPROM values can be rewritten if device needs recalibration. This can be done for example if white point

changes due to aging effect of the LEDs. To store current register values to EEPROM user needs to first write

04h to register 40h (EE init bit to “1”) followed by 02h to register 40h (EE prog bit to “1”). LM3549 Internal charge

pump generates the high voltage required for programming the EEPROM. To be able to generate this high

voltage Vin needs to be set to 5V during EEPROM programming. EEPROM programming should be completed

within approximately 200 ms. Once EEPROM programming is completed LM3549 sets EE_ready bit to 1. After

this Vin voltage can be set back to normal operating level. EEPROM programming should always be done in

standby mode.

CURRENT SETTING

There are three 10 bit current settings for each driver. 10 bits are divided into two eight bit registers. First register

holds the eight least significant bits (LSB) and the second register holds the two most significant bits (MSB).

These settings are grouped into three banks. IR0, IG0 and IB0 form a bank0; IR1, IG1 and IB1 form a bank1 and

IR2, IG2 and IB2 form a bank2. For example IR0_MSB holds the two MSB for red on bank0 and IR0_LSB the

eight LSB for red on bank0. Bank is selected with BANK_SEL register (00 = bank0, 01 = bank1 and 10 or 11 =

bank2).

Current setting is linear up to 550mA output current (see figure LED Current vs Current Setting in Typical

Performance Characteristics). 550mA current is achieved with current setting I_SET= 710. After this the current

step decreases slightly. For currents up to 550 mA current setting can be calculated using formula:

I_SET= (target current in mA - 100 mA)/(650mA/1024)

Fot currents between 550mA and 700mA current setting can be calculated using formula:

I_SET= (target current in mA - 550 mA)/0.479 mA + 710

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BRIGHTNESS CONTROL

Output current of all drivers can be adjusted using PWM input or FADER register. This can be used to easilly

adjust the total brightness of the LEDs. Brightness control function can be enabled from the CTRL register as

seen in table below. In case of PWM input brightness control (BRC) is the positive duty cycle of the input signal.

In case of FADER register brightness is MASTER FADER[7:0]/255.

MFE

PWM

Brightness Control

No brightness control

PWM input

FADER register

PWM input

The maximum currents of the drivers are set in the current setting registers. Brightness control keeps the ratio of

the driver currents constant and adjusts the output currents based on the highest current setting. Driver currents

can be adjusted between 100 mA to the maximum current set in the registers (see figures PWM Output Current

Control and Master Fader Register Current Control in Typical Performance Characteristics).

I_SET1=highest current setting

I_SET2=current setting 2

I_SET3=current setting 3

=(I_SET2/I_SET1), ratio of current 2 and the highest current

=(I_SET3/I_SET1), ratio of current 3 and the highest current

BRC =brightness control

I1 = I_SET1x BRC)

I2 = I1 x R1

I3 = I1x R2

PWM TIMING

Figure 18 shows example of PWM brightness control. PWM input can be change at any given time but control

takes effect when next enable is pulled high. To ensure that control takes effect for the next color time from PWM

change to next enable needs to be greater than timeout time (300 µs typical).

At the beginning of the example frame PWM input is changed from 100% to 80% while green driver is enabled.

Brightness level is not changed in the middle of the green frame but at the beginning of the next color which in

this example is blue. During next green PWM is set back to 100%. This is done at least 300 µs before next

enable is pulled high and control takes effect then. During next green PWM is changed to 0%. Time from PWM

change to next enable (blue) is less than 300 µs and control don’t take effect when blue starts but one color later,

what in this example is red.

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60 Hz

RED

GREEN

BLUE

RED

GREEN

BLUE

RED

GREEN

R_EN

G_EN

B_EN

PWM

100%

80%

100%

t < Timeout

t > Timeout

80%

BRIGHTNESS

100%

MINIMUM

Figure 18. PWM Timing

FAULT DETECTION

LM3549 can detect several different fault conditions. These are LED open, LED short, thermal shutdown (TSD),

under voltage lockout (UVLO) and buck-boost converter over current protection (OCP). If any of the fault

conditions occur corresponding fault bit is set in the fault register. If fault mask bit is not set also Fault output is

pulled low. Reading Fault register resets its value to zero and sets Fault output to high impedance state.

LED OPEN FAULT

Open fault is generated when at the end of color VOUT is at maximum and no current is flowing through driver

(VDx = 0V). Also OCP fault needs to be low. Open fault can be generated by broken LED or a soldering defect.

VOUT

VIN

Buck-boost

converter

VDx

Driver

current limit

Figure 19. LED Open Fault

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LED SHORT FAULT

Short fault is detected when VOUT < 1.0V at the end of a color. Short fault is generated when VOUT is shorted

to driver by soldering defect or faulty LED. Driver current limit limits the maximum current. Depending on output

current and positive limit settings, LED short can also generate OCP fault to fault register.

VOUT

VIN

Buck-boost

converter

VDx

Driver

current limit

Figure 20. LED Short Fault

TSD FAULT

Thermal shutdown (TSD) fault is generated if junction temperature rises above TSD level. TSD engages at T_J=

150°C (typ) and disengages at T_J= 140°C (typ). TSD sets device to standby mode. Occasionally a false TSD

fault is generated to Fault register when device goes from shutdown mode to standby mode. It is good practice to

reset the fault register by reading it every time after device is set from shutdown mode to standby mode.

UVLO FAULT

Under voltage lock out (UVLO) fault is generated if VIN drops below UVLO level (~2.5V). UVLO sets device to

standby mode. When VIN rises back above the 2.5V device exits UVLO. If control register values were changed

from EEPROM defaults they need to be rewritten to registers because UVLO condition can generate EEPROM

read sequence.

OVER CURRENT PROTECTION FAULT

Over current protection (OCP) fault is generated when positive current limit is active at the end of a color. It is

important to notice that OCP fault is not always set when positive current limit is activated. Positive current limit

can activate during normal operation when buck-boost is adjusting the output voltage to a higher level. OCP can

be caused by short from VOUT to GND, short from driver to GND or if too low positive current limit value is set

for desired output current.

I²C Compatible Interface

I²C ADDRESS

LM3549 I²C address is 36 hex (7 bits).

I²C SIGNALS

The SCL pin is used for the I²C clock and the SDA pin is used for bidirectional data transfer. Both these signals

need a pull-up resistor according to I²C specification. The values of the pull-up resistors are determined by the

capacitance of the bus (typ. ~1.8k). Signal timing specifications are shown in Table 1.

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I²C VALIDITY

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when CLK is LOW.

SCL

SDA

data

data valid

data

data valid

change

allowed

change

allowed

change

allowed

Figure 21. I²C Signals: Data Validity

I²C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as SDA

signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP bits.

The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I²C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

SDA

SCL

START condition

STOP condition

Figure 22. Start and Stop Conditions

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the ninth clock pulse, signifying an acknowledge. A receiver which has been

addressed must generate an acknowledge after each byte has been received.

After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). The LM3549 address is 36 hex. For the eighth bit, a “0” indicates a

WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The

third byte contains data to write to the selected register.

Slave Address

(7 bits)

Control Register Add.

(8 bits)

W A

A P

From Slave to Master

From Master to Slave

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

W - WRITE

Figure 23. I²C Write Cycle

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When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

Figure 24

Slave Address

( 7 bits)

Slave Address

( 7 bits)

Data- Data

( 8 bits)

Control Register Add.

( 8 bits)

W A

A RS

A P

A - ACKNOWLEDGE

S - START CONDITION

RS - REPEATED START CONDITION

P - STOP CONDITION

W - WRITE

From Slave to Master

From Master to Slave

R - READ

Figure 24. I²C Read Cycle

SDA

SCL

Figure 25. I²C Timing Diagram

Table 1. I²C Timing Parameters

Limit

Symbol

Parameter

Units

Min

0.6

Max

Hold Time (repeated) START Condition

Clock Low Time

µs

1.3

Clock High Time

600

Setup Time for a Repeated START Condition

Data Hold

600

300

900

Data Hold Time (input direction)

Data Setup Time

100

Rise Time of SDA and SCL

Fall Time of SDA and SCL

20 + 0.1Cb

15 + 0.1Cb

600

300

Set-up Time for STOP condition

Bus Free Time between a STOP and a START Condition

Capacitive Load for Each Bus Line

1.3

200

ADDR

00H

01H

02H

03H

04H

05H

06H

07H

08H

NAME

DEFAULT

00H

NOTE

BANK_SEL

IR0_LSB

IR0_MSB

IG0_LSB

IG0_MSB

IB0_LSB

IB0_MSB

IR1_LSB

IR1_MSB

Bank_sel[1:0]

Red 0 [9:8]

Green 0 [9:8]

Blue 0 [9:8]

Red 1 [9:8]

EEPROM

Red 0 [7:0]

81H

N/A

01H

Green 0 [7:0]

Blue 0 [7:0]

Red 1 [7:0]

81H

01H

81H

01H

E7H

00H

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ADDR

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

NAME

IG1_LSB

IG1_MSB

IB1_LSB

IB1_MSB

IR2_LSB

IR2_MSB

IG2_LSB

IG2_MSB

IB2_LSB

IB2_MSB

FADER

DEFAULT

E7H

00H

NOTE

Green 1 [7:0]

Blue 1 [7:0]

Red 2 [7:0]

Green 2 [7:0]

Blue 2 [7:0]

EEPROM

N/A

Green 1 [9:8]

Blue 1 [9:8]

Red 2 [9:8]

Green 2 [9:8]

Blue 2 [9:8]

E7H

00H

4DH

00H

4DH

00H

4DH

00H

MASTER FADER [7:0]

FFH

00H

CTRL

N/A

SOFT

TIME OUT[1:0]

MFE

PWM

START[1:0]

POS_LIMIT[1:0]

SHORT

15H

16H

17H

19H

1AH

40H

ILIMIT

F_MASK

FAULT

USR1

N/A

NEG_LIMIT[1:0]

11H

00H

EEPROM

Read Only

EEPROM

R/W

N/A

OPEN

UVLO

TSD

OCP

N/A

SHORT[1:0]

OPEN[1:0]

User Register1[7:0]

User Register2[7:0]

USR2

EEPROM

EE init EE prog EE read

CONTROL

ready

I²C Register Details

00h BANK_SEL[1:0]

Bank selection register. Selects one of the three current setting banks.

BIT

BANK SELECTION

Bank 0

Bank 1

Bank 2

01h IR0_LSB and 02h IR0_MSB

Red LED current setting for Bank 0. IR0_LSB holds the eight least significant bits and IR0_MSB the two most

significant bits.

03h IG0_LSB and 04h IG0_MSB

Green LED current setting for Bank 0. IG0_LSB holds the eight least significant bits and IG0_MSB the two most

significant bits.

05h IB0_LSB and 06h IB0_MSB

Blue LED current setting for Bank 0. IB0_LSB holds the eight least significant bits and IB0_MSB the two most

significant bits.

07h IR1_LSB and 08h IR1_MSB

Red LED current setting for Bank 1. IR1_LSB holds the eight least significant bits and IR1_MSB the two most

significant bits.

09h IG1_LSB and 0Ah IG1_MSB

Green LED current setting for Bank 1. IG1_LSB holds the eight least significant bits and IG1_MSB the two most

significant bits.

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0Bh IB1_LSB and 0Ch IB1_MSB

Blue LED current setting for Bank 1. IB1_LSB holds the eight least significant bits and IB1_MSB the two most

significant bits.

0Dh IR2_LSB and 0Eh IR2_MSB

Red LED current setting for Bank 2. IR2_LSB holds the eight least significant bits and IR2_MSB the two most

significant bits.

0Fh IG2_LSB and 10h IG2_MSB

Green LED current setting for Bank 2. IG2_LSB holds the eight least significant bits and IG2_MSB the two most

significant bits.

11h IB2_LSB and 12h IB2_MSB

Blue LED current setting for Bank 2. IB2_LSB holds the eight least significant bits and IB2_MSB the two most

significant bits.

13h FADER

Master fader control register. Can be used to control the total brightness of the LEDs if MFE is enabled.

14h CTRL

Control register. Controls many of the LM3549 features.

BIT[1:0] PWM and MFE

Control register bits [1:0] can be used to enable master control or PWM brightness control.

MFE

PWM

BRIGHTNESS CONTROL

No brightness control

PWM input

Master input

PWM input

BIT[3:2] TIME OUT[1:0]

Selects how long device stays in active mode after all x_EN controls have been set low

BIT

TIME OUT

125 ms

250 ms

500 ms

BIT[5:4] SOFT START[1:0]

Enables soft start feature and selects soft start time.

BIT

SOFT START TIME

disabled

0.5s

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15h ILIMIT

ILIMIT register sets the buck-boost converters current limit values.

BIT[1:0] NEG_LIMIT[1:0]

Selects buck-boost converters negative current limit.

BIT

NEGATIVE CURRENT LIMIT

550 mA

1100 mA

1650 mA

2200 mA

BIT[5:4] POS_LIMIT[1:0]

Selects buck-boost converters positive current limit.

BIT

POSITIVE CURRENT LIMIT

500 mA

1000 mA

1500 mA

2000 mA

16h F_MASK

Fault output mask register. Can be used to disable fault output from desired faults.

17h FAULT

Fault register. If fault occurs corresponding fault bits are set in fault register. Reading Fault register resets it.

Read only register.

BIT[0] OCP

Over current protection. Buck-boost converters current limit has been reached.

BIT[1] TSD

Thermal shutdown fault. Junction temperature has risen abowe TSD level.

BIT[2] UVLO

Under voltage lock-out. Input voltage has fallen below UVLO threshold level.

BIT[4:3] OPEN[1:0]

LED open fault.

BIT

FAULT

No fault

Red open

Green open

Blue open

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BIT[6:5] SHORT[1:0]

LED short fault.

BIT

FAULT

No fault

Red short

Green short

Blue short

19h and 1AH USR1 and USR2

User registers 1 and 2. Can be used to store any user data. No affect on the device.

40h EEPROM CONTROL

EEPROM Control register. This register is used to program EEPROM. EEPROM programming is described in the

EEPROM Programming chapter.

Table 2. Recommended External Components

Symbol

Symbol Explanation

Input Capacitor

Value

10 µF,6.3V/10V

4.7 µF, 6.3V/10V

2.2 µH, 1900 mA

Type

X7R

Example

CIN

COUT

Output Capacitor

Switcher Inductor

TDK VLF4014ST-2R2M1R9

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REVISION HISTORY

Changes from Original (May 2013) to Revision A

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 19

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LM3549SQ/NOPB

LM3549SQE/NOPB

LM3549SQX/NOPB

ACTIVE

WQFN

RTW

1000 RoHS & Green

250 RoHS & Green

4500 RoHS & Green

Level-1-260C-UNLIM

-30 to 85

L3549SQ

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM3549SQ/NOPB

LM3549SQE/NOPB

LM3549SQX/NOPB

WQFN

RTW

1000

250

178.0

330.0

12.4

4.3

1.3

8.0

12.0

4500

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Oct-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM3549SQ/NOPB

LM3549SQE/NOPB

LM3549SQX/NOPB

WQFN

RTW

1000

250

208.0

367.0

191.0

367.0

35.0

4500

Pack Materials-Page 2

PACKAGE OUTLINE

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

PIN 1 INDEX AREA

4.1

3.9

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 2.5

(0.1) TYP

EXPOSED

THERMAL PAD

20X 0.5

2.5

2.6 0.1

0.3

24X

0.2

PIN 1 ID

(OPTIONAL)

0.1

C A B

0.05

0.5

0.3

24X

4222815/A 03/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.6)

SYMM

24X (0.6)

24X (0.25)

(1.05)

SYMM

(3.8)

20X (0.5)

(R0.05)

TYP

(

0.2) TYP

VIA

(1.05)

(3.8)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222815/A 03/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

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EXAMPLE STENCIL DESIGN

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.15)

(0.675) TYP

(R0.05) TYP

24X (0.6)

24X (0.25)

(0.675)

TYP

SYMM

20X (0.5)

(3.8)

METAL

TYP

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25:

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4222815/A 03/2016

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LM3549SQE/NOPB [TI]

相关型号：

LM3549SQX

LM3549SQX/NOPB

LM3550

LM3550SP

LM3550SP/NOPB

LM3550SPX

LM3550SPX/NOPB

LM3551

LM3551

LM3551SD

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LM3551SD/NOPB