LM359M/NOPB [TI]
Dual, High Speed, Programmable, Current Mode (Norton) Amplifiers;
| 型号： | LM359M/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual, High Speed, Programmable, Current Mode (Norton) Amplifiers |
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LM359
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LM359 Dual, High Speed, Programmable, Current Mode (Norton) Amplifiers
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1
FEATURES
APPLICATIONS
2
•
User Programmable Gain Bandwidth Product,
Slew Rate, Input Bias Current, Output Stage
Biasing Current and Total Device Power
Dissipation
•
•
•
•
General Purpose Video Amplifiers
High Frequency, High Q Active Filters
Photo-Diode Amplifiers
Wide Frequency Range Waveform Generation
Circuits
•
•
•
High Gain Bandwidth Product (ISET = 0.5 mA)
–
–
400 MHz for AV = 10 to 100
30 MHz for AV = 1
•
All LM3900 AC Applications Work to Much
Higher Frequencies
High Slew Rate (ISET = 0.5 mA)
DESCRIPTION
–
–
60 V/μs for AV = 10 to 100
30 V/μs for AV = 1
The LM359 consists of two current differencing
(Norton) input amplifiers. Design emphasis has been
placed on obtaining high frequency performance and
providing user programmable amplifier operating
characteristics. Each amplifier is broadbanded to
provide a high gain bandwidth product, fast slew rate
and stable operation for an inverting closed loop gain
of 10 or greater. Pins for additional external
frequency compensation are provided. The amplifiers
are designed to operate from a single supply and can
accommodate input common-mode voltages greater
than the supply.
Current Differencing Inputs Allow High
Common-Mode Input Voltages
•
•
Operates from a Single 5V to 22V Supply
Large Inverting Amplifier Output Swing, 2 mV
to VCC − 2V
•
Low Spot Noise, 6 nV /√Hz, for f > 1 kHz
Typical Application
Connection Diagram
Figure 1. PDIP/SOIC Package
Top View
See Package Number D0014A or NFF0014A
•
•
•
AV = 20 dB
−3 dB bandwidth = 2.5 Hz to 25 MHz
Differential phase error < 1° at 3.58
MHz
•
Differential gain error < 0.5% at 3.58
MHz
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM359
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage
22 VDC or ±11 VDC
1W
D Package
Power Dissipation(3)
NFF Package
D Package
750 mW
+150°C
Maximum TJ
NFF Package
+125°C
147°C/W still air
D Package θjA
110°C/W with 400
linear feet/min air flow
Thermal Resistance
100°C/W still air
NFF Package θjA
75°C/W with 400
linear feet/min air flow
Input Currents, IIN(+) or IIN(−)
Set Currents, ISET(IN) or ISET(OUT)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
10 mADC
2 mADC
0°C to +70°C
−65°C to +150°C
260°C
(Soldering, 10 sec.)
Soldering (10 sec.)
Vapor Phase (60 sec.)
Infrared (15 sec.)
PDIP Package
SOIC Package
260°C
Soldering Information
215°C
220°C
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) See Figure 22.
Electrical Characteristics
ISET(IN) = ISET(OUT) = 0.5 mA, Vsupply = 12V, TA = 25°C unless otherwise noted
Parameter
Open Loop Voltage
Gain
Conditions
Vsupply = 12V, RL = 1k, f = 100 Hz
Min
Typ
72
Max
Units
dB
62
TA = 125°C
68
dB
Bandwidth Unity Gain
RIN = 1 kΩ, Ccomp = 10 pF
15
30
MHz
Gain Bandwidth Product,
Gain of 10 to 100
RIN = 50Ω to 200Ω
200
400
MHz
V/μs
dB
Unity Gain
RIN = 1 kΩ, Ccomp = 10 pF
RIN < 200Ω
30
60
Slew Rate
Gain of 10 to 100
Amplifier to Amplifier
Coupling
f = 100 Hz to 100 kHz, RL = 1k
−80
at 2 mA IIN(+), ISET = 5 μA, TA = 25°C
at 0.2 mA IIN(+), ISET = 5 μA Over Temp.
at 20 μA IIN(+), ISET = 5 μA Over Temp.
0.9
0.9
0.9
1.0
1.0
1.0
3
1.1
1.1
1.1
5
μA/μA
μA/μA
μA/μA
%
Mirror Gain(1)
ΔMirror Gain(1)
at 20 μA to 0.2 mA IIN(+) Over Temp, ISET = 5 μA
Inverting Input, TA = 25°C
Over Temp.
8
15
30
μA
Input Bias Current
μA
Input Resistance (βre)
Inverting Input
2.5
3.5
kΩ
Output Resistance
IOUT = 15 mA rms, f = 1 MHz
Ω
(1) Mirror gain is the current gain of the current mirror which is used as the non-inverting input.
AI for two different mirror currents at any given temperature.
ΔMirror Gain is the % change in
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Electrical Characteristics (continued)
ISET(IN) = ISET(OUT) = 0.5 mA, Vsupply = 12V, TA = 25°C unless otherwise noted
Parameter
Conditions
Min
Typ
10.3
2
Max
Units
V
VOUT High
VOUT Low
IIN(−) and IIN(+) Grounded
IIN(−) = 100 μA, IIN(+) = 0
9.5
Output Voltage Swing (RL
= 600Ω)
50
mV
IIN(−) and IIN(+)
Grounded, RL = 100Ω
16
40
Source
V
comp−0.5V = VOUT = 1V,
4.7
Output Currents
Supply Current
Sink (Linear Region)
Sink (Overdriven)
mA
IIN(+) = 0
IIN(−) = 100 μA, IIN(+) = 0,
VOUT Force = 1V
1.5
40
3
Non-Inverting Input Grounded, RL = ∞
18.5
50
22
mA
dB
Power Supply Rejection(2) f = 120 Hz, IIN(+) Grounded
(2) See Figure 15 and Figure 16.
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Typical Performance Characteristics
Open Loop Gain
Open Loop Gain
Note: Shaded area refers to LM359
Figure 2.
Figure 3.
Open Loop Gain
Gain Bandwidth Product
Figure 4.
Figure 5.
Gain and Phase
Feedback Gain = − 100
Slew Rate
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
Inverting Input Bias Current
Inverting Input Bias Current
Note: Shaded area refers to LM359
Figure 8.
Figure 9.
Mirror Gain
Mirror Gain
Note: Shaded area refers to LM359
Figure 10.
Figure 11.
Mirror Gain
Mirror Current
Note: Shaded area refers to LM359
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
Supply Current
Supply Rejection
Figure 14.
Figure 15.
Supply Rejection
Output Sink Current
Figure 16.
Figure 17.
Output Swing
Output Impedance
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
Amplifier to Amplifier
Coupling (Input Referred)
Noise Voltage
Figure 20.
Figure 21.
Maximum Power Dissipation
Note: Shaded area refers to LM359J/LM359N
Figure 22.
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APPLICATION HINTS
The LM359 consists of two wide bandwidth, decompensated current differencing (Norton) amplifiers. Although
similar in operation to the original LM3900, design emphasis for these amplifiers has been placed on obtaining
much higher frequency performance as illustrated in Figure 23.
This significant improvement in frequency response is the result of using a common-emitter/common-base
(cascode) gain stage which is typical in many discrete and integrated video and RF circuit designs. Another
versatile aspect of these amplifiers is the ability to externally program many internal amplifier parameters to suit
the requirements of a wide variety of applications in which this type of amplifier can be used.
Figure 23.
DC BIASING
The LM359 is intended for single supply voltage operation which requires DC biasing of the output. The current
mirror circuitry which provides the non-inverting input for the amplifier also facilitates DC biasing the output. The
basic operation of this current mirror is that the current (both DC and AC) flowing into the non-inverting input will
force an equal amount of current to flow into the inverting input . The mirror gain (AI) specification is the measure
of how closely these two currents match. For more details see TI Application Note AN-72 (Literature Number
SNOA666).
DC biasing of the output is accomplished by establishing a reference DC current into the (+) input, IIN(+), and
requiring the output to provide the (−) input current. This forces the output DC level to be whatever value
necessary (within the output voltage swing of the amplifier) to provide this DC reference current, Figure 24.
Figure 24.
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The DC input voltage at each input is a transistor VBE(≃ 0.6 VDC) and must be considered for DC biasing. For
most applications, the supply voltage, V+, is suitable and convenient for establishing IIN(+). The inverting input
bias current, Ib(−), is a direct function of the programmable input stage current (see OPERATING CURRENT
PROGRAMMABILITY (ISET)) and to obtain predictable output DC biasing set IIN(+) ≥ 10Ib(−).
The following figures illustrate typical biasing schemes for AC amplifiers using the LM359:
Figure 25. Biasing an Inverting AC Amplifier
Figure 26. Biasing a Non-Inverting AC Amplifier
Figure 27. nVBE Biasing
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The nVBE biasing configuration is most useful for low noise applications where a reduced input impedance can
be accommodated (see Typical Applications section).
OPERATING CURRENT PROGRAMMABILITY (ISET
)
The input bias current, slew rate, gain bandwidth product, output drive capability and total device power
consumption of both amplifiers can be simultaneously controlled and optimized via the two programming pins
ISET(OUT) and ISET(IN)
.
ISET(OUT)
The output set current (ISET(OUT)) is equal to the amount of current sourced from pin 1 and establishes the class A
biasing current for the Darlington emitter follower output stage. Using a single resistor from pin 1 to ground, as
shown in Figure 28, this current is equal to:
Figure 28. Establishing the Output Set Current
The output set current can be adjusted to optimize the amount of current the output of the amplifier can sink to
drive load capacitance and for loads connected to V+. The maximum output sinking current is approximately 10
times ISET(OUT). This set current is best used to reduce the total device supply current if the amplifiers are not
required to drive small load impedances.
ISET(IN)
The input set current ISET(IN) is equal to the current flowing into pin 8. A resistor from pin 8 to V+ sets this current
to be:
Figure 29. Establishing the Input Set Current
ISET(IN) is most significant in controlling the AC characteristics of the LM359 as it directly sets the total input stage
current of the amplifiers which determines the maximum slew rate, the frequency of the open loop dominant pole,
the input resistance of the (−) input and the biasing current Ib(−). All of these parameters are significant in wide
band amplifier design. The input stage current is approximately 3 times ISET(IN) and by using this relationship the
following first order approximations for these AC parameters are:
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(1)
where Ccomp is the total capacitance from the compensation pin (pin 3 or pin 13) to ground, AVOL is the low
frequency open loop voltage gain in V/V and an ambient temperature of 25°C is assumed (KT/q = 26 mV and
βtyp = 150). ISET(IN) also controls the DC input bias current by the expression:
(2)
which is important for DC biasing considerations.
The total device supply current (for both amplifiers) is also a direct function of the set currents and can be
approximated by:
Isupply ≃ 27 × ISET(OUT) + 11 × ISET(IN)
(3)
with each set current programmed by individual resistors.
PROGRAMMING WITH A SINGLE RESISTOR
Operating current programming may also be accomplished using only one resistor by letting ISET(IN) equal
ISET(OUT). The programming current is now referred to as ISET and it is created by connecting a resistor from pin 1
to pin 8 (Figure 30).
(4)
ISET(IN) = ISET(OUT) = ISET
Figure 30. Single Resistor Programming of ISET
This configuration does not affect any of the internal set current dependent parameters differently than previously
discussed except the total supply current which is now equal to:
Isupply ≃ 37 × ISET
(5)
Care must be taken when using resistors to program the set current to prevent significantly increasing the supply
voltage above the value used to determine the set current. This would cause an increase in total supply current
due to the resulting increase in set current and the maximum device power dissipation could be exceeded. The
set resistor value(s) should be adjusted for the new supply voltage.
One method to avoid this is to use an adjustable current source which has voltage compliance to generate the
set current as shown in Figure 31.
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Figure 31. Current Source Programming of ISET
This circuit allows ISET to remain constant over the entire supply voltage range of the LM359 which also improves
power supply ripple rejection as illustrated in the Typical Performance Characteristics. It should be noted,
however, that the current through the LM334 as shown will change linearly with temperature but this can be
compensated for (see LM334 data sheet).
Pin 1 must never be shorted to ground or pin 8 never shorted to V+ without limiting the current to 2 mA or less to
prevent catastrophic device failure.
CONSIDERATIONS FOR HIGH FREQUENCY OPERATION
The LM359 is intended for use in relatively high frequency applications and many factors external to the amplifier
itself must be considered. Minimization of stray capacitances and their effect on circuit operation are the primary
requirements. The following list contains some general guidelines to help accomplish this end:
1. Keep the leads of all external components as short as possible.
2. Place components conducting signal current from the output of an amplifier away from that amplifier's non-
inverting input.
3. Use reasonably low value resistances for gain setting and biasing.
4. Use of a ground plane is helpful in providing a shielding effect between the inputs and from input to output.
Avoid using vector boards.
5. Use a single-point ground and single-point supply distribution to minimize crosstalk. Always connect the two
grounds (one from each amplifier) together.
6. Avoid use of long wires (> 2″) but if necessary, use shielded wire.
7. Bypass the supply close to the device with a low inductance, low value capacitor (typically a 0.01 μF
ceramic) to create a good high frequency ground. If long supply leads are unavoidable, a small resistor
(∼10Ω) in series with the bypass capacitor may be needed and using shielded wire for the supply leads is
also recommended.
COMPENSATION
The LM359 is internally compensated for stability with closed loop inverting gains of 10 or more. For an inverting
gain of less than 10 and all non-inverting amplifiers (the amplifier always has 100% negative current feedback
regardless of the gain in the non-inverting configuration) some external frequency compensation is required
because the stray capacitance to ground from the (−) input and the feedback resistor add additional lagging
phase within the feedback loop. The value of the input capacitance will typically be in the range of 6 pF to 10 pF
for a reasonably constructed circuit board. When using a feedback resistance of 30 kΩ or less, the best method
of compensation, without sacrificing slew rate, is to add a lead capacitor in parallel with the feedback resistor with
a value on the order of 1 pF to 5 pF as shown in Figure 32.
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Cf = 1 pF to 5 pF for stability
Figure 32. Best Method of Compensation
Another method of compensation is to increase the effective value of the internal compensation capacitor by
adding capacitance from the COMP pin of an amplifier to ground. An external 20 pF capacitor will generally
compensate for all gain settings but will also reduce the gain bandwidth product and the slew rate. These same
results can also be obtained by reducing ISET(IN) if the full capabilities of the amplifier are not required. This
method is termed over-compensation.
Another area of concern from a stability standpoint is that of capacitive loading. The amplifier will generally drive
capacitive loads up to 100 pF without oscillation problems. Any larger C loads can be isolated from the output as
shown in Figure 33. Over-compensation of the amplifier can also be used if the corresponding reduction of the
GBW product can be afforded.
Figure 33. Isolating Large Capacitive Loads
In most applications using the LM359, the input signal will be AC coupled so as not to affect the DC biasing of
the amplifier. This gives rise to another subtlety of high frequency circuits which is the effective series inductance
(ESL) of the coupling capacitor which creates an increase in the impedance of the capacitor at high frequencies
and can cause an unexpected gain reduction. Low ESL capacitors like solid tantalum for large values of C and
ceramic for smaller values are recommended. A parallel combination of the two types is even better for gain
accuracy over a wide frequency range.
AMPLIFIER DESIGN EXAMPLES
The ability of the LM359 to provide gain at frequencies higher than most monolithic amplifiers can provide makes
it most useful as a basic broadband amplification stage. The design of standard inverting and non-inverting
amplifiers, though different than standard op amp design due to the current differencing inputs, also entail subtle
design differences between the two types of amplifiers. These differences will be best illustrated by design
examples. For these examples a practical video amplifier with a passband of 8 Hz to 10 MHz and a gain of 20 dB
will be used. It will be assumed that the input will come from a 75Ω source and proper signal termination will be
considered. The supply voltage is 12 VDC and single resistor programming of the operating current, ISET, will be
used for simplicity.
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AN INVERTING VIDEO AMPLIFIER
1. Basic circuit configuration:
2. Determine the required ISET from the characteristic curves for gain bandwidth product.GBWMIN= 10 × 10 MHz
= 100 MHzFor a flat response to 10 MHz a closed loop response to two octaves above 10 MHz (40 MHz) will
be sufficient.
Actual GBW = 10 × 40 MHz = 400 MHz ISET required = 0.5 mA
3. Determine maximum value for Rf to provide stable DC biasing
Optimum
output DC level for maximum symmetrical swing without clipping is:
Rf(MAX)
This value should not be exceeded for predictable
can now be found:
DC biasing.
4. Select Rs to be large enough so as not to appreciably load the input termination resistance:Rs ≥ 750Ω; Let Rs
= 750Ω
5. Select Rf for appropriate gain:
predictability is insured.
7.5 kΩ is less than the calculated Rf(MAX) so DC
6. Since Rf = 7.5k, for the output to be biased to 5.1 VDC
the reference current IIN(+) must be:
Now Rb can be found by:
,
7. Select Ci to provide the proper gain for the 8 Hz minimum input frequency:
A larger value of Ci will allow a flat frequency response down to 8 Hz and a
0.01 μF ceramic capacitor in parallel with Ci will maintain high frequency gain accuracy.
8. Test for peaking of the frequency response and add a feedback “lead” capacitor to compensate if necessary.
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Figure 34. Final Circuit Using Standard 5%
Tolerance Resistor Values
Vo(DC) = 5.1V
Differential phase error < 1° for 3.58 MHz fIN
Differential gain error < 0.5% for 3.58 MHz fIN
f−3 dB low = 2.5 Hz
Figure 35. Circuit Performance
A NON-INVERTING VIDEO AMPLIFIER
For this case several design considerations must be dealt with.
•
•
•
•
The output voltage (AC and DC) is strictly a function of the size of the feedback resistor and the sum of AC
and DC “mirror current” flowing into the (+) input.
The amplifier always has 100% current feedback so external compensation is required. Add a small (1 pF–5
pF) feedback capacitance to leave the amplifier's open loop response and slew rate unaffected.
To prevent saturating the mirror stage the total AC and DC current flowing into the amplifier's (+) input should
be less than 2 mA.
The output's maximum negative swing is one diode above ground due to the VBE diode clamp at the (−) input.
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DESIGN EXAMPLE
eIN = 50 mV (MAX), fIN = 10 MHz (MAX), desired circuit BW = 20 MHz, AV = 20 dB, driving source impedance =
75Ω, V+ = 12V.
1. Basic circuit configuration:
2. Select ISET to provide adequate amplifier bandwidth so that the closed loop bandwidth will be determined by
Rf and Cf. To do this, the set current should program an amplifier open loop gain of at least 20 dB at the
desired closed loop bandwidth of the circuit. For this example, an ISET of 0.5 mA will provide 26 dB of open
loop gain at 20 MHz which will be sufficient. Using single resistor programming for
ISET
:
3. Since the closed loop bandwidth will be determined by
to obtain a 20 MHz bandwidth,
both Rf and Cf should be kept small. It can be assumed that Cf can be in the range of 1 pF to 5 pF for
carefully constructed circuit boards to insure stability and allow a flat frequency response. This will limit the
value of Rf to be within the range of:
Also, for a closed loop gain of +10, Rf
must be 10 times Rs + re where re is the mirror diode resistance.
4. So as not to appreciably load the 75Ω input termination resistance the value of (Rs + re) is set to 750Ω.
5. For Av = 10; Rf is set to 7.5 kΩ.
6. The optimum output DC level for symmetrical AC swing is:
7. The DC feedback current must be:
DC biasing predictability will be insured
because 640 μA is greater than the minimum of ISET/5 or 100 μA.
8. For gain accuracy the total AC and DC mirror current should be less than 2 mA. For this example the
maximum AC mirror current will be:
therefore the total mirror current range will be 574
μA to 706 μA which will insure gain accuracy.
9. Rb can now be found:
10. Since Rs + re will be 750Ω and re is fixed by the DC mirror current to be:
Rs must
be 750Ω–40Ω or 710Ω which can be a 680Ω resistor in series with a 30Ω resistor which are standard 5%
tolerance resistor values.
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11. As a final design step, Ci must be selected to pass the lower passband frequency corner of 8 Hz for this
example. A larger value may be used and a 0.01 μF ceramic capacitor
in parallel with Ci will maintain high frequency gain accuracy.
Figure 36. Final Circuit Using Standard 5% Tolerance Resistor Values
Vo(DC) = 5.4V
Differential phase error < 0.5°
Differential gain error < 2%
f−3 dB low = 2.5 Hz
Figure 37. Circuit Performance
GENERAL PRECAUTIONS
The LM359 is designed primarily for single supply operation but split supplies may be used if the negative supply
voltage is well regulated as the amplifiers have no negative supply rejection.
The total device power dissipation must always be kept in mind when selecting an operating supply voltage, the
programming current, ISET, and the load resistance, particularly when DC coupling the output to a succeeding
stage. To prevent damaging the current mirror input diode, the mirror current should always be limited to 10 mA,
or less, which is important if the input is susceptible to high voltage transients. The voltage at any of the inputs
must not be forced more negative than −0.7V without limiting the current to 10 mA.
The supply voltage must never be reversed to the device; however, plugging the device into a socket backwards
would then connect the positive supply voltage to the pin that has no internal connection (pin 5) which may
prevent inadvertent device failure.
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Typical Applications
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DC Coupled Inputs
Figure 38. Inverting
Figure 39. Non-Inverting
•
•
Eliminates the need for an input coupling capacitor
Input DC level must be stable and can exceed the supply voltage of the LM359 provided that maximum input
currents are not exceeded.
Figure 40. Noise Reduction using nVBE Biasing
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•
R1 and C2 provide additional filtering of the negative biasing supply
Figure 41. nVBE Biasing with a Negative Supply
Figure 42. Typical Input Referred Noise Performance
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•
•
•
•
•
•
FET input voltage mode op amp
For AV = +1; BW = 40 MHz, Sr = 60 V/μs; CC = 51 pF
For AV = +11; BW = 24 MHz, Sr = 130 V/μs; CC = 5 pF
For AV = +100; BW = 4.5 MHz, Sr = 150 V/μs; CC = 2 pF
VOS is typically <25 mV; 100Ω potentiometer allows a VOS adjust range of ≈ ±200 mV
Inputs must be DC biased for single supply operation
Figure 43. Adding a JFET Input Stage
D1 ∼ RCA N-Type Silicon P-I-N Photodiode
•
•
Frequency response of greater than 10 MHz
If slow rise and fall times can be tolerated the gate on the output can be removed. In this case the rise and the
fall time of the LM359 is 40 ns.
•
TPDL = 45 ns, TPDH = 50 ns − T2L output
Figure 44. Photo Diode Amplifier
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SNOSBT4C –MAY 1999–REVISED MARCH 2013
•
•
•
•
1 MHz−3 dB bandwidth with gain of 10 and 0 dbm into 600Ω
0.3% distortion at full bandwidth; reduced to 0.05% with bandwidth of 10 kHz
Will drive CL = 1500 pF with no additional compensation, ±0.01 μF with Ccomp = 180 pF
70 dB signal to noise ratio at 0 dbm into 600Ω, 10 kHz bandwidth
Figure 45. Balanced Line Driver
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SNOSBT4C –MAY 1999–REVISED MARCH 2013
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•
CMRR is adjusted for max at expected CM input signal
•
•
•
Wide bandwidth
70 dB CMRR typ
Wide CM input voltage range
Figure 46. Difference Amplifier
•
•
5 MHz operation
T2L output
Figure 47. Voltage Controlled Oscillator
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SNOSBT4C –MAY 1999–REVISED MARCH 2013
•
•
Up to 5 MHz operation
T2L compatible input
All diodes = 1N914
Figure 48. Phase Locked Loop
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f = 1 MHz
Output is TTL compatible
Frequency is adjusted by R1 & C (R1 ≪ R2)
Figure 49. Squarewave Generator
Output is TTL compatible
Duty cycle is adjusted by R1
Frequency is adjusted by C
f = 1 MHz
Duty cycle = 20%
Figure 50. Pulse Generator
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SNOSBT4C –MAY 1999–REVISED MARCH 2013
Vo = 500 mVp-p
f = 9.1 MHz
THD < 2.5%
Figure 51. Crystal Controlled Sinewave Oscillator
•
•
•
The high speed of the LM359 allows the center frequency Qo product of the filter to be: fo× Qo ≤ 5 MHz
The above filter(s) maintain performance over wide temperature range
One half of LM359 acts as a true non-inverting integrator so only 2 amplifiers (instead of 3 or 4) are needed for
the biquad filter structure
Figure 52. High Performance 2 Amplifier Biquad Filter(s)
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SNOSBT4C –MAY 1999–REVISED MARCH 2013
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Table 1. DC Biasing Equations for V01(DC) ≃ V02(DC) ≃V+/2
Type I
Type II
Type III
Table 2. Analysis and Design Equations
Type
VO1
BP
HP
VO2
LP
Ci
O
Ri2
Ri2
∞
Ri1
∞
fo
Qo
fZ(notch)
Ho(LP)
R/Ri2
—
Ho(BP)
RQ/Ri2
Ho(HP)
—
Ho(BR)
I
1/2πRC
1/2πRC
RQ/R
RQ/R
—
—
—
—
II
BP
Ci
∞
RQCi/RC
Ci/C
Notch/
BR
III
—
Ci
∞
Ri1
1/2πRC
RQ/R
1/2π√RRiCCi
—
—
—
V2 output is TTL compatible
R2 adjusts for symmetry of the triangle waveform
Frequency is adjusted with R5 and C
Figure 53. Triangle Waveform Generator
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SNOSBT4C –MAY 1999–REVISED MARCH 2013
Schematic Diagram
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 27
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
LM359M
NRND
ACTIVE
SOIC
SOIC
D
D
14
14
55
TBD
Call TI
Call TI
0 to 70
0 to 70
LM359M
LM359M/NOPB
55
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
LM359M
LM359MX
NRND
SOIC
SOIC
D
D
14
14
2500
2500
TBD
Call TI
Call TI
0 to 70
0 to 70
LM359M
LM359M
LM359MX/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM359MX
SOIC
SOIC
D
D
14
14
2500
2500
330.0
330.0
16.4
16.4
6.5
6.5
9.35
9.35
2.3
2.3
8.0
8.0
16.0
16.0
Q1
Q1
LM359MX/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM359MX
SOIC
SOIC
D
D
14
14
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
LM359MX/NOPB
Pack Materials-Page 2
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