LM3676SD-ADJ/NOPB [TI]
具有模式控制的 2MHz、600mA 降压直流/直流控制器 | NGQ | 8 | -30 to 85;
| 型号： | LM3676SD-ADJ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有模式控制的 2MHz、600mA 降压直流/直流控制器 | NGQ | 8 | -30 to 85 控制器 开关 |
| 文件： | 总27页 (文件大小：4250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM3676
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SNVS426C –NOVEMBER 2006–REVISED MAY 2013
2-MHz 600-mA Step-Down DC-DC Converter With Mode Control
Check for Samples: LM3676
1
FEATURES
DESCRIPTION
The LM3676 step-down DC-DC converter is
optimized for powering low voltage circuits from a
single Li-Ion cell battery and input voltage rails from
2.9V to 5.5V. It provides up to 600mA load current,
over the entire input voltage range. There are several
different fixed voltage output options available as well
as an adjustable output voltage version.
2
•
•
•
•
16µA Typical Quiescent Current
600mA Maximum Load Capability
2MHz Typical PWM Fixed Switching Frequency
Automatic PFM/PWM Mode Switching or
Forced PWM Mode
•
Available in Fixed Output Voltages and
Adjustable Version
The LM3676 has a mode-control pin that allows the
user to select continuous Pulse Width Modulation
(PWM) mode over the complete load range or an
intelligent PFM-PWM mode that changes modes
depending on the load. PWM mode offers superior
efficiency under high load conditions (>100mA) and
the lowest output noise performance. In Auto mode,
PFM-PWM, hysteretic PFM extends the battery life
through reduction of the quiescent current to 16µA
(typ.) during light loads and system standby.
•
•
8-Lead Non-Pullback WSON Package
Internal Synchronous Rectification for High
Efficiency
•
•
•
•
Internal Soft Start
0.01µA Typical Shutdown Current
Operates From a Single Li-Ion Cell Battery
Only Three Tiny Surface-Mount External
Components Required (One Inductor, Two
Ceramic Capacitors)
The LM3676 is available in a 8-lead non-pullback
WSON package in leaded (PB) and lead-free (NO
PB) versions. A high switching frequency of 2 MHz
(typ) allows use of tiny surface-mount components,
an inductor and two ceramic capacitors.
•
Current Overload and Thermal Shutdown
Protection
APPLICATIONS
•
•
•
•
•
•
•
Mobile Phones
PDAs
MP3 Players
WLAN
Portable Instruments
Digital Still Cameras
Portable Hard Disk Drives
TYPICAL APPLICATION CIRCUITS
V
IN
L1: 2.2 mH
2.9V to 5.5V
V
IN
V
OUT
SW
2
8
C
OUT
C
IN
LM3676
10 mF
PGND
NC
4.7 mF
FB
4
7
3
1
6
5
SGND
MODE
EN
Figure 1. Typical Application Circuit
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LM3676
SNVS426C –NOVEMBER 2006–REVISED MAY 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
V
IN
L1: 2.2 mH
V
OUT
2.9V to 5.5V
V
IN
SW
FB
8
2
C
OUT
C
LM3676-
ADJ
IN
R1
R2
C1
C2
10 mF
4
4.7 mF
PGND
1
SGND
7
NC
EN
6
5
MODE
3
Figure 2. Typical Application Circuit for ADJ Version
PIN DIAGRAM
VIN
1
2
8
7
6
5
PGND
SW
SGND
NC
MODE
FB
3
4
EN
Figure 3. Top View
WSON-8 Package
Package Number NGQ0008A
PIN DESCRIPTIONS (8-Lead WSON)
Pin No.
Name
PGND
SW
Description
1
2
3
Power Ground Pin.
Switching node connection to the internal PFET switch and NFET synchronous rectifier.
MODE
Mode Control Pin: > 1.0V selects continuous PWM mode ; <0.4V selects Auto (PFM-PWM) mode. Do not
leave this pin floating.
4
5
FB
EN
Feedback analog input. Connect directly to the output filter capacitor for fixed voltage versions. For
adjustable version external resistor dividers are required (see Figure 2). The internal resistor dividers are
disabled for the adjustable version.
Enable pin. The device is in shutdown mode when voltage to this pin is <0.4V and enabled when >1.0V.
Do not leave this pin floating.
6
7
8
NC
SGND
VIN
Not Connected. Leave Pin Floating. Do Not Connect to other pins
Signal Ground Pin.
Power Supply input. Connect to the input filter capacitor (see Figure 1).
2
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SNVS426C –NOVEMBER 2006–REVISED MAY 2013
ORDERING INFORMATION(1)(2)
LM3676 (8-Lead WSON)
Ordering Information
Voltage Option (V)
LM3676SD-1.5
LM3676SDX-1.5
1.5
LM3676SD-1.5/NOPB
LM3676SDX-1.5/NOPB
LM3676SD-1.8
LM3676SDX-1.8
1.8
3.3
LM3676SD-1.8/NOPB
LM3676SDX-1.8/NOPB
LM3676SD-3.3
LM3676SDX-3.3
LM3676SD-3.3/NOPB
LM3676SDX-3.3/NOPB
LM3676SD-ADJ
LM3676SDX-ADJ
Adjustable
LM3676SD-ADJ/NOPB
LM3676SDX-ADJ/NOPB
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Absolute Maximum Ratings(1)(2)
VIN Pin: Voltage to GND
FB, SW, EN, Mode Pin:
Continuous Power Dissipation
−0.2V to 6.0V
(GND−0.2V) to (VIN + 0.2V)
Internally Limited
+125°C
(3)
Junction Temperature (TJ-MAX
Storage Temperature Range
)
−65°C to +150°C
260°C
Maximum Lead Temperature (Soldering, 10 sec.)
Human Body Model
Machine Model
2 kV
(4)
ESD Rating
200V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings may not imply performance limits. For performance limits and associated
test conditions, see the Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 150°C (typ.) and
disengages at TJ= 130°C (typ.).
(4) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF
capacitor discharged directly into each pin. MIL-STD-883 3015.7
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Operating Ratings(1) (2)
Input Voltage Range
2.9V to 5.5V
0mA to 600 mA
−30°C to +125°C
−30°C to +85°C
Recommended Load Current
Junction Temperature (TJ) Range
(3)
Ambient Temperature (TA) Range
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings may not imply performance limits. For performance limits and associated
test conditions, see the Electrical Characteristics tables.
(2) All voltages are with respect to the potential at the GND pin.
(3) In Applications where high power dissipation and/or poor package resistance is present, the maximum ambient temperature may have
to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX), the
maximum power dissipation of the device in the application (PD-MAX) and the junction to ambient thermal resistance of the package (θJA
)
in the application, as given by the following equation:TA-MAX= TJ-MAX− (θJAx PD-MAX). Refer to Dissipation rating table for PD-MAX values at
different ambient temperatures.
Thermal Properties
Junction-to-Ambient Thermal Resistance (θJA) for 4 layer board
(1)
56°C/W
(1) Junction to ambient thermal resistance (θJA) is highly application and board layout dependent. In applications where high power
dissipation exists, special care must be given to thermal dissipation issues in board design. Specified value of 130 °C/W for WSON is
based on a 4 layer, 4" x 3", 2/1/1/2 oz. Cu board as per JEDEC standards is used.
Electrical Characteristics(1) (2) (3)
Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the full operating junction temperature range
(−30°C ≤ TJ ≤ +125°C). Unless otherwise noted, specifications apply to the LM3676SD with VIN = 3.6V
Symbol
VFB
Parameter
Feedback Voltage (Fixed / Adj)
Line Regulation
Test Conditions
Min
-4
Typ
Max
+4
Unit
%
(4)
2.9V ≤ VIN ≤ 5.5V
0.031
%/V
IO = 10 mA
Load Regulation
100 mA ≤ IO ≤ 600 mA
0.0013
%/mA
VIN= 3.6V
VREF
ISHDN
IQ
Internal Reference Voltage
Shutdown Supply Current
DC Bias Current into VIN
0.5
0.01
16
V
EN = 0V
2
µA
µA
No load, device is not switching (FB
forced higher than programmed output
voltage)
35
RDSON (P)
RDSON (N)
ILIM
Pin-Pin Resistance for PFET
Pin-Pin Resistance for NFET
380
250
500
400
mΩ
mΩ
mA
V
(5)
Switch Peak Current Limit
Open Loop
830
1.0
1020
1200
VIH
Logic High Input for EN and Mode Pin
Logic Low Input for EN and Mode Pin
Enable (EN) Input Current
VIL
0.4
1
V
IEN
0.01
0.01
2
µA
µA
MHz
IMode
FOSC
Mode Pin Input Current
1
Internal Oscillator Frequency
PWM Mode
1.6
2.6
(1) All voltages are with respect to the potential at the GND pin.
(2) Min and Max limits are specified by design, test or statistical analysis. Typical numbers represent the most likely norm.
(3) The parameters in the electrical characteristic table are tested at VIN= 3.6V unless otherwise specified. For performance over the input
voltage range refer to datasheet curves.
(4) Test condition: for VOUT less than 2.5V, VIN = 3.6V; for VOUT greater than or equal to 2.5V, VIN = VOUT + 1V.
(5) Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Electrical Characteristic
table reflects open loop data (FB=0V and current drawn from SW pin ramped up until cycle by cycle current limit is activated). Closed
loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops
by 10%.
Dissipation Ratings
θJA
TA≤ 25°C
TA= 60°C
TA= 85°C
Power Rating
Power Rating
Power Rating
56°C/W (4 layer board) 8 Lead non-pullback WSON package
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1.78W
1.16W
714mW
4
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BLOCK DIAGRAM
V
EN
SW
IN
Current Limit
Comparator
+
Undervoltage
Lockout
Ramp
Generator
Soft
Start
-
Ref1
PFM Current
Comparator
Thermal
Shutdown
+
Bandgap
2 MHz
Oscillator
-
Ref2
PWM Comparator
+
-
Error
Amp
Control Logic
Driver
pfm_low
pfm_hi
V
+
-
REF
0.5V
Vcomp
1.0V
+
-
+
-
Zero Crossing
Comparator
Frequency
Compensation
Adj Ver
Fixed Ver
FB
SGND
PGND
MODE
Figure 4. Simplified Functional Diagram
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Typical Performance Characteristics
Circuit of LM3676, VIN= 3.6V, VOUT= 1.5V, TA= 25°C, unless otherwise noted.
Quiescent Supply Current vs. Supply Voltage
Shutdown Current vs. Temp
EN = GND
20
18
16
14
12
10
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
EN = V
IN
I
= 0 mA
OUT
T
= 85°C
= 25°C
A
T
A
T
= -30°C
A
V
IN
= 5.5V
V
IN
= 3.6V
V
= 2.9V
IN
-30
-10
10
30
50
70
90
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 5.
Figure 6.
Feedback Bias Current vs. Temp
Switching Frequency vs. Temperature
2.02
2.00
1.98
1.96
1.94
1.92
1.90
1.88
V
= 3.6V
IN
V
= 4.5V
IN
V
= 2.9V
IN
I
= 300 mA
OUT
-40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
Figure 7.
Figure 8.
RDS(ON) vs. Temperature
Open/Closed Loop Current Limit vs. Temperature
1200
VIN = 4.5V
1150
1100
1050
1000
950
CLOSE LOOP
V
= 2.9V
IN
V
= 3.6V
IN
V
= 4.5V
IN
V
IN
= 3.6V
V
= 2.9V
IN
OPEN LOOP
60 80 100
900
-40 -20
0
20
40
TEMPERATURE (°C)
Figure 9.
Figure 10.
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Typical Performance Characteristics (continued)
Circuit of LM3676, VIN= 3.6V, VOUT= 1.5V, TA= 25°C, unless otherwise noted.
Output Voltage vs. Supply Voltage
Output Voltage vs. Temperature
(VOUT = 1.5V)
(VOUT = 1.5V)
1.5300
1.5300
1.5200
1.5100
1.5000
1.4900
1.4800
V
= 1.5 V
OUT
1.5250
1.5200
1.5150
1.5100
1.5050
1.5000
1.4950
1.4900
1.4850
1.4800
PFM Mode
I
= 10 mA
OUT
I
= 10 mA
OUT
I
= 300 mA
OUT
I
= 300 mA
OUT
PWM Mode
I
= 500 mA
OUT
V
V
= 3.6V
IN
= 1.5V
I
= 600 mA
OUT
OUT
I
= 600 mA
OUT
3.5
-30
-10
10
30
50
70
90
2.5
3
4
4.5
5
5.5
TEMPERATURE (oC)
SUPPLY VOLTAGE(V)
Figure 11.
Figure 12.
Output Voltage vs. Output Current
(VOUT = 1.5V)
Line Transient Response
VOUT = 1.5V (PWM Mode)
1.54
1.52
1.5
V
V
= 3.6V
IN
= 1.5V
OUT
20 mV/DIV
AC Coupled
V
OUT
PFM Mode
3.6V
3.0V
V
IN
PWM Mode
V
OUT
= 1.5V
I
= 400 mA
OUT
1.48
40 ms/DIV
0
100
200
300
400
500
600
OUTPUT CURRENT (mA)
Figure 13.
Figure 14.
Efficiency vs. Output Current
(VOUT = 1.5V, L = 2.2 µH)
Efficiency vs. Output Current
(VOUT = 3.3V, L = 2.2 µH)
Figure 15.
Figure 16.
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Typical Performance Characteristics (continued)
Circuit of LM3676, VIN= 3.6V, VOUT= 1.5V, TA= 25°C, unless otherwise noted.
Load Transient Response (VOUT = 1.5V)
(PFM Mode 0.5mA to 50mA)
Load Transient Response (VOUT = 1.5V)
(PFM Mode 50mA to 0.5mA)
Figure 17.
Figure 18.
Mode Change by Load Transients
VOUT = 1.5V (PFM to PWM)
Mode Change by Load Transients
VOUT = 1.5V (PWM to PFM)
Figure 19.
Figure 20.
Mode Change by Mode Pin
VOUT = 1.5V (PFM to PWM)
Mode Change by Mode Pin
VOUT = 1.5V (PWM to PFM)
Figure 21.
Figure 22.
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Typical Performance Characteristics (continued)
Circuit of LM3676, VIN= 3.6V, VOUT= 1.5V, TA= 25°C, unless otherwise noted.
Load Transient Response
VOUT = 1.5V (PWM Mode)
Start Up into PWM Mode
VOUT = 1.5V (Output Current= 300mA)
2V/DIV
V
SW
I
= 300 mA
OUT
500 mA/DIV
1V/DIV
I
L
V
= 3.6V
IN
V
OUT
EN
V
OUT
= 1.5V
2V/DIV
TIME (100 ms/DIV)
Figure 23.
Figure 24.
Start Up into PFM Mode
VOUT = 1.5V (Output Current= 1mA)
2V/DIV
V
SW
500 mV/DIV
V
OUT
V
V
= 3.6V
IN
OUT
= 1 mA
= 1.5V
I
OUT
2V/DIV
EN
TIME (100 ms/DIV)
Figure 25.
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OPERATION DESCRIPTION
DEVICE INFORMATION
The LM3676, a high efficiency step down DC-DC switching buck converter, delivers a constant voltage from a
single Li-Ion battery and input voltage rails from 2.9V to 5.5V to portable devices such as cell phones and PDAs.
Using a voltage mode architecture with synchronous rectification, the LM3676 has the ability to deliver up to 600
mA depending on the input voltage, output voltage, ambient temperature and the inductor chosen.
There are three modes of operation depending on the current required and Mode pin - PWM (Pulse Width
Modulation), PFM (Pulse Frequency Modulation), and shutdown. The device operates in PWM mode if the load
current > 80 mA or when the Mode pin is set high. When the mode pin is set low, Auto mode, lighter load current
causes the device to automatically switch into PFM for reduced current consumption (IQ = 16 µA typ) and prolong
battery life . Shutdown mode turns off the device, offering the lowest current consumption (ISHUTDOWN = 0.01 µA
typ).
Additional features include soft-start, under voltage protection, current overload protection, and thermal shutdown
protection. As shown in Figure 1, only three external power components are required for implementation.
The part uses an internal reference voltage of 0.5V. It is recommended to keep the part in shutdown until the
input voltage is 2.9V or higher.
CIRCUIT OPERATION
During the first portion of each switching cycle, the control block in the LM3676 turns on the internal PFET
switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The
inductor limits the current to a ramp with a slope of (VIN–VOUT)/L, by storing energy in a magnetic field.
During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the
input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the
NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of - VOUT/L.
The output filter stores charge when the inductor current is high, and releases it when inductor current is low,
smoothing the voltage across the load.
The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and
synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The
output voltage is equal to the average voltage at the SW pin.
MODE PIN
Setting the Mode pin low (<0.4V) places the LM3676 in Auto mode. During Auto mode the device automatically
switches between PFM-PWM depending on the load. Setting Mode high (>1.0V) places the part in Forced PWM.
The part is in forced PWM regardless of the load. Do not leave the Mode pin floating.
PWM OPERATION
During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This
allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to
the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is
introduced.
While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating
the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned
on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The
current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the
NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off
the NFET and turning on the PFET.
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V
SW
2V/DIV
I
L
200 mA/DIV
V
V
= 3.6V
IN
I
= 400 mA
OUT
= 1.5V
OUT
V
OUT
10 mV/DIV
AC Coupled
TIME (200 ns/DIV)
Figure 26. Typical PWM Operation
Internal Synchronous Rectification
While in PWM mode, the LM3676 uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
Current Limiting
A current limit feature allows the LM3676 to protect itself and external components during overload conditions.
PWM mode implements current limiting using an internal comparator that trips at 1020 mA (typ). If the output is
shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration
until the inductor current falls below a low threshold. This allows the inductor current more time to decay, thereby
preventing runaway.
PFM OPERATION
At very light load, the converter enters PFM mode and operates with reduced switching frequency and supply
current to maintain high efficiency.
The part automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or
more clock cycles:
A. The NFET current reaches zero.
B. The peak PMOS switch current drops below the IMODE level, (Typically IMODE < 30mA + VIN/42 Ω ).
2V/DIV
V
SW
I
L
200 mA/DIV
VIN = 3.6V
I
= 20 mA
OUT
VOUT = 1.5V
V
OUT
20 mV/DIV
AC Coupled
TIME (4 ms/DIV)
Figure 27. Typical PFM Operation
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During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between ~0.6% and ~1.7% above the nominal PWM output voltage. If
the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains
on until the output voltage reaches the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for
PFM mode. The typical peak current in PFM mode is: IPFM = 112mA + VIN/27Ω .
Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps
to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output
voltage is below the ‘high’ PFM comparator threshold (see Figure 28), the PMOS switch is again turned on and
the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM
threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output
switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this
‘sleep’ mode is 16µA (typ), which allows the part to achieve high efficiency under extremely light load conditions.
If the load current should increase during PFM mode (see Figure 28) causing the output voltage to fall below the
‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode. When VIN =2.9V the
part transitions from PWM to PFM mode at ~35mA output current and from PFM to PWM mode at ~85mA , when
VIN=3.6V, PWM to PFM transition happens at ~50mA and PFM to PWM transition happens at ~100mA, when VIN
=4.5V, PWM to PFM transition happens at ~65mA and PFM to PWM transition happens at ~115mA.
High PFM Threshold
PFM Mode at Light Load
~1.017*Vout
Load current
increases
Low1 PFM Threshold
~1.006*Vout
Current load
increases,
draws Vout
towards
Low2 PFM
Threshold
High PFM
Nfet on
drains
conductor
current
until
I inductor=0
Low PFM
Threshold,
turn on
Pfet on
until
Voltage
Threshold
reached,
go into
Ipfm limit
reached
PFET
Low2 PFM Threshold
Vout
sleep mode
PWM Mode at
Moderate to Heavy
Loads
Low2 PFM Threshold,
switch back to PWMmode
Figure 28. Operation in PFM Mode and Transfer to PWM Mode
SHUTDOWN MODE
Setting the EN input pin low (<0.4V) places the LM3676 in shutdown mode. During shutdown the PFET switch,
NFET switch, reference, control and bias circuitry of the LM3676 are turned off. Setting EN high (>1.0V) enables
normal operation. It is recommended to set EN pin low to turn off the LM3676 during system power up and
undervoltage conditions when the supply is less than 2.9V. Do not leave the EN pin floating.
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SOFT START
The LM3676 has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current
limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after Vin reaches
2.9V. Soft start is implemented by increasing switch current limit in steps of 70mA, 140mA, 280mA and 1020mA
(typical switch current limit). The start-up time thereby depends on the output capacitor and load current
demanded at start-up. Typical start-up times with a 10µF output capacitor and 300mA load is 400µs and with
1mA load is 275µs.
LDO - LOW DROP OUT OPERATION
The LM3676-ADJ can operate at 100% duty cycle (no switching; PMOS switch completely on) for low drop out
support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input
voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV.
The minimum input voltage needed to support the output voltage is
VIN, MIN = ILOAD * (RDSON (P) + RINDUCTOR) + VOUT
ILOAD = Load current
RDSON (P) = Drain to source resistance of PFET switch in the triode region
RINDUCTOR = Inductor resistance
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APPLICATION INFORMATION
OUTPUT VOLTAGE SELECTION FOR LM3676-ADJ
The output voltage of the adjustable parts can be programmed through the resistor network connected from VOUT
to FB, then to GND. VOUT is adjusted to make the voltage at FB equal to 0.5V. The resistor from FB to GND (R2)
should be 200 kΩ to keep the current drawn through this network well below the 16 µA quiescent current level
(PFM mode) but large enough that it is not susceptible to noise. If R2 is 200 kΩ, and VFB is 0.5V, the current
through the resistor feedback network will be 2.5 µA. The output voltage of the adjustable parts ranges from 1.1V
to 3.3V.
The formula for output voltage selection is:
R1
’
◊
≈
VOUT = VFB * 1 +
R2
«
(1)
•
•
•
•
VOUT: output voltage (volts)
VFB : feedback voltage = 0.5V
R1: feedback resistor from VOUT to FB
R2: feedback resistor from FB to GND
For any output voltage greater than or equal to 1.1V, a zero must be added around 45 kHz for stability. The
formula for calculation of C1 is:
1
C1 =
(2 * p * R1 * 45 kHz)
(2)
For output voltages higher than 2.5V, a pole must be placed at 45 kHz as well. If the pole and zero are at the
same frequency the formula for calculation of C2 is:
1
C2 =
(2 * p * R2 * 45 kHz)
(3)
The formula for location of zero and pole frequency created by adding C1 and C2 is given below. By adding C1,
a zero as well as a higher frequency pole is introduced.
1
Fz =
(2 * p * R1 * C1)
(4)
(5)
1
Fp =
2 * p * (R1 R2) * (C1+C2)
See Table 1.
Table 1. LM3676-ADJ Configurations For Various VOUT (Circuit of Figure 2)
VOUT(V)
1.1
R1(kΩ)
240
280
320
357
442
432
464
523
402
464
562
R2 (kΩ)
200
200
200
178
200
178
178
191
100
100
100
C1 (pF)
15
C2 (pF)
none
none
none
none
none
none
none
none
none
33
L (µH)
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
CIN (µF)
4.7
COUT(µF)
10
1.2
12
4.7
10
1.3
12
4.7
10
1.5
10
4.7
10
1.6
8.2
8.2
8.2
6.8
8.2
8.2
6.8
4.7
10
1.7
4.7
10
1.8
4.7
10
1.875
2.5
4.7
10
4.7
10
2.8
4.7
10
3.3
33
4.7
10
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INDUCTOR SELECTION
There are two main considerations when choosing an inductor: the inductor should not saturate, and the inductor
current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current
rating specifications are followed by different manufacturers so attention must be given to details. Saturation
current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of
application should be requested from the manufacturer. The minimum value of inductance to ensure good
performance is 1.76µH at ILIM (typ) dc current over the ambient temperature range. Shielded inductors
radiate less noise and should be preferred.
There are two methods to choose the inductor saturation current rating.
Method 1:
The saturation current should be greater than the sum of the maximum load current and the worst case average
to peak inductor current. This can be written as
>
ISAT IOUTMAX + IRIPPLE
VIN - VOUT
VOUT
VIN
1
≈
∆
«
’* ≈
÷ ∆
◊ «
’* ≈ ’
where IRIPPLE
=
÷ ∆ ÷
2 * L
◊ « f ◊
(6)
•
•
•
•
•
•
IRIPPLE: average to peak inductor current
IOUTMAX: maximum load current (600mA)
VIN: maximum input voltage in application
L : min inductor value including worst case tolerances (30% drop can be considered for method 1)
f : minimum switching frequency (1.6Mhz)
VOUT: output voltage
Method 2:
A more conservative and recommended approach is to choose an inductor that has a saturation current rating
greater than the maximum current limit of 1200mA.
A 2.2 µH inductor with a saturation current rating of at least 1200 mA is recommended for most applications.The
inductor’s resistance should be less than 0.3Ω for good efficiency. Table 2 lists suggested inductors and
suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical
applications, a toroidal or shielded-bobbin inductor should be used. A good practice is to lay out the board with
overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor,
in the event that noise from low-cost bobbin models is unacceptable.
Table 2. Suggested Inductors and Their Suppliers
Model
Vendor
Coilcraft
Coilcraft
Panasonic
Sumida
Dimensions LxWxH (mm)
3.3 x 3.3 x 1.4
D.C.R (max)
200 mΩ
150 mΩ
53 mΩ
DO3314-222MX
LPO3310-222MX
ELL5GM2R2N
CDRH2D14-2R2
3.3 x 3.3 x 1.0
5.2 x 5.2 x 1.5
3.2 x 3.2 x 1.55
94 mΩ
INPUT CAPACITOR SELECTION
A ceramic input capacitor of 4.7 µF, 6.3V is sufficient for most applications. Place the input capacitor as close as
possible to the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or
X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting
case sizes like 0805 and 0603. The minimum input capacitance to ensure good performance is 2.2µF at 3V
dc bias; 1.5µF at 5V dc bias including tolerances and over ambient temperature range. The input filter
capacitor supplies current to the PFET switch of the LM3676 in the first half of each cycle and reduces voltage
ripple imposed on the input power source. A ceramic capacitor’s low ESR provides the best noise filtering of the
input voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple current rating.
The input current ripple can be calculated as:
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2
VOUT
VIN
VOUT
VIN
r
≈
∆
«
’
÷
◊
1 -
+
*
IRMS = IOUTMAX
*
12
(VIN - VOUT
) V
*
OUT
r =
L* f * IOUTMAX *VIN
*
The worst case is when VIN = 2 VOUT
(7)
OUTPUT CAPACITOR SELECTION
A ceramic output capacitor of 10 µF, 6.3V is sufficient for most applications. Use X7R or X5R types; do not use
Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and
0603. DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be requested
from them as part of the capacitor selection process.
The minimum output capacitance to ensure good performance is 5.75µF at 1.8V dc bias including
tolerances and over ambient temperature range. The output filter capacitor smoothes out current flow from
the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces
output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to
perform these functions.
The output voltage ripple is caused by the charging and discharging of the output capacitor and by the RESR and
can be calculated as:
Voltage peak-to-peak ripple due to capacitance can be expressed as follow:
IRIPPLE
=
VPP-C
4*f*C
(8)
Voltage peak-to-peak ripple due to ESR can be expressed as follow:
VPP-ESR = (2 * IRIPPLE) * RESR
Because these two components are out of phase the rms (root mean squared) value can be used to get an
approximate value of peak-to-peak ripple.
The peak-to-peak ripple voltage, rms value can be expressed as follow:
2
VPP-RMS
=
VPP-C2 + VPP-ESR
(9)
Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series
resistance of the output capacitor (RESR).
The RESR is frequency dependent (as well as temperature dependent); make sure the value used for calculations
is at the switching frequency of the part.
Table 3. Suggested Capacitors and Their Suppliers
Case Size
Inch (mm)
Model
4.7 µF for CIN
Type
Vendor
Voltage Rating
C2012X5R0J475K
JMK212BJ475K
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
TDK
Taiyo-Yuden
Murata
6.3V
6.3V
6.3V
6.3V
0805 (2012)
0805 (2012)
0805 (2012)
0603 (1608)
GRM21BR60J475K
C1608X5R0J475K
TDK
10 µF for COUT
GRM21BR60J106K
JMK212BJ106K
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Murata
Taiyo-Yuden
TDK
6.3V
6.3V
6.3V
6.3V
0805 (2012)
0805 (2012)
0805 (2012)
0603 (1608)
C2012X5R0J106K
C1608X5R0J106K
TDK
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BOARD LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or
instability.
Good layout for the LM3676 can be implemented by following a few simple design rules below. See Figure 29 for
top layer board layout.
Figure 29. Top Layer of Board Layout for LM3676
1. Place the LM3676, inductor and filter capacitors close together and make the traces short. The traces
between these components carry relatively high switching currents and act as antennas. Following this rule
reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN
and GND pin.
2. Arrange the components so that the switching current loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor through the LM3676 and inductor to the output filter
capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled
up from ground through the LM3676 by the inductor to the output filter capacitor and then back through
ground forming a second current loop. Routing these loops so the current curls in the same direction
prevents magnetic field reversal between the two half-cycles and reduces radiated noise.
3. Connect the ground pins of the LM3676 and filter capacitors together using generous component-side
copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several
vias. This reduces ground-plane noise by preventing the switching currents from circulating through the
ground plane. It also reduces ground bounce at the LM3676 by giving it a low-impedance ground connection.
Connect SGND to PGND at one single point within the board layout.
4. Use wide traces between the power components and for power connections to the DC-DC converter circuit.
This reduces voltage errors caused by resistive losses across the traces.
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5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power
components. The voltage feedback trace must remain close to the LM3676 circuit and should be direct but
should be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC converter’s own
voltage feedback trace. A good approach is to route the feedback trace on another layer and to have a
ground plane between the top layer and layer on which the feedback trace is routed. In the same manner for
the adjustable part it is desired to have the feedback dividers on the bottom layer.
6. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks
and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced through
distance.
In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board,
arrange the CMOS digital circuitry around it (since this also generates noise), and then place sensitive
preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a
metal pan and power to it is post-regulated to reduce conducted noise, using low-dropout linear regulators.
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SNVS426C –NOVEMBER 2006–REVISED MAY 2013
REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 18
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM3676SD-1.8/NOPB
LM3676SD-3.3/NOPB
LM3676SD-ADJ/NOPB
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
NGQ
NGQ
NGQ
8
8
8
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-30 to 85
-30 to 85
-30 to 85
S009B
SN
SN
S010B
S008B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3676SD-1.8/NOPB
LM3676SD-3.3/NOPB
LM3676SD-ADJ/NOPB
WSON
WSON
WSON
NGQ
NGQ
NGQ
8
8
8
1000
1000
1000
178.0
178.0
178.0
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
1.0
1.0
1.0
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM3676SD-1.8/NOPB
LM3676SD-3.3/NOPB
LM3676SD-ADJ/NOPB
WSON
WSON
WSON
NGQ
NGQ
NGQ
8
8
8
1000
1000
1000
208.0
208.0
208.0
191.0
191.0
191.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
NGQ0008A
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
0.8
0.7
SEATING PLANE
0.08 C
1.6 0.1
SYMM
(0.1) TYP
0.05
0.00
EXPOSED
THERMAL PAD
4
5
8
SYMM
9
2X
2
0.1
1.5
1
6X 0.5
0.3
0.2
8X
0.1
C A B
C
0.5
0.3
PIN 1 ID
8X
0.05
4214922/A 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
NGQ0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
SYMM
8X (0.6)
1
8
(0.75)
8X (0.25)
9
SYMM
(2)
6X (0.5)
5
4
(R0.05) TYP
(
0.2) VIA
TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214922/A 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
NGQ0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.6)
SYMM
METAL
TYP
9
8
1
8X (0.25)
SYMM
(1.79)
6X (0.5)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 9:
82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4214922/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Copyright © 2021, Texas Instruments Incorporated
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