LM3677TL-1.2/NOPB [TI]
3MHz, 600mA Miniature Step-Down DC-DC Converter for Ultra Low Voltage Circuits;
| 型号： | LM3677TL-1.2/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3MHz, 600mA Miniature Step-Down DC-DC Converter for Ultra Low Voltage Circuits 开关 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM3677
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SNVS502F –MARCH 2007–REVISED MAY 2013
3MHz, 600mA Miniature Step-Down DC-DC Converter for Ultra Low Voltage Circuits
Check for Samples: LM3677
1
FEATURES
APPLICATIONS
2
•
16 µA typical quiescent current
•
•
•
•
•
•
•
Mobile Phones
PDAs
•
•
•
•
600 mA maximum load capability
3 MHz PWM fixed switching frequency (typ.)
Automatic PFM/PWM mode switching
MP3 Players
W-LAN
Available in 5-bump DSBGA package and 6-pin
USON package
Portable Instruments
Digital Still Cameras
Portable Hard Disk Drives
•
Internal synchronous rectification for high
efficiency
•
•
•
•
Internal soft start
DESCRIPTION
The LM3677 step-down DC-DC converter is
optimized for powering ultra-low voltage circuits from
a single Li-Ion cell battery and input voltage rails from
2.7V to 5.5V. It provides up to 600 mA load current
over the entire input voltage range. The LM3677 is
configured to different fixed voltage output options as
well as an adjustable output voltage version range
from 1.2V to 3.3V.
0.01 µA typical shutdown current
Operates from a single Li-Ion cell battery
Only three tiny surface-mount external
components required (solution size less than
20 mm2)
•
Current overload and thermal shutdown
protection
TYPICAL APPLICATION CIRCUITS
V
IN
L1: 1.0 mH
V
OUT
2.7V to 5.5V
V
IN
SW
1
2
3
5
C
OUT
C
IN
LM3677
10 mF
4.7 mF
GND
EN
FB
4
Figure 1. Typical Application Circuit
V
IN
L1: 1.0 mH
V
V
OUT
2.7V to 5.5V
IN
SW
1
2
3
5
C
C
LM3677-
ADJ
IN
OUT
R1
R2
C1
C2
4.7 mF
10 mF
GND
EN
FB
4
Figure 3. Efficiency vs. Output Current
(VOUT = 1.8V)
Figure 2. Typical Application Circuit - ADJ.
Version
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LM3677
SNVS502F –MARCH 2007–REVISED MAY 2013
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DESCRIPTION (CONTINUED)
The device offers superior features and performance for mobile phones and similar portable applications with
complex power management systems. Automatic intelligent switching between PWM low-noise and PFM low-
current mode offers improved system control. During PWM mode operation, the device operates at a fixed
frequency of 3 MHz (typ). PWM mode drives loads from ~ 80 mA to 600 mA max. Hysteretic PFM mode extends
the battery life by reducing the quiescent current to 16 µA (typ.) during light load and standby operation. Internal
synchronous rectification provides high efficiency. In shutdown mode (Enable pin pulled down), the device turns
off and reduces battery consumption to 0.01 µA (typ.).
The LM3677 is available in a lead-free (NOPB) 5-bump DSBGA package and 6-pin USON package. A switching
frequency of 3 MHz (typ.) allows use of tiny surface-mount components. Only three external surface-mount
components, an inductor and two ceramic capacitors, are required.
CONNECTION DIAGRAMS
A3
A1
Vin
EN
GND
Vin
EN
A1
A3
GND
B2
B2
SW
FB
SW
FB
C1
C3
C3
C1
Top View
Bottom View
5-Bump DSBGA Package
See Package Number YZR0005
VIN 1
SW 2
VIN 1
SW 2
6 GND
5 SW
6 GND
5 SW
4 FB
EN 3
EN 3
4 FB
TOP VIEW
BOTTOM VIEW
6-Pin USON Package
See Package Number NGE0006A
PIN DESCRIPTIONS(1)
Name
VIN
Pin No.
Description
A1
A3
C1
1
6
3
Power supply input. Connect to the input filter capacitor (Figure 1).
Ground pin.
GND
EN
Enable pin. The device is in shutdown mode when voltage to this pin is < 0.4V and
enabled when > 1.0V. Do not leave this pin floating.
FB
C3
B2
4
Feedback analog input. Connect directly to the output filter capacitor ( FIGURE 1).
SW
2, 5
Switching node connection to the internal PFET switch and NFET synchronous
rectifier.
(1) For output voltage 1.2V or lower, input voltage needs to be derated to the range of 2.7V to 5.0V in order to perform within specification.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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ABSOLUTE MAXIMUM RATINGS(1)(2)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributor for
availability and specifications.
VIN Pin: Voltage to GND
FB, SW, EN Pin:
−0.2V to 6.0V
(GND−0.2V) to
(VIN + 0.2V)
(3)
Continuous Power Dissipation
Internally Limited
+125°C
Junction Temperature (TJ-MAX
Storage Temperature Range
)
−65°C to +150°C
260°C
Maximum Lead Temperature
(Soldering, 10 sec.)
(4)
ESD Rating
Human Body Model: All Pins
Machine Model: All Pins
2.0 kV
200V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 150°C (typ.) and
disengages at TJ= 130°C (typ.).
(4) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF
capacitor discharged directly into each pin. MIL-STD-883 3015.7
(2)
OPERATING RATINGS(1),
Input Voltage Range
2.7V to 5.5V
0 mA to 600 mA
−30°C to +125°C
−30°C to +85°C
Recommended Load Current
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range
(3)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics tables.
(2) All voltages are with respect to the potential at the GND pin.
(3) In Applications where high power dissipation and/or poor package resistance is present, the maximum ambient temperature may have
to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX), the
maximum power dissipation of the device in the application (PD-MAX) and the junction to ambient thermal resistance of the package (θJA
in the application, as given by the following equation: TA-MAX= TJ-MAX− (θJAx PD-MAX). Refer to Dissipation rating table for PD-MAX values
at different ambient temperatures.
)
THERMAL PROPERTIES
Junction-to-Ambient Thermal Resistance (θJA
(1)
)
85°C/W
(1) Junction to ambient thermal resistance is highly application and board layout dependent. In applications where high power dissipation
exists, special care must be given to thermal dissipation issues in board design. Value specified here 85 °C/W is based on
measurement results using a 4 layer board as per JEDEC standards.
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ELECTRICAL CHARACTERISTICS(1)(2)(3)
Limits in standard typeface are for TJ = TA = 25°C. Limits in boldface type apply over the operating ambient temperature
range (−30°C ≤ TA ≤ +85°C). Unless otherwise noted, specifications apply to the LM3677 with VIN = EN = 3.6V.
Parameter
Test Conditions
Min
2.7
Typ
Max
5.5
Units
(4)
VIN
Input Voltage
V
Feedback Voltage (TL)
Feedback Voltage (LE)
Internal Reference Voltage
Shutdown Supply Current
DC Bias Current into VIN
Pin-Pin Resistance for PFET
Pin-Pin Resistance for NFET
Switch Peak Current Limit
Logic High Input
-2.5
-4.0
+2.5
+4.0
VFB
PWM mode
%
VREF
ISHDN
IQ
0.5
0.01
16
V
µA
µA
mΩ
mΩ
mA
V
EN = 0V
1
No load, device is not switching
VIN= VGS= 3.6V, ISW= 100mA
VIN= VGS= 3.6V, ISW= -100mA
Open Loop(5)
35
RDSON (P)
RDSON (N)
ILIM
350
150
1220
450
250
1375
1085
1.0
VIH
VIL
Logic Low Input
0.4
1
V
IEN
Enable (EN) Input Current
Internal Oscillator Frequency
0.01
3
µA
MHz
FOSC
PWM Mode
2.5
3.5
(1) All voltages are with respect to the potential at the GND pin.
(2) Min and Max limits are specified by design, test or statistical analysis. Typical numbers represent the most likely norm.
(3) The parameters in the electrical characteristic table are tested under open loop conditions at VIN= 3.6V unless otherwise specified. For
performance over the input voltage range and closed loop condition, refer to the datasheet curves.
(4) For output voltage 1.2V or lower, input voltage needs to be derated to the range of 2.7V to 5.0V in order to perform within specification.
(5) Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Electrical Characteristic
table reflects open loop data (FB=0V and current drawn from SW pin ramped up until cycle by cycle current limit is activated). Closed
loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops
by 10%.
DISSIPATION RATING TABLE
TA≤ 25°C
Power Rating
TA= 60°C
Power Rating
TA= 85°C
Power Rating
θJA
85°C/W (4-layer board)
DSBGA
1178 mW
855 mW
785 mW
556 mW
470 mW
342 mW
117°C/W (4-layer board)
USON
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BLOCK DIAGRAM
V
EN
SW
IN
Current Limit
Comparator
+
Undervoltage
Lockout
Ramp
Generator
Soft
Start
-
Ref1
PFM Current
Comparator
Thermal
Shutdown
+
Bandgap
3 MHz
Oscillator
-
Ref2
PWM Comparator
Error
Amp
+
-
Control Logic
Driver
pfm_low
pfm_hi
V
+
-
REF
0.5V
Vcomp
1.0V
+
-
+
-
Zero Crossing
Comparator
Frequency
Compensation
Fixed Ver
FB
GND
Figure 4. Simplified Functional Diagram
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TYPICAL PERFORMANCE CHARACTERISTICS
LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted.
Quiescent Supply Current vs. Supply Voltage
(Switching)
Shutdown Current vs. Temp
Figure 5.
Figure 6.
Switching Frequency vs. Temperature
RDS(ON) vs. Temperature
Figure 7.
Figure 8.
Open/Closed Loop Current Limit
vs. Temperature
Output Voltage vs. Supply Voltage
(VOUT = 1.8V)
Figure 9.
Figure 10.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted.
Output Voltage vs. Supply Voltage
Output Voltage vs. Temperature
(VOUT = 2.5V)
(VOUT = 1.3V)
Figure 11.
Figure 12.
Output Voltage vs. Temperature
(VOUT = 1.8V)
Output Voltage vs. Temperature
(VOUT = 2.5V)
Figure 13.
Figure 14.
Output Voltage vs. Output Current
(VOUT = 1.8V)
Output Voltage vs. Output Current
(VOUT = 2.5V)
Figure 15.
Figure 16.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted.
Efficiency vs. Output Current
Efficiency vs. Output Current
(VOUT = 1.3V)
(VOUT = 1.8V)
Figure 17.
Figure 18.
Efficiency vs. Output Current
(VOUT = 2.5V)
Output Current vs. Input Voltage at Mode Change Point
(VOUT = 1.3V)
Figure 19.
Figure 20.
Output Current vs. Input Voltage at Mode Change Point
(VOUT = 1.8V)
Output Current vs. Input Voltage at Mode Change Point
(VOUT = 2.5V)
Figure 21.
Figure 22.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted.
Line Transient Response
VOUT = 1.3V (PWM Mode)
Line Transient Response
VOUT = 1.8V (PWM Mode)
Figure 23.
Figure 24.
Line Transient Response
VOUT = 1.8V (PWM Mode)
Line Transient Response
VOUT = 2.5V (PWM Mode)
Figure 25.
Figure 26.
Load Transient Response (VOUT = 1.3V)
(PFM Mode 1mA to 50mA)
Load Transient Response (VOUT = 1.3V)
(PFM Mode 50mA to 1mA)
Figure 27.
Figure 28.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted.
Load Transient Response (VOUT = 1.8V)
Load Transient Response (VOUT = 1.8V)
(PFM Mode 1mA to 50mA)
(PFM Mode 50mA to 1mA)
Figure 29.
Figure 30.
Load Transient Response (VOUT = 2.5V)
(PFM Mode 1mA to 50mA)
Load Transient Response (VOUT = 2.5V)
(PFM Mode 50mA to 1mA)
Figure 31.
Figure 32.
Mode Change by Load Transients
VOUT = 1.3V (PFM to PWM)
Mode Change by Load Transients
VOUT = 1.3V (PWM to PFM)
Figure 33.
Figure 34.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted.
Mode Change by Load Transients
Mode Change by Load Transients
VOUT = 1.8V (PFM to PWM)
VOUT = 1.8V (PWM to PFM)
Figure 35.
Figure 36.
Load Transient Response
VOUT = 1.3V (PWM Mode)
Load Transient Response
VOUT = 1.8V (PWM Mode)
Figure 37.
Figure 38.
Load Transient Response
VOUT = 2.5V (PWM Mode)
Start Up into PWM Mode
VOUT = 1.3V (Output Current= 300mA)
Figure 39.
Figure 40.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted.
Start Up into PFM Mode
VOUT = 1.3V (Output Current= 1mA)
Start Up into PWM Mode
VOUT = 1.8V (Output Current= 300mA)
Figure 41.
Figure 42.
Start Up into PFM Mode
VOUT = 1.8V (Output Current= 1mA)
Start Up into PWM Mode
VOUT = 2.5V (Output Current= 300mA)
Figure 43.
Figure 44.
Start Up into PFM Mode
VOUT = 2.5V (Output Current= 1mA)
Figure 45.
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OPERATION DESCRIPTION
DEVICE INFORMATION
The LM3677, a high-efficiency step-down DC-DC switching buck converter, delivers a constant voltage from a
single Li-Ion battery and input voltage rails from 2.7V to 5.5V to devices such as cell phones and PDAs. Using a
voltage-mode architecture with synchronous rectification, the LM3677 has the ability to deliver up to 600 mA
depending on the input voltage and output voltage, ambient temperature, and the inductor chosen.
There are three modes of operation depending on the current required: PWM (Pulse Width Modulation), PFM
(Pulse Frequency Modulation), and shutdown. The device operates in PWM mode at load current of
approximately 80 mA or higher, having a voltage precision of ±2.5% with 90% efficiency or better. Lighter load
current causes the device to automatically switch into PFM mode for reduced current consumption (IQ = 16 µA
typ.) and a longer battery life. Shutdown mode turns off the device, offering the lowest current consumption
(ISHUTDOWN = 0.01 µA (typ.).
Additional features include soft-start, under voltage protection, current overload protection, and thermal shutdown
protection. As shown in Figure 1, only three external power components are required for implementation.
The part uses an internal reference voltage of 0.5V. It is recommended to keep the part in shutdown until the
input voltage exceeds 2.7V.
CIRCUIT OPERATION
The LM3677 operates as follows. During the first portion of each switching cycle, the control block in the LM3677
turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output
filter capacitor and load. The inductor limits the current to a ramp with a slope of (VIN–VOUT)/L, by storing energy
in a magnetic field.
During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the
input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the
NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of - VOUT/L.
The output filter stores charge when the inductor current is high, and releases it when inductor current is low,
smoothing the voltage across the load.
The output voltage is regulated by modulating the PFET switch-on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and
synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The
output voltage is equal to the average voltage at the SW pin.
PWM OPERATION
During PWM operation, the converter operates as a voltage-mode controller with input voltage feed forward. This
allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to
the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is
introduced.
While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating
the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned
on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The
current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the
NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off
the NFET and turning on the PFET.
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Figure 46. Typical PWM Operation
INTERNAL SYNCHRONOUS RECTIFICATION
While in PWM mode, the LM3677 uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
CURRENT LIMITING
A current limit feature allows the LM3677 to protect itself and external components during overload conditions.
PWM mode implements current limiting using an internal comparator that trips at 1220 mA (typ.). If the output is
shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration
until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby
preventing runaway.
PFM OPERATION
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply
current to maintain high efficiency.
The part will automatically transition into PFM mode when either of the following conditions occurs for a duration
of 32 or more clock cycles:
A. The NFET current reaches zero.
B. The peak PMOS switch current drops below the IMODE level, (Typically IMODE < 75 mA + VIN/55Ω ).
Figure 47. Typical PFM Operation
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During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between ~0.2% and ~1.8% above the nominal PWM output voltage. If
the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains
on until the output voltage reaches the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for
PFM mode. The typical peak current in PFM mode is: IPFM = 112 mA + VIN/20Ω .
Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps
to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output
voltage is below the ‘high’ PFM comparator threshold (see Figure 48), the PMOS switch is again turned on and
the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM
threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero, and then both output
switches are turned off and the part enters an extremely low-power mode. Quiescent supply current during this
‘sleep’ mode is 16 µA (typ.), which allows the part to achieve high efficiencies under extremely light load
conditions.
If the load current should increase during PFM mode (Figure 48) causing the output voltage to fall below the
‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode. When VIN =2.7V the
part transitions from PWM to PFM mode at ~ 35 mA output current and from PFM to PWM mode at ~ 95 mA ,
when VIN=3.6V, PWM to PFM transition occurs at ~ 42 mA and PFM to PWM transition occurs at ~ 115 mA,
when VIN =4.5V, PWM to PFM transition occurs at ~ 60 mA and PFM to PWM transition occurs at ~ 135 mA.
High PFM Threshold
~1.018*Vout
PFM Mode at Light Load
Load current
increases
Low1 PFM Threshold
~1.002*Vout
Current load
increases,
draws Vout
towards
Low2 PFM
Threshold
High PFM
Nfet on
drains
conductor
current
until
I inductor=0
Low PFM
Threshold,
turn on
Pfet on
until
Voltage
Threshold
reached,
go into
Ipfm limit
reached
PFET
Low2 PFM Threshold
Vout
sleep mode
PWM Mode at
Moderate to Heavy
Loads
Low2 PFM Threshold,
switch back to PWMmode
Figure 48. Operation in PFM Mode and Transfer to PWM Mode
SHUTDOWN MODE
Setting the EN input pin low (<0.4V) places the LM3677 in shutdown mode. During shutdown the PFET switch,
NFET switch, reference, control and bias circuitry of the LM3677 are turned off. Setting EN high (>1.0V) enables
normal operation. It is recommended to set EN pin low to turn off the LM3677 during system power up and
undervoltage conditions when the supply is less than 2.7V. Do not leave the EN pin floating.
SOFT START
The LM3677 has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current
limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after VIN reaches
2.7V. Soft start is implemented by increasing switch current limit in steps of 200 mA, 400 mA, 600 mA and 1220
mA (typical switch current limit). The start-up time thereby depends on the output capacitor and load current
demanded at start-up. Typical start-up times with a 10 µF output capacitor and 300 mA load is 300 µs and with 1
mA load is 200 µs.
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APPLICATION INFORMATION
INDUCTOR SELECTION
There are two main considerations when choosing an inductor: the inductor should not saturate, and the inductor
current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current
rating specifications are followed by different manufacturers so attention must be given to details. Saturation
current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of
application should be requested form the manufacturer. The minimum value of inductance to ensure good
performance is 0.7 µH at ILIM (typ.) DC current over the ambient temperature range. Shielded inductors
radiate less noise and should be preferred.
There are two methods to choose the inductor saturation current rating.
Method 1:
The saturation current is greater than the sum of the maximum load current and the worst case average to peak
inductor current. This can be written as
>
ISAT IOUTMAX + IRIPPLE
VIN - VOUT
VOUT
VIN
1
≈
∆
«
’* ≈
÷ ∆
◊ «
’* ≈ ’
where IRIPPLE
=
÷ ∆ ÷
2 * L
◊ « f ◊
(1)
•
•
•
•
•
•
IRIPPLE: average to peak inductor current
IOUTMAX: maximum load current (600 mA)
VIN: maximum input voltage in application
L : min inductor value including worst case tolerances (30% drop can be considered for method 1)
f : minimum switching frequency (2.5 MHz)
VOUT: output voltage
Method 2:
A more conservative and recommended approach is to choose an inductor that has saturation current rating
greater than the max current limit of 1375 mA.
A 1.0 µH inductor with a saturation current rating of at least 1375 mA is recommended for most applications. The
inductor’s resistance should be less than 0.15Ω for good efficiency. Table 1 lists suggested inductors and
suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical
applications, a toroidal or shielded-bobbin inductor should be used. A good practice is to lay out the board with
overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor
in the event that noise from low-cost bobbin models is unacceptable.
INPUT CAPACITOR SELECTION
A ceramic input capacitor of 4.7 µF, 6.3V is sufficient for most applications. Place the input capacitor as close as
possible to the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or
X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting
case sizes like 0603 and 0805. The minimum input capacitance to ensure good performance is 2.2 µF at 3V
DC bias; 1.5 µF at 5V DC bias including tolerances and over ambient temperature range. The input filter
capacitor supplies current to the PFET switch of the LM3677 in the first half of each cycle and reduces voltage
ripple imposed on the input power source. A ceramic capacitor’s low ESR provides the best noise filtering of the
input voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple current rating.
The input current ripple can be calculated as:
2
VOUT
VIN
VOUT
VIN
r
≈
∆
«
’
÷
◊
1 -
+
*
IRMS = IOUTMAX
*
12
(VIN - VOUT
r =
) V
*
OUT
L* f * IOUTMAX *VIN
*
The worst case is when VIN = 2 VOUT
(2)
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Table 1. Suggested Inductors and Their Suppliers
Model
Vendor
FDK
Dimensions LxWxH(mm)
2.5 x 2.0 x 1.2
D.C.R (max)
100 mΩ
MIPSA2520D 1R0
LQM2HP 1R0
Murata
2.5 x 2.0 x 0.95
100 mΩ
BRL2518T1R0M
Taiyo Yuden
2.5x 1.8 x 1.2
80 mΩ
OUTPUT CAPACITOR SELECTION
A ceramic output capacitor of 10 µF, 6.3V is sufficient for most applications. Use X7R or X5R types; do not use
Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0603 and
0805. DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be requested
from them as part of the capacitor selection process.
The minimum output capacitance to ensure good performance is 5.75 µF at 2.5V DC bias including
tolerances and over ambient temperature range. The output filter capacitor smooths out current flow from the
inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output
voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform
these functions.
The output voltage ripple is caused by the charging and discharging of the output capacitor and by the RESR and
can be calculated as:
Voltage peak-to-peak ripple due to capacitance can be expressed as follows
IRIPPLE
=
VPP-C
4*f*C
(3)
Voltage peak-to-peak ripple due to ESR can be expressed as follows
VPP-ESR = (2 * IRIPPLE) * RESR
Because these two components are out of phase the rms (root mean squared) value can be used to get an
approximate value of peak-to-peak ripple.
Voltage peak-to-peak ripple, rms can be expressed as follow:
2
VPP-RMS
=
VPP-C2 + VPP-ESR
(4)
Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series
resistance of the output capacitor (RESR).
The RESR is frequency dependent (as well as temperature dependent); make sure the value used for calculations
is at the switching frequency of the part.
Table 2. Suggested Capacitors and Their Suppliers
Case Size
Inch (mm)
Model
4.7 µF for CIN
Type
Vendor
Voltage Rating
C1608X5R0J475
C2012X5R0J475
GRM21BR60J475
JMK212BJ475
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
TDK
TDK
6.3V
6.3V
6.3V
6.3V
0603 (1608)
0805 (2012)
0805 (2012)
0805 (2012)
muRata
Taiyo-Yuden
10 µF for COUT
C1608X5R0J106
C2012X5R0J106
GRM21BR60J106
JMK212BJ106
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
TDK
TDK
6.3V
6.3V
6.3V
6.3V
0603 (1608)
0805 (2012)
0805 (2012)
0805 (2012)
muRata
Taiyo-Yuden
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OUTPUT VOLTAGE SELECTION FOR LM3677-ADJ
The output voltage of the adjustable parts can be programmed through the resistor network connected from VOUT
to FB to GND. The resistor and FB to GND (R2) should be 200 kΩ to keep the current drawn through this
network well below 16 µA quiescent current level (PFM mode) but large enough that it is not susceptible to noise.
If R2 is 200 kΩ, and given the VFB is 0.5V, then the current through the resistor feedback network will be 2.5 µA.
The output voltage of the adjustable parts ranges from 1.2V and 3.3V. The output voltage formula is:
R1
R2
+ 1
VOUT = VFB
VOUT: output voltage (V)
VFB: feedback voltage (0.5V typical)
R1: feedback resistor from VOUT to FB (Ω)
R2: feedback resistor from to FB to GND (Ω)
For the fixed output voltage parts the feedback resistors are internal and R1 is 0Ω.
The bypass capacitors C1 and C2 (labeled C3 and C4 on Evaluation Board) in parallel with the feedback resistors
are chosen for increased stability. Below are the formulas for C1 and C2:
1
C1 =
2 x p x R1 x 70 kHz
1
C2 =
2 x p x R2 x 70 kHz
Table 3. LM3677–ADJ Configurations for Various VOUT (Circuit of Figure 2)
VOUT (V)
1.2
R1(kΩ )
280
R2(kΩ )
200
C1(pF)
8.2
C2(pF)
none
none
none
none
none
none
24
L (µH)
1.0
CIN (µF)
4.7
COUT (µF)
10
10
10
10
10
10
10
10
1.3
320
200
8.2
1.0
4.7
1.5
357
178
6.8
1.0
4.7
1.6
442
200
5.6
1.0
4.7
1.8
464
178
5.6
1.0
4.7
2.5
402
100
6.0
1.0
4.7
2.8
464
100
5.6
1.0
4.7
3.3
562
100
5.6
24
1.0
4.7
DSBGA PACKAGE ASSEMBLY AND USE
Use of the DSBGA package requires specialized board layout, precision mounting and careful re-flow
techniques, as detailed in Application Report 1112, DSBGA Wafer Level Chip Scale Package (SNVA009). Refer
to the section "Surface Mount Technology (SMD) Assembly Considerations". For best results in assembly,
alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style used with
DSBGA package must be the NSMD (non-solder mask defined typ.). This means that the solder-mask opening is
larger than the pad size. This prevents a lip that otherwise forms if the solder-mask and pad overlap, from
holding the device off the surface of the board and interfering with mounting. See Application Note 1112 for
specific instructions how to do this. The 5-bump package used for LM3677 has 300–micron solder balls and
requires 10.82 mils pads for mounting on the circuit board. The trace to each pad should enter the pad with a 90°
entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad should be 7 mil
wide, for a section approximately 7 mil long or longer, as a thermal relief. Then each trace should neck up or
down to its optimal width. The important criteria is symmetry. This ensures the solder bumps on the LM3677 re-
flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads
for bumps A1 and A3, because GND and VIN are typically connected to large copper planes, inadequate thermal
relief can result in late or inadequate re-flow of these bumps.
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SNVS502F –MARCH 2007–REVISED MAY 2013
The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque
cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is
vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed
circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA
devices are sensitive to light, in the red and infrared range, shining on the package’s exposed die edges.
BOARD LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or
instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA
package and board pads. Poor solder joints can result in erratic or degraded performance.
Figure 49. Board Layout Design Rules for the LM3677
Good layout for the LM3677 can be implemented by following a few simple design rules.
•
•
•
Place the LM3677 on 10.82 mil pads. As a thermal relief, connect to each pad with a 7 mil wide,
approximately 7 mil long trace, and then incrementally increase each trace to its optimal width. The important
criterion is symmetry to ensure the solder bumps on the re-flow evenly (see DSBGA Package Assembly and
Use).
Place the LM3677, inductor and filter capacitors close together and make the traces short. The traces
between these components carry relatively high switching currents and act as antennas. Following this rule
reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN and
GND pin.
Arrange the components so that the switching current loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor, through the LM3677 and inductor to the output filter
capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled
up from ground, through the LM3677 by the inductor, to the output filter capacitor and then back through
ground, forming a second current loop. Routing these loops so the current curls in the same direction
prevents magnetic field reversal between the two half-cycles and reduces radiated noise.
•
•
Connect the ground pins of the LM3677, and filter capacitors together using generous component-side copper
fill as a pseudo-ground plane. Then connect this to the ground-plane (if one is used) with several vias. This
reduces ground-plane noise by preventing the switching currents from circulating through the ground plane. It
also reduces ground bounce at the LM3677 by giving it a low-impedance ground connection.
Use wide traces between the power components and for power connections to the DC-DC converter circuit.
This reduces voltage errors caused by resistive losses across the traces
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•
•
Route noise sensitive traces such as the voltage feedback path away from noisy traces between the power
components. The voltage feedback trace must remain close to the LM3677 circuit and should be routed
directly from FB to VOUT at the output capacitor and should be routed opposite to noise components. This
reduces EMI radiated onto the DC-DC converter’s own voltage feedback trace.
Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks
and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced through
distance.
In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board,
arrange the CMOS digital circuitry around it (since this also generates noise), and then place sensitive
preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a
metal pan and power to it is post-regulated to reduce conducted noise, using low-dropout linear regulators.
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SNVS502F –MARCH 2007–REVISED MAY 2013
REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
PACKAGING INFORMATION
Orderable Device
LM3677LEE-1.2/NOPB
LM3677LEE-1.5/NOPB
LM3677LEE-1.8/NOPB
LM3677LEE-1.82/NOPB
LM3677TL-1.2/NOPB
LM3677TL-1.8/NOPB
LM3677TL-1.82/NOPB
LM3677TL-2.5/NOPB
LM3677TL-ADJ/NOPB
LM3677TLX-1.8/NOPB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
USON
USON
NGE
6
6
6
6
5
5
5
5
5
5
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
K
L
N
5
3
Y
3
Z
4
Y
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NGE
NGE
NGE
YZR
YZR
YZR
YZR
YZR
YZR
250
250
250
250
250
250
250
250
3000
Green (RoHS
& no Sb/Br)
CU SN
USON
Green (RoHS
& no Sb/Br)
CU SN
USON
Green (RoHS
& no Sb/Br)
CU SN
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
Green (RoHS
& no Sb/Br)
-30 to 85
-30 to 85
-30 to 85
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3677LEE-1.2/NOPB
LM3677LEE-1.5/NOPB
LM3677LEE-1.8/NOPB
USON
USON
USON
NGE
NGE
NGE
NGE
YZR
YZR
YZR
YZR
YZR
YZR
6
6
6
6
5
5
5
5
5
5
250
250
250
250
250
250
250
250
250
3000
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
12.4
12.4
12.4
12.4
8.4
1.7
1.7
2.2
2.2
2.2
2.2
1.7
1.7
1.7
1.7
1.7
1.7
0.8
0.8
8.0
8.0
8.0
8.0
4.0
4.0
4.0
4.0
4.0
4.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
1.7
0.8
LM3677LEE-1.82/NOPB USON
1.7
0.8
LM3677TL-1.2/NOPB
LM3677TL-1.8/NOPB
DSBGA
DSBGA
1.24
1.24
1.24
1.24
1.24
1.24
0.76
0.76
0.76
0.76
0.76
0.76
8.4
8.0
LM3677TL-1.82/NOPB DSBGA
8.4
8.0
LM3677TL-2.5/NOPB
LM3677TL-ADJ/NOPB
DSBGA
DSBGA
8.4
8.0
8.4
8.0
LM3677TLX-1.8/NOPB DSBGA
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM3677LEE-1.2/NOPB
LM3677LEE-1.5/NOPB
LM3677LEE-1.8/NOPB
LM3677LEE-1.82/NOPB
LM3677TL-1.2/NOPB
LM3677TL-1.8/NOPB
LM3677TL-1.82/NOPB
LM3677TL-2.5/NOPB
LM3677TL-ADJ/NOPB
LM3677TLX-1.8/NOPB
USON
USON
NGE
NGE
NGE
NGE
YZR
YZR
YZR
YZR
YZR
YZR
6
6
6
6
5
5
5
5
5
5
250
250
250
250
250
250
250
250
250
3000
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
USON
USON
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
Pack Materials-Page 2
MECHANICAL DATA
NGE0006A
LEB06A (Rev B)
www.ti.com
MECHANICAL DATA
YZR0005xxx
D
0.600±0.075
E
TLA05XXX (Rev C)
D: Max = 1.514 mm, Min =1.454 mm
E: Max = 1.133 mm, Min =1.073 mm
4215043/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
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