LM3686 [TI]

具有集成后置线性稳压器系统和低噪声线性稳压器的降压直流/直流转换器;


型号：	LM3686
厂家：	TEXAS INSTRUMENTS
描述：	具有集成后置线性稳压器系统和低噪声线性稳压器的降压直流/直流转换器转换器稳压器
文件：	总29页 (文件大小：2325K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LM3686

SNVS520F –AUGUST 2008–REVISED NOVEMBER 2016

LM3686 Step-Down DC-DC Converter With Integrated Post Linear Regulators System And

Low-Noise Linear Regulator

1 Features

2 Applications

•

DC-DC Regulator

•

Mobile TVs, Hand-Held Radios

Personal Digital Assistants, Palm-Top PCs

Portable Instruments and Personal Clients

Battery-Powered Devices

–

V_{OUT_DCDC}= 1.2 V to 2.5 V

600-mA Maximum I_LOAD

3-MHz Typical PWM Fixed Switching

Frequency

3 Description

–

Automatic PFM/PWM Mode Switching

Internal Synchronous Rectification

Internal Soft Start

The LM3686 is a step-down DC-DC converter with a

very low-dropout linear regulator and a low-noise

linear regulator optimized for powering ultra-low

voltage circuits. It provides three outputs with

combined load current up to 900 mA over an input

voltage range from 2.7 V to 5.5 V.

•

Dual-Rail Linear Regulator: LILO

–

Load Transients < 50-mV Peak Typical

Line Transients < 1-mV Peak Typical

V_{OUT_LILO}= 0.7 V to 2 V

The device offers superior features and performance

for many applications. Automatic intelligent switching

between PWM low-noise and PFM low-current mode

offers improved system control. During full-power

operation, a fixed-frequency 3 MHz (typical), PWM

mode drives loads from approximately 70 mA to 600

mA maximum. Hysteretic PFM mode extends the

battery life through reduction of the quiescent current

to 28 μA (typical) at light load and system standby.

Internal synchronous rectification provides high

efficiency.

70-µA Typical I_Qand 300-mA Maximum I_LOAD

Linear Regulator: LDO

–

Load Transients < 80-mV Peak Typical

Line Transients < 1-mV Peak Typical

V_{OUT_LDO}= 1.5 V to 3.3 V

50-µA Typical I_Qand 350-mA Maximum I_LOAD

Combined Global Features

–

V_BATT≥ Maximum (V_{OUT_LILO}+ 1.5 V, 2.7 V)

Device Information⁽¹⁾

Operates From a Single Li-Ion Cell or 3-Cell

NiMH/NiCd Batteries

PART NUMBER

PACKAGE

BODY SIZE (NOM)

LM3686

DSBGA (12)

2.435 mm × 1.687 mm

–

100-µA I_Qand 900-mA Maximum I_LOAD

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Application

BATT

2.7 V to 5.5 V

4.7 mF, 0603

EN_DCDC

PGND

LM3686

3 MHz

DC-DC

1 mH

1.8 V

FB_DCDC

IN_LILO

10 mF

0603

PGND

LILO

EN_LILO

EN_LDO

PGND

Dual Rail

LILO

350 mA

0.7 V to 2 V

2.2 mF,

0402

350 mA

QGND

VIN_LDO

LDO

1.2 V to 3.3 V

Linear Regulator

300 mA

1 mF,

0402

1 mF, 0402

QGND

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM3686

SNVS520F –AUGUST 2008–REVISED NOVEMBER 2016

www.ti.com

Table of Contents

8.3 Feature Description................................................. 12

8.4 Device Functional Modes........................................ 16

Application and Implementation ........................ 17

9.1 Application Information............................................ 17

9.2 Typical Application ................................................. 17

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description (Continued)........................................ 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics: Linear Regulator - LILO... 5

7.6 Electrical Characteristics: Linear Regulator - LDO ... 6

7.7 Electrical Characteristics: DC-DC Converter ............ 7

10 Power Supply Recommendations ..................... 22

11 Layout................................................................... 22

11.1 Layout Guidelines ................................................ 22

11.2 Layout Example .................................................... 23

11.3 DSBGA Package Assembly and Use ................... 23

12 Device and Documentation Support ................. 24

12.1 Device Support...................................................... 24

12.2 Related Documentation ....................................... 24

12.3 Receiving Notification of Documentation Updates 24

12.4 Community Resources.......................................... 24

12.5 Trademarks........................................................... 24

12.6 Electrostatic Discharge Caution............................ 24

12.7 Glossary................................................................ 24

7.8 Electrical Characteristics: Global Parameters (DCDC,

LILO, and LDO).......................................................... 8

7.9 Typical Characteristics.............................................. 9

Detailed Description ............................................ 11

8.1 Overview ................................................................. 11

8.2 Functional Block Diagram ....................................... 12

13 Mechanical, Packaging, and Orderable

Information ........................................................... 24

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (May 2013) to Revision F

Page

•

Deleted "one integrated" ........................................................................................................................................................ 1

Deleted "from a single Li-Ion cell or 3-cell NiMH/NiCd batteries." ......................................................................................... 1

Added Device Information and ESD Ratings tables, Pin Configuration and Functions, Feature Description, Device

Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and

Documentation Support, and Mechanical, Packaging, and Orderable Information sections ................................................. 1

•

Combine some bullet items and delete parentheticals from Features to get more space .................................................... 1

Deleted out-of-date Device Comparison table ...................................................................................................................... 3

Deleted lead temperature from Abs Max per TI data sheet standard ................................................................................... 4

Changed R_θJAfrom "120°C/W" to "80.9°C/W"; added additional thermal values................................................................... 4

Changed "drains conductor" to "drains inductor" on Figure 13 ............................................................................................ 14

Changes from Revision D (April 2013) to Revision E

Page

•

Changed layout of National Semiconductor data sheet to TI format.................................................................................... 22

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SNVS520F –AUGUST 2008–REVISED NOVEMBER 2016

5 Description (Continued)

Three enable (EN_x) pins allow the separate operation of either the DC-DC, post-regulation linear regulator, or

the linear regulator alone. If the DC-DC is not enabled during start-up of the post-regulation linear regulator, a

parallel small-pass transistor supplies the linear regulator from V_BATTwith maximal 50 mA. In the combined

operation where both enables are raised together, the small-pass transistor is deactivated and the big pass

transistor provides 350 mA output current. In shutdown mode (EN_x pins pulled low), the device turns off and

reduces battery consumption to 2.5 μA (typical).

The LM3686 is available in a 12-pin DSBGA package. A high-switching frequency of 3 MHz (typical) allows the

use of a few tiny surface-mount components. Only six external surface-mount components, an inductor and five

ceramic capacitors, are required to establish a 15.66 mm²total solution size.

6 Pin Configuration and Functions

YZR Package

12-Pin DSBGA

Top View

YZR Package

12-Pin DSBGA

Bottom View

Pin Functions

TYPE

DESCRIPTION

NO.

NAME

PGND

Ground

Analog

Input

Power ground pin

Switching node connection to the internal PFET switch and NFET synchronous rectifier.

Feedback analog input for the DC-DC converter. Connect to the output filter capacitor.

Power supply input for switcher. Connect to the input filter capacitor.

FB_DCDC

V_BATT

Power

Enable input for the linear regulator. The linear regulator is in shutdown mode if voltage at

this pin is

EN_LILO

Input

< 0.4 V and enabled if > 1.1 V. Do not leave this pin floating.

Enable input for the DC-DC converter. The DC-DC converter is in shutdown mode if voltage

at this pin is < 0.4 V and enabled if > 1.1 V. Do not leave this pin floating.

EN_DCDC

V_{IN_LDO}

Input

Input power to LDO — must tie to V_BATTat all times.

Enable input for the linear regulator. The linear regulator is in shutdown mode if voltage at

this pin is

EN_LDO

Input

< 0.4 V and enabled if > 1.1 V. Do not leave this pin floating.

QGND

V_{OUT_LDO}

V_{OUT_LILO}

V_{IN_LILO}

Ground

Output

Input

Quiet GND pin for LDO and reference circuit

Voltage output of the linear regulator

Voltage output of the low input linear regulator

Input power to LILO (V_{IN_LILO}) connects to output of DCDC or standalone.

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SNVS520F –AUGUST 2008–REVISED NOVEMBER 2016

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^(1)(2)(3)(4)

MIN

MAX

UNIT

V_BATTpin to GND and QGND

–0.2

(GND – 0.2 V) to (V_BATT+0.2 V) with 6 V

maximum

EN_x pins, FB_DC-DC pin, SW pin

Continuous power dissipation⁽⁵⁾

Junction temperature, T_J-MAX

Storage temperature, T_stg

Internally limited

150

°C

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pin.

(3) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(4) For detailed soldering specifications and information, see AN-1112 DSBGA Wafer Level Chip Scale Package.

(5) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 150°C (typical) and

disengages at T_J= 130°C (typical).

7.2 ESD Ratings

VALUE

±2000

±200

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

5.5

UNIT

Input voltage, V_BATT(DC-DC and LDO)

Junction temperature, T_J

2.7

–40

125

°C

(1)

Ambient temperature, T_A

(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (R_θJA

× _PD-MAX).

7.4 Thermal Information

LM3686

THERMAL METRIC⁽¹⁾

YZR (DSBGA)

12 PINS

80.9

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

0.4

16.8

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.2

ψ_JB

16.9

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

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SNVS520F –AUGUST 2008–REVISED NOVEMBER 2016

7.5 Electrical Characteristics: Linear Regulator - LILO

Unless otherwise noted, limits apply for T_A= 25°C, specifications apply to the closed-loop typical application circuits (linear

regulator) with V_{IN_LDO}= V_BATT= 3.6 V⁽¹⁾, V_{IN_LILO}= V_{OUT_DCDC(NOM)}, V_EN(All) = V_BATT, C_{IN_DC}= 4.7 μF, C_{OUT_LILO}= 2.2 μF,

C_{IN_LDO}= 1 μF , C_{OUT_LDO}= 1 μF, C_{OUT_DC}= C_{IN_LILO}= 10 μF.^(2)(3)(4)(5)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EN_DC-DC = EN_LILO = ON – LARGE NMOS

I_{OUT_LILO}= 1 mA to 350 mA,

V_{IN_LILO}= V_{OUT_DCDC}

V_BATT= 3.6 V

1.2

ΔV_{OUT_LILO}

V_{OUT_LILO}

Output voltage accuracy,

V_OUT-LILO

I_{OUT_LILO}= 1 mA to 350 mA,

V_{IN_LILO}= V_{OUT_DCDC}

1.176

1.224

V_BATT= 3.6 V, –40°C ≤ T_A= T_J≤ 85°C

I_{OUT_LILO}= 1 mA to 350 mA,

V_{IN_LILO}= V_{OUT_DCDC}

V_BATT= 3.6 V

ΔV_{OUT_LILO}

ΔmA

Load regulation⁽⁶⁾

μV/mA

I_{OUT_LILO}= 1 mA to 350 mA,

V_{IN_LILO}= V_{OUT_DCDC}

V_BATT= 3.6 V, –40°C ≤ T_A= T_J≤ 85°C

V_BATT= V_{OUT_LILO}+ 1.5 V (V_{IN_LILO}

disconnected from V_{OUT_DCDC}

I_OUT= 350 mA

)

V_DROP

Dropout voltage⁽⁷⁾

V_BATT= V_{OUT_LILO}+ 1.5 V (V_{IN_LILO}

disconnected from V_{OUT_DCDC}

I_OUT= 350 mA, –40°C ≤ T_A= T_J≤ 85°C

)

V_BATT= V_{IN_LILO}= 3.6 V

I_{Q_VIN_LILO}

Quiescent current

µA

V_BATT= V_{IN_LILO}= 3.6 V

–40°C ≤ T_A= T_J≤ 85°C

V_OUT= GND (V_{OUT_LILO}= 0)

–40°C ≤ T_A= T_J≤ 85°C

I_{SC_LILO}

Short-circuit current limit

400

EN_DC-DC = OFF, EN_LILO = ON – SMALL NMOS

ΔV_{OUT_LILO}

V_{OUT_LILO}

Output voltage accuracy

V_{OUT_LILO}

I_OUT= 1 mA to 50 mA

–40°C ≤ T_A= T_J≤ 85°C

1.176

1.224

1.5

V_{IN_LILO}= (V_{OUT_LILO}+ 0.3 V) to 5.5 V

0.4

ΔV_{OUT_LILO}

ΔV_BATT

Line regulation (small NMOS)⁽⁸⁾

mV/V

V_{IN_LILO}= (V_{OUT_LILO}+ 0.3 V) to 5.5 V

–40°C ≤ T_A= T_J≤ 85°C

V_{OUT_LILO}= GND, –40°C ≤ T_A= T_J≤

85°C

I_{SC_LILO}

Short-circuit current

Start-up time

T_STARTUP

EN to 0.95 V_OUT

µs

(1) V_{IN_LDO}must be ON at all time for biasing internal reference circuits.

(2) All voltages are with respect to the potential at the GND pin.

(3) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers represent the

most likely norm. Unless otherwise specified, conditions for typical specifications are: V_BATT= 3.6 V and T_A= 25°C.

(4) The parameters in the electrical characteristic table are tested at V_BATT= 3.6 V unless otherwise specified. For performance over the

input voltage range refer to Typical Characteristics.

(5) The input voltage ranges recommended for ideal application performance for the specified output voltages are:

V_BATT= 2.7 V to 5.5 V for 1 V ≤ V_{OUT_DCDC}< 1.8 V

V_BATT= (V_{OUT_DCDC}+ 1 V) to 5.5 V for 1.8 V ≤ V_{OUT_DCDC}< 3.6 V.

(6) To calculate the output voltage from the load regulation specified, use the following equation:

ΔV_OUT= load regulation (%/mA) × nominal V_OUT(V) × ΔI_OUT(mA).

(7) Dropout voltage is defined as the input to output voltage differential at which the output voltage falls to 100 mV below the nominal output

voltage.

(8) To calculate the output voltage from the line regulation specified, use the following equation:

ΔV_OUT= line regulation (%/V) × nominal V_OUT(V) × ΔV_IN(V).

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Electrical Characteristics: Linear Regulator - LILO (continued)

Unless otherwise noted, limits apply for T_A= 25°C, specifications apply to the closed-loop typical application circuits (linear

regulator) with V_{IN_LDO}= V_BATT= 3.6 V⁽¹⁾, V_{IN_LILO}= V_{OUT_DCDC(NOM)}, V_EN(All) = V_BATT, C_{IN_DC}= 4.7 μF, C_{OUT_LILO}= 2.2 μF,

C_{IN_LDO}= 1 μF , C_{OUT_LDO}= 1 μF, C_{OUT_DC}= C_{IN_LILO}= 10 μF.^(2)(3)(4)(5)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SYSTEM CHARACTERISTICS⁽⁹⁾

Signal to V_BATT= 3.6 V, V_{IN_LILO}= 1.8 V,

I_OUT= 200 mA, ƒ = 100 Hz

PSRR

Power supply rejection ratio

Signal to V_{IN_LILO}= 1.8 V,

I_OUT= 200 mA, ƒ = 100 kHz

BW = 10 Hz to 100 kHz, V_{IN_LILO}= 1.8 V,

I_OUT= 200 mA, V_{IN_LDO}= 3.6 V

e_{N_LILO}

Output noise voltage

166

µV_RMS

Dynamic load transient

response

Pulsed load 1 mA to 350 mA

di/dt = 350 mA / 1 µs

ΔV_{OUT_LILO}

±30⁽¹⁰⁾

V_BATT= 3.1 V to 3.7 V

V_{IN_LILO}= V_{OUT_DCDC}

tr, tf = 10 µs, I_OUT= 200 mA

Dynamic load transient

response on V_BATT

ΔV_{IN_LILO}

±15⁽¹⁰⁾

(9) Specified by design. Not production tested.

(10) For line and load transient specifications, the + symbol represents an overshoot in the output voltage and the – symbol represents an

undershoot in the output voltage. The first value signifies overshoot or undershoot at the rising edge and the second value signifies the

overshoot or undershoot at the falling edge.

7.6 Electrical Characteristics: Linear Regulator - LDO

Unless otherwise noted, limits apply for T_A= 25°C.^(1)(2)(3)(4)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{IN_LDO}

LDO input voltage range

2.7

5.5

V_IN= 3.6 V, I_{OUT_LDO}= 1 mA and 300 mA

2.8

V_IN= 3.6 V, I_{OUT_LDO}= 1 mA and 300 mA

–40°C ≤ T_A= T_J≤ 85°C

2.744

2.94

2.856

3.06

ΔV_{OUT_LDO}Output voltage accuracy, V_OUT-

/ V_{OUT_LDO}

LDO

V_IN= 3.6 V, I_{OUT_LDO}= 1 mA and 300 mA

–40°C ≤ T_A= T_J≤ 85°C

ΔV_{OUT_LDO}

Load regulation⁽⁵⁾

/ ΔmA

I_{OUT_LDO}= 1 mA and 300 mA

μV/mA

ΔV_{OUT_LDO}

/ ΔV_BATT

Line regulation⁽⁶⁾

V_{IN_LDO}= (V_{OUT_LDO(NOM)}+ 0.3 V) to 5.5 V

0.2

mV/V

I_OUT= 300 mA

120

V_DROP

Dropout voltage⁽⁷⁾

I_OUT= 300 mA, –40°C ≤ T_A= T_J≤ 85°C

V_en= 0.95 V, I_OUT= 0 mA

200

I_Q

Quiescent current

µA

V_en= 0.95 V, I_OUT= 0 mA

–40°C ≤ T_A= T_J≤ 85°C

I_{SC_LDO}

Short-circuit current limit

V_OUT= GND, –40°C ≤ T_A= T_J≤ 85°C

350

(1) All voltages are with respect to the potential at the GND pin.

(2) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers represent the

most likely norm. Unless otherwise specified, conditions for typical specifications are: V_BATT= 3.6 V and T_A= 25°C.

(3) The parameters in the Electrical Characteristics tables are tested at V_BATT= 3.6 V unless otherwise specified. For performance over the

input voltage range refer to Typical Characteristics.

(4) The input voltage ranges recommended for ideal application performance for the specified output voltages are

V_BATT= 2.7 V to 5.5 V for 1 V ≤ V_{OUT_DCDC}< 1.8 V

V_BATT= (V_{OUT_DCDC}+ 1 V) to 5.5 V for 1.8 V ≤ V_{OUT_DCDC}< 3.6 V

(5) To calculate the output voltage from the load regulation specified, use the following equation:

ΔV_OUT= load regulation (%/mA) × nominal V_OUT(V) × ΔI_OUT(mA)

(6) To calculate the output voltage from the line regulation specified, use the following equation:

ΔV_OUT= line regulation (%/V) × nominal V_OUT(V) × ΔV_IN(V)

(7) Dropout voltage is defined as the input to output voltage differential at which the output voltage falls to 100 mV below the nominal output

voltage.

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SNVS520F –AUGUST 2008–REVISED NOVEMBER 2016

Electrical Characteristics: Linear Regulator - LDO (continued)

Unless otherwise noted, limits apply for T_A= 25°C.^(1)(2)(3)(4)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SYSTEM CHARACTERISTICS⁽⁸⁾

EN_DC = EN_LILO = GND

I_OUT= 200 mA, ƒ = 1 kHz

PSRR

Power supply rejection ratio

Signal to V_{IN_LDO}= 3.6 V,

I_OUT= 200 mA, ƒ = 10 kHz

BW = 10 Hz to 100 kHz, V_{IN_LDO}= 3.6 V,

I_OUT= 200 mA

e_{N_LDO}

Output noise voltage

6.7

µV_RMS

V_{IN_LDO}= 3.8 V to 4.4 V

tr, tf = 30 µs, I_OUT= 1 mA

ΔV_{IN_LDO}

ΔV_{IN_LILO}

Dynamic line transient response

±2⁽⁹⁾

±30⁽⁹⁾

Dynamic load transient

response on V_BATT

Pulsed load 1 mA and 300 mA

tr, tf = 10 µs

(8) Specified by design. Not production tested.

(9) For line and load transient specifications, the + symbol represents an overshoot in the output voltage and the – symbol represents an

undershoot in the output voltage. The first value signifies overshoot or undershoot at the rising edge and the second value signifies the

overshoot or undershoot at the falling edge.

7.7 Electrical Characteristics: DC-DC Converter

Unless otherwise noted, limits apply for T_A= 25°C.^(1)(2)(3)(4)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Feedback voltage

accuracy

PWM mode⁽⁵⁾

PWM mode⁽⁵⁾, –40°C ≤ T_A= T_J≤ 85°C

1.8

V_{FB_DCDC}

1.746

1.836

Internal reference

voltage

V_REF

0.5

Pin-pin resistance for

PFET

V_BATT= 3.6 V

I_SW= 100 mA

R_DSON(P)

R_DSON(N)

350

450

250

mΩ

Pin-pin resistance for

NFET

V_BATT= 3.6 V

I_SW= 100 mA

150

Quiescent current for

auto mode

No load, device is not switching, FB = HIGH

I_{Q_AUTO}

µA

No load, device is not switching, FB = HIGH

–40°C ≤ T_A= T_J≤ 85°C

Switch peak current

limit

Open loop

1.22

I_LIM

Open loop, –40°C ≤ T_A= T_J≤ 85°C

PWM mode

1.035

2.4

1.375

3.4

Internal oscillator

frequency

ƒ_OSC

MHz

PWM mode, –40°C ≤ T_A= T_J≤ 85°C

(1) All voltages are with respect to the potential at the GND pin.

(2) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers represent the

most likely norm. Unless otherwise specified, conditions for typical specifications are: V_BATT= 3.6 V and T_A= 25°C.

(3) The parameters in the electrical characteristic table are tested at V_BATT= 3.6 V unless otherwise specified. For performance over the

input voltage range refer to Typical Characteristics.

(4) The input voltage ranges recommended for ideal application performance for the specified output voltages are:

V_BATT= 2.7 V to 5.5 V for 1 V ≤ V_{OUT_DCDC}< 1.8 V

V_BATT= (V_{OUT_DCDC}+ 1 V) to 5.5 V for 1.8 V ≤ V_{OUT_DCDC}< 3.6 V

(5) Electrical Characteristics tables reflects open loop data (FB = 0 V and current drawn from SW pin ramped up until cycle by cycle current

limit is activated). Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current

until output voltage drops by 10%.

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7.8 Electrical Characteristics: Global Parameters (DCDC, LILO, and LDO)

Unless otherwise noted, limits apply for T_A= 25°C.^(1)(2)(3)(4)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Full power mode

I_{OUT_DCDC}= I_{OUT_LILO}= I_{OUT_LDO}= 0 mA, DC-DC

is not switching (FB_DCDC forced higher than

100

V_{OUT_DCDC}

)

V_en= 1.1V,

Quiescent current into

V_BATT

I_{Q_VBATT}

µA

Full power mode

I_{OUT_DCDC}= I_{OUT_LILO}= I_{OUT_LDO}= 0 mA, DC-DC

is not switching (FB_DCDC forced higher than

130

V_{OUT_DCDC}

)

V_en= 1.1V,

–40°C ≤ T_A= T_J≤ 85°C

Shutdown current into

V_BATT

V_{EN_DCDC}= V_{EN_LILO}= V_{EN_LDO}= 0 V

2.5

.01

I_{Q_GLOBAL}

µA

V_{EN_DCDC}= V_{EN_LILO}= V_{EN_LDO}= 0

–40°C ≤ T_A= T_J≤ 85°C

ENABLE PINS (EN_DCDC, EN_LILO, EN_LDO)

I_EN

Enable pin input

current

All EN = 0 V

All EN = 0 V, –40°C ≤ T_A= T_J≤ 85°C

–40°C ≤ T_A= T_J≤ 85°C

V_IH

V_IL

Logic high input

Logic low input

1.1

0.4

(1) All voltages are with respect to the potential at the GND pin.

(2) Mininum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers represent the

most likely norm. Unless otherwise specified, conditions for typical specifications are: V_BATT= 3.6 V and T_A= 25°C.

(3) The parameters in the Electrical Characteristics tables are tested at V_BATT= 3.6 V unless otherwise specified. For performance over the

input voltage range refer to Typical Characteristics.

(4) The input voltage ranges recommended for ideal application performance for the specified output voltages are:

V_BATT= 2.7 V to 5.5 V for 1 V ≤ V_{OUT_DCDC}< 1.8 V

V_BATT= (V_{OUT_DCDC}+ 1 V) to 5.5 V for 1.8 V ≤ V_{OUT_DCDC}< 3.6 V

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7.9 Typical Characteristics

Unless otherwise specified, typical application (post regulation), V_BATT= 3.6 V, T_A= 25°C, enable pins tied to V_BATT, V_{OUT_DCDC}

= 1.8 V, V_{OUT_LILO}= 1.2 V, V_{OUT_LDO}= 2.8 V.

1.830

1.825

1.203

1.202

= 3.6V

1.201

1.200

1.199

1.198

1.197

1.196

1.195

1.194

1.193

= 2.9V

1.820

1.815

1.8. 10

1.8. 05

1.8. 00

= 2.9V

= 4.5V

= 3.6V

150

= 4.5V

100

200

300

400

500

600

100

200

250

300

OUTPUT CURRENT DC-DC (mA)

OUTPUT CURRENT (mA)

Figure 1. V_{OUT_DCDC}vs I_{OUT_DCDC}

Figure 2. V_{OUT_LILO}vs I_{OUT_LILO}

-10

-20

-30

-40

-50

-60

-70

= 200 mA

LILO

-80

100

10k

100k 1000k 10000k

FREQUENCY (Hz)

LILO – V_{IN_LILO}= 3.6 V

Figure 4. PSRR vs Frequency

Figure 3. Efficiency DC-DC vs Output Current LILO and LDO

Disabled

-20

-40

-60

= 200 mA

-80

-100

-120

LDO

100

10k

100k 1000k 10000k

FREQUENCY (Hz)

LDO – V_{IN_LDO}= 3.6 V

Figure 6. Noise vs Frequency

Figure 5. PSRR vs Frequency

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Typical Characteristics (continued)

Unless otherwise specified, typical application (post regulation), V_BATT= 3.6 V, T_A= 25°C, enable pins tied to V_BATT, V_{OUT_DCDC}

= 1.8 V, V_{OUT_LILO}= 1.2 V, V_{OUT_LDO}= 2.8 V.

Open Loop

Figure 7. Switching Frequency vs Temperature

Figure 8. Current Limit vs Temperature

All Three Enables Tied

Together

Figure 9. R_DSONvs Temperature

Figure 10. Start-up

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8 Detailed Description

8.1 Overview

The LM3686 incorporates a high efficiency synchronous switching step-down DC-DC converter, a very low

dropout linear regulator (LILO), and ultra-low-noise linear regulator.

The DC-DC converter delivers a constant voltage from a single Li- Ion battery and input voltage rails from 2.7 V

to 5.5 V to portable devices such as cell phones and PDAs. Using a voltage mode architecture with synchronous

rectification, it has the ability to deliver up to 600-mA load current (when not powering the LILO) depending on

the input voltage, output voltage, ambient temperature, and the inductor chosen.

The linear regulator delivers a constant voltage biased from V_{IN_LILO}power input typically the output voltage of

the DC-DC converter is used (post regulation) with a maximum load current of 350 mA.

The other linear regulator delivers a constant voltage biased from V_{IN_LDO}power input with a maximum load

current of 300 mA.

Three enable pins allow the independent control of the three outputs. Shutdown mode turns off the device,

offering the lowest current consumption (I_SHUTDOWN= 2.5 µA typical).

Besides the shutdown feature, there are two more modes of operation for the DC-DC converter, depending on

the current required:

•

Pulse width modulation (PWM) and

Pulse frequency modulation (PFM).

The device operates in PWM mode at load current of approximately 80 mA or higher. Lighter load current cause

the device to automatically switch into PFM for reduced current consumption (I_{Q_VBATT}= 28 µA typical) and a

longer battery life.

Additional features include soft-start, start-up mode of the linear regulator, undervoltage protection, current

overload protection, and overtemperature protection.

An internal reference generates a 1.8-V biasing an internal resistive divider to create a reference voltage range

from 0.7 V to 1.8 V (in 50-mV steps) for the LILO and the 0.5-V reference used for the DC-DC converter. The

ultra-low-noise linear regulator also has internal reference that generates a 1.8-V biasing for a internal resistor

divider, thus creating a reference voltage ranging from 1.5 V to 3.3 V.

The undervoltage lockout feature enables the device to start-up once V_BATThas reached 2.65 V typically and

turns the device off if V_BATTdrops below 2.41 V typically.

NOTE

Post regulation: When the DC-DC converter is switched off while the linear regulator is still

enabled, the LILO can still support up to 50 mA. The linear regulator LILO is turned on via

a small NMOS device supplied by V_{IN_LDO}The maximum current is 50 mA when this

small NMOS is ON. If higher current > 50 mA is desired the following condition must be

met:

•

EN_DC = HIGH

When the condition is met, the LILO transitions to the large NMOS and can support up to

350 mA.

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8.2 Functional Block Diagram

IN_LDO IN_ BATT

BATT

IN_LILO

Driver

LDO

LILO

Digital

REF

Analog

buck

(error amplifier)

OUT_LILO

OUT_LDO

PGND

(Power ground)

Buck system

QGND

(Analog ground)

Always connect V_{IN_LDO}to V_BATT

8.3 Feature Description

8.3.1 DC-DC Converter Operation

During the first part of each switching cycle, the control block in the LM3686 turns on the internal PFET switch.

This allows current to flow from the input V_BATTthrough the switch pin SW and the inductor to the output filter

capacitor and load. The inductor limits the current to a ramp with a slope of (V_BATT– V_{OUT_DCDC}) / L, by storing

energy in the magnetic field.

During the second part of each cycle, the controller turns the PFET switch off, blocking current flow from the

input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the

NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of (– V_{OUT_DCDC}

/ L).

The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage

across the load.

The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the

load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and

synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The

output voltage is equal to the average voltage at the SW pin.

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Feature Description (continued)

8.3.1.1 PWM Operation

During pulse width modulation (PWM) operation the converter operates as a voltage-mode controller with input

voltage feed forward. This allows the converter to achieve good load and line regulation. The DC gain of the

power stage is proportional to the input voltage. To eliminate this dependency, feed forward inversely

proportional to the input voltage is introduced.

While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating

the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned

on and the inductor current ramps up until the duty-cycle comparator trips and the control logic turns off the

switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is

exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by

the clock turning off the NFET and turning on the PFET.

2V/DIV

= 3.6V

= 1.8V

BATT

= 500 mA

OUT

200 mA/DIV

2 mV/DIV

AC Coupled

OUT

TIME (330 ns/DIV)

Figure 11. Typical PWM Operation

8.3.1.2 PFM Operation

At very light load, the DC-DC converter enters PFM mode and operates with reduced switching frequency and

supply current to maintain high efficiency. The part automatically transitions into PFM mode when either of two

conditions occurs for a duration of 32 or more clock cycles:

1. The NFET current reaches zero.

2. The peak PMOS switch current drops below the I_MODElevel, (typically I_MODE< 75 mA + V_BATT/ 55 Ω ).

= 3.6V

BATT

= 20 mA

= 1.8V

OUT

TIME (1 µs/DIV)

Figure 12. Typical PFM Operation

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Feature Description (continued)

During PFM operation, the DC-DC converter positions the output voltage slightly higher than the nominal output

voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to

heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the

output FETs such that the output voltage ramps between approximately 0.2% and approximately 1.8% above the

nominal PWM output voltage. If the output voltage is below the high PFM comparator threshold, the PMOS

power switch is turned on. It remains on until the output voltage reaches the high PFM threshold or the peak

current exceeds the I_PFMlevel set for PFM mode. The typical peak current in PFM mode is: I_PFM= 112 mA +

V_BATT/ 20 Ω.

Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps

to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output

voltage is below the high PFM comparator threshold (see Figure 13), the PMOS switch is again turned on and

the cycle is repeated until the output reaches the desired level. Once the output reaches the high PFM threshold,

the NMOS switch is turned on briefly to ramp the inductor current to zero. Both output switches are then turned

off, and the device enters an extremely low power mode. Quiescent supply current during this sleep mode is 28

µA (typical), which allows the part to achieve high efficiency under extremely light load conditions.

If the load current should increase during PFM mode (see Figure 13) causing the output voltage to fall below the

low2 PFM threshold, the part automatically transitions into fixed-frequency PWM mode.

When V_BATT= 2.7 V the device transitions from PWM to PFM mode at approximately 35 mA output current and

from PFM mode to PWM mode at approximately 95 mA. When V_BATT= 3.6 V, PWM-to-PFM transition happens at

approximately 42 mA and PFM-to-PWM transition happens at approximately 115 mA. When V_BATT= 4.5 V,

PWM-to-PFM transition happens at approximately 60 mA and PFM-to-PWM transition happens at approximately

135 mA.

High PFM Threshold

PFM Mode at Light Load

~1.017*Vout

Load current

increases

Low1 PFM Threshold

~1.006*Vout

Current load

increases,

draws Vout

towards

Low2 PFM

Threshold

High PFM

Nfet on

drains

inductor

current

until

I inductor = 0

Low PFM

Threshold,

turn on

Pfet on

until

Voltage

Threshold

reached,

go into

Ipfm limit

reached

PFET

Low2 PFM Threshold

Vout

sleep mode

PWM Mode at

Moderate to Heavy

Loads

Low2 PFM Threshold,

switch back to PWMmode

Figure 13. Operation In PFM Mode and Transfer to PWM Mode

8.3.1.3 Internal Synchronous Rectification

While in PWM mode, the DC-DC converter uses an internal NFET as a synchronous rectifier to reduce rectifier

forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in

efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier

diode.

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Feature Description (continued)

8.3.1.4 Current Limiting

A current limit feature allows the LM3686 to protect itself and external components during overload conditions.

PWM mode implements current limiting using an internal comparator that trips at 1220 mA (typical). If the output

is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer

duration until the inductor current falls below a low threshold. This allows the inductor current more time to

decay, thereby preventing runaway.

8.3.1.5 Soft Start

The DC-DC converter has a soft-start circuit that limits in-rush current during start-up. During start-up the switch-

current limit is increased in steps. Soft start is activated only if EN_DCDC goes from logic low to logic high after

V_BATTreaches 2.7 V. Soft start is implemented by increasing switch current limit in steps of 200 mA, 400 mA, 600

mA and 1220 mA (typical switch current limit). The start-up time thereby depends on the output capacitor and

load current demanded at start-up. Typical start-up times with a 10 µF output capacitor and 200 mA load is 350

µs and with 1 mA load is 200 µs.

8.3.2 Linear Regulator Operation (LILO)

In a typical post-regulation application the power input voltage V_{IN_LILO}for the linear regulator is generated by the

DC-DC converter. Using a buck converter to reduce the battery voltage to a lower input voltage for the linear

regulator translates to higher efficiency and lower power dissipation.

It is also possible to operate the linear regulator independent of the DC-DC converter output voltage either from

V_{IN_LDO/}V_BATTor from a different source (V_{IN_LILO}) – (I_{OUT_LILO}= 50 mA maximum in independent mode).

An input capacitor of 1 µF at V_{IN_LILO}is needed to be added if no other filter or bypass capacitor is present in the

V_{IN_LILO}path.

8.3.2.1 Start-up Mode

If V_{IN_LILO}> V_{OUT_LILO(NOM)}+ 250 mV the main regulator is active, offering a rated output current of 350 mA and

supplied by V_{IN_LILO}(large NMOS).

If V_{IN_LILO}< V_{OUT_LILO(NOM)}+ 150 mV the start-up LILO is active, providing a reduced rated output current of 50

mA typical, supplied by V_BATT(small NMOS).

Figure 14. Start-Up Sequence, V_{EN_DCDC}= V_{EN_LILO}= V _{EN_LDO}= V_BATT

8.3.3 Current Limiting (LDO and LILO)

The LM3686 incorporates also a current limit for the LDO and LILO to protect itself and external components

during overload conditions at their outputs. In the event of a peak overcurrent condition at V_{OUT_LDO}or V_{OUT_LILO}

the output current through the NFET pass device is limited.

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8.4 Device Functional Modes

Table 1. Enable Combinations

EN_DCDC

EN_LILO

EN_LDO

FUNCTION

No outputs

Linear regulator enabled only (EN_LDO), supply from V_{IN_LDO}, I_{OUT_MAX}= 300 mA

Linear regulator enabled only LILO supplies from V_{IN_LDO}

I_{OUT_MAX}= 50 mA, V_{IN_LDO}> = V_{OUT_LILO}

DC-DC converter enabled only

Linear regulator and DC-DC enabled

1. V_{IN_LILO}< V_{OUT_LILO}+ 150 mV (typical), the small NMOS device is active (I_MAX= 50

mA) and supplied by V_{IN_LDO}

2. If V_{IN_LILO}> V_{OUT_LILO}+ 250 mV (typical), the large NMOS device is active (I_MAX

350 mA) and supplied by V_{IN_LILO}. Maxium current of DC-DC when EN_LILO = High

is 250 mA⁽¹⁾⁽²⁾

DC-DC converter and linear regulator active.

Linear regulator starts after DC-DC converter.

(1) The LILO is turned on via a small NMOS device supplied by V_{IN_LDO .}The maximum current is 50 mA when this small NMOS is ON. If

higher current > 50 mA is desired this condition must be done: EN_DC = HIGH .

(2) When the switcher is enabled, a transition occurs from the small NMOS to a larger NMOS. The transition occurs when V_{IN_LILO}

V_{OUT_LILO}+ 250 mV. If V_{IN_LILO}< V_{OUT_LILO}+ 150 mV, the LILO switches back to small NMOS (switcher EN = low).

1.8V

-DCDC

OUT

1.2V

OUT

-LILO

LARGE NMOS

-LILO > 50 mA

OUT

FET OF LILO (SMALL NMOS)

I -LILO 7 50 mA

OUT

(SMALL NMOS TO LARGE NMOS TRANSITION)

Figure 15. Mode Transition

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LM3686 is a step-down DC-DC converter with integrated low-dropout linear regular and a low-noise linear

regulator optimized for powering ultra-low voltage circuits from a single Li-Ion cell or 3-cell NiMH/NiCd batteries.

It provides three outputs with combined load current up to 900 mA over an input-voltage range from 2.7 V to 5.5

9.2 Typical Application

BATT

2.7 V to 5.5 V

4.7 mF, 0603

EN_DCDC

PGND

LM3686

3 MHz

DC-DC

1 mH

1.8 V

FB_DCDC

IN_LILO

10 mF

0603

PGND

LILO

EN_LILO

EN_LDO

PGND

Dual Rail

LILO

350 mA

0.7 V to 2 V

2.2 mF,

0402

350 mA

QGND

VIN_LDO

LDO

1.2 V to 3.3 V

Linear Regulator

300 mA

1 mF,

0402

1 mF, 0402

QGND

Figure 16. LM3686 Typical Application

9.2.1 Design Requirements

For typical step-down DC-DC converter applications, use the parameters listed in Table 2.

Table 2. Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

2.7 V to 5.5 V

1.8 V

Output voltage

Output current

100 mA

Minimum switching frequency

RMS noise, 10 Hz to100 kHz

PSRR at 100 kHz

2.55 MHz

166 μV_RMS

60 dB

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9.2.2 Detailed Design Procedure

9.2.2.1 Application Selection

TI strongly recommends selection of the required components for the LM3686 device as described within the

data sheet. If other components are selected, the device will not perform up to standards, and electrical

characteristics cannot be ensured.

9.2.2.2 Inductor Selection

There are two main considerations when choosing an inductor: the inductor must not saturate, and the inductor

current ripple must be small enough to achieve the desired output voltage ripple. Different saturation current

rating specifications are followed by different manufacturers so attention must be given to details. Saturation

current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of

application should be requested from the manufacturer. The minimum value of inductance to ensure good

performance is 0.7 µH at I_LIM(typical) DC current over the ambient temperature range. Shielded inductors radiate

less noise and are preferred. There are two methods to choose the inductor saturation current rating.

9.2.2.2.1 Method 1

The saturation current must be greater than the sum of the maximum load current and the worst case average-

to-peak inductor current. This can be written as:

I_SAT> I_{OUT_DCDC_MAX}+ I_RIPPLE

(1)

where

I_SATI_OUTMAX+ I_RIPPLE

V_BATT- V_OUT

V_OUT

≈

∆

’_x≈

’_x≈¹’

÷ ∆ _f÷

where I_RIPPLE

÷ ∆

◊ «^V◊ « ◊

2 x L

BATT

•

I_RIPPLE: average-to-peak inductor current

I_{OUT_DCDCMAX}: maximum load current (600 mA)

V_BATT: maximum input voltage in application

L: minimum inductor value including worst case tolerances (30% drop can be considered for Method 1)

f: minimum switching frequency (2.55 MHz)

(2)

9.2.2.2.2 Method 2

A more conservative and recommended approach is to choose an inductor that has a saturation current rating

greater than the maximum current limit of 1375 mA.

A 1-µH inductor with a saturation current rating of at least 1375 mA is recommended for most applications.

Resistance of the inductor must less than 0.3 Ω for good efficiency. Table 3 lists suggested inductors and

suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical

applications, a toroidal or shielded- bobbin inductor should be used. A good practice is to lay out the board with

overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor,

in the event that noise from low-cost bobbin models is unacceptable.

Table 3. Suggested Inductors and Their Suppliers

MODEL

VENDOR

TAIYO YUDEN

TOKO

DIMENSIONS L × W × H (mm)

2.5 × 1.8 × 1.2

DCR (maximum)

BRL2518T1R0M

MDT2520CR1R0M

KSLI252010AG1R0

2.5 × 2.0 × 1.0

HITACHI METALS

2.5 × 2.0 × 1.0

9.2.2.3 External Capacitors

As common with most regulators, the LM3686 requires external capacitors to ensure stable operation. The

LM3686 is specifically designed for portable applications requiring minimum board space and the smallest size

components. These capacitors must be correctly selected for good performance.

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9.2.2.4 Input Capacitor Selection

9.2.2.4.1 C_{IN_DC-DC}

A ceramic input capacitor of 4.7 µF, 6.3 V is sufficient for most applications. Place the input capacitor as close as

possible to the V_BATTpin of the device. A larger value may be used for improved input voltage filtering. Use X7R

or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting

case sizes like 0805 and 0603. The minimum input capacitance to ensure good performance is 2.2 µF at 3-V DC

bias; 1.5 µF at 5-V DC bias including tolerances and over ambient temperature range. The input filter capacitor

supplies current to the PFET switch of the LM3686 DC-DC converter in the first half of each cycle and reduces

voltage ripple imposed on the input power source. The low ESR of a ceramic capacitor provides the best noise

filtering of the input voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple

current rating. The input current ripple can be calculated as:

V_OUT

≈

’

◊

1 -

I_RMS= I_OUTMAX

∆

V_BATT

(V_BATT- V_OUT

)

OUT

r =

I_OUTMAXV_BATT

The worst case is when V_BATT= 2 V_OUT

(3)

9.2.2.4.2 C_{IN_LILO}

If the LILO is used as post regulation no additional capacitor is needed at V_{IN_LILO}as the output filter capacitor of

the DC-DC converter is close by and therefore sufficient.

In case of independent mode use, a 1-µF ceramic capacitor is recommended at V_{IN_LILO}if no other filter capacitor

is present in the V_{IN_LILO}supply path. This capacitor must be located a distance of not more than 1 cm from the

V_{IN_LILO}input pin and returned to Q_GND

9.2.2.4.3 C_{IN_LDO}

An input capacitor is required for stability. TI recommends using a 1-µF ceramic capacitor and connected

between the V_{IN_LDO}and QGND.

9.2.2.5 Output Capacitor

9.2.2.5.1 C_{OUT_DCDC}

A ceramic output capacitor of 10 µF, 6.3 V is sufficient for most applications. Use X7R or X5R types; do not use

Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and

0603. DC bias characteristics vary from manufacturer to manufacturer, and DC bias curves should be requested

from them as part of the capacitor selection process.

The minimum output capacitance to ensure good performance is 5.75 µF at 1.8-V DC bias including tolerances

and over ambient temperature range. The output filter capacitor smooths out current flow from the inductor to the

load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple.

These capacitors must be selected with sufficient capacitance and sufficiently low equivalent series resistance

(ESR) to perform these functions.

The output voltage ripple is caused by the charging and discharging of the output capacitor and by the R_ESRand

can be calculated as:

Voltage peak-to-peak ripple due to capacitance can be expressed as:

I_RIPPLE

V_PP-C

4 x f x C

(4)

(5)

Voltage peak-to-peak ripple due to ESR can be expressed as:

V_PP-ESR= (2 × I_RIPPLE) × R_ESR

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Because these two components are out of phase, the root mean squared (RMS) value can be used to get an

approximate value of peak-to-peak ripple. The peak-to-peak ripple voltage, RMS value can be expressed as:

V_PP-RMS

V_PP-C²+ V_PP-ESR

(6)

Note that the output voltage ripple is dependent on the inductor current ripple and the ESR of the output

capacitor (R_ESR). The R_ESRis frequency dependent (as well as temperature dependent); make sure the value

used for calculations is at the switching frequency of the part.

9.2.2.5.2 C_{OUT_LILO}

The linear regulator is designed specifically to work with very small ceramic output capacitors. A ceramic

capacitor (dielectric types X7R, Z5U, or Y5V) in the 2.2-µF range (up to 10 µF) and with an ESR between 3 mΩ

to 300 mΩ is suitable as C_{OUT_LIN}in the LM3686 application circuit.

This capacitor must be located a distance of not more than 1 cm from the V_{OUT_LILO}pin and returned to a clean

analog ground. Tantalum or film capacitors may also be used at the device output, V_{OUT_LILO}but these are not as

attractive for reasons of size and cost (see Table 4).

9.2.2.5.3 C_{OUT_LDO}

A ceramic capacitor in the 1-uF to 2.2-uF range, and with ESR between 5 mΩ to 500 mΩ, is suitable for the

linear regulator. Connect this output capacitor no more than 1 cm from V_{OUT_LDO}and QGND.

0603, 10V, X5R

100%

80%

60%

0402, 6.3V, X5R

40%

20%

1.0

2.0

3.0

4.0

5.0

DC BIAS (V)

Figure 17. Graph Showing A Typical Variation In Capacitance vs DC Bias

Table 4. Suggested Capacitors and Their Suppliers

CAPACITANCE (µF)

MODEL

VOLTAGE RATING (V)

Vendor

TDK

Type

Case Size / Inch (mm)

0603 (1608)

4.7

2.2

C1608X5R0J106K

C1608X5R0J475

C1608X5R0J225M

C1005JB0J105KT

6.3

Ceramic, X5R

TDK

0603 (1608)

TDK

0603 (1608)

TDK

0402 (1005)

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9.2.3 Application Curves

Figure 18. V_BATTLine Transient Response

Figure 19. Line Transient Response

PFM Mode: 1 mA to

PWM Mode: 100 mA to

350 mA

150 mA

Figure 21. Load Transient Response DC-DC

Figure 20. Load Transient Response DC-DC

LILO 50 mA to 250 mA

Figure 22. Load Transient Response

LDO 100 mA to 250 mA

Figure 23. Load Transient Response

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10 Power Supply Recommendations

The LM3686 requires a single supply input voltage. This voltage can range between 2.7 V to 5.5 V and must be

able to supply enough current for a given application.

11 Layout

11.1 Layout Guidelines

PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance

of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss

in the traces. These can send erroneous signals to the DC-DC converter device, resulting in poor regulation or

instability. Implement good layout for the LM3686 by following a few simple design rules:

1. Place the LM3686, inductor,and filter capacitor close together and make the traces short. The traces

between these components carry relatively high switching currents and act as antennas. Following this rule

reduces radiated noise. Special care must be given to place the input filter capacitor very close to the V_BATT

and PGND pin. Place the output capacitor of the linear regulator close to the output pin.

2. Arrange the components so that the switching current loops curl in the same direction. During the first half of

each cycle, current flows from the input filter capacitor through the LM3686 and inductor to the output filter

capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled

up from ground through the LM3686 by the inductor to the output filter capacitor and then back through

ground forming a second current loop. Routing these loops so the current curls in the same direction

prevents magnetic field reversal between the two half-cycles and reduces radiated noise.

3. Connect the ground pins of the LM3686 and filter capacitors together using generous component-side

copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several

vias. This reduces ground-plane noise by preventing the switching currents from circulating through the

ground plane. It also reduces ground bounce at the LM3686 by giving it a low impedance ground connection.

Route SGND to the ground-plane by a separate trace.

4. Use wide traces between the power components and for power connections to the DC-DC converter circuit.

This reduces voltage errors caused by resistive losses across the traces.

5. Route noise sensitive traces, such as the voltage feedback path (FB_DCDC), away from noisy traces

between the power components. The voltage feedback trace must remain close to the LM3686 circuit, must

be direct, and must be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC

converter voltage feedback trace. A good approach is to route the feedback trace on another layer and to

have a ground plane between the top layer and layer on which the feedback trace is routed.

6. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks

and other noisy circuitry. Interference with noise sensitive circuitry in the system can be reduced through

distance.

In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board,

arrange the CMOS digital circuitry around it (since this also generates noise), and then place sensitive pre-

amplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a metal

plane; power to it is post-regulated to reduce conducted noise, a good field of application for the on-chip low-

dropout linear regulator.

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11.2 Layout Example

Figure 24. LM3686 Layout

11.3 DSBGA Package Assembly and Use

Use of the DSBGA package requires specialized board layout, precision mounting and careful re-flow

techniques, as detailed in AN-1112 DSBGA Wafer Level Chip Scale Package. Refer to the section Surface

Mount Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC

board must be used to facilitate placement of the device. The pad style used with DSBGA package must be the

non-solder mask defined (NSMD) type. This means that the solder-mask opening is larger than the pad size.

This prevents a lip that otherwise forms if the solder mask and pad overlap, from holding the device off the

surface of the board and interfering with mounting. See AN-1112 DSBGA Wafer Level Chip Scale Package for

specific instructions how to do this. The 12-pin package used for LM3686 has 300 micron solder balls and

requires 275 micron pads for mounting on the circuit board. The trace to each pad must enter the pad with a 90°

entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad must not exceed

183 micron, for a section approximately 183 micron long or longer, as a thermal relief —then each trace must

neck up or down to its optimal width. The important criteria is symmetry. This ensures the solder bumps on the

LM3686 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid

to the pads for bumps A1 and B1 because PGND and VBATT are typically connected to large copper planes,

inadequate thermal relief can result in late or inadequate re-flow of these bumps. The DSBGA package is

optimized for the smallest possible size in applications with red or infrared opaque cases. Because the DSBGA

package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside

metallization and/or epoxy coating, along with frontside shading by the printed circuit board, reduce this

sensitivity. However, the package has exposed die edges. In particular, DSBGA devices are sensitive to light, in

the red and infrared range, shining on the exposed die edges of the package.

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Related Documentation

For additional information, see the following:

AN-1112 DSBGA Wafer Level Chip Scale Package

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LM3686TLE-AADW/NOPB

ACTIVE

DSBGA

YZR

250

RoHS & Green

SNAGCU

Level-1-260C-UNLIM

-30 to 85

SUEB

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM3686TLE-AADW/NOPB DSBGA

YZR

250

178.0

8.4

1.83

2.49

0.76

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

DSBGA YZR 12

SPQ

Length (mm) Width (mm) Height (mm)

208.0 191.0 35.0

LM3686TLE-AADW/NOPB

250

Pack Materials-Page 2

MECHANICAL DATA

YZR0012xxx

0.600±0.075

TLA12XXX (Rev C)

D: Max = 2.465 mm, Min =2.405 mm

E: Max = 1.717 mm, Min =1.656 mm

4215049/A

12/12

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

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LM3686 [TI]

相关型号：

LM3686TL-AADW

LM3686TL-AADW

LM3686TLE-AADW

LM3686TLE-AADW/NOPB

LM3686TLE-AAED

LM3686TLE-AAEF

LM3686TLX-AADW

LM3686TLX-AAED

LM3686TLX-AAEF

LM3687

LM3687

LM3687TL-1812