LM3710 [TI]
具有电源故障输入、低电平线路输出、手动复位和看门狗计时器的电压监控器和复位 IC;
| 型号： | LM3710 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电源故障输入、低电平线路输出、手动复位和看门狗计时器的电压监控器和复位 IC 监控 |
| 文件： | 总21页 (文件大小：1386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM3710, LM3711
www.ti.com
SNVS150E –NOVEMBER 2000–REVISED MARCH 2013
LM3710/LM3711 Microprocessor Supervisory Circuits with Power Fail Input, Low Line
Output, Manual Reset and Watchdog Timer
Check for Samples: LM3710, LM3711
1
FEATURES
DESCRIPTION
The LM3710/LM3711 series of microprocessor
supervisory circuits provide the maximum flexibility for
monitoring power supplies and battery controlled
functions in systems without backup batteries. The
LM3710/LM3711 series are available in VSSOP-10
and 9-bump DSBGA packages.
2
•
Standard Reset Threshold Voltage: 3.08V
•
Custom Reset Threshold Voltages: For other
voltages between 2.2V and 5.0V in 10mV
increments, contact TI
•
•
•
•
•
No External Components Required
Manual-Reset Input
Built-in features include the following:
RESET (LM3710) or RESET (LM3711) Outputs
Precision Supply Voltage Monitor
Reset: Reset is asserted during power-up, power-
down, and brownout conditions. RESET is ensured
down to VCC of 1.0V.
Factory Programmable Reset and Watchdog
Timeout Delays
Manual Reset Input: An input that asserts reset when
pulled low.
•
•
Separate Power Fail Comparator
Available in DSBGA Package for Minimum
Footprint
Power-Fail Input: A 1.225V threshold detector for
power fail warning, or to monitor a power supply other
than VCC
.
•
•
•
•
±0.5% Reset Threshold Accuracy at Room
Temperature
Low Line Output: This early power failure warning
indicator goes low when the supply voltage drops to a
value which is 2% higher than the reset threshold
voltage.
±2% Reset Threshold Accuracy Over
Temperature Extremes
Reset Assertion Down to 1V VCC (RESET
Option Only)
Watchdog Timer: The WDI (Watchdog Input)
monitors one of the µP's output lines for activity. If no
output transition occurs during the watchdog timeout
period, reset is activated.
28 µA VCC Supply Current
APPLICATIONS
•
•
•
•
Embedded Controllers and Processors
Intelligent Instruments
Automotive Systems
Critical µP Power Monitoring
Typical Application
V
IN1
V
CC
V
CC
Reset
PFO
Reset
NMI
V
IN2
PFI
mP
WDI
MR
bus
INT
LLO
GND
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
LM3710, LM3711
SNVS150E –NOVEMBER 2000–REVISED MARCH 2013
www.ti.com
Connection Diagram
1
2
3
4
5
10
9
VCC
Reset
NC
MR
PFI
8
PFO
LLO
NC
7
WDI
GND
6
Figure 1. VSSOP-10
1
2
3
VCC
Reset
MR
PFI
NC
PFO
WDI
A
GND
B
LLO
C
Figure 2. Top View
(looking from the coating side)
DSBGA 9 Bump Package
PIN DESCRIPTIONS
Pin No.
Name
Function
DSBGA
VSSOP
A1
2
MR
Manual-Reset input. When MR is less than VMRT (Manual Reset Threshold) RESET/RESET is
engaged.
B1
C1
1
VCC
Power Supply input.
10
RESET
Reset Logic Output. Pulses low for tRP (Reset Timeout Period) when triggered, and stays low
whenever VCC is below the reset threshold or when MR is below VMRT. It remains low for tRP after
either VCC rises above the reset threshold, or after MR input rises above VMRT (LM3710 only).
RESET
PFO
Reset Logic Output. RESET is the inverse of RESET (LM3711 only).
C2
C3
8
7
Power-Fail Logic Output. When PFI is below VPFT, PFO goes low; otherwise, PFO remains high.
LLO
Low-Line Logic Output. Early Power-Fail warning output. Low when VCC falls below VLLOT (Low-
Line Output Threshold). This output can be used to generate an NMI (Non-Maskable Interrupt) to
provide an early warning of imminent power-failure.
B3
A3
5
4
GND
WDI
Ground reference for all signals.
Watchdog Input Transition Monitor: If no transition activity occurs for a period exceeding tWD
(Watchdog Timeout Period), reset is engaged.
A2
B2
3
PFI
NC
Power-Fail Comparator Input. When PFI is less than VPFT (Power-Fail Reset Threshold), the PFO
goes low; otherwise, PFO remains high.
6, 9
No Connect. Test input used at factory only. Leave floating.
2
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SNVS150E –NOVEMBER 2000–REVISED MARCH 2013
Block Diagram
Table Of Functions
Part
Number
Active
Low
Reset
Active
High
Reset
Output
(X = totem-pole)
(Y = open-drain)
Reset
Timeout
Period
Watchdog
Timeout
Period
Manual
Reset
Power Fail
Comparator
Low Line
Output
LM3710
LM3711
x
X, Y(1)
Customized
Customized
Customized
Customized
x
x
x
x
x
x
x
X
(1) Available upon request. Contact TI.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC
)
−0.3V to 6.0V
All Other Inputs
−0.3V to VCC + 0.3V
(3)
ESD Ratings
Human Body Model
Machine Model
1.5kV
150V
(4)
Power Dissipation
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The Human Body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200pF
capacitor discharged directly into each pin.
(4) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJ-A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperture is calculated
using:
Where the value of θJ-A for the VSSOP-10 package is 195°C/W in a typical PC board mounting and the DSBGA package is 220°C/W.
Operating Ratings(1)
Temperature Range
−40°C ≤ TJ ≤ 85°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed conditions.
LM3710/LM3711 Series Electrical Characteristics
Limits in the standard typeface are for TJ = 25°C and limits in boldface type apply over full operating range. Unless otherwise
specified: VCC = +2.2V to 5.5V.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
POWER SUPPLY
VCC
Operating Voltage
Range: VCC
LM3710
LM3711
1.0
1.2
5.5
5.5
50
V
ICC
VCC Supply Current
All inputs = VCC; all outputs floating
28
µA
RESET THRESHOLD
VRST
Reset Threshold
VCC falling
−0.5
−2
+0.5
+2
VRST
%
VCC falling: TA = 0°C to 70°C
−1.5
+1.5
VRSTH
tRP
Reset Threshold
Hysteresis
0.0032•VRST
mV
Reset Timeout Period Reset Timeout Period = E, J, N, S
Reset Timeout Period = F, K, P, T
1
20
140
1120
1.4
28
200
1600
2
40
280
2240
ms
µs
Reset Timeout Period = G, L, Q, U
Reset Timeout Period = H, M, R, V
tRD
VCCto Reset Delay
VCCfalling at 1mV/µs
20
RESET (LM3711)
VOL RESET
VCC > 2.25V, ISINK = 900µA
VCC > 2.7V, ISINK = 1.2mA
VCC > 4.5V, ISINK = 3.2mA
VCC > 1.2V, ISOURCE = 50µA
VCC > 1.8V, ISOURCE = 150µA
VCC > 2.25V, ISOURCE = 300µA
VCC > 2.7V, ISOURCE = 500µA
VCC > 4.5V, ISOURCE = 800µA
0.3
0.3
0.4
V
V
VOH
RESET
0.8 VCC
0.8 VCC
0.8 VCC
0.8 VCC
CC − 1.5V
V
4
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SNVS150E –NOVEMBER 2000–REVISED MARCH 2013
LM3710/LM3711 Series Electrical Characteristics (continued)
Limits in the standard typeface are for TJ = 25°C and limits in boldface type apply over full operating range. Unless otherwise
specified: VCC = +2.2V to 5.5V.
Symbol
Parameter
Conditions
Min
Typ
Max
1.0
Units
ILKG
Output Leakage
Current
VRESET = 5.5V
µA
RESET (LM3710)
VOL RESET
VCC > 1.0V, ISINK = 50µA
0.3
0.3
0.3
0.3
0.4
VCC > 1.2V, ISINK = 100µA
VCC > 2.25V, ISINK = 900µA
VCC > 2.7V, ISINK = 1.2mA
VCC > 4.5V, ISINK = 3.2mA
VCC > 2.25V, ISOURCE = 300µA
VCC > 2.7V, ISOURCE = 500µA
VCC > 4.5V, ISOURCE = 800µA
V
VOH
RESET
0.8 VCC
0.8 VCC
CC − 1.5V
V
WDI
WDI
WDIT
tWD
Watchdog Input
Current
−1
+1
µA
V
Watchdog Input
Threshold
0.2•VCC
1.225
0.8•VCC
Watchdog Timeout
Period
Watchdog Timeout Period = E, F, G, H
Watchdog Timeout Period = J, K, L, M
Watchdog Timeout Period = N, P, Q, R
Watchdog Timeout Period = S, T, U, V
4.3
71
1120
17900
6.2
102
1600
25600
9.3
153
2400
38400
ms
PFI/MR
VPFT
PFI Input Threshold
MR Input Threshold
1.200
2.0
1.225
1.250
0.8
V
V
VMRT
MR, Low
MR, High
VPFTH
VMRTH
/
PFI/MR Threshold
Hysteresis
PFI/MR falling: VCC = VRST MAX to 5.5V
0.0032•VRST
mV
IPFI
Input Current
(PFI only)
−75
75
75
nA
RMR
MR Pull-up
Resistance
35
56
12
kΩ
tMD
tMR
MR to Reset Delay
MR Pulse Width
µS
µS
25
PFO, LLO
VOL
PFO, LLO Output
Voltage
VCC > 2.25V, ISINK = 900µA
VCC > 2.7V, ISINK = 1.2mA
VCC > 4.5V, ISINK = 3.2mA
VCC > 2.25V, ISOURCE = 300µA
VCC > 2.7V, ISOURCE = 500µA
VCC > 4.5V, ISOURCE = 800µA
0.3
0.3
0.4
V
V
VOH
0.8 VCC
0.8 VCC
CC − 1.5V
V
LLO OUTPUT
VLLOT
LLO Output
Threshold
1.01•VRST
1.02•VRST
1.03•VRST
(VLLO − VRST, VCC
falling)
VLLOTH
tCD
Low-Line Comparator
Hysteresis
0.0032•VRST
20
mV
µs
Low-Line Comparator VCC falling at 1mV/µs
Delay
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Typical Performance Characteristics
Supply Current vs Supply Voltage
3.3V Supply Current vs Temperature
30
29
30
25
28
20
15
10
27
26
25
24
23
5
0
25
70
85
-40
0
5
1
3
4
2
Temperature (°C)
Supply Voltage (V)
Figure 3.
Figure 4.
Normalized Reset Threshold Voltage vs Temperature
Reset Timeout Period vs VCC
0.5
220
215
210
0.4
0.3
0.2
205
200
195
190
0.1
0
-0.1
-0.2
-0.3
185
180
-0.4
-0.5
-40
25
85
5.5
5
6
3.0
4.5
3.5
4
Temperature (°C)
Supply Voltage (V)
Figure 5.
Figure 6.
Max. Transient Duration vs Reset Comparator Overdrive
(VCC = 3.3V)
Reset Timeout Period vs Temperature
215
210
205
200
80
70
60
50
40
30
20
195
190
10
0
25
-40
85
10
100
1000
Temperature (°C)
Reset Comparator Overdrive (mV)
VRST - VCC
Figure 7.
Figure 8.
6
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SNVS150E –NOVEMBER 2000–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Watchdog Timeout Period vs Temperature
(tWD programmed as 6.2ms)
Low-Line Comparator Propagation Delay vs Temperature
7
39
6.8
37
35
6.6
6.4
6.2
6
33
31
5.8
29
27
25
5.6
5.4
5.2
5
-40
-20
0
20
40
60
80
85
25
-40
Temperature (oC)
Temperature (oC)
Figure 9.
Figure 10.
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CIRCUIT INFORMATION
RESET OUTPUT
The Reset input of a µP initializes the device into a known state. The LM3710/LM3711 microprocessor
supervisory circuits assert a forced reset output to prevent code execution errors during power-up, power-down,
and brownout conditions.
RESET is ensured valid for VCC > 1V. Once VCC exceeds the reset threshold, an internal timer maintains the
output for the reset timeout period. After this interval, reset goes high. The LM3710 offers an active-low RESET;
The LM3711 offers an active-high RESET.
Any time VCC drops below the reset threshold (such as during a brownout), the reset activates. When VCC again
rises above the reset threshold, the internal timer starts. Reset holds until VCC exceeds the reset threshold for
longer than the reset timeout period. After this time, reset releases.
The Manual Reset input (MR) will initiate a forced reset also. See the MANUAL RESET INPUT (MR) section.
RESET THRESHOLD
The LM3710/LM3711 family is available with a reset voltage of 3.08V. Other reset thresholds in the 2.20V to
5.0V range, in steps of 10 mV, are available; contact Texas Instruments for details.
MANUAL RESET INPUT (MR)
Many µP-based products require a manual reset capability, allowing the operator to initiate a reset. The MR input
is fully debounced and provides an internal 56 kΩ pull-up. When the MR input is pulled below VMRT (1.225V) for
more than 25 µs, reset is asserted after a typical delay of 12 µs. Reset remains active as long as MR is held low,
and releases after the reset timeout period expires after MR rises above VMRT. Use MR with digital logic to assert
or to daisy chain supervisory circuits. It may be used as another low-line comparator by adding a buffer.
POWER-FAIL COMPARATOR (PFI/PFO)
The PFI is compared to a 1.225V internal reference, VPFT. If PFI is less than VPFT, the Power Fail Output PFO
drops low. The power-fail comparator signals a falling power supply, and is driven typically by an external voltage
divider that senses either the unregulated supply or another system supply voltage. The voltage divider generally
is chosen so the voltage at PFI drops below VPFT several milliseconds before the main supply voltage drops
below the reset threshold, providing advanced warning of a brownout.
The voltage threshold is set by R1 and R2 and is calculated as follows:
(1)
Note this comparator is completely separate from the rest of the circuitry, and may be employed for other
functions as needed.
LOW-LINE OUTPUT (LLO)
The low-line output comparator is typically used to provide a non-maskable interrupt to a µP when VCC begins
falling. LLO monitors VCC and goes low when VCC falls below VLLOT (typically 1.02 • VRST) with hysteresis of
0.0032 • VRST
.
WATCHDOG TIMER INPUT (WDI)
The watchdog timer input monitors one of the microprocessor's output lines for activity. Each time a transition
occurs on this monitored line, the watchdog counter is reset. However, if no transition occurs and the timeout
period is reached, the LM3710/LM3711 assumes that the microprocessor has locked up and the reset output is
activated.
WDI is a high impedance input.
8
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SNVS150E –NOVEMBER 2000–REVISED MARCH 2013
SPECIAL PRECAUTIONS FOR THE DSBGA PACKAGE
As with most integrated circuits, the LM3710 and LM3711 are sensitive to exposure from visible and infrared (IR)
light radiation. Unlike a plastic encapsulated IC, the DSBGA package has very limited shielding from light, and
some sensitivity to light reflected from the surface of the PC board or long wavelength IR entering the die from
the side may be experienced. This light could have an unpredictable affect on the electrical performance of the
IC. Care should be taken to shield the device from direct exposure to bright visible or IR light during operation.
DSBGA MOUNTING
The DSBGA package requires specific mounting techniques which are detailed in TI Application Note AN-1112
(SNVA009). Referring to the section Surface Mount Assembly Considerations, it should be noted that the pad
style which must be used with the 9-pin package is the NSMD (non-solder mask defined) type.
For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the
DSBGA device.
Timing Diagrams
Figure 11. LM3710/LM3711 Reset Time with MR and WDI
Figure 12. LLO Output
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Figure 13. PFI Comparator Timing Diagram
Typical Application Circuits
VIN2
VIN1
R1
V
CC
RESET
INT
RESET
PFI
mP
GND
(
WDI
MR
LLO
PFO
R2
GND
R1
R2
.
Power-Fail Reset Threshold, VPFT = 1.225
+ 1
(
Active Data Line
Figure 14. Monitoring Two Critical Supplies And Dataline
10
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SNVS150E –NOVEMBER 2000–REVISED MARCH 2013
1.8V
3.3V
107k
VI/O
Vcore
VCC
PFI
RESET
RESET
PFO
332k
WDI
MR
GND
3.3k
Active Data Line
Figure 15. Monitoring Two Supplies plus Manual Reset And Dataline
1.8
V
3.3V
107k
VCC
VI/O
VCORE
RESET
PFO
RESET
PFI
332k
WDI
MR
GND
Active Data Line
FAULT
(Normally High)
Figure 16. Monitoring Dual Supplies plus External Fault Input And Dataline
Raw Supply
(Battery)
System
Regulator
3.3V
0.1m ceramic
R1
VCC
INT
PFO
PFI
mP
WDI
R2
RESET
MR
RESET
GND
Active Data
Line
R1
R2
(
+ 1
.
Power-Fail Reset Threshold, VPFT = 1.225
(
Note: MR input with its 1.225V nominal threshold, may monitor an additional supply voltage. An internal 56 kΩ pull-up
resistor is included on this input.
Figure 17. Microprocessor Supervisor with Early Warning Detector
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+3.3 to 5V
VCC
PFI
OUTPUT
RESET
WDI
tWD
GND
tRP
Period = tRP + tWD
Figure 18. LM3710 Long Period oscillator
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM3710XKMM-463/NOPB
LM3710XQMM-308/NOPB
LM3710YQMM-232/NOPB
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
DGS
DGS
DGS
10
10
10
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
R74B
R37B
R77B
SN
SN
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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22-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3710XKMM-463/NOPB VSSOP
LM3710XQMM-308/NOPB VSSOP
LM3710YQMM-232/NOPB VSSOP
DGS
DGS
DGS
10
10
10
1000
1000
1000
178.0
178.0
178.0
12.4
12.4
12.4
5.3
5.3
5.3
3.4
3.4
3.4
1.4
1.4
1.4
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM3710XKMM-463/NOPB
LM3710XQMM-308/NOPB
LM3710YQMM-232/NOPB
VSSOP
VSSOP
VSSOP
DGS
DGS
DGS
10
10
10
1000
1000
1000
208.0
208.0
208.0
191.0
191.0
191.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
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EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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