LM3712XSBPX-308 [TI]
2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA9, MICRO, BUMP, SMD-9;
| 型号： | LM3712XSBPX-308 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA9, MICRO, BUMP, SMD-9 |
| 文件： | 总14页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 9, 2008
LM3712
Microprocessor Supervisory Circuits with Separate
Watchdog Timer Output, Power Fail Input and Manual
Reset
General Description
Features
The LM3712 series of microprocessor supervisory circuits
provide the maximum flexibility for monitoring power supplies
and battery controlled functions in systems without backup
batteries. The LM3712 series are available in a 9-bump micro
SMD package.
Standard Reset Threshold voltage: 3.08V
■
■
Custom Reset Threshold voltages: For other voltages
between 2.2V and 5.0V in 10mV increments, contact
National Semiconductor Corp.
No external components required
■
■
■
■
Built-in features include the following:
Manual-Reset input
Reset: Reset is asserted during power-up, power-down, and
brownout conditions. RESET is guaranteed down to VCC of
1.0V.
RESET output
Precision supply voltage monitor
Factory programmable Reset and Watchdog Timeout
Delays
■
Manual Reset Input: An input that asserts reset when pulled
low.
Separate Watchdog output
■
■
■
■
Power-Fail Input: A 1.225V threshold detector for power fail
warning, or to monitor a power supply other than VCC
Separate Power Fail comparator
.
Available in micro SMD package for minimum footprint
Watchdog Timer: The WDI (Watchdog Input) monitors one of
the µP's output lines for activity. If no output transition occurs
during the watchdog timeout period, the watchdog output
(WDO) pulls low.
±0.5% Reset threshold accuracy at room temperature
±2% Reset threshold accuracy over temperature
extremes
■
Reset assertion down to 1V VCC
■
■
28 µA VCC supply current
Applications
Embedded Controllers and Processors
■
■
■
■
Intelligent Instruments
Automotive Systems
Critical µP Power Monitoring
Typical Application
20011903
© 2008 National Semiconductor Corporation
200119
www.national.com
Connection Diagram
Top View
(looking from the coating side)
micro SMD 9 Bump Package
BPA09
20011901
Pin Descriptions
Bump No.
Name
MR
Function
A1
B1
C1
Manual-Reset input. When MR is less than VMRT (Manual Reset Threshold) RESET is engaged.
Power Supply input.
VCC
RESET
Reset Logic Output. Pulses low for tRP (Reset Timeout Period) when triggered, and stays low
whenever VCC is below the reset threshold or when MR is below VMRT. It remains low for tRP after
either VCC rises above the reset threshold, or after MR input rises above VMRT
.
C2
C3
PFO
Power-Fail Logic Output. When PFI is below VPFT PFO goes low; otherwise, PFO remains high.
WDO
Watchdog Output. If no digital activity is detected on WDI (Watchdog Input) for a period exceeding
tWD, this output pulls low.
B3
A3
GND
WDI
Ground reference for all signals.
Watchdog Input Transition Monitor: If no transition activity occurs for a period exceeding tWD
(Watchdog Timeout Period), reset is engaged.
A2
B2
PFI
NC
Power-Fail Comparator Input. When PFI is less than VPFT (Power-Fail Reset Threshold), the PFO
goes low; otherwise, PFO remains high.
No Connect. Test input used at factory only. Leave floating.
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2
Block Diagram
20011905
3
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Ordering Information
20011904
*For other voltages between 2.2V and 5.0V, please contact National Semiconductor sales office.
Package
Part Number
LM3712XQBP-308
Output
Reset Timeout Period
Watchdog Timeout Period
Marking
%%IC
%%IC
%%IC
%%IC
totem-pole
totem-pole
totem-pole
totem-pole
200ms
200ms
200ms
200ms
1600ms
1600ms
1600ms
1600ms
LM3712XQBPX-308
LM3712XQTP-308
LM3712XQTPX-308
%% is the datecode and will vary with time.
Table Of Functions
Part Number
Active
Low Reset
Active
High
Reset
Output
(X = totem-pole)
(Y = open-drain)
Reset Timeout
Watchdog
Timeout Period
Manual
Reset
Power Fail
Comparator
Period
LM3712
x
X, Y*
Customized
Customized
x
x
* = available upon request. Contact National
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4
ESD Ratings (Note 2)
Human Body Model
Machine Model
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
1.5kV
150V
(Note 3)
Power Dissipation
Supply Voltage (VCC
All Other Inputs
)
−0.3V to 6.0V
Operating Ratings (Note 1)
Temperature Range
−0.3V to VCC + 0.3V
−40°C ≤ TJ ≤ 85°C
Electrical Characteristics
Limits in the standard typeface are for TJ = 25°C and limits in boldface type apply over full operating range. Unless otherwise
specified: VCC = +2.2V to 5.5V.
Symbol
Parameter
Conditions
Min
1.0
Typ
Max
5.5
50
Units
POWER SUPPLY
VCC
Operating Voltage
Range: VCC
V
ICC
VCC Supply Current All inputs = VCC; all outputs floating
28
µA
RESET THRESHOLD
VRST
Reset Threshold
VCC falling
−0.5
+0.5
−2
+2
VRST
%
VCC falling: TA = 0°C to 70°C
−1.5
+1.5
VRSTH
tRP
Reset Threshold
Hysteresis
0.0032•VRST
mV
Reset Timeout
Period
Reset Timeout Period = E, J, N, S
Reset Timeout Period = F, K, P, T
Reset Timeout Period = G, L, Q, U
Reset Timeout Period = H, M, R, V
1
20
140
1120
1.4
28
200
1600
2
40
280
2240
ms
µs
tRD
RESET
VOL
VCC to Reset Delay VCC falling at 1mV/µs
20
RESET
RESET
VCC > 1.0V, ISINK = 50µA
0.3
0.3
0.3
0.3
0.4
VCC > 1.2V, ISINK = 100µA
VCC > 2.25V, ISINK = 900µA
VCC > 2.7V, ISINK = 1.2mA
VCC > 4.5V, ISINK = 3.2mA
VCC > 2.25V, ISOURCE = 300µA
VCC > 2.7V, ISOURCE = 500µA
VCC > 4.5V, ISOURCE = 800µA
V
VOH
0.8 VCC
0.8 VCC
VCC − 1.5V
WDI
WDI
Watchdog Input
Current
−1
+1
µA
V
WDIT
tWD
Watchdog Input
Threshold
0.2•VCC
0.8•VCC
1.225
Watchdog Timeout Watchdog Timeout Period = E, F, G, H
Period
4.3
71
1120
17900
6.2
102
1600
25600
9.3
153
2400
38400
Watchdog Timeout Period = J, K, L, M
Watchdog Timeout Period = N, P, Q, R
Watchdog Timeout Period = S, T, U, V
ms
PFI/MR
VPFT
PFI Input Threshold
1.200
2.0
1.225
1.250
0.8
V
V
VMRT
MR Input Threshold MR, Low
MR, High
VPFTH
/
PFI/MR Threshold
Hysteresis
PFI/MR falling: VCC = VRST MAX to 5.5V
0.0032•VRST
mV
VMRTH
IPFI
Input Current (PFI
only)
−75
75
nA
5
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Symbol
Parameter
MR Pull-up
Resistance
Conditions
Min
35
Typ
Max
75
Units
RMR
56
kΩ
tMD
tMR
MR to Reset Delay
MR Pulse Width
12
µS
µS
25
PFO, WDO
VOL
PFO, WDO Output VCC > 2.25V, ISINK = 900µA
0.3
0.3
0.4
Voltage
VCC > 2.7V, ISINK = 1.2mA
VCC > 4.5V, ISINK = 3.2mA
V
V
VOH
VCC > 2.25V, ISOURCE = 300µA
VCC > 2.7V, ISOURCE = 500µA
VCC > 4.5V, ISOURCE = 800µA
0.8 VCC
0.8 VCC
VCC − 1.5V
LLO OUTPUT
VLLOT
LLO Output
1.01•VRST
1.02•VRST
1.03•VRST
Threshold
(VLLO − VRST, VCC
falling)
VLLOTH
Low-Line
Comparator
Hysteresis
0.0032•VRST
mV
µs
tCD
Low-Line
VCC falling at 1mV/µs
20
Comparator Delay
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed conditions.
Note 2: The Human Body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200pF capacitor discharged
directly into each pin.
Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, θJ-
A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperture is calculated using:
Where the value of θJ-A for the micro SMD package is 220°C/W.
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6
Typical Performance Characteristics
Supply Current vs Supply Voltage
3.3V Supply Current vs Temperature
20011911
20011915
Normalized Reset Threshold Voltage vs Temperature
Reset Timeout Period vs VCC
20011912
20011932
Reset Timeout Period vs Temperature
Max. Transient Duration vs Reset Comparator Overdrive
(VCC = 3.3V)
20011910
20011916
7
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Watchdog Timeout Period vs Temperature
(tWD programmed as 6.2ms)
20011913
supply voltage drops below the reset threshold, providing ad-
vanced warning of a brownout.
Circuit Information
The voltage threshold is set by R1 and R2 and is calculated
as follows:
RESET OUTPUT
The Reset input of a µP initializes the device into a known
state. The LM3712 microprocessor supervisory circuits assert
a forced reset output to prevent code execution errors during
power-up, power-down, and brownout conditions.
RESET is guaranteed valid for VCC > 1V. Once VCC exceeds
the reset threshold, an internal timer maintains the output for
the reset timeout period. After this interval, reset goes high.
The LM3712 offers an active-low RESET.
Note this comparator is completely separate from the rest of
the circuitry, and may be employed for other functions as
needed.
Any time VCC drops below the reset threshold (such as during
a brownout), the reset activates. When VCC again rises above
the reset threshold, the internal timer starts. Reset holds until
VCC exceeds the reset threshold for longer than the reset
timeout period. After this time, reset releases.
WATCHDOG TIMER INPUT (WDI)
The watchdog timer input monitors one of the
microprocessor's output lines for activity. Each time a transi-
tion occurs on this monitored line, the watchdog counter is
reset. However, if no transition occurs and the timeout period
is reached, the LM3712 assumes that the microprocessor has
locked up and the watchdog output WDO, is activated.
The Manual Reset input (MR) will initiate a forced reset also.
See the Manual Reset Input section.
WDI is a high impedance input. WDO is an active-low totem
pole output.
RESET THRESHOLD
The LM3712 family is available with a reset voltage of 3.08V.
Other reset thresholds in the 2.20V to 5.0V range, in steps of
10 mV, are available; contact National Semiconductor for de-
tails.
SPECIAL PRECAUTIONS FOR THE micro SMD
PACKAGE
As with most integrated circuits, the LM3712 is sensitive to
exposure from visible and infrared (IR) light radiation. Unlike
a plastic encapsulated IC, the micro SMD package has very
limited shielding from light, and some sensitivity to light re-
flected from the surface of the PC board or long wavelength
IR entering the die from the side may be experienced. This
light could have an unpredictable affect on the electrical per-
formance of the IC. Care should be taken to shield the device
from direct exposure to bright visible or IR light during oper-
ation.
MANUAL RESET INPUT (MR)
Many µP-based products require a manual reset capability,
allowing the operator to initiate a reset. The MR input is fully
debounced and provides an internal 56 kΩ pull-up. When the
MR input is pulled below VMRT (1.225V) for more than 25 µs,
reset is asserted after a typical delay of 12 µs. Reset remains
active as long as MR is held low, and releases after the reset
timeout period expires after MR rises above VMRT. Use MR
with digital logic to assert or to daisy chain supervisory cir-
cuits. It may be used as another low-line comparator by
adding a buffer.
micro SMD MOUNTING
The micro SMD package requires specific mounting tech-
niques which are detailed in National Semiconductor Appli-
cation Note AN-1112. Referring to the section Surface Mount
Technology (SMT) Assembly Considerations, it should be
noted that the pad style which must be used with the 9-pin
package is the NSMD (non-solder mask defined) type.
POWER-FAIL COMPARATOR (PFI/PFO)
The PFI is compared to a 1.225V internal reference, VPFT. If
PFI is less than VPFT, the Power Fail Output PFO drops low.
The power-fail comparator signals a falling power supply, and
is driven typically by an external voltage divider that senses
either the unregulated supply or another system supply volt-
age. The voltage divider generally is chosen so the voltage at
PFI drops below VPFT several milliseconds before the main
For best results during assembly, alignment ordinals on the
PC board may be used to facilitate placement of the micro
SMD device.
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8
Timing Diagrams
20011928
FIGURE 1. LM3712 Reset Time with MR
20011930
FIGURE 2. PFI Comparator Timing Diagram
9
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Typical Application Circuits
20011918
FIGURE 3. Monitoring Two Critical Supplies Plus Dataline
20011919
FIGURE 4. Monitoring Two Supplies plus Manual Reset And Dataline
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10
Physical Dimensions inches (millimeters) unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
1. EPOXY COATING
2. 63Sn/37Pb EUTECTIC BUMP
3. RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD.
4. PIN 1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION. REMAINING PINS ARE NUMBERED COUNTER CLOCK-
WISE.
5. XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH, X2 IS PACKAGE LENGTH AND X3 IS PACK-
AGE HEIGHT.
6.NO JEDEC REGISTRATION AS OF AUG.1999.
9 bump micro SMD Package
NS Package Number BPA09FFB
The dimensions of X1, X2 and X3 are given below
X1 = 1.412mm
X2 = 1.412mm
X3 = 0.850mm
11
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NOTES: UNLESS OTHERWISE SPECIFIED
1. EPOXY COATING
2. 63Sn/37Pb EUTECTIC BUMP
3. RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD.
4. PIN 1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION. REMAINING PINS ARE NUMBERED COUNTER CLOCK-
WISE.
5. XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH, X2 IS PACKAGE LENGTH AND X3 IS PACK-
AGE HEIGHT.
6.NO JEDEC REGISTRATION AS OF AUG.1999.
9 bump micro SMD Package
NS Package Number TPA09GGA
The dimensions of X1, X2 and X3 are given below
X1 = 1.412mm
X2 = 1.412mm
X3 = 0.50mm
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Notes
13
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