LM3754_技术文档

LM3754

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SNVS789B –JANUARY 2012–REVISED APRIL 2013

LM3754 Scalable 2-Phase Synchronous Buck Controller with Integrated FET Drivers and

Linear Regulator Controller

Check for Samples: LM3754

1

FEATURES

APPLICATIONS

2

•

Wide Input Voltage Range of 4.5V to 18V

Up to 12 Channels for 300A Load

•

CPUs, GPUs (Graphic Cards), ASICs, FPGAs,

Large Memory Arrays, DDR

•

High Current POL Converters

Networking Systems

System Accuracy Better Than 1%

0.6V to 3.6V Output Voltage Range

Switching Frequency From 200 kHz to 1 MHz

Power Distribution Systems

Telecom/Datacom DC/DC Converters

Desktops, Servers and Workstations

Phase Current Sharing ±12% Max Over

Temperature

•

Integrated 4.35V ±2.3% LDO

DESCRIPTION

Inductor DCR or Sense Resistor Current

Sensing

The LM3754 is a full featured single-output dual-

phase voltage-mode synchronous PWM buck

controller. It can be configured to control from 2 to 12

interleaved power stages creating a single high power

output. This controller utilizes voltage-mode control

with input voltage feed-forward for high noise

immunity. An internal average current loop forces real

time current sharing between phases during load

transients.

•

Interleaved Switching for Low I/O Ripple

Current

•

Integrated Synchronous NFET Drivers

Programmable Soft-Start

Pre-Biased Startup

Output Voltage Differential Remote Sensing

Minimum Controllable On-Time of Only 50 ns

Programmable Enable and Input UVLO

Power Good flag

The LM3754 supports adjustable Soft-Start. The Soft-

Start function can only drive the output upwards – it

will not pull it down, therefore, pre-biased loads will

not be discharged. Available in the 5 mm x 5 mm

thermally enhanced 32-lead WQFN package with a

thermal pad.

OVP, UVP and Hiccup Over-Current Protection

Simplified Application

V

OUT

IN

6V TO 18V DC

1.2V 100A

C

IN

C

OUT

VDD

D

VDD

D

BOOT3

BOOT1

V

IN

BOOT1

HG1

BOOT1

HG1

Q

T1

T3

L1

L3

C

BOOT3

BOOT1

C

R

DCR1

SW1

CS1

C

R

DCR3

CS1

LG1

Q

LG1

LM3754

CSM

B3

B1

LM3754

CSM

D

BOOT2

D

BOOT4

V

IN

V

BOOT2

HG2

IN

BOOT2

HG2

SW2

Q

T4

T2

L2

L4

C

BOOT4

BOOT2

R

C

DCR2 DCR2

SW2

C

R

DCR4 DCR4

CS2

LG2

CS2

LG2

Q

B4

B2

R

ILIM2

ILIM1

ILIM

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

2

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM3754

SNVS789B –JANUARY 2012–REVISED APRIL 2013

www.ti.com

Connection Diagram

8

7

6

5

4

3

2

1

9

BOOT2

PH

BOOT1

32

31

10

PGOOD

SYNCOUT

SYNC

DAP (should be tied to

SGND and PGND on board)

11

12

13

14

30

29

28

27

CS1

CSM

LM3754

WQFN-32

5 x 5 x 0.8 mm body size

0.5 mm pitch

FAULT

NBASE

ILIM

CS2

VIN

15

16

EN

26

25

VCC

IAVE

20

21

17

18

19

22

23

24

Figure 1. Top View

32-Lead WQFN

Pin Descriptions

Pin Number

Pin Name

HG2

Description

1

2

3

4

Gate drive of the high-side N-channel MOSFET for Phase 2.

Switching node of the power stage of Phase 2.

SW2

LG2

Gate drive of the low-side N-channel MOSFETs for Phase 2.

VDD

Power supply for gate drivers. Decouple VDD to PGND with a ceramic capacitor. VDD can either be

supplied by an external 5V ±10% bus, or by the internal regulator, which uses an external NPN pass

device. If using the internal regulator, connect VDD to the emitter of the NPN pass device.

5

6

PGND

LG1

Power Ground. Tie PGND and SGND together on the board through the DAP.

Gate drive of the low-side N-channel MOSFETs for Phase 1.

Switching node of the power stage of Phase 1.

7

SW1

8

HG1

Gate drive of the high-side N-channel MOSFET for Phase 1.

Bootstrap of Phase 1 for the high-side gate drive power supply.

Power Good open-drain output. Active HIGH.

9

BOOT1

PGOOD

SYNCOUT

10

11

Synchronization Output. For multi-controller systems this pin should be connected to the SYNC pin of

the next controller in daisy-chain configuration

2

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Pin Descriptions (continued)

Pin Number

Pin Name

Description

12

SYNC

Synchronization Input. SYNCOUT of one controller is connected to SYNC of the next controller in a

daisy-chain fashion. To synchronize the whole chain of controllers to an external clock, wire the external

clock to the SYNC pin of the first controller of the chain (called the Master controller). Otherwise,

connect the SYNC input of the Master controller to ground and all of the controllers will be controlled by

the internal oscillator of the Master.

13

FAULT

Input/Output. Wire the FAULT pin of all controllers together. FAULT gets pulled Low during startup, an

over-current fault, or an over-voltage fault. FAULT = Low signals all controllers to stop switching and

prepare for the next startup sequence. The first LM3754 in the system (the Master) supplies the FAULT

pin pull-up current for all of the controllers.

14

15

16

NBASE

VIN

Connect to the base of external series-pass NPN if using the LM3754 internal LDO controller to

generate VDD. Otherwise leave unconnected.

Input Voltage. Connect VIN to the input supply rail used to supply the power stages. This input is used

to provide the feed-forward for the voltage control of V_OUTand for generating the internal VCC voltage.

VCC

Supply for internal control circuitry. Decouple VCC to PGND with a ceramic capacitor. When VIN > 5.5V,

the internal LDO will supply 4.35V to this pin. When 4.5V < VIN < 5.5V, connect VIN to VCC. In this

case the internal VCC LDO will turn off and VCC current will be supplied directly by VIN.

17

18

SGND

COMP

Signal Ground. Tie PGND and SGND together on the board through the DAP.

Error Amplifier Output. For the Master, a compensation network is placed between the COMP pin and

the FB pin. The COMP pin of the Master should be connected to the SNSP pin of each of the Slaves.

The COMP pin of each of the Slaves must be connected to its VDIF pin

19

20

21

22

23

24

FB

Feedback Input. This is the inverting input of the error amplifier. Connect the Master FB pin to the output

voltage divider and compensation network. Connect each Slave FB pin to its own VCC pin. This will put

that controller in Slave mode and disable its error amplifier.

VDIF

SNSM

SNSP

SS

Output of the remote-sense differential amplifier. Connect the Master VDIF pin to the output voltage

divider and compensation network. The Slave differential amplifier is used to buffer COMP from the

Master controller. Connect each Slave VDIF pin to its own COMP pin.

Inverting input of the remote-sense differential amplifier. Connect SNSM of the Master controller to

PGND at the load point. On Slave controllers, the differential amplifier is used to buffer COMP from the

Master controller. Connect SNSM of each Slave controller directly to the Master controller SGND pin.

Non-inverting input of the remote-sense differential amplifier. Connect the SNSP of the Master controller

to V_OUTat the load point. On Slave controllers, the differential amplifier is used to buffer COMP of the

Master controller. Connect SNSP of each Slave controller to the Master controller COMP pin.

Soft-Start. Connect the SS pins of all of the controllers in the system together. At the Master controller,

connect a soft-start capacitor between SS and SGND. Only the Master controller supplies the pull up

current to the SS capacitor.

FREQ

Frequency Adjust. A frequency adjust resistor and decoupling capacitor are connected between FREQ

and SGND to program the switching frequency between 200 kHz to 1 MHz (each phase). These

components must be supplied on the Master and Slaves, even if the system is synchronized to an

external clock.

25

26

IAVE

EN

Current Averaging. Connect a 4.02 kΩ, 1%, resistor between each controller’s IAVE pin and SGND. In

the case where one phase is not used, connect an 8.06 kΩ resistor. Connect a filter capacitor between

IAVE and SGND at each controller,

Enable Input. Used for VIN UVLO function, connect EN to the midpoint of a voltage divider from VIN to

SGND. The EN pins of all controllers must be wired together. For an on/off EN function, wire the EN

pins of all controllers together and control with an open drain output.

27

28

CS2

ILIM

Positive current-sense input of Phase 2. Connect to the DCR network or the current-sense resistor of

Phase 2. The negative current-sense input is the CSM pin.

Current Limit Set. Connect a resistor between ILIM and CSM. The resistance between ILIM and CSM

programs the current limit.

29

30

CSM

CS1

Negative current-sense input of the internal current-sense amplifiers. Connect to V_OUT.

Positive current-sense input of Phase 1. Connect to the DCR network or the current-sense resistor of

Phase 1. The negative current-sense input is the CSM pin.

31

32

PH

Phase Select Input. Connect this pin to the middle of a resistor divider between VCC and SGND to

program the number of phases in the system.

BOOT2

DAP

Bootstrap pin of Phase 2 for the high-side gate drive power supply.

Die Attach Pad. Must be connected to PGND and SGND but cannot be used as the primary ground

connection; do not place any traces or vias other than GND in the outer layer under the DAP; see

application note AN-1187 (literature number SNOA401).

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings⁽¹⁾⁽²⁾

VIN to SGND, PGND

−0.3V to 24V

−0.3V to 0.3V

+0.3V

SGND to PGND

VCC and VDD to VIN

VDD to PGND

−0.3V to 6V

PGOOD, FAULT to SGND

VCC, EN, SS, SYNC, CS1, CS2, CSM, ILIM, SNSM, SNSP to SGND

FREQ, PH, FB to SGND

BOOT1, BOOT2 to PGND⁽³⁾

SW1, SW2 to PGND⁽³⁾

−0.3V to 6V

−0.3 to VCC + 0.3V

−0.3V to 24V Peak

−0.3VDC to 24V Peak

−3V for less than 40 ns

BOOT1 to SW1,

BOOT2 to SW2⁽³⁾

−0.3V to 6.0V Peak

SYNCOUT

PGOOD, FAULT

VDIF

±20 mA

±5 mA

COMP

±4 mA

ESD Rating, HBM⁽⁴⁾

2 kV

Junction Temperature (T_J-MAX

Storage Temperature Range

)

+150°C

−65°C to +150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate

the conditions at which the device is functional and the device should not be operated beyond such conditions. For ensured

specifications and conditions, see the Electrical Characteristics table.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) Peak is the dc plus transient voltage including switching spikes.

(4) Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Applicable standard is JESD22-

A114C. All pins pass 2 kV HBM except VDD, VIN and VCC which are rated for 1.5 kV.

Operating Ratings⁽¹⁾

VIN Low Range

4.5V to 5.5V

5.5V to 18V

VIN High Range when using integrated VCC LDO

VIN High Range when using integrated VDD linear regulator controller

6V to 18V

VCC External Supply Voltage

VDD External Supply Voltage

Output Voltage Range

SYNC, EN

4.5V to 5.5V

0.6V to 3.6V

0V to 5.5V

SNSM

−0.25V to 1.0V

0V to 3.6V

SNSP to SNSM

IAVE

0V to 1.15V

CS1 and CS2 to CSM

CS1, CS2, ILIM and CSM to SGND

ILIM to CSM

−15 mV to 45 mV

0V to 3.6V

0V to 200 mV

−5°C to +125°C

Junction Temperature Range

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate

the conditions at which the device is functional and the device should not be operated beyond such conditions. For ensured

specifications and conditions, see the Electrical Characteristics table.

4

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Operating Ratings⁽¹⁾(continued)

Thermal Data

(2)

Junction-to-Ambient Thermal Resistance (θ_JA), WQFN-32 Package

26.4°C/W

(2) Tested on a four layer JEDEC board. Four vias provided under the exposed pad. See JEDEC standards JESD51-5 and JESD51-7.

Electrical Characteristics

Limits in standard type are for T_J= 25°C only; limits in boldface type apply over the junction temperature (T_J) range of −5°C to

+125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent

the most likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated V_VIN

12V, V_VDD= 5V, V_VCC= internal LDO, V_EN= 2V, R_FRQ= 78.7 kΩ, V_PH= 0V, V_CS1= V_CS2= V_CSM= V_SS= V_SNSP= 1.8V, V_ILIM

V_CSM= 100 mV, V_SNSM= V_SYNC= 0V, V_SYNCOUTfloating.

=

−

Symbol

System Accuracy

V_OUTOutput Voltage Accuracy

Parameter

Conditions

Min

Typ

Max

Units

V_OUT= 3.6V

V_OUT= 2.5V

V_OUT= 1.8V

V_OUT= 0.6V

–0.65

–0.75

–0.9

–0.11

–0.134

–0.165

–0.4

0.45

0.6

%

Includes trimmed EA and diff

amplifier offset and gain errors;

0.5 mA load at VDIF

0.7

–2.25

1.25

Phase Current Equalization

ΔI_PHCurrent Equalization (from

average per phase current)

V_CSM= 1.8V, V_CS1= V_CS2= V_CSM+ 30 mV,

V_IAVE= 740 mV, V_COMP= 1.9V

–12

12

%

System Supplies and UVLO

VIN

I_VIN

VIN Operating Current

2-phase switching gate drivers unloaded

15

9

mA

I_VIN-Q

VIN Quiescent Current

V_FB= 650 mV, no PWM switching,

NBASE is floating (no NPN)

18

I_VIN-SD

VIN Shutdown Current

V_EN= 0V

200

450

µA

VCC

V_VCC

I_VCC

I_VCC-SD

I_VCC-LIM

VCC Linear Regulator Output

Voltage

0 to 3 mA sourced to an external load;

V_VIN= 5.5V to 18V

4.25

4.35

10

4.45

20

V

VCC Input Current from External V_VIN= 5.5V, V_VCC= 5.5V

Supply

mA

µA

mA

VCC Input Shutdown Current

from External Supply

V_EN= 0V, V_VIN= 12V, V_VCC= 5V

260

VCC Output Current Limit

V_VCC= 2.5V

V_VCC= 0V

9

30

50

53

V_VCC-EN

VCC UVLO Thresholds

V_VCCRising

V_VCCFalling

4.04

3.9

4.14

4

4.24

4.1

V

V_VCC-HYS

t_D-VCC

VCC Threshold Hysteresis

140

8

mV

µs

VCC UVLO/UVP Debounce Time

VDD, NBASE, BOOT1, BOOT2, SW1, SW2

V_VDD

VDD Controller Regulation

Voltage

V_VIN= 6V to 18V

4.6

4.85

330

130

4

5.1

V

V_NBASE

VIN-to-NBASE Dropout

V_VIN− 5.5V, 700 mV source connected from

mV

VDD to NBASE, I_NBASE= 5 mA

V_VIN− 5.5V, 700 mV source connected from

VDD to NBASE, I_NBASE= 1 mA

V_NBASE-REG

I_VDD

NBASE Load Regulation

V_VIN= 18V, 700 mV source connected from

VDD to NBASE, I_NBASEsteps 1 mA to 5 mA

mV

mA

VDD Operating Current from

External Power Supply

V_VDD= V_VIN= V_VCC= 5.5V, f_SW= 300 kHz,

Gate Drivers unloaded

1

I_VDD-SD

VDD Shutdown Current

NBASE Current Limit

V_EN= 0V, V_VIN= 12V, V_VDD= 5V

V_NBASE= V_VDD+ 0.7V, ΔV_VDD= −100 mV

V_NBASE= V_VDD= 0V

2

30

µA

I_NBASE-CL

5.8

10

20

mA

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Electrical Characteristics (continued)

Limits in standard type are for T_J= 25°C only; limits in boldface type apply over the junction temperature (T_J) range of −5°C to

+125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent

the most likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated V_VIN

12V, V_VDD= 5V, V_VCC= internal LDO, V_EN= 2V, R_FRQ= 78.7 kΩ, V_PH= 0V, V_CS1= V_CS2= V_CSM= V_SS= V_SNSP= 1.8V, V_ILIM

V_CSM= 100 mV, V_SNSM= V_SYNC= 0V, V_SYNCOUTfloating.

=

−

Symbol

Parameter

Conditions

Min

Typ

Max

15

Units

I_BOOT-SD

BOOT1, BOOT2 Shutdown

Current

V_EN= 0V, V_SW1(2)= 0V, V_BOOT− V_SW= 5V

4.5

µA

I_BOOT

I_SW

BOOT1, BOOT2 Operating

Current

V_BOOT1(2)= 17.0V, V_SW1(2)= 12.0V, f_SW= 300

kHz, Gate Drivers unloaded

650

3

µA

SW1, SW2 Leakage Current with V_VCC= 0V, V_EN= 0V, V_SW1(2)= 3.6V

Pre-Biased Output

V_VDD-TH

VDD UVLO Thresholds

V_VDDRising

V_VDDFalling

3.8

4.02

3.71

310

11

4.28

4.03

V

3.37

V_VDD-HYS

t_D-VDD

VDD UVLO/UVP Hysteresis

mV

µs

VDD UVLO/UVP Debounce Time

Thermal Shutdown

T_J-SD

Thermal Shutdown Threshold

Rising

160

30

°C

T_J-HYS

Thermal Shutdown Threshold

Hysteresis

EN

V_EN-H

V_EN-L

HIGH Level Input Voltage

LOW Level Input Voltage

EN Threshold

1.51

V

1.14

1.51

1.35

V_EN-TH

V_VIN= 4.5V to 18V, V_VCC= 4.5V (Rising)

V_VIN= 4.5V to 18V, V_VCC= 4.5V (Falling)

1.26

1.14

1.39

1.25

140

0.1

V

V_EN-HYS

I_EN

EN Threshold Hysteresis

EN Input Bias Current

mV

µA

V_EN= 1.5V

V_EN= 1.0V

0.4

1.7

Reference, Feedback & Error Amplifier: FB, COMP

V_FB

FB Voltage Under Regulation

FB Voltage VIN Line Regulation

V_COMP= 1.8V

0.593

0.599

±0.01

±0.15

0.605

V

%

V_FB-REG1

V_FB-REG2

V_VIN= 5.5V to 18V

FB Voltage VCC Line Regulation V_VCC= V_VIN= V_VDD= 4.5V to 5.5V (same

source)

I_FB

FB Input Bias Current

45

130

nA

V

V_FB-PTH

FB Pin Master/Slave

3.2

Programming Threshold

A_OL

f_BW

DC Gain

FB to COMP, V_COMP= V_FB+ 1.0V

70

15

dB

Error Amplifier

R_COMP-SGND= 1.5 kΩ, C_COMP-SGND= 50 pF

MHz

Unity Gain Bandwidth

V_COMP-SLEW

V_COMP-REG

Error Amplifier Slew Rate

6

V/µS

mV

COMP Load Regulation,

Sourcing

V_COMP= 2.7V, ΔI_COMP= +1 mA, DC Gain =

40

−3

PWM Ramp and Input Voltage Feed-Forward

D_MAXMaximum Duty Cycle Controlled V_VIN= 6V, V_COMP= 3.5V

81

%

by Clock

D_FF

Duty Cycle Controlled by VIN

Feed-Forward

V_VIN= 9V, V_COMP= 2.2V

42

t_ON-MIN

V_RAMP-MIN

V_RAMP-MAX

V_RAMP

Minimum Controllable On-Time

PWM Ramp Range

50

1.3

2.8

1.5

ns

V

Ramp Minimum

Ramp Maximum

V

PWM Ramp Amplitude

V

6

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Electrical Characteristics (continued)

Limits in standard type are for T_J= 25°C only; limits in boldface type apply over the junction temperature (T_J) range of −5°C to

+125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent

the most likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated V_VIN

12V, V_VDD= 5V, V_VCC= internal LDO, V_EN= 2V, R_FRQ= 78.7 kΩ, V_PH= 0V, V_CS1= V_CS2= V_CSM= V_SS= V_SNSP= 1.8V, V_ILIM

V_CSM= 100 mV, V_SNSM= V_SYNC= 0V, V_SYNCOUTfloating.

=

−

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Differential Amplifier: SNSP, SNSM, VDIF

V_OS-INPUT

R_INPUT-SNSP

A_V-DIF

Input Offset Voltage

Input Resistance of SNSP

Gain

V_SNSP= 1.8V

3

30

1

mV

kΩ

V_SNSP= 0.6V to 3.6V

0.996

1.004

V/V

MHz

mV

f_BW-DIF

3dB Bandwidth

2

V_DIF-REG1

V_DIF-REG2

VDIF Load Regulation, Sourcing V_VDIF= 3.6V, I_VDIF= 0.5 mA

VDIF Load Regulation, Sourcing V_VDIF= 0.6V, I_VDIF= 0.5 mA

−3

Current-Sense, Current Limit and Hiccup Mode: CS1, CS2, CSM, ILIM

V_CS-OS

Current-Sense Input Offset

Voltage Range, V_CS1(2)– V_CSM

V_OUT= 1.8V

±2

mV

nA

µA

I_CS

CS1, CS2 Input Bias Current

V_CSM= 3.6V, V_CS1(2)− V_CSM= −15 mV and

+40 mV

−200

−450

200

450

240

V_CSM= 0.6V, V_CS1(2)− V_CSM= −15 mV and

+40 mV

I_CSM

I_CSL

CSM Input Source Bias Current

CS1+ CS2 + CSM + ILIM

V_CSM= 0.6V and 3.6V, V_CS1(2)− V_CSM= 40

mV

150

0.1

V_VCC= 0V, V_EN= 0V, V_CSM= V_CS1= V_CS2

=

Leakage Current with Pre-Biased V_ILIM= 3.6V

Output

f_BW-CS

3dB Bandwidth, CS1(2) to PWM

COMPARATOR Input

1.0

MHz

I_ILIM-SOURCE

V_CL

ILIM Source Current

V_ILIM= 0.6V to 3.6V, V_VIN= 5.5V

85

94

0

103

4.6

µA

Current Limit Threshold Voltage

V_ILIM= 0.6V to 3.6V, V_VIN= 5.5V

−2.5

mV

V_ILIM− V_CS1(2)

t_D-CL

Current Limit Comparator

Propagation Delay

V_CS1or V_CS2stepped from 0.9V to 1.1V, V_ILIM

= 1V

200

7

ns

t_D-ILIM

Master or Slave Fast Current

Limit Delay

V_FB= 280 mV, 1-phase over-current:

V_CS1OR V_CS2> V_ILIM

Switch

cycles

V_FB= 280 mV, 2-phase over-current:

V_CS1AND V_CS2> V_ILIM

3

Switch

cycles

t_D-HICCUP

Master or Slave Over-Current

Hiccup Mode Delay

1-phase over-current:

V_CS1OR V_CS2> V_ILIM

446

223

6

Switch

cycles

2-phase over-current:

V_CS1AND V_CS2> V_ILIM

Switch

cycles

t_D-COOL-DOWNHiccup Over-Current Cool-Down

Time

ms

Power Good: PGOOD, OVP, UVP

V_OVP

OVP Threshold

V_FBrising edge

V_FBfalling edge

125

75

130

2

135

85

%V_FB

ms

t_D-RESTART

N_OVP-LATCH

OVP Restart Delay

Number of OVP Events Before

Latch-Off

7

V_UVP

UVP Threshold

80

25

5

%V_FB

mV

µs

V_UVP-HYS

t_D-OVP/UVP

V_PG-LO

UVP Threshold Hysteresis

OVP/UVP Debounce Time

PGOOD Low Level

I_PGOOD= −4 mA

0.14

5

0.25

300

V

I_PG-LEAK

PGOOD Leakage Current

V_PGOOD= 5.5V

nA

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Electrical Characteristics (continued)

Limits in standard type are for T_J= 25°C only; limits in boldface type apply over the junction temperature (T_J) range of −5°C to

+125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent

the most likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated V_VIN

12V, V_VDD= 5V, V_VCC= internal LDO, V_EN= 2V, R_FRQ= 78.7 kΩ, V_PH= 0V, V_CS1= V_CS2= V_CSM= V_SS= V_SNSP= 1.8V, V_ILIM

V_CSM= 100 mV, V_SNSM= V_SYNC= 0V, V_SYNCOUTfloating.

=

−

Symbol

FAULT

Parameter

Conditions

Min

Typ

Max

Units

I_FAULT

Internal Pullup Current in Master

Mode

325

µA

V_OL-FAULT

V_OH-FAULT

FAULT Output Low Level

FAULT Output High Level

I_FAULTsinking 500 µA

I_FAULTsourcing 50 µA

0.21

V

VCC −

0.1

Oscillator and Synchronization (PLL): SYNC, SYNCOUT, FREQ

f_SW-MIN

f_SW-MAX

f_SW

Minimum Switching Frequency

Maximum Switching Frequency

Switching Frequency Accuracy

R_FRQ= 121 kΩ

R_FRQ= 21.3 kΩ

R_FRQ= 78.7 kΩ

200

1000

300

±25

1.46

1.3

kHz

%

282

318

f_SYNC

SYNC Frequency Capture Range 200 kHz to 1 MHz

SYNC Rising Threshold

V_SYNC-RISE

V_SYNC-FALL

t_SYNC-MIN

I_SYNC

1.68

V

SYNC Falling Threshold

1.12

V

SYNC Minimum Pulse Width

150

ns

SYNC Bias Current

V_SYNC= 0 to 5.5V

−15

25

µA

(internal or external VCC)

V_SYNCOUT-HISYNCOUT Logic High Level

Sourcing 10 mA, V_VCC= 4.5V external

VCC −

0.42

V

V_SYNCOUT-LOSYNCOUT Logic Low Level

Sinking 10 mA, V_VCC= 4.5V external

0.48

PH_RATIO

V_PH/V_VCCDivider Ratio to Set

Phase Number

2 & 4 Phases

3 Phases

0

0.138

0.279

0.418

0.562

0.703

0.844

0.152

0.294

0.438

0.587

0.730

0.874

−150

3/14

5/14

7/14

9/14

11/14

1

5 Phases

6 Phases

8 Phases

10 Phases

12 Phases

I_PH

PH Bias Current

V_VCC= 4.5V forced, V_PH= 0 to V_VCC

150

nA

°

Φ_HG1-N2

HG1 to HG2 Phase Shift for 2, 4,

6, 8, 10 or 12-Phase Modes

180

240

216

Φ_HG1-N3

Φ_HG1-N5

Φ_SYNC

HG1 to HG2 Phase Shift for 3-

Phase Mode

°

HG1 to HG2 Phase Shift for 5-

Phase Mode

SYNC to SYNCOUT Phase Shift N > 2

for N-phase Operation

360/N

90

N = 2

t_SYNC-ERR

SYNC to SYNCOUT Phase Shift

Error

5

ns

t_SYNC-HG

SYNC to HG1(2)

165

5

ns

°

Φ_HG-ERR

HG1 and HG2 Controller-to-

Controller Phase Delay Error

300 kHz, 6-phase

Soft-Start: SS, Pre-Biased Startup

I_SS

SS Source Current

V_SS= 0.3V

5.7

10

14.6

µA

Ohm

ns

R_DS-SS

t_LG-PW1

Soft-Start Pull-Down Resistance

750

460

First LG High Pulse Width during

Soft-Start

8

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Electrical Characteristics (continued)

Limits in standard type are for T_J= 25°C only; limits in boldface type apply over the junction temperature (T_J) range of −5°C to

+125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent

the most likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated V_VIN

12V, V_VDD= 5V, V_VCC= internal LDO, V_EN= 2V, R_FRQ= 78.7 kΩ, V_PH= 0V, V_CS1= V_CS2= V_CSM= V_SS= V_SNSP= 1.8V, V_ILIM

V_CSM= 100 mV, V_SNSM= V_SYNC= 0V, V_SYNCOUTfloating.

=

−

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t_LG-GT

LG Asynchronous-to-

Synchronous Gradual Transition

Time

2

ms

t_D-EN-SW

EN-to-Switching Delay

Delay from EN = High to FAULT = High; no

pre-bias

2

ms

Gate Drivers

I_PK-HG-SOURCEHG1 and HG2 Peak Source

Current

Less than 100 ns

1.9

2.5

A

R_HG-SOURCE

HG1 and HG2 Source

Resistance

V_BOOT− V_SW= 5V

Ω

I_PK-HG-SINK

R_HG-SINK

HG1 and HG2 Peak Sink Current Less than 100 ns

HG1 and HG2 Sink Resistance _BOOT− V_SW= 5V

Less than 100 ns

4

1

A

Ω

A

V

I_PK-LG-SOURCELG1 and LG2 Peak Source

Current

2.3

R_LG-SOURCE

I_PK-LG-SINK

R_LG-SINK

LG1 and LG2 Source Resistance

2

4

Ω

A

LG1 and LG2 Peak Sink Current Less than 100 ns

LG1 and LG2 Sink Resistance

1

Ω

R_HG-PULLDOWNHG-SW Pull-Down Resistor

R_LG-PULLDOWNLG-PGND Pull-Down Resistor

16

30

kΩ

ns

t_D-HG-LG

HG Falling to LG Rising Cross-

Conduction Protection Delay

(Dead-Time)

SW node not switching

SW node switching

t_D-LG-HG

LG Falling to HG Rising Delay

28

10

ns

t_DS-HG-LG

HG Falling to LG Rising Cross-

Conduction Protection Delay

(Dead-Time)

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Typical Performance Characteristics

System Accuracy vs V_OUT

f_SWvs Temperature

Figure 2.

Figure 3.

V_REFDeviation

R_FRQvs f_SW

Figure 4.

Figure 5.

V_REFvs Temperature

Load Step (High Slew)

1.8V

V_OUT50 mV/Div

I_OUT30A/Div

20 µs/Div

Figure 6.

Figure 7.

10

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Typical Performance Characteristics (continued)

Startup from 0V

Over-Voltage Fault

Over Voltage pulse

200 mV/DIV injected into FB

EN 2V/DIV

PGOOD 1V/DIV

V_OUT500 mV/Div

SS 500 mV/DIV

FB

V

OUT

1.5V/DIV

500 mV/Div

2 ms/DIV

2 ms/Div

Figure 8.

Pre-Biased Output Startup

Figure 9.

Repeated Over-Voltage Conditions

EN 2V/Div

Over Voltage pulse 200 mV/Div added to FB

V_OUT

0.5V/

Div

SS 500 mV/Div

V_OUT500 mV/Div

V_OUT= 600 mV

FB

0.5V/

Div

2 ms/Div

10ms/Div

Figure 10.

Figure 11.

Over-Current Fault (Soft Short)

OC PULSE 5V/DIV

R_ILIMV_OUT

ILIM

OC

R = 18

kꢀ

PULSE

V_OUT

0.5V/DIV

2 ms/DIV

Figure 12.

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Block Diagram

VCC

BOOT2

32

PWM

COMPARATOR

HG2

I_AVE1= 2 mA/V

VCC

COMP

1

SW2

2

+

-

DRIVER

CONTROL

DEADTIME

CONTROL

A = 50

+

I_AVE2= 2 mA/V

OV Fault

OC Fault

Prebias

+

VDD

IAVE

25

PWM 2

LG2

3

A = 3.125

PGND

480 mV

ILIM

UVP

OVP

CURRENT LIMIT

COMPARATOR

VCC

CS2

CSM

I_SS= 10 mA

CURRENT SENSE

AMPLIFIER

27

V_CS2- V_CSM+ 15 mV

780 mV

Closed for

-

+

Master Controller

A = 1

15 mV

BOOT1

VCC - 1.2V

MASTER

9

8

7

PWM

COMPARATOR

COMP

HG1

SW1

Closed for

Master Controller

+

-

COMP

18

A = 50

+

DRIVER

CONTROL

DEADTIME

CONTROL

OV Fault

+

OC Fault

Prebias

VDD

PWM 1

VDD

LG1

6

5

4.02V

FB

SS

PGND

19

23

VCC

VREF = 0.6V

BANDGAP

REFERENCE

I_FAULT

= 300 mA

4.14V

VCC

I_ILIM= 100 mA

POWER_OK

Closed for

Master

Controller

OVER

TEMP

CURRENT LIMIT

COMPARATOR

STARTUP AND

FAULT LOGIC

ILIM

CS1

28

30

29

K_FF= 0.232 V/V

VIN

VIN FEED-FORWARD

15

26

CURRENT SENSE

AMPLIFIER

2.8V

1.3V

PWM 1

2.8V

1.3V

PWM 2

REGULATORS,

SUPPLY UVLO

V_CS1- V_CSM+ 15 mV

CSM

+

EN

VCC

-

OSCILLATOR, PLL,

PWM RAMP

DIFFERENTIAL

AMPLIFIER

A To D

A = 1

15 mV

VDD

R

1.39V

VCC

+

-

VCC

R

VCC NBASE

SNSP

22

PGOOD FAULT

10

13

VDD

FREQ SYNC

24 12

SYNCOUT

SNSM

VDIF SGND

20

PH

4

16

14

11

21

31

17

12

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Functional Description

General

The LM3754 is a two-phase voltage-mode step-down (buck) switching regulator controller. From one to six

LM3754 controllers can be connected together to control from two to twelve phases (2, 3, 4, 5, 6, 8, 10, or 12

phases). Since external switching components can typically handle 25A per phase, a 12 phase system can

supply a total of 300A.

Multiple controllers in a system communicate with each other and work together. They will startup and shut down

together, each phase on each controller will share current equally, and all the phases will react in unison to fault

conditions. In a multi-controller system, all controllers are the same part. One controller functions as the Master

and all the others act as Slaves. The Master and Slave are differentiated by how they are connected in the

system. The Master controller senses the system output voltage and VIN (as well as SS) and sets the target duty

cycle for each phase on all of the controllers. The Master and Slave controllers monitor the current-sense

information from each phase. Based on this current information, the controllers adjust the duty cycle on each

phase up or down from the target level, in order to achieve optimal current sharing.

Each controller incorporates a phase locked loop (PLL) that communicates with the PLLs on the other

controllers. By this means, the switching edges of the different phases are spread out equally within one switch

period. For N phases operating at any switching frequency, the angle in degrees between one phase switching

and the next is 360° / N. A SYNC pin is available that can be used to lock the Master switching frequency and

phase to an external clock.

The LM3754 has a Soft-Start function. The Master controller sources 10 µA out of the SS pin so that the output

voltage rise time is controlled by the size of the external SS capacitor. The LM3754 will not pull down a pre-

biased load. The synchronous NFET switch is not turned on during the soft-start cycle until the SS ramp exceeds

either the FB voltage or the internal reference voltage VREF. At this point a gradual transition to synchronous

switching is initiated.

Control Algorithm

The control architecture is primarily voltage-mode. An error amplifier amplifies the difference between the FB pin

voltage and the internal reference voltage to generate a COMP signal. This signal is compared against a ramp

that consists of a fixed value plus a term proportional to VIN which controls the duty cycle. In order to facilitate

current sharing there is an inner current-sense loop. Information for the current through the inductor in each

phase is sensed either with a sense resistor or with a DCR arrangement which uses the DC resistance of the

inductor. This current-sense signal is connected to the CS pin (CS1 or CS2). The negative reference for current-

sense is V_OUTwhich is common for both phases and connected to the controller’s CSM pin. The controller

amplifies the (CS1(2) – CSM) voltage difference for each phase, and compares it to the voltage on the IAVE pin,

which tracks the average current of all phases. Any phase whose current is more than the average has its duty

cycle decreased and vice versa. The IAVE signal is common to all controllers in a system. Each controller

outputs a current onto the IAVE bus so that the total current on the bus is the sum of the current signals from all

of the phases. An external resistor to ground translates this current signal to a voltage, which all of the controllers

read back.

The LM3754 includes an uncommitted differential amplifier. On the Master controller this amplifier is used to

remotely sense the converter’s output voltage, typically at the load. On the Slave controllers this amplifier is used

to buffer the Master controller’s COMP signal and level shift it to the Slave controller’s local ground.

Power Connections

The LM3754 has three supply pins, which are VIN, VCC, and VDD. It employs two ground pins, SGND and

PGND. VDD and PGND are the power and ground for the gate driver stage that controls the HG and LG pins.

The quiescent current drawn by VDD is very small – around 1 mA. To predict the VDD current requirement one

can assume it is mostly switching current and use the standard formula:

I_VDD= (1 or 2) x f_SWx Q_{TOTAL_PHASE}

(1)

Q_{TOTAL_PHASE}is the sum of the high-side switch gate charge and the low-side gate charge. The (1 or 2) factor

corresponds to one or two phases running. The low-side driver is powered directly from VDD. The high-side

driver draws its power from VDD through the external bootstrap Schottky diode. The rest of the controller is

powered by VCC and SGND.

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The LM3754 has two on-board regulators, one to generate VCC and one to generate VDD. The VCC regulator is

self-contained and only needs a 4.7 μF ceramic capacitor to SGND. The VDD regulator uses an external NPN

pass device. This device should be sized to meet the VIN to VDD dropout requirements for the calculated I_VDD

.

The collector of this device goes to VIN, the base goes to NBASE and the emitter goes to VDD. VDD also needs

a 4.7 µF bypass capacitor to PGND. The internal VIN to NBASE dropout is approximately 300 mV. The minimum

VIN is calculated as:

VIN_MIN= VDD_MIN+ V_{BE_NPN}+ 300 mV

VDD_MIN= MAX(VDD_UVLO, V_GATE-MIN

(2)

(3)

)

VDD_UVLOis the controller’s maximum VDD under-voltage lockout voltage, which is 4.06V. V_GATE-MINis the

minimum required gate drive voltage for the power MOSFET switches. VIN_MINis typically 5.5V to 6.0V. For VIN

less than 5.5V, the regulators are omitted and the VCC and VDD pins are connected as shown in Figure 15.

V

IN

18V > V > 6V

IN

2.2W

V

IN

NBASE

VDD

BOOT1

BOOT2

1 mF

VCC

4.7 mF

SGND

PGND

Figure 13. Power Connections Using the Internal Regulator

V

IN

18V > V > 5.5V

IN

Optional Schottky

(if 5V Rail is up when V is off)

IN

2.2W

5V Rail

VIN

N/C

NBASE

VDD

BOOT1

BOOT2

1 mF

VCC

4.7 mF

SGND

PGND

Figure 14. Power Connections Using a System 5V Rail

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V

IN

V

= 5V +/- 10%

IN

2.2W

VIN

N/C

NBASE

VDD

BOOT1

BOOT2

1W

1 mF

VCC

4.7 mF

SGND

PGND

Figure 15. Power Connections for V_IN= 5V

Under-Voltage Lockouts and Enable

The LM3754 controller has internal under-voltage lockout (UVLO) detection on the VCC and VDD supplies. The

under-voltage lockout on VIN is set using the EN pin threshold. Connect a voltage divider between VIN and

SGND with the midpoint going to the EN pin. The division ratio and the EN pin threshold determine the VIN level

that enables the controller. This divider should be used in all cases. If the system does not have a particular VIN

under-voltage lockout requirement, the level is set to be below the minimum VIN level at the worst case

combination of tolerances and operating conditions.

V_{IN_UVLO}

R_UV2

R_UV1

- 1

=

V_EN

(4)

To ensure startup at the lowest input voltage, set the divider to the V_EN-THrising max specification. For a higher

accuracy VIN UVLO operation, the resistor divider minimum current should be 1 mA or higher. This will reduce

the threshold error contribution of the EN pin bias current, which is specified to be less than 1.7 µA over

temperature. The enable pin can also be used as a digital on-off. To do this, the enable signal should be used to

pull down the midpoint of the voltage divider using open-drain logic or a transistor. A customary implementation

uses an external MOSFET.

V

IN

R

UV2

EN

EXT_EN

R

UV1

Figure 16. Input Voltage UVLO with External Enable

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While the EN pin has a threshold hysteresis of 140 mV typical, a small noise-filtering capacitor may be added

between the EN pin and SGND. This is particularly useful when the controller is turning on via the resistor divider

by a slowly rising VIN rail.

Startup Sequence

When EN is below its threshold, the internal regulators are off and the controller is in a low power state. When

EN crosses above its threshold the VCC regulator turns on. When VCC rises above its under-voltage lockout

threshold the VDD regulator turns on. When VDD rises above its under-voltage lockout threshold the controller is

ready to start.

If VDD or VCC is supplied externally and already sitting above its under-voltage lockout point, then the controller

is ready for startup as soon as EN crosses above its threshold. Anytime VCC or VDD drops below its UV

threshold, switching stops and the controller goes into a standby state. It will go through normal startup once the

supplies recover.

When the controller is ready to start, it reads the voltage on the PH pin and determines how many phases are

running in the system. By this means the phase delay from SYNC to SYNCOUT through the PLL is configured.

Following this the oscillator and PLL turn on and pulses will be observed on SYNCOUT.

A 2 ms timer is initiated so that all of the PLLs in the system can synchronize up. As each controller times out, it

stops pulling its FAULT pin low. At the end of this sequence, the FAULT bus rises and the controllers are ready

to switch.

The error amplifier uses a different input stage when SS is below VREF. During normal operation the error

amplifier employs a low offset bipolar input stage. At startup, the input bias current of this stage is large enough

in relation to the soft-start current to affect the soft-start timing. A MOS input stage is used during the soft-start or

track phase which has a lower input bias current but a higher input offset voltage. A 40 mV offset is introduced

when SS is less than 70 mV. This offset forces the error amplifier output to be low during startup. The offset

transitions progressively to zero as SS moves from 0 to 70 mV.

Soft-Start

The LM3754 implements a soft-start function, and operates so as to prevent discharge of a pre-biased output.

The error amplifier amplifies the minimum of VREF or SS at the FB pin. By means of the closed loop regulation

through the switching stage, FB will be regulated to SS. The Master controller sources 10 µA onto the SS pin,

while the Slaves do not source any current. This sets the total soft-start current in a multi-controller system to 10

µA.

The SS pin is automatically pulled down to SGND prior to the onset of switching and during a restart from a fault

condition. When SS is initially released, COMP is low and no switching occurs. Both LG and HG are held low

while SS is below FB, which ensures that a pre-biased load will not be pulled down. When SS crosses above

either FB or VREF, COMP will slew up and switching will start. The first switching pulse is a 300 ns LG pulse to

charge the external HG bootstrap capacitor. After this the LG pulse width is reduced to zero. This insures that

V_OUTdoes not get pulled down while COMP slews up and the system loop is settling. Pulses on HG cause the

high-side FET to turn-on so that FB tracks the SS pin as it slews up. During the switch cycle off-time the inductor

current can only flow through the body diode of the synchronous switch. During each successive cycle the LG

pulse width gradually increases. Over the course of 0.3 ms to 2.0 ms, depending on the amount of pre-bias, LG

pulses get longer until full synchronous switching occurs. The internal timer waits 2 ms, regardless of duty cycle,

for this transition in LG pulse width to complete.

Following this PGOOD goes high if FB is above the output under-voltage threshold on the Master, SS is above

VREF, no fault conditions are present, and SYNC is toggling on the Slaves.

Phase Number Selection

The voltage at the PH pin determines the phase shift between the two phases of each controller and also the

phase shift between the SYNC and SYNCOUT pulses in a Master-Slave configuration. This voltage is read at

startup and the resulting phase configuration saved. The PH pin should be connected to the center of a resistor

divider between VCC and SGND to select and program the required number of phases and the corresponding

phase delays per Table 1. Each controller requires the same resistor divider at the PH pin.

16

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V

CC

R

PH1

PH

R

PH2

Figure 17. Phase Selection

Table 1. Phase Divider Resistors

Number Of Phases

Divide Ratio Target

R_PH1

R_PH2

(± 1%)

2 & 4 Phases

3 Phases

5 Phases

6 Phases

8 Phases

10 Phases

12 Phases

0.000

0.214

0.357

0.5

Omit

7870Ω

6490Ω

4990Ω

3570Ω

2150Ω

0

2150Ω

3570Ω

4990Ω

6490Ω

7870Ω

Omit

0.643

0.786

1

Over-Current and Over-Voltage Faults

If any controller experiences a fault condition, it will pull the FAULT bus low and all of the controllers will stop

switching. From the time when EN is low to the point where FAULT rises, both HG and LG are low so that the

SW node of each phase is floating. The FAULT input may be pulled low externally through an open drain

MOSFET to disable the system.

The LM3754 employs cycle-by-cycle current limiting. This occurs on each phase for both Master and Slave

controllers. The current (that is the CS1(2) − CSM voltage) is continuously compared to the over-current set point

(ILIM − CSM). Any time that the current-sense signal exceeds current limit, the cycle is ended.

In order to determine that a current fault has occurred, each controller counts the number of over-current pulses.

When the sum of the counts for phase 1 and phase 2 reaches 446 an over-current fault is declared. The counter

is reset after 16 consecutive switching cycles with no over-current on either phase.

There is a second method for achieving an over-current fault, which is meant to react to heavy shorts on V_OUT

.

The Master controller will determine that an over-current fault has occurred after 7 over-current cycles if the

voltage at the FB pin is less than 50% of its target value. This feature is disabled during startup. Since the Slave

controllers do not see the FB voltage, they cannot detect this type of fault.

Any controller which sees an over-current fault will respond by pulling the FAULT bus low. All of the controllers

will react and stop switching. Both HG and LG on each phase will be pulled low. The inductor current in each

phase will decay through the body diodes of the low-side switches. The controller which recognized the over-

current fault will hold FAULT low for 6 ms, which determines the hiccup time. This allows the energy stored in the

inductors to dissipate. After this, FAULT is released and all of the controllers will restart together.

The restart after fault process for the LM3754 is the same as the initial startup process. SS is pulled low and the

system will go through a full soft-start cycle. Switching will resume when SS crosses above FB.

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Over-voltage faults are only recognized by the Master controller. About 5 µs after FB crosses above the OVP

threshold, which is 30% above VREF, the Master controller declares an over-voltage fault. It pulls the FAULT bus

low and all of the controllers stop switching, with HG being low and LG being high. The low-side MOSFETs pull

V_OUTdown to remove the over-voltage condition. As soon as FB crosses below the under-voltage detect point,

which is 20% below VREF, the LG outputs go low to turn off the low-side MOSFETs. This prevents the negative

inductor current from ramping too high. The Master controller then waits 2 ms to allow any negative inductor

current to transition into the high-side MOSFETs body diodes.

The restart from an over-voltage fault is the same as the restart from an over-current fault. In addition there is an

over-voltage fault counter. On the seventh over-voltage fault, the system does not restart. It waits for power or

EN to be cycled. This counter is reset to zero when power goes low or EN crosses below its threshold.

PGOOD and PGOOD Delay

PGOOD is an open-drain logic output. It is asserted HIGH when the output voltage level is within the PGOOD

window, which is typically −20% to +30%. In order to operate, the PGOOD output requires a pull-up resistor to an

appropriate supply voltage. This voltage is typically the supply for an external monitoring circuit. The resistor is

selected so that it limits the PGOOD sink current to less than 4 mA.

PGOOD is delayed from either power-up or VIN under-voltage lockout, and has three primary factors:

1) A synchronization delay, set to 2 ms after the slowest controller in the system recognizes a valid level on

EN, VCC and VDD. This delay is timed out internally and allows for the phase lock loops to synchronize.

2) Soft-Start up, in non-fault conditions.

3) Transition period from diode emulation mode to fully synchronous operation, set to 2 ms.

Current Sense and Current Limit

The LM3754 senses current to enforce equal current sharing and to protect against over-current faults. There are

two system options for sensing current; a current-sense resistor, or a DCR configuration which uses the DC

resistance of the inductor. The current-sense resistor is more accurate but less efficient than the DCR

configuration.

The input range of the differential current-sense signal (CS1(2) – CSM) is from −15 mV to +40 mV. The common

mode range is the same as the controller’s output range which is 0V to 3.6V. Two considerations determine the

value of the current-sense resistor. If the resistor is too large there is an efficiency loss. If it is too small the

current-sense signal to the controller will be too low. Choose a resistor that gives a full load current-sense signal

of at least 25 mV. This is typically a resistor in the 1 mΩ to 2 mΩ range. The current-sense resistor is inserted

between the inductor and the load. The load side of the resistor which is V_OUT, is connected to CSM, the

negative current-sense input. This is the negative current-sense reference for both phases. The positive side of

the current-sense resistor goes to CS1(2).

For the DCR configuration a series resistor-capacitor combination is substituted for the current-sense resistor.

The resistor connects to the switch node (SW) and the capacitor connects to V_OUT. CSM is connected to V_OUTas

with the sense resistor. CS1(2) is connected to the center point of the resistor and capacitor, so that the current-

sense signal is developed across the capacitor. The voltage across the capacitor is a low pass filtered version of

the voltage across the resistor-capacitor combination, in the same way the current through the inductor is a low

pass filtered version of the voltage applied across the inductor and its intrinsic series resistance. Choose the

DCR time constant (R_DCRx C_DCR) to be 1.0 to 1.5 times the inductor time constant (L / R_L). R_DCRis selected so

that the CS pin input bias current times R_DCRdoes not cause a significant change in the CS voltage. The inductor

time constant and the DCR time constant will skew over temperature since the components have different

temperature coefficients. Critical applications may employ a correction circuit based on a positive temperature

coefficient thermistor (PTC).

The over-current limit is set by placing a resistor between ILIM and CSM. The value of the resistor times the ILIM

current of 94 µA sets the over-current limit.

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Current Sharing and Current Averaging

The current sharing works by adjusting the duty cycle of each phase up or down to make the phase current

equal to the average current. The maximum duty cycle shift is ±20%.

To determine the average current, each phase sources a current onto the IAVE bus proportional to its load

current as measured by the current sense amplifier connected to the CS1(2) and CSM pins. The IAVE pins of all

controllers are connected together and a resistance of 8 kΩ per phase (parallel) to SGND provides the proper

voltage level for the IAVE bus. Each phase compares its current sense output to the IAVE bus and sums the

resultant voltage into the common COMP signal to adjust the duty cycle for optimum current sharing.

IAVE forms the current sharing bus for the entire power converter. The IAVE pins of all controllers must be

connected together. Filter capacitors with a time constant of R_AVx C_AV= 1 / f_SWare connected between IAVE

and SGND of each controller. The parallel combination of the filter capacitors times the summing resistors (one

set per controller) forms the time constant of the current sharing bus.

Error Amplifier and Loop Compensation

The LM3754 uses a voltage mode PWM control method. This requires a TYPE III or 3 pole, 2 zero compensation

for optimum bandwidth and stability. The error amplifier is a voltage type operational amplifier with 70 dB open

loop gain and unity gain bandwidth of 15 MHz. This allows for sufficient phase boost at high control loop

frequencies without degrading the error amplifier performance.

The error amplifier output COMP connections are different for Master and Slave controllers. For the Master, a

compensation network is placed between the COMP pin and the FB pin. The COMP pin of the Master is

connected to the SNSP pin of each Slave. The SNSM pin of each Slave is connected to the bottom of the Master

feedback divider at SGND. The COMP pin of each Slave is connected to its corresponding VDIF pin. This

provides sufficient buffering of the master COMP signal for the internal summing of the current averaging circuit.

Oscillator and Synchronization

A resistor and decoupling capacitor are connected between FREQ and SGND to program the switching

frequency between 200 kHz to 1 MHz. These components must be supplied on each controller, even if the

system is synchronized to an external clock.

The switching frequency and synchronization are controlled by the Master. The Master can switch in a free-

running mode or be synchronized to an external clock. To synchronize the Master apply the external clock to the

SYNC pin of the Master, otherwise ground this pin. The amplitude of the signal on the SYNC pin must be limited

to be between 0V and VCC.

The value of the frequency setting resistor is determined as:

1

- 142 ns

f_SW

R_FRQ

=

40.56 pF

(5)

A 1000 pF ceramic capacitor is used to provide sufficient decoupling. If the Master is synchronized set the

resistor according the nominal applied frequency. If the signal on the SYNC pin is below 150 kHz the signal will

be ignored and the device will revert to free-running mode. The SYNCOUT signal from the Master is applied to

the first Slave’s SYNC pin. The SYNCOUT pin of the first Slave is connected to the SYNC pin of the second

Slave, and so on, in a daisy chain configuration. SYNCOUT of the last Slave (or the Master in a single controller

system) is left unconnected.

The configuration of the system, namely the number of controllers and phases is programmed by the voltage on

the PH pin. For each controller connect the midpoint of a resistor divider between VCC and SGND to the PH pin.

The division ratios are given in the Electrical Characteristics table and nominal resistor values in Table 1. This

sets the phase shift between SYNC and the SYNCOUT pin. Where an even number of phases (N) are

employed, the phase delay from SYNC to SYNCOUT is 360°/N. The phase difference between the two phases

on the same controller is 180°. For systems with an odd number of the phases, the HG2 and LG2 gate drivers on

the last Slave are unconnected and the phase arrangement is set according to Table 1

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Duty Cycle Limitation

The minimum controllable on-time is typically 50 ns. This limits the maximum V_IN, V_OUTand f_SWcombination.

f_SW< (V_OUT/ V_IN) x 20 MHz

(6)

(7)

The maximum specified duty cycle is 81%. This limits the minimum V_INto V_OUTratio.

(V_OUT/ V_IN) x 1.25 < 0.81

The 1.25 term allows margin for efficiency and transient response.

Thermal Shutdown

The internal thermal shutdown circuit causes the PWM control circuitry to be reset and the NFET drivers to turn

off all external power MOSFETs. The controller remains enabled and all bias circuitry remains on. After the die

temperature falls below the lower hysteresis point, the controller will restart.

NFET Synchronous Drivers

The LM3754 has two sets of gate drivers designed for driving N-channel MOSFETs in a synchronous mode.

Power to the high-side driver is supplied through the BOOT pin. For the high-side gate HG to turn on the high-

side FET, the BOOT voltage must be at least one V_GSgreater than VIN. This voltage is supplied from a local

charge pump which consists of a Schottky diode and bootstrap capacitor, shown in Figure 18. For the Schottky,

a rating of at least 250 mA and 30V is recommended. A dual package may be used to supply both BOOT1 and

BOOT2 for each controller.

Both the bootstrap and the low-side FET driver are fed from VDD. The drive voltage for the top FET driver is

about VDD − 0.5V at light load condition and about VDD at normal to full load condition.

D

BOOT

C

BOOT

VDD

BOOT

V

IN

HG

V

OUT

LM3754

SW

LG

+

Figure 18. Bootstrap Circuit

Remote Sense Differential Amplifier

The differential amplifier connected internally to the SNSP, SNSM and VDIF pins is a single stage unity gain

Instrumentation amplifier. The differential gain is tightly controlled to within 0.4%.

R

SNSP

+

VDIF

R

SNSM

-

R

Figure 19. Differential Amplifier

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On the master controller, the differential amplifier is used to provide Kelvin sensing of the output voltage at the

load. This provides the most accurate sampling for load regulation.

On the slave controllers, the differential amplifier is used to sense the COMP signal of the master controller with

respect to its signal ground and drive the COMP pin of that slave controller relative to its local signal ground. This

allows the master controller to accurately provide the target duty cycle of the slave controllers.

The differential amplifier has a low output impedance to allow it to drive the COMP pins of the Slave controllers.

This is necessary because the current sense signal is internally added to COMP to provide the duty cycle

adjustment for phase-to-phase current sharing.

APPLICATION INFORMATION

Number of Phases

The number of phases can be calculated by dividing the maximum output load current by 25A. Therefore a 120A

load requirement will need at least 5 phases, or 3 controllers. It may be better to use 6 phases which will still

require 3 controllers, but will reduce the maximum current/phase to 20A. Increasing the number of phases will

also reduce the output voltage ripple and the input capacitor requirements. Note that the 25A/phase is dictated

by external components and not by the LM3754. After the number of phases has been chosen, the PH pin on

each controller should be programmed as discussed in the Functional Description under Phase Number

Selection. The same number of phases must be selected for each controller.

Powering Options

The power connections will be determined by the VIN range and the availability of an external 5V rail. This is

discussed in detail in the Functional Description under Power Connections. For 12V input systems, the use of an

external 5V rail to power the VDD bus can improve overall system efficiency.

Multi-Controller Systems

For systems with more than 2 phases, there will be one controller configured as the Master and from 1 to 5

controllers configured as Slave.

The Master controller uses the differential amplifier to sense the output voltage at the load point. It also provides

the common COMP signal used by all controllers, provides the loop compensation and synchronizes the system

clock to an external clock if one is provided.

The SYNCOUT of the Master is connected to the SYNC input of the first Slave controller.

The Slave controllers are configured by tying the FB input to the VCC pin of that controller. Each Slave uses the

differential amplifier to sense the COMP signal of the Master controller and drive its own COMP input. The

SYNCOUT of each Slave controller is connected to the SYNC input of the next Slave controller.

All controllers have the same parallel RC components connected from the FREQ pin to local ground

corresponding to the desired system clock even if synchronizing to an external clock.

Common connections for all controllers:

1) IAVE (each controller will have a parallel RC filter to local ground).

2) FAULT

3) EN

4) SS

5) PGOOD

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Soft-Start

To avoid current limit during startup, the soft-start time t_SSshould be substantially longer than the time required

to charge C_OUTto V_OUTat the maximum output current. To meet this requirement:

V_OUTx C_OUT

t_SS

>

I_LIMITœ I_OUT

(8)

Choose a soft-start capacitor according to the formula:

10 mA

0.6V

C_SS= t_SS

x

where

•

C_SSis the soft-start capacitor

t_SSis the soft-start time

(9)

External Components Selection

The following is a design example selecting components for the Typical Application Schematic of Figure 29. The

circuit is designed for two controller 4-phase operation with 1.2V out at 100A from an input voltage of 6V to 18V.

The expected load is a microprocessor or ASIC with fast load transients, and the type of MOSFETs used are in

SO-8 or its equivalent packages such as PowerPAK ®, PQFN and LFPAK (LFPAK-i).

Switching Frequency

The selection of switching frequency is based on the tradeoff between size, cost, and efficiency. In general, a

lower frequency means larger, more expensive inductors and capacitors will be needed. A higher switching

frequency generally results in a smaller but less efficient solution. For this application a frequency of 300 kHz

was selected as a good compromise between the size of the inductor and MOSFETs, transient response and

efficiency. Following the equation given for R_FRQin the Functional Description under Oscillator and

Synchronization, for 300 kHz operation a 78.7 kΩ 1% resistor is used for R_FRQ. A 1000 pF capacitor is used for

C_FRQ

.

Output Inductors

The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is

based on the desired peak-to-peak ripple current, ΔI_Lthat flows in the inductor along with the load current. As

with switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductance

means lower ripple current and hence lower output voltage ripple. Lower inductance results in smaller, less

expensive devices. An inductance that gives a ripple current of 1/5 to 2/5 of the maximum output current is a

good starting point. (ΔI_L= (1/5 to 2/5) x I_OUT). Minimum inductance is calculated from this value, using the

maximum input voltage as:

V_IN(MAX)- V_OUT

x D

L_MIN

=

f_SWx DI_L

(10)

By calculating in terms of amperes, volts, and megahertz, the inductance value will come out in micro henries.

The inductor ripple current is found from the minimum inductance equation:

V_IN(MAX)- V_OUT

x D

DI_L=

f_SWx L_ACTUAL

(11)

The second criterion is inductor saturation current rating. The LM3754 has an accurately programmed peak

current limit. During an output short circuit, the inductor should be chosen so as not to exceed its saturation

rating at elevated temperature. For the design example, a standard value of 440 nH is chosen to fall within the

ΔI_L= (1/5 to 2/5) x I_OUTrange.

The dc loss in the inductor is determined by its series resistance R_L. The dc power dissipation is found from:

P_DC= I_OUT²x R_L

(12)

The ac loss can be estimated from the inductor manufacturer’s data, if available. The ac loss is set by the peak-

to-peak ripple current ΔI_Land the switching frequency f_SW

.

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Output Capacitors

The output capacitors filter the inductor ripple current and provide a source of charge for transient load

conditions. A wide range of output capacitors may be used with the LM3754 that provides excellent performance.

The best performance is typically obtained using aluminum electrolytic, tantalum, polymer, solid aluminum,

organic or niobium type chemistries in parallel with ceramic capacitors. The ceramic capacitors provide extremely

low impedance to reduce the output ripple voltage and noise spikes, while the aluminum or other capacitors

provide a larger bulk capacitance for transient loading.

When selecting the value for the output capacitors the two performance characteristics to consider are the output

voltage ripple and transient response. The output voltage ripple for a single phase can be approximated as:

2

1

2

DV_O= DI_Lx

R_C

+

8 x f_SWx C_O

(13)

With all values normalized to a single phase, ΔV_O(V) is the peak to peak output voltage ripple, ΔI_L(A) is the

peak to peak inductor ripple current, R_C(Ω) is the equivalent series resistance or ESR of the output capacitors,

f_SW(Hz) is the switching frequency, and C_O(F) is the output capacitance. The amount of output ripple that can

be tolerated is application specific. A general recommendation is to keep the output ripple less than 1% of the

rated output voltage. Figure 20 shows the output voltage ripple for multi-phase operation.

Figure 20. Multi-Phase Output Voltage Ripple

Based on the normalized single phase ripple, the worst case multi-phase output voltage ripple can be

approximated as:

ΔV_O(N) = ΔV_O/ N

(14)

Where N is the number of phases.

The output capacitor selection will also affect the output voltage droop and overshoot during a load transient. The

peak transient of the output voltage during a load current step is dependent on many factors. Given sufficient

control loop bandwidth an approximation of the transient voltage can be obtained from:

2

L x DI_O

R_C²x C_Ox V_L

2 x L

V_P=

+

2 x C_Ox V_L

(15)

With all values normalized to a single phase, V_P(V) is the output voltage transient and ΔI_O(A) is the load current

step change. C_O(F) is the output capacitance, L (H) is the value of the inductor and R_C(Ω) is the series

resistance of the output capacitor. V_L(V) is the minimum inductor voltage, which is duty cycle dependent.

For D < 0.5, V_L= V_OUT

For D > 0.5, V_L= V_IN− V_OUT

This shows that as the input voltage approaches V_OUT, the transient droop will get worse. The recovery

overshoot remains fairly constant.

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The loss associated with the output capacitor series resistance can be estimated as:

2

DI_L

P_CO= R_Cx

12

(16)

Output Capacitor Design Procedure

For the design example V_IN= 12V, V_OUT= 1.2V, D = V_OUT/ V_IN= 0.1, L = 440 nH, ΔI_L= 9A, ΔI_O= 20A and V_P=

0.12V.

To meet the transient voltage specification, the maximum R_Cis:

V_P

DI_O

R_CÇ

(17)

For the design example, the maximum R_Cis 6 mΩ. Choose R_C= 3 mΩ as the design limit.

From the equation for V_P, the minimum value of C_Ois:

2

L x DI_O

1

x

C_O

í

V_Px V_L

2

R_Cx DI_O

1 + 1 -

V_P

(18)

For D < 0.5, V_L= V_OUT

For D > 0.5, V_L= V_IN− V_OUT

With R_C= V_P/ ΔI_Othis reduces to:

2

L x DI_O

C_Oí

V_Px V_L

(19)

(20)

With R_C= 0 this reduces to:

2

L x DI_O

C_Oí

2 x V_Px V_L

Since D < 0.5, V_L= V_OUT. With R_C= 3 mΩ, the minimum value for C_Ois 476 μF.

The minimum control loop bandwidth f_Cis given by:

DI_O

f_Cí

8 x C_Ox V_P

(21)

For the design example, the minimum value for f_Cis 44 kHz. Two 220 μF, 5 mΩ polymer capacitors in parallel

with two 22 μF, 3 mΩ ceramics per phase will meet the target output voltage ripple and transient specification.

Input Capacitors

The input capacitors for a buck regulator are used to smooth the large current pulses drawn by the inductor and

load when the high-side MOSFET is on. Due to this large ac stress, input capacitors are usually selected on the

basis of their ac rms current rating rather than bulk capacitance. Low ESR is beneficial because it reduces the

power dissipation in the capacitors. Although any of the capacitor types mentioned in the Output Capacitors

section can be used, ceramic capacitors are common because of their low series resistance. In general the input

to a buck converter does not require as much bulk capacitance as the output.

The input capacitors should be selected for rms current rating and minimum ripple voltage. The equation for the

rms current and power loss of the input capacitor in a single phase can be estimated as:

I_CIN(RMS)

D x (1 œ D)

ö I_Ox

ö I_O²x D x (1 œ D) x R_CIN

P_CIN

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where

•

I_O(A) is the output load current

R_CIN(Ω) is the series resistance of the input capacitor

(22)

Since the maximum values occur at D = 0.5, a good estimate of the input capacitor rms current rating in a single

phase is one-half of the maximum output current.

Neglecting the series inductance of the input capacitance, the input voltage ripple for a single phase can be

estimated as:

DI_L

I_Ox D x (1 œ D)

x R_CIN

+

I_O+

DV_IN

=

2

C_INx f_SW

(23)

By defining the maximum input voltage ripple, the minimum requirement for the input capacitance can be

calculated as:

I_Ox D x (1 œ D)

C_IN

í

DI_L

DV_IN

œ

I_O+

x R_CIN

x f_SW

2

(24)

For multi-phase operation, the general equation for the input capacitor rms current is approximated as:

1

N

I_CIN(RMS)ö I_Ox D x

- D

(25)

This is valid for D < 1 / N and repeats for a total of N times. I_Orepresents the total output current and N is the

number of phases. Figure 21 shows the input capacitor rms current as a function of the output current, duty cycle

and number of phases.

Figure 21. Input Capacitor RMS Current as a Function of Output Current

For multi-phase operation the maximum rms current can be approximated as:

I_CIN(RMS)MAX≈ 0.5 x I_O/ N

(26)

In most applications for point-of-load power supplies, the input voltage is the output of another switching

converter. This output often has a lot of bulk capacitance, which may provide adequate damping.

When the converter is connected to a remote input power source through a wiring harness, a resonant circuit is

formed by the line impedance and the input capacitors. If step input voltage transients are expected near the

maximum rating of the LM3754, a careful evaluation of the ringing and possible overshoot at the device VIN pin

should be completed. To minimize overshoot make C_IN> 10 x L_IN. The characteristic source impedance and

resonant frequency are:

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L_IN

C_IN

1

Z_S=

f_S=

2 x p x L_INx C_IN

(27)

The converter exhibits a negative input impedance which is lowest at the minimum input voltage:

2

V_IN

-

=

Z_IN

P_OUT

(28)

The damping factor for the input filter is given by:

R_LIN+ R_CINZ_S

+

1

2

x

á =

Z_S

Z_IN

where

•

R_LINis the input wiring resistance

R_CINis the series resistance of the input capacitors

(29)

The term Z_S/ Z_INwill always be negative due to Z_IN.

When δ = 1, the input filter is critically damped. This may be difficult to achieve with practical component values.

With δ < 0.2, the input filter will exhibit significant ringing. If δ is zero or negative, there is not enough resistance

in the circuit and the input filter will sustain an oscillation.

When operating near the minimum input voltage, an aluminum electrolytic capacitor across C_INmay be needed

to damp the input for a typical bench test setup. Any parallel capacitor should be evaluated for its rms current

rating. The current will split between the ceramic and aluminum capacitors based on the relative impedance at

the switching frequency. Using a square wave approximation, the rms current in each capacitor is found from:

C1 = C_IN1R1 = R_CIN1C2 = C_IN2R2 = R_CIN2

1

X₁ö

2.2 x p x f_SWx C1

1

X₂ö

2.2 x p x f_SWx C2

R2²+ X2²

x

I_CIN(RMS)

I_CIN1(RMS)

=

(R1 + R2)²+ (X1 + X2)²

R1²+ X1²

I_CIN(RMS)

x

I_CIN2(RMS)

(R1 + R2)²+ (X1 + X2)²

(30)

Input Capacitor Design Procedure

Ceramic capacitors are sized to support the required rms current. An aluminum electrolytic capacitor is used for

damping. Find the minimum value for the ceramic capacitors from:

I_O

C_IN

í

DV_INx 4 x N x f_SW

(31)

Allowing ΔV_IN= 0.6V for the design example, the minimum value is C_IN= 34.7 μF. Find the rms current rating

from:

I_CIN(RMS)MAX≈ 0.5 x I_O/ N

(32)

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Using the same criteria, the result is 12.5A rms. Manufacturer data for 4.7 μF, 25V, X7R capacitors in a 1210

package allows for 4A rms with a 20°C temperature rise. For the design example, using two ceramic capacitors

for each phase will meet both the input voltage ripple and rms current target. Since the series resistance is so

low at about 4 mΩ per capacitor, a parallel aluminum electrolytic is used for damping. A good general rule is to

make the damping capacitor at least five times the value of the ceramic. By sizing the aluminum such that it is

primarily resistive at the switching frequency, the design is greatly simplified since the ceramic capacitors are

primarily reactive. In this case the approximation for the rms current in the damping capacitor is:

I_CIN(RMS)

I_CIN2(RMS)

ö

2.2 x p x N x f_SWx R_CIN2x C_IN1

where

•

C_IN2is the damping capacitance

R_CIN2is its series resistance

C_IN1is the ceramic capacitance

(33)

A 470 μF, 25V, 0.06Ω, 1.19A rms aluminum electrolytic capacitor in a 10 mm x 10.2 mm package is chosen for

the damping capacitor. Calculated rms current for the aluminum electrolytic is 0.67A.

MOSFETs

Selection of the power MOSFETs is governed by a tradeoff between cost, size and efficiency.

Losses in the high-side FET can be broken down into conduction loss, gate charge loss and switching loss.

Conduction or I²R loss is approximately:

P_{COND_HI}= D x (I_OUT²x R_{DS(on)_HI}x 1.3) (High-side FET)

P_{COND_LO}= (1 − D) x (I_OUT²x R_{DS(on)_LO}x 1.3) (Low-side FET)

(34)

(35)

In the above equations the factor 1.3 accounts for the increase in MOSFET R_DS(on)due to self heating.

Alternatively, the 1.3 can be ignored and the R_DS(on)of the MOSFET estimated using the R_DS(on)vs. Temperature

curves in the MOSFET datasheets.

The gate charge loss results from the current driving the gate capacitance of the power MOSFETs, and is

approximated as:

P_DR= V_INx (Q_{G_HI}+ Q_{G_LO}) x f_SW

where

•

Q_{G_HI}and Q_{G_LO}are the total gate charge of the high-side and low-side FETs respectively at the typical 5V

driver voltage

(36)

Gate charge loss differs from conduction and switching losses in that the majority of dissipation occurs in the

LM3754 and VDD regulator.

The switching loss occurs during the brief transition period as the FET turns on and off, during which both current

and voltage is present in the channel of the FET. This can be approximated as:

P_{SW_ON}= V_INx I_{L_VL}x a x R_{G_ON}x f_SW

Q_GD

V_DR- V_TH

x

+ C_ISSx Ln

V_DR- V_PLT1

V_DR- V_PLT2

(37)

P_{SW_OFF}= V_INx I_{L_PK}x b x R_{G_OFF}x f_SW

Q_GD

V_PLT2

V_TH

x

+ C_ISSx Ln

V_PLT2

where

•

Q_GDis the high-side FET Miller charge with a V_DSswing between 0 to V_IN

C_ISSis the input capacitance of the high-side MOSFET in its off state with V_DS= V_IN

α and β are fitting coefficient numbers, which are usually between 0.5 to 1, depending on the board level

parasitic inductances and reverse recovery of the low-side power MOSFET body diode

(38)

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Under ideal condition, setting α = β = 0.5 is a good starting point. Other variables are defined as:

I_{L_VL}= I_OUT− 0.5 x ΔI_L

I_{L_PK}= I_OUT+ 0.5 x ΔI_L

(39)

(40)

I_{L_VL}

V_PLT1ꢀ V_TH

+

g_{mFET_HI}

(41)

I_{L_PK}

g_{mFET_HI}

V_PLT2ꢀ V_TH

+

(42)

(43)

(44)

R_{G_ON}= 5 + R_{G_INT}+ R_{G_EXT}

R_{G_OFF}= 2 + R_{G_INT}+ R_{G_EXT}

Switching loss is calculated for the high-side FET only. 5 and 2 represent the LM3754 high-side driver resistance

in the transient region. R_{G_INT}is the gate resistance of the high-side FET, and R_{G_EXT}is the extra external gate

resistance if applicable. R_{G_EXT}may be used to damp out excessive parasitic ringing at the switch node.

For this example, the maximum drain-to-source voltage applied to either MOSFET is 18V. The maximum drive

voltage at the gate of the high-side MOSFET is 5V, and the maximum drive voltage for the low-side MOSFET is

5V. The selected MOSFET must be able to withstand 18V plus any ringing from drain to source, and be able to

handle at least 5V plus ringing from gate to source. If the duty cycle of the converter is small, then the high-side

MOSFET should be selected with a low gate charge in order to minimize switching loss whereas the bottom

MOSFET should have a low R_DS(on)to minimize conduction loss.

For a typical input voltage of 12V and output current of 25A per phase, the MOSFET selections for the design

example are SIR850DP for the high-side MOSFET and 2 x SIR892DP for the low-side MOSFET.

A 2.2Ω resistor for the high-side gate drive may be added in series with the HG output. This helps to control the

MOSFET turn-on and ringing at the switch node. Additionally, 0.5A Schottky diodes may be placed across the

high-side MOSFETs. The external Schottky diodes have a much faster recovery characteristic than the MOSFET

body diode, and help to minimize switching spikes by clamping the SW pin to VIN. Another technique to control

ringing at the switch node is to place an RC snubber from SW to PGND directly across the low-side MOSFET.

Typical values at 300 kHz are 1Ω and 680 pF.

To improve efficiency, 3A Schottky diodes may be placed across the low-side MOSFETs. The external Schottky

diodes have a much lower forward voltage than the MOSFET body diode, and help to minimize the loss due to

the body diode recovery characteristic.

EN and VIN UVLO

For operation at 6V minimum input, set the EN divider to enable the LM3754 at approximately 5.5V nominal.

Values of R_UV1= 1.37 kΩ and R_UV2= 4.02 kΩ will meet the target threshold.

Current Sense

For resistor current sense, a 1 mΩ 1W resistor is used for a full scale voltage of 25 mV at 25A out.

For DCR sensing, R_Sis equal to the inductor resistance of R_L= 0.32 mΩ plus an estimated trace resistance of

0.2 mΩ.. The full scale voltage is about 13 mV at 25A. For equal time constants, the relationship of the

integrating RC is determined by:

L

R_DCRx C_DCR

=

R_L

(45)

(46)

(47)

Choosing C_DCR= 0.15 μF:

R_DCR= 440 nH / (0.15 μF x 0.52 mΩ) = 5.64 kΩ.

Using a standard value of 5.90 kΩ, the average current through R_DCRis calculated as 203 μA from:

I_DCR= V_OUT/ R_DCR

I_DCRis sufficiently high enough to keep the CS input bias current from being a significant error term.

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Current Limit

For the design example, the desired current limit set point is chosen as 34.5A peak per phase, which is about

25% above the full load peak value. Using DCR sense with R_S= 0.52 mΩ:

R_ILIM= 34.5A x 0.52 mΩ / 94 μA = 191Ω

(48)

For resistor sense, the relatively low output inductor value forms a voltage divider with the intrinsic inductance of

the sense resistor. When the MOSFETs switch, this adds a step to the otherwise triangular current sense

voltage. The step voltage is simply the input voltage times the inductive divider. With L = 440 nH and L_S= 1 nH,

the step voltage is:

V_LS= 12V x 1 nH / 441 nH = 27.2 mV

(49)

Using the same method as DCR sense, an RC filter is added to recover the actual resistive sense voltage.

Choosing C = 1 nF the resistor is calculated as:

R = 1 nH / (1 nF x 1 mΩ) = 1 kΩ

(50)

The current limit resistor is then calculated as:

R_ILIM= 34.5A x 1 mΩ / 94 μA = 367Ω

(51)

The closest standard value of 365Ω 1% is selected for the design example.

Soft-Start

To prevent over-shoot, the soft-start time is set to be longer than the time it would take to charge the output

voltage at the maximum output current. Following the equations in the Application Information under Soft-Start:

t_SS(MIN)= (1.2V x 484 μF) / (34.5A − 25A) = 61 μs

(52)

Choosing a value of C_SS= 0.1 μF, the soft-start time is:

t_SS= (0.1 μF x 0.6V) / 10 μA = 6 ms

(53)

VCC, VDD and BOOT

VCC is used as the supply for the internal control and logic circuitry. A 4.7 μF ceramic capacitor provides

sufficient filtering for VCC.

C_VDDprovides power for both the high-side and low-side MOSGET gate drives, and is sized to meet the total

gate drive current. Allowing for ΔV_VDD= 100 mV of ripple, the minimum value for C_VDDis found from:

Q_{G_HI}+ Q_{G_LO}

C_VDD

í

DV_VDD

(54)

Using Q_{G_HI}= 2 x 10 nC and Q_{G_LO}= 4 x 21 nC per controller with a 5V gate drive, the minimum value for C_VDD

= 1.04 μF. To use common component values, C_VDD1and C_VDD2are also selected as 4.7 μF ceramic.

A general purpose NPN transistor is sized to meet the requirements for the VDD supply. Based on the gate

charge of 104 nC per controller, the required current is found from:

I_GC= Q_{G_TOTAL}x f_SW

(55)

At 300 kHz, I_GC= 31.2 mA per controller. For a two controller system, the minimum HFE for the transistor is

determined by:

HFE_MIN= I_{GC_TOTAL}/ 5 mA

(56)

The power dissipated by the transistor is:

P_R= (V_IN− V_DD) x I_{GC_TOTAL}

(57)

The transistor must support 62.4 mA with an HFE of at least 12.5 over the entire operating range. At 18V in the

power dissipated is 0.8W. A CJD44H11 in a DPAK case is chosen for the design example. A 0.047 μF capacitor

from base to PGND will improve the transient performance of the VDD supply.

C_BOOTprovides power for the high-side gate drive, and is sized to meet the required gate drive current. Allowing

for ΔV_BOOT= 100 mV of ripple, the minimum value for C_BOOTis found from:

Q_{G_HI}

C_BOOT

í

DV_BOOT

(58)

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Using Q_{G_HI}= 10 nC per phase with a 5V gate drive, the minimum value for C_BOOT= 0.1 μF. C_BOOTis selected as

0.22 μF ceramic per phase for the design example. A 0.5A Schottky diode is used for D_BOOTat each controller.

Pre-Load Resistor

For normal operation, a pre-load resistor is generally not required. During an abnormal fault condition with the

output completely disconnected from the load, the output voltage may rise. This is primarily due to the high-side

driver off-state bias current, and reverse leakage current of the high-side Schottky clamp diode.

At room temperature with 12V input, the reverse leakage of each 0.5A Schottky diode is about 15 μA. With the

EN pin high and the FAULT pin low, the bias current in each high-side driver is about 105 μA. Allowing for a 2 to

1 variation, the maximum value of resistor to keep the output voltage from rising above 5% of its nominal value is

found from:

R = 0.05 x 1.2V / 330 µA = 182Ω

(59)

A value of 120Ω is selected for the design example. This represents a 10 mA pre-load at the rated output

voltage, which is 0.01% of the 100A full load current.

Control Loop Compensation

The LM3754 uses voltage-mode PWM control to correct changes in output voltage due to line and load

transients. Input voltage feed-forward is used to adjust the amplitude of the PWM ramp. This stabilizes the

modulator gain from variations due to input voltage, providing a robust design solution. A fast inner current

sharing circuit ensures good dynamic response to changes in load current.

The control loop is comprised of two parts. The first is the power stage, which consists of the duty cycle

modulator, current sharing circuit, output filter and load. The second part is the error amplifier, which is a voltage

type operational amplifier with a typical dc gain of 70 dB and a unity gain frequency of 15 MHz. Figure 22 shows

the power stage, error amplifier and current sharing components.

L

R

L

V

OUT

+

V

IN

C

R

C

O2

HG

O1

+

-

R

O

R

C

DCR

LG

DRIVERS

2 mA/V

R

C2

CS

CSM

C1

+

-

2 mA/V

15 mV

- +

+

-

125 mA/V

IAVE

+

K

= 0.232

FF

-

CURRENT SHARE

SNSP

SNSM

C

AV

R

AV

A = 50

V

x K

FF

IN

{

VDIF

1.3V

+

-

C

HF

PWM

C

R

DIFF AMP

FF

25 kW

-

+

COMP

R

FBT

FF

C

R

COMP

FB

-

+

R

FBB

+

ERROR AMP

V

REF

-

Figure 22. Power Stage, Error Amplifier and Current Sharing

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The simplified power stage transfer function (also called the control-to-output transfer function) for the LM3754

can be written as:

s

ö_Z

1 +

v_O

v_C

= A_VP

x

s

s²

1 +

+

2

ö_Px Q_Pö_P

where

K_m

1

A_VP

=

K_m

=

K_D

T

L

(0.5 œ D) x R_ix

+ K_FF

K_D

K_mx R_ix H_a(s)

R_O

1

2

K_D= 1 +

ö_Z=

ö_P

=

C_Ox R_C

L x C_O

K_D

ö

_Px Q_P=

L

R_O

+ C_Ox (R_C+ K_mx R_ix H_a(s))

•

(60)

(61)

With:

V_O

R_i= A x R_S

D =

T =

V_IN

s x C_AVx R_AV

1 + s x C_AVx R_AV

1

H_a(s) =

f_SW

K_mis the dc modulator gain and R_iis the current-sharing gain. K_FFis the input voltage feed-forward term, which

is internally set to a value of 0.232 V/V. The IAVE filter is accounted for by H_a(s), which provides additional

damping of the modulator transfer function.

R_AVsets the gain of the current averaging amplifier. A fixed value of 8 kΩ/phase must be used for proper scaling.

Since the effective resistance is in parallel, each LM3754 should have a 4.02 kΩ 1% resistor at IAVE for 2-

phase/controller operation. C_AVsets the IAVE filter time constant of the current sharing amplifier. For optimal

performance of the current sharing circuit, the IAVE filter is designed to settle to its final value in five switching

cycles. The optimal IAVE time constant is defined as:

T = C_AVx R_AV

(62)

A value of C_AV= 1/(R_AVx f_SW) per phase must be used for the optimal time constant. Each LM3754 should have

a value of two times the normalized single phase value of C_AVat IAVE for 2-phase/controller operation. In this

manner, the IAVE time constant maintains a fixed value of T for any number of phases.

Typical frequency response of the gain and the phase for the power stage are shown in Figure 23 and Figure 24.

It is designed for V_IN= 12V, V_OUT= 1.2V, I_OUT= 25A per phase and a switching frequency of 300 kHz. For 2-

phase operation R_AV= 4.02 kΩ and C_AV= 1000 pF. The power stage component values per phase are:

L = 0.44 μH, R_L= 0.52 mΩ, C_O1= 440 μF, R_C1= 2.5 mΩ, C_O2= 44 μF, R_C2= 1.5 mΩ, R_S= R_L= 0.52 mΩ and

R_O= V_OUT/ I_OUT= 48 mΩ.

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Figure 23. Power Stage Gain

Figure 24. Power Stage Phase

Assuming a pole at the origin, the simplified equation for the error amplifier transfer function can be written in

terms of the mid-band gain as:

ö_ZEA

s

ö_FZ

s

ö_HF

1 +

v_C

v_O

A_VM

K_HF

-

x

=

ö_FP

where

R_COMP

C_HF

A_VM

=

K_HF= 1 +

R_FBT

C_COMP

1

ö_FZ

=

ö_ZEA

=

C_COMPx R_COMP

C_FFx (R_FF+ R_FBT)

C_HF+ C_COMP

1

C_FFx R_FF

ö_FP

=

ö_HF

=

C_HFx C_COMPx R_COMP

•

(63)

In general, the goal of the compensation circuit is to give high gain, a bandwidth that is between one-fifth and

one-tenth of the switching frequency, and at least 45° of phase margin.

Control Loop Design Procedure

Once the power stage design is complete, the power stage components are used to determine the proper

frequency compensation. Knowing the dc modulator gain and assuming an ideal single-pole system response,

the mid-band error amplifier gain is set by the target crossover frequency. Based on the ideal amplifier transfer

function, the zero-pair is set to cancel the complex conjugate pole of the output filter. One pole is set to cancel

the ESR of the output capacitor. The second pole is set equal to the switching frequency. A correction factor is

used to accommodate the modulator damping when the output filter pole is within a decade of the target

crossover frequency.

The compensation components will scale from the feedback divider ratio and selection of the bottom feedback

divider resistor. A maximum value for the divider current is typically set at 1 mA. Using a divider current of 200

μA will allow for a reasonable range of values. For the bottom feedback resistor R_FBB= V_REF/ 200 μA = 3 kΩ.

Choosing a standard 1% value of 3.01 kΩ, the top feedback resistor is found from:

V_OUT

R_FBT= R_FBB

x

- 1

V_REF

(64)

For V_OUT= 1.2V and V_REF= 0.6V, R_FBT= 3.01 kΩ.

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Based on the previously defined power stage values, calculate general terms:

V_O

1

f_SW

R_i= A x R_S

D =

T =

V_IN

1

K_m=

T

L

(0.5 œ D) x R_ix

+ K_FF

(65)

(66)

For the design example D = 0.1, R_i= 0.026Ω, T = 3.33 μs and K_m= 3.22.

Calculate the output filter pole frequency and the ESR zero frequency from:

1

ö_P=

ö_Z=

C_Ox R_C

L x C_O

For the output filter pole using C_O= C_O1+ C_O2, ω_P= 68.5 krad/sec. Since C_O1>> C_O2, the ESR zero is

calculated using C_O1and R_C1as ω_Z= 909 krad/sec.

Choose a target crossover frequency f_Cgreater than the minimum control loop bandwidth from the Output

Capacitors section. The optimum value of the crossover frequency is usually between 5 and 10 times the filter

pole frequency. With f_P= ω_P/ (2 x π) = 10.9 kHz, this places f_Cbetween 54.5 kHz and 109 kHz. The upper limit

for f_Cis typically set at 1/5 of the switching frequency.

ö_C= 2 x p x f_C

ö_SW= 2 x p x f_SW

(67)

Choosing f_C= 60 kHz for the design example ω_C= 377 krad/sec. The switching frequency is ω_SW= 1.88

Mrad/sec.

For output capacitors with very low ESR, if the target crossover frequency is more than 10 times the filter pole

frequency, bandwidth limiting of the error amplifier may occur. See the Comprehensive Equations section to

incorporate the error amplifier bandwidth into the design procedure.

For reference, the parallel equivalent C_Oand R_Cat any frequency can be calculated from:

C1 = C_O1

R1 = R_C1

X1 =

C2 = C_O2

R2 = R_C2

1

X2 =

ö = 2 x p x f

ö x C2

ö x C1

R2²+ X2²

R1²+ X1²

x

Z =

(R1 + R2)²+ (X1 + X2)²

X1

R1

X2

R2

X1 + X2

R1 + R2

A = tan^-1

+ tan^-1

- tan^-1

1

R_C= Z x cos(A)

C_O=

ö x Z x sin(A)

(68)

At the target crossover frequency X1 = 0.00603, X2 = 0.0603, Z = 0.00592 and A = 1.213. The parallel

equivalent C_O= 478 μF and R_C= 2.1 mΩ.

Calculate the error amplifier gain coefficient and the compensation component values. The (1 − ω_P/ω_C) term is

the correction factor for the modulator damping.

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ö_C

1

C_HF

=

G_C=

K_mx ö_P

ö

_SWx G_Cx R_FBT

ö_SW

ö_P

ö_C

- 1 x 1 -

C_COMP= C_HF

x

1

R_COMP

=

ö_Px C_COMP

1

ö_P

ö_Z- ö_P

R_FF= R_FBT

x

C_FF=

ö_Zx R_FF

(69)

For the design example, the calculated values are G_C= 1.71, C_HF= 103 pF, C_COMP= 2236 pF, R_COMP= 6527Ω,

R_FF= 245 and C_FF= 4483 pF.

Using standard values of C_HF= 100 pF, C_COMP= 2200 pF, R_COMP= 6.2 kΩ, R_FF= 240Ω and C_FF= 4700 pF, the

error amplifier plots of gain and phase are shown in Figure 25 and Figure 26.

Figure 25. Error Amplifier Gain

Figure 26. Error Amplifier Phase

The complete control loop transfer function is equal to the product of the power stage transfer function and error

amplifier transfer function. For the Bode plots, the overall loop gain is the equal to the sum in dB and the overall

phase is equal to the sum in degrees. Results are shown in Figure 27 and Figure 28. The crossover frequency is

57 kHz with a phase margin of 73°.

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Figure 27. Control Loop Gain

Figure 28. Control Loop Phase

For the small-signal analysis, it is assumed that the control voltage at the COMP pin is dc. In practice, the output

ripple voltage is amplified by the error amplifier gain at the switching frequency, which appears at the COMP pin

adding to the control ramp. This tends to reduce the modulator gain, which may lower the actual control loop

crossover frequency. This effect is greatly reduced as the number of phases is increased.

Efficiency and Thermal Considerations

The buck regulator steps down the input voltage and has a duty ratio D of:

V_OUT

V_IN

1

x

D =

h

(70)

(71)

Where η is the estimated converter efficiency. The efficiency is defined as:

P_OUT

h =

P_OUT+ P_{TOTAL_LOSS}

The total power dissipated in the power components can be obtained by adding together the loss as mentioned

in the Output Inductors, Output Capacitors, Input Capacitors and MOSFETs sections.

The highest power dissipating components are the power MOSFETs. The easiest way to determine the power

dissipated in the MOSFETs is to measure the total conversion loss (P_IN− P_OUT), then subtract the power loss in

the capacitors, inductors, LM3754 and VDD regulator. The resulting power loss is primarily in the switching

MOSFETs. Selecting MOSFETs with exposed pads will aid the power dissipation of these devices. Careful

attention to R_DS(on)at high temperature should be observed.

If a snubber is used, the power loss can be estimated with an oscilloscope by observation of the resistor voltage

drop at both the turn-on and turn-off transitions. Assuming that the RC time constant is << 1 / f_SW

:

P = ½ x C x (V_P²+ V_N²) x f_SW

(72)

V_Pand V_Nrepresent the positive and negative peak voltage across the snubber resistor, which is ideally equal to

V_IN.

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LM3754 and VDD Regulator Operating Loss

These terms accounts for the currents drawn at the VIN and VDD pins, used for driving the logic circuitry and the

power MOSFETs. For the LM3754, the VIN current is equal to the steady state operating current I_VIN. The VDD

current is primarily determined by the MOSFET gate charge current I_GC, which is defined as:

I_GC= Q_{G_TOTAL}x f_SW

(73)

(74)

P_D= (V_INx I_VIN) + (V_DDx I_GC

)

Q_{G_TOTAL}is the total gate charge of the MOSFETs connected to each LM3754. P_Drepresents the total power

dissipated in each LM3754. I_VINis about 15 mA from the Electrical Characteristics table. The LM3754 has an

exposed thermal pad to aid power dissipation.

The power dissipated in the VDD regulator is determined by:

P_R= (V_IN− V_DD) x I_{GC_TOTAL}

(75)

I_{GC_TOTAL}is the sum of the MOSFET gate charge currents for all of the controllers.

Layout Considerations

To produce an optimal power solution with a switching converter, as much care must be taken with the layout

and design of the printed circuit board as with the component selection. The following are several guidelines to

aid in creating a good layout.

Kelvin Traces for Gate Drive and Sense Lines

The HG and SW pins provide the gate drive and return for the high-side MOSFETs. These lines should run as

parallel pairs to each MOSFET, being connected as close as possible to the respective MOSFET gate and

source. Likewise the LG and PGND pins provide the gate drive and return for the low-side MOSFETs. A good

ground plane between the PGND pin and the low-side MOSFETs source connections is needed to carry the

return current for the low-side gates.

The SNSP and SNSM pins of the Master should be connected as a parallel pair, running from the output power

and ground sense points. Keep these lines away from the switch node and output inductor to avoid stray

coupling. If possible, the SNSP and SNSM traces should be shielded from the switch node by ground planes.

SGND and PGND Connections

Good layout techniques include a dedicated ground plane, usually on an internal layer adjacent to the LM3754

and signal component side of the board. Signal level components connected to FB, SS, FREQ, IAVE, EN and

PH along with the VCC and VIN bypass capacitors should be tied directly to the SGND pin. Connect the SGND

and PGND pins directly to the DAP, with vias from the DAP to the ground plane. The ground plane is then

connected to the input capacitors and low-side MOSFET source at each phase.

Minimize the Switch Node

The copper area that connects the power MOSFETs and output inductor together radiates more EMI as it gets

larger. Use just enough copper to give low impedance for the switching currents and provide adequate heat

spreading for the MOSFETs.

Low Impedance Power Path

In a buck regulator the primary switching loop consists of the input capacitor connection to the MOSFETs.

Minimizing the area of this loop reduces the stray inductance, which minimizes noise and possible erratic

operation. The ceramic input capacitors at each phase should be placed as close as possible to the MOSFETs,

with the VIN side of the capacitors connected directly to the high-side MOSFET drain, and the PGND side of the

capacitors connected as close as possible to the low-side source. The complete power path includes the input

capacitors, power MOSFETs, output inductor, and output capacitors. Keep these components on the same side

of the board and connect them with thick traces or copper planes. Avoid connecting these components through

vias whenever possible, as vias add inductance and resistance. In general, the power components should be

kept close together, minimizing the circuit board losses.

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Comprehensive Equations

Power Stage Transfer Function

To include all terms, it is easiest to use the impedance form of the equation:

v_O

K_mx Z_O

=

Z_O+ Z_L+ K_mx R_ix H(s) x H_a(s)

v_C

where

1

K_m

=

T

L

(0.5 œ D) x R_ix

+ K_FF

R_Ox (1 + s x C_Ox R_C)

1 + s x C_Ox (R_O+ R_C)

Z_L= s x L + R_DC

Z_O

=

R_DC= R_{DS(on)_HI}x D + R_{DS(on)_LO}x (1 œ D) + R_L+ R_S

•

(76)

(77)

With:

s²

V_O

R_i= A x R_S

H (s) =

D =

T =

2

V_IN

ö_n

s x C_AVx R_AV

1 + s x C_AVx R_AV

p

T

1

H_a(s) =

ö_n=

f_SW

Error Amplifier Transfer Function

Using a single-pole operational amplifier model, the complete error amplifier transfer function is given by:

v_C

1

= - G_EA(s) x

v_O

1

A_OL

s

x

1 + G_FB(s)

1 +

+

ö_BW

(78)

(79)

Where the open loop gain A_OL= 3162 (70 dB) and the unity gain bandwidth ω_BW= 2 x π x f_BW

.

The ideal transfer function is expressed in terms of the mid-band gain as:

ö_ZEA

s

ö_FZ

s

ö_HF

1 +

A_VM

K_HF

x

G_EA(s) =

ö_FP

The feedback gain is then:

ö_ZEA

s

ö_FB

s

ö_HF

1 +

A_VM

x

G_FB(s) =

K_HFx K_FB

1 +

ö_FP

where

R_COMP

C_HF

A_VM

=

K_HF= 1 +

R_FBT

C_COMP

1

ö_FZ

=

ö_ZEA

=

C_COMPx R_COMP

C_FFx (R_FF+ R_FBT

)

C_HF+ C_COMP

1

ö_FP

=

ö_HF

=

C_FFx R_FF

C_HFx C_COMPx R_COMP

R_FBB

1

ö_FB

=

K_FB

C_FFx (R_FF+ K_FBx R_FBT

)

R_FBB+ R_FBT

•

(80)

37

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Error Amplifier Bandwidth Limit

When the ideal error amplifier gain reaches the open loop gain-bandwidth limit, the phase goes to zero. To

incorporate the amplifier bandwidth into the design procedure, determine the boundary limit with respect to the

ESR zero frequency:

0.333

2

ö

_ZB= ö_BWx K_mx ö_P

(81)

Based on the relative ESR zero, the crossover frequency is set at 1/3 of the bandwidth limiting frequency.

If ω_Z> ω_ZB, calculate the optimal crossover frequency from:

0.333

1

2

x

f_C=

ö_BWx K_mx ö_P

(2 x p) x 3

(82)

(83)

If ω_Z< ω_ZB, calculate the optimal crossover frequency from:

0.5

2

ö

_BWx K_mx ö_P

1

x

f_C=

ö_Z

(2 x p) x 3

Using this method, the maximum phase boost is achieved at the optimal crossover frequency.

In either case, the upper limit for f_Cis typically set at 1/5 of the switching frequency.

38

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SNVS789B –JANUARY 2012–REVISED APRIL 2013

Typical Application

V

IN

V

IN

V

IN

MASTER

V

C

VCC1

IN

C

IN

D

C

VDD1

BOOT1

V

IN

R

FF

C

FF

BOOT1

HG1

SNSP

SNSM

Q

T1

L1

R

FBB

FBT

SNSM

VDIF

FB

R

DCR1

SW1

C

DCR1

C

BOOT1

V

EXT

R

C

COMP

CS1

LG1

COMP

Q

B1

R

PGD

C

HF

PGOOD

FAULT

FREQ

CSM

LM3754

D

V

IN

BOOT2

PGOOD

BOOT2

HG2

R

FRQ1

Q

L2

T2

C

FRQ1

V

IN

R

SW2

CS2

LG2

C

DCR2

C

SYNC

R

UV2

SYNCOUT

EN

SS

Q

V

OUT

B2

C

SS

R

ILIM1

UV1

ILIM

SNSP

SNSM

C

OUT

R

AV1

C

VDD2

C

AV1

SLAVE

C

VCC2

V

IN

NC

D

V

IN

BOOT3

BOOT1

HG1

SNSP

SNSM

Q

T3

L3

R

DCR3

C

SW1

DCR3

VDIF

C

BOOT3

FB

CS1

LG1

Q

B3

COMP

PGOOD

FAULT

FREQ

CSM

D

LM3754

BOOT4

V

IN

BOOT2

HG2

R

FRQ2

Q

L4

T4

C

BOOT4

C

FRQ2

R

C

DCR4 DCR4

SW2

CS2

LG2

SYNC

NC

SYNCOUT

EN

Q

B4

R

ILIM2

SS

ILIM

C

R

AV2

All controllers in the system are the same part. The Master and Slave are differentiated by how they are connected in

the system.

Figure 29. Typical Application

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Design Examples

Figure 30. Master with DCR Sense

Figure 31. Slave with DCR Sense

40

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Figure 32. Master with Resistor Sense

Figure 33. Slave with Resistor Sense

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REVISION HISTORY

Changes from Revision A (April 2013) to Revision B

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 41

42

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PACKAGE MATERIALS INFORMATION

www.ti.com

8-Apr-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM3754SQ/NOPB

LM3754SQX/NOPB

WQFN

RTV

32

1000

4500

178.0

330.0

12.4

5.3

1.3

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Apr-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM3754SQ/NOPB

LM3754SQX/NOPB

WQFN

RTV

32

1000

4500

213.0

367.0

191.0

367.0

55.0

35.0

Pack Materials-Page 2

MECHANICAL DATA

RTV0032A

SQA32A (Rev B)

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型号：	LM3754
厂家：	TEXAS INSTRUMENTS
描述：	Scalable 2-Phase Synchronous Buck Controller with Integrated FET Drivers and Linear Regulator Controller
文件：	总47页 (文件大小：1880K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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