LM3881MMX/NOPB [TI]
LM3881 Simple Power Sequencer With Adjustable Timing;
| 型号： | LM3881MMX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LM3881 Simple Power Sequencer With Adjustable Timing 光电二极管 |
| 文件： | 总17页 (文件大小：791K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM3881
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SNVS555C –JANUARY 2008–REVISED APRIL 2013
LM3881 Power Sequencer
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1
FEATURES
DESCRIPTION
The LM3881 Power Sequencer offers the easiest
method to control power up and power down of
multiple power supplies (switching or linear
regulators). By staggering the startup sequence, it is
possible to avoid latch conditions or large in-rush
currents that can affect the reliability of the system.
2
•
•
•
•
•
•
•
Easiest Method to Sequence Rails
Power Up and Power Down Control
Input Voltage Range of 2.7V to 5.5V
Small Footprint VSSOP-8 Package
Low Quiescent Current of 80 µA
Output Invert Feature
Available in VSSOP-8 package, the Power
Sequencer contains a precision enable pin and three
open drain output flags. Upon enabling the LM3881,
the three output flags will sequentially release, after
individual time delays, permitting the connected
power supplies to startup. The output flags will follow
a reverse sequence during power down to avoid latch
conditions. Time delays are defined using an external
capacitor and the output flag states can be inverted
by the user.
Timing Controlled by Small Value External
Capacitor
APPLICATIONS
•
•
•
Multiple Supply Sequencing
Microprocessor / Microcontroller Sequencing
FPGA Sequencing
Typical Application Circuit
Connection Diagram
Input Supply
(2.7 Vœ 5.5V)
8
7
6
1
2
3
VCC
FLAG1
FLAG2
LM3881
EN
GND
INV
LM3881
FLAG3
TADJ
VCC
4
5
EN
Flag1
Flag2
Flag3
FLAG1
FLAG2
INV
FLAG3
TADJ
Figure 1. Top View
VSSOP-8 Package
GND
CADJ
PIN DESCRIPTIONS
Pin #
Name
Function
1
2
3
4
5
6
7
8
VCC
Input Supply
EN
Precision Enable
Ground
GND
INV
Output Logic Invert
Timer Adjust
TADJ
FLAG3
FLAG2
FLAG1
Open Drain Output #3
Open Drain Output #2
Open Drain Output #1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
LM3881
SNVS555C –JANUARY 2008–REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
VCC, EN, INV, TADJ, FLAG1, FLAG2, FLAG3 to GND
-0.3V to +6.0V
-65°C to +150°C
150°C
Storage Temperature Range
Junction Temperature
Lead Temperature (Soldering, 5 sec.)
260°C
(3)
Minimum ESD Rating
2 kV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions,
see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Operating Ratings(1)
VCC to GND
2.7V to 5.5V
-0.3V to VCC + 0.3V
-40°C to +125°C
EN, INV, TADJ, FLAG1, FLAG2, FLAG3 to GND
Junction Temperature
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions,
see the Electrical Characteristics.
Electrical Characteristics
Specifications with standard typeface are for TJ = 25°C, and those in bold face type apply over the full Operating Temperature
Range (TJ = -40°C to +125°C). Minimum and Maximum limits are ensured through test, design or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. VCC
=
3.3V, unless otherwise specified.
Symbol
IQ
Parameter
Conditions
Min(1)
Typ(2)
Max(1)
110
Unit
Operating Quiescent Current
80
µA
Open Drain Flags
IFLAG
FLAGx Leakage Current
VFLAGx = 3.3V
IFLAGx = 1.2 mA
0.001
1
µA
V
VOL
FLAGx Output Voltage Low
0.4
Time Delays
ITADJ_SRC
ITADJ_SNK
VHTH
TADJ Source Current
TADJ Sink Current
High Threshold Level
Low Threshold Level
Clock Cycle
4
12
12
20
20
µA
µA
V
4
1.0
0.3
1.22
0.5
1.2
1.4
0.7
VLTH
V
TCLK
CADJ = 10 nF
ms
TD1, TD4
Flag Time Delay
9
10
Clock
Cycles
TD2, TD3, TD5, TD6
Flag Time Delay
8
Clock
Cycles
ENABLE Pin
VEN
EN Pin Threshold
1.0
1.22
7
1.5
V
IEN
EN Pin Pull-up Current
VEN = 0V
µA
INV Pin
VIH_INV
VIL_INV
Invert Pin VIH
Invert Pin VIL
90% VCC
V
V
10%
VCC
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical
Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
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Typical Performance Characteristics
VCC = 3.3V unless otherwise specified.
Quiescent Current
Quiescent Current
vs
vs
VCC
Temperature
82
80
80.4
80.2
80.0
79.8
79.6
78
76
74
-25
0
25
50
75 100
-50
125
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
V
(V)
CC
Figure 2.
Figure 3.
Time Delay
Enable Threshold
vs
Temperature
vs
VIN
(CADJ = 10 nF Nominal)
1.235
1.230
1.225
1.220
1.215
9.56
9.55
9.54
9.53
9.52
9.51
9.50
1.210
1.205
-25
0
25
50
75 100
-50
125
2.5
3
3.5
4
4.5
5
5.5
TEMPERATURE (°C)
V
(V)
IN
Figure 4.
Figure 5.
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Typical Performance Characteristics (continued)
VCC = 3.3V unless otherwise specified.
Time Delay
VFLAG
vs
vs
Temperature
(CADJ = 10 nF Nominal)
VIN
(INV Low, RFLAG = 100 kΩ)
9.75
9.70
9.65
9.60
9.55
1
0.8
0.6
0.4
0.2
0
9.50
9.45
-25
0
25
50
75 100
-50
125
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
(V)
2
TEMPERATURE (°C)
V
IN
Figure 6.
Figure 7.
FLAG Voltage
vs
Current
1
0.8
0.6
0.4
0.2
0
V
CC
= 3.3V
V
CC
= 5V
0
1
2
3
4
5
I
(mA)
FLAG
Figure 8.
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Block Diagram
VCC
FLAG1
FLAG2
7 mA
EN
T
+
-
D1
T
D2
T
D3
Timing
Delay
Generation
Sequence
Control
1.22V
T
D4
T
D5
T
D6
Clock
FLAG3
TADJ
GND
INV
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APPLICATION INFORMATION
OVERVIEW
The LM3881 Power Sequencer provides a simple solution for sequencing multiple rails in a controlled manner. A
clock signal is established that facilitates control of the power up and power down of three open drain FET output
flags. These flags permit connection to shutdown or enable pins of linear regulators and/or switching regulators
to control the power supplies’ operation. This allows a complete power system to be designed without worrying
about large in-rush currents or latch-up conditions that can occur during an uncontrolled startup. An invert (INV)
pin is provided that reverses the logic of the output flags. This pin should be tied to a logic output high or low and
not allowed to remain open circuit. The following discussion assumes the INV pin is held low such that the flag
output is active high.
A small external timing capacitor is connected to the TADJ pin that establishes the clock waveform. This
capacitor is linearly charged/discharged by a fixed current source/sink, denoted ITADJ_SRC / ITADJ_SNK, of
magnitude 12 µA between pre-defined voltage threshold levels, denoted VLTH and VHTH, to generate the timing
waveform as shown in the following diagram.
High Threshold Level,
V
H = 1.22V
HT
TADJ
Low Threshold Level,
= 0.5V
V
LTH
T
CLK
Figure 9. TADJ Pin Timing Waveform
Thus, the clock cycle duration is directly proportional to the timing capacitor value. Considering the TADJ voltage
threshold levels and the charge/discharge current magnitude, it can be shown that the timing capacitor-clock
period relationship is typically 120 µs/nF. For example, a 10 nF capacitor sets up a clock period of 1.2 ms.
The timing sequence of the LM3881 is controlled by the enable (EN) pin. Upon power up, all the flags are held
low until the precision enable pin exceeds its threshold. After the EN pin is asserted, the power up sequence will
commence and the open-drain flags will be sequentially released.
An internal counter will delay the first flag (FLAG1) from rising until a fixed time period, denoted by TD1 in the
following timing diagram, elapses. This corresponds to at least nine, maximum ten, clock cycles depending on
where EN is asserted relative to the clock signal. Upon release of the first flag, another timer will begin to delay
the release of the second flag (FLAG2). This time delay, denoted TD2, corresponds to exactly eight clock periods.
Similarly, FLAG3 is released after time delay TD3, again eight clock cycles, has expired. Accordingly, a TADJ
capacitor of 10 nF generates typical time delays TD2 and TD3 of 9.6 ms and TD1 of between 10.8 ms and 12.0 ms.
The power down sequence is the same as power up, but in reverse order. When the EN pin is de-asserted, a
timer will begin that delays the third flag (FLAG3) from pulling low. The second and first flag will then follow in a
sequential manner after their appropriate time delays. These time delays, denoted TD4, TD5, TD6, are equal to
TD1, TD2, TD3, respectively.
For robustness, the pull down FET associated with each flag is designed such that it can sustain a short circuit to
VCC.
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EN
FLAG1
FLAG2
FLAG3
TADJ
T
D1
T
T
D3
D2
9 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
Figure 10. Power Up Sequence, INV Low
EN
FLAG1
FLAG2
FLAG3
TADJ
T
D1
T
T
D3
D2
9 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
Figure 11. Power Up Sequence, INV High
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EN
FLAG1
FLAG2
FLAG3
TADJ
T
D4
T
T
D6
D5
9 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
Figure 12. Power Down Sequence, INV Low
EN
FLAG1
FLAG2
FLAG3
TADJ
T
T
T
D6
D4
D5
9 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
Figure 13. Power Down Sequence, INV High
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ENABLE CIRCUIT
The enable circuit is designed with an internal comparator, referenced to a bandgap voltage (1.22V), to provide a
precision threshold. This allows the timing to be set externally using a capacitor as shown in the diagram below.
Alternatively, sequencing can be based on a certain event such as a line voltage reaching 90% of its nominal
value by employing a resistor divider from VCC to Enable.
7 mA
EN
Enable
+
-
1.22V
CEN
Figure 14. Precision Enable Circuit
Using the internal pull-up current source to charge the external capacitor CEN, the time delay while the enable
voltage reaches the required threshold, assuming EN is charging from 0V, can be calculated by the equation as
follows.
1.22V x CEN
Tenable_delay
=
7 mA
EN
1.22V
0V
T
enable delay
Figure 15. Enable Delay Timing
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A resistor divider can also be used to enable the LM3881 based on exceeding a certain VCC supply voltage
threshold. Care needs to be taken when sizing the resistor divider to include the effects of the internal EN pull-up
current source. The supply voltage for which EN is asserted is given by
REN1
≈
’
÷
◊
- 7 mA (REN1llREN2
)
1 +
VCCENABLE = 1.22V
∆
REN2
«
Input Supply
(2.7V - 5.5V)
LM3881
REN1
VCC
EN
FLAG1
FLAG2
FLAG3
INV
REN2
TADJ
GND
CADJ
Figure 16. Enable Based On Input Supply Level
One of the features of the enable pin is that it provides glitch free operation. The timer will start counting at a
rising threshold, but will always reset if the enable pin is de-asserted before the first output flag is released. This
is illustrated in the timing diagram below, assuming INV is low.
EN
FLAG1
T
D1
Figure 17. Enable Glitch Timing, INV Low
If the EN pin remains high for the entire power up sequence, then the part will operate as shown in the standard
timing diagrams. However, if the EN signal is de-asserted before the power-up sequence is completed, the part
will enter a controlled shutdown. This allows the system to initiate a controlled power sequence, preventing any
latch conditions to occur. The following timing diagrams describe the flag sequence if the EN pin is de-asserted
after FLAG1 releases, but before the entire power-up sequence is completed. INV is assumed low.
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EN
FLAG1
FLAG2
FLAG3
TADJ
T
T
D1
D4
9 Clock
Cycles
9 Clock
Cycles
< 8 Clock
Cycles
EN
FLAG1
FLAG2
FLAG3
TADJ
T
D1
T
D2
T
D5
T
D4
9 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
< 8 Clock
Cycles
9 Clock
Cycles
Figure 18. Incomplete Sequence Timing, INV Low
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
LM3881MM/NOPB
LM3881MME/NOPB
LM3881MMX/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
VSSOP
VSSOP
VSSOP
DGK
8
8
8
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
STBB
ACTIVE
ACTIVE
DGK
DGK
250
Green (RoHS
& no Sb/Br)
-40 to 125
STBB
STBB
3500
Green (RoHS
& no Sb/Br)
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3881MM/NOPB
LM3881MME/NOPB
LM3881MMX/NOPB
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
8
8
8
1000
250
178.0
178.0
330.0
12.4
12.4
12.4
5.3
5.3
5.3
3.4
3.4
3.4
1.4
1.4
1.4
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
3500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM3881MM/NOPB
LM3881MME/NOPB
LM3881MMX/NOPB
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
8
8
8
1000
250
210.0
210.0
367.0
185.0
185.0
367.0
35.0
35.0
35.0
3500
Pack Materials-Page 2
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