LM393LV [TI]
LM393LV Dual and LM339LV Quad Low Voltage, Rail-to-Rail Comparators;
| 型号： | LM393LV |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LM393LV Dual and LM339LV Quad Low Voltage, Rail-to-Rail Comparators |
| 文件： | 总53页 (文件大小：3740K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM393LV, LM339LV
SNOSDA4B – JUNE 2020 – REVISED DECEMBER 2020
LM393LV Dual and LM339LV Quad Low Voltage, Rail-to-Rail Comparators
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
1.65 V to 5.5 V Supply range
Rail-to-Rail input with Failsafe
Low input offset voltage 400 μV Typ
600ns Typ propagation delay
Low quiescent current 25 µA/Ch Typ
Low input bias current 5 pA Typ
Open-drain output
Full -40°C to +125°C temperature range
Power-On Reset (POR) for known start-up
2 kV ESD protection
The LV device family consists of two (LM393LV), or
four (LM339LV), independent voltage comparators
that are designed to operate from a wide range of
supply voltages. The LV devices can drop-in replace
the standard LM2xx, LM3xx and LM290x comparator
family in low voltage (≤ 5 V) applications for improved
performance and added features.
The LV devices include a Power On Reset (POR)
feature that ensures the output is in a High-Z state
until the minimum supply voltage has been reached.
This prevents output transients during system power-
up and power-down.
Improved replacement for LM393 & LM339 family
for VCC ≤ 5 V.
These comparators also feature Rail to Rail inputs
and no output phase inversion with inputs that can go
up to 6V without damage. This makes this family of
comparators well suited for precision voltage
monitoring in harsh, noisy environments.
2 Applications
•
•
•
•
•
•
•
•
•
•
Vacuum robot
Single phase UPS
Server PSU
Cordless power tool
Wireless Infrastructure
Applicances
Building Automation
Factory automation & control
Motor drives
The LV devices are specified for the temperature
range of -40°C to +125°C, which covers the
temperature ranges of all the LM2xx, LM3xx and
LM290x comparator families.
Device Information
PART NUMBER
PACKAGE (1)
BODY SIZE (NOM)
3.91 mm × 4.90 mm
3.00 mm × 4.40 mm
3.00 mm × 3.00 mm
2.00 mm × 2.00 mm
1.60 mm × 2.90 mm
3.91 mm × 8.65 mm
4.40 mm × 5.00 mm
4.20 mm x 2.00 mm
3.00 mm × 3.00 mm
SOIC (8)
Infotainment & cluster
TSSOP (8)
VSSOP (8)
WSON (8)
LM393LV
(Dual)
SOT-23 (8)
SOIC (14)
TSSOP (14)
SOT-23-THIN (14)
WQFN (16)
LM339LV
(Quad)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
V+
IN+
IN-
+
-
OUT
Output
Control
V+
SNAPBACK
ESD
CLAMPS
SUPPLY
CLAMP
GND
GND
GND
GND
Bias
Power-On-Reset
GND
Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
LM393LV, LM339LV
SNOSDA4B – JUNE 2020 – REVISED DECEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
5.1 Pin Functions: LM393LV.............................................3
5.2 Pin Functions: LM339LV.............................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information, LM393LV ..................................6
6.5 Thermal Information, LM339LV ..................................6
6.6 Electrical Characteristics, LM393LV .......................... 7
6.7 Switching Characteristics, LM393LV ..........................8
6.8 Electrical Characteristics, LM339LV .......................... 9
6.9 Switching Characteristics, LM339LV ........................10
6.10 Typical Characteristics............................................ 11
7 Detailed Description......................................................16
7.1 Overview...................................................................16
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................16
8 Application and Implementation..................................19
8.1 Application Information............................................. 19
8.2 Typical Applications.................................................. 22
9 Power Supply Recommendations................................30
10 Layout...........................................................................30
10.1 Layout Guidelines................................................... 30
10.2 Layout Example...................................................... 30
11 Device and Documentation Support..........................31
11.1 Related Documentation...........................................31
11.2 Receiving Notification of Documentation Updates..31
11.3 Support Resources................................................. 31
11.4 Trademarks............................................................. 31
11.5 Electrostatic Discharge Caution..............................31
11.6 Glossary..................................................................31
12 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2020) to Revision B (December 2020)
Page
•
Updated LM339LV quad tables...........................................................................................................................5
Changes from Revision * (June 2020) to Revision A (September 2020)
Page
•
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Added LM339LV quad tables..............................................................................................................................5
Added Typical Graphs.......................................................................................................................................11
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5 Pin Configuration and Functions
OUT1
1
2
3
4
8
7
6
5
V+
OUT2
IN2œ
IN2+
IN1œ
IN1+
GND
Figure 5-1. D, DGK, PW, DDF Packages
8-Pin SOIC, VSSOP, TSSOP, SOT-23-8
Top View
8
V+
OUT1
1
2
Exposed
Thermal
Die Pad
on
IN1œ
7
6
OUT2
IN2œ
IN1+
GND
3
4
Underside
5
IN2+
NOTE: Connect exposed thermal pad directly to GND pin.
Figure 5-2. DSG Package
8-Pad WSON With Exposed Thermal Pad
Top View
5.1 Pin Functions: LM393LV
PIN
I/O
DESCRIPTION
NAME
OUT1
NO.
1
O
I
Output pin of the comparator 1
Inverting input pin of comparator 1
Noninverting input pin of comparator 1
Negative supply
IN1–
2
IN1+
3
I
GND
4
—
I
IN2+
5
Noninverting input pin of comparator 2
Inverting input pin of comparator 2
Output pin of the comparator 2
Positive supply
IN2–
6
I
OUT2
V+
7
O
—
—
8
Thermal Pad
—
Connect directly to GND pin
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OUT2
OUT1
V+
1
2
3
4
5
6
7
14 OUT3
OUT4
GND
IN4+
IN4œ
13
12
11
10
9
IN1œ
IN1+
IN2œ
IN3+
IN2+
IN3œ
8
Figure 5-3. D, PW, DYY Package
14-Pin SOIC, TSSOP, SOT-23
Top View
V+
IN1œ
NC
1
2
3
4
12
11
10
9
GND
IN4+
NC
Thermal
Pad
IN1+
IN4œ
Not to scale
NOTE: Connect exposed thermal pad directly to GND pin.
Figure 5-4. RTE Package
16-Pad WQFN With Exposed Thermal Pad
Top View
5.2 Pin Functions: LM339LV
PIN
I/O
DESCRIPTION
NAME(1)
OUT1
OUT2
V+
SOIC
1
WQFN
15
16
1
Output
Output
—
Output pin of the comparator 1
2
Output pin of the comparator 2
3
Positive supply
IN2–
4
2
Input
Input
Input
Input
Input
Input
Input
Input
—
Negative input pin of the comparator 2
Positive input pin of the comparator 2
Negative input pin of the comparator 1
Positive input pin of the comparator 1
Negative input pin of the comparator 3
Positive input pin of the comparator 3
Negative input pin of the comparator 4
Positive input pin of the comparator 4
Negative supply
IN2+
5
4
IN1–
6
5
IN1+
7
6
IN3–
8
7
IN3+
9
8
IN4–
10
11
12
13
14
—
—
—
9
IN4+
11
12
13
14
3
GND
OUT3
OUT4
NC
Output
Output
—
Output pin of the comparator 4
Output pin of the comparator 3
No Internal Connection - Leave floating or GND
No Internal Connection - Leave floating or GND
Connect directly to GND pin
NC
10
PAD
—
Thermal Pad
—
(1) Some manufacturers transpose the names of channels 1 & 2. Electrically the pinouts are identical, just a difference in channel naming
convention.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
6
UNIT
V
Supply voltage: VS = (V+) – (GND)
Input pins (IN+, IN–) from GND(2)
Current into Input pins (IN+, IN–)
Output (OUT) from GND(3)
–0.3
–0.3
–10
6
V
10
6
mA
V
–0.3
Output short circuit duration(4)
10
150
150
s
Junction temperature, TJ
°C
°C
Storage temperature, Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input terminals are diode-clamped to GND pin. Input signals that can swing more than 0.3 V beyond the supply rails must be current-
limited to 10 mA or less. Additionally, Inputs (IN+, IN–) can be greater than V+ and OUT as long as it is within the –0.3 V to 6 V range
(3) Output (OUT) can be greater than V+ and inputs (IN+, IN–) as long as it is within the –0.3 V to 6 V range
(4) Short circuits from outputs to V+ can cause excessive heating and eventual destruction.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.65
–0.1
–40
MAX
UNIT
V
Supply voltage: VS = (V+) – (GND)
Input voltage range (IN+, IN–) from (GND)
Ambient temperature, TA
5.5
5.6
V
125
°C
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6.4 Thermal Information, LM393LV
LM393LV
DGK
PW
DSG
DDF
THERMAL METRIC (1)
D (SOIC)
UNIT
(TSSOP) (VSSOP) (WSON) (SOT-23)
8 PINS
167.7
107.0
111.2
53.1
8 PINS
221.7
109.1
152.5
36.4
8 PINS
8 PINS
175.2
178.1
139.5
47.2
8 PINS
RqJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
–
–
–
–
–
–
–
–
–
–
–
–
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RqJC(top)
RqJB
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
yJB
110.4
–
150.7
–
138.9
127.3
RqJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information, LM339LV
LM339LV
PW
RTE
DYY
THERMAL METRIC(1)
D (SOIC)
UNIT
(TSSOP) (WQFN) (SOT-23)
14 PINS 14 PINS 16 PINS 14 PINS
RqJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
136.0
91.2
92.0
46.9
91.6
–
155.0
82.0
98.5
25.7
97.6
–
134.1
122.6
109.3
30.9
–
–
–
–
–
–
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RqJC(top)
RqJB
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
yJB
108.3
98.7
RqJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics, LM393LV
For VS (Total Supply Voltage) = (V+) – ( GND) = 5 V, VCM = ( GND) at TA = 25°C (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.4
±1.5
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
Input offset voltage
VS = 1.8 V and 5 V
VS = 1.8 V and 5 V, TA = –40°C to +125°C
–2
–3
2
3
mV
mV
VOS
dVIO/dT
Input offset voltage drift VS = 1.8 V and 5 V, TA = –40°C to +125°C
µV/°C
POWER SUPPLY
Quiescent current per
comparator
IQ
VS = 1.8 V and 5 V, No Load, Output Low
25
80
35
50
µA
dB
Quiescent current per
comparator
VS = 1.8 V and 5 V, No Load, Output Low, TA =
–40°C to +125°C
IQ
Power-supply rejection
ratio
PSRR
VS = 1.8 V to 5 V, TA = –40°C to +125°C
70
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
VCM = VS/2
VCM = VS/2
5
1
pA
pA
IOS
INPUT CAPACITANCE
Input Capacitance,
Differential
CID
CIC
VCM = VS/2
VCM = VS/2
2
3
pF
pF
Input Capacitance,
Common Mode
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM-Range
CMRR
VS = 1.8 V and 5 V, TA = –40°C to +125°C
(GND)
60
(V+)
V
Common-mode
rejection ratio
VS = 5 V, (GND) < VCM < (V+), TA = –40°C to
+125°C
65
60
dB
dB
Common-mode
rejection ratio
VS = 1.8 V, (GND) < VCM < (V+), TA = –40°C to
+125°C
CMRR
50
OPEN-LOOP GAIN
Large signal differential
voltage amplification
AVD
50
200
150
V/mV
OUTPUT
VOL
Voltage swing from
GND
ISINK = 4 mA, TA = 25°C
200
300
mV
mV
Voltage swing from
GND
VOL
ISINK = 4 mA, TA = –40°C to +125°C
Open-drain output
leakage current
ILKG
ISC
VPULLUP = (V+), TA = 25°C
VS = 5 V, Sinking
100
100
pA
Short-circuit current
60
mA
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6.7 Switching Characteristics, LM393LV
For VS (Total Supply Voltage) = (V+) – ( GND) = 5 V, VCM = VS / 2, CL = 15 pF at TA = 25°C (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Propagation delay time, high-
to-low
VID = –10 mV; Delay from mid-point of
input to mid-point of output (RP = 2.5 KΩ)
TPD-HL
600
600
20
ns
ns
Propagation delay time, low-to- VID = 10 mV; Delay from mid-point of input
high
TPD-LH
TFALL
to mid-point of output (RP = 2.5 KΩ)
5V Output Fall Time, 80% to
20%
VID = –100 mV
ns
VID = 100 mV (RP = 2.5 KΩ)
FTOGGLE
5V, Toggle Frequency
1
MHz
POWER ON TIME
PON Power on-time
VS = 1.8 V and 5 V, VCM = (GND), VID = –
0.1 V, VPULL-UP = VS / 2, Delay from VS /
2 to VOUT = 0.1 x VS / 2 (RP = 2.5 KΩ)
50
µs
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6.8 Electrical Characteristics, LM339LV
For VS (Total Supply Voltage) = (V+) – ( GND) = 5 V, VCM = ( GND) at TA = 25°C (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.4
±1.5
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
Input offset voltage
VS = 1.8 V and 5 V
VS = 1.8 V and 5 V, TA = –40°C to +125°C
–2
–3
2
3
mV
mV
VOS
dVIO/dT
Input offset voltage drift VS = 1.8 V and 5 V, TA = –40°C to +125°C
µV/°C
POWER SUPPLY
Quiescent current per
comparator
IQ
VS = 1.8 V and 5 V, No Load, Output Low
25
80
35
50
µA
dB
Quiescent current per
comparator
VS = 1.8 V and 5 V, No Load, Output Low, TA =
–40°C to +125°C
IQ
Power-supply rejection
ratio
PSRR
VS = 1.8 V to 5 V, TA = –40°C to +125°C
70
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
VCM = VS/2
VCM = VS/2
5
1
pA
pA
IOS
INPUT CAPACITANCE
Input Capacitance,
Differential
CID
CIC
VCM = VS/2
VCM = VS/2
2
3
pF
pF
Input Capacitance,
Common Mode
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM-Range
CMRR
VS = 1.8 V and 5 V, TA = –40°C to +125°C
(GND)
60
(V+)
V
Common-mode
rejection ratio
VS = 5 V, (GND) < VCM < (V+), TA = –40°C to
+125°C
65
60
dB
dB
Common-mode
rejection ratio
VS = 1.8 V, (GND) < VCM < (V+), TA = –40°C to
+125°C
CMRR
50
OPEN-LOOP GAIN
Large signal differential
voltage amplification
AVD
50
200
150
V/mV
OUTPUT
VOL
Voltage swing from
GND
ISINK = 4 mA, TA = 25°C
200
300
mV
mV
Voltage swing from
GND
VOL
ISINK = 4 mA, TA = –40°C to +125°C
Open-drain output
leakage current
ILKG
ISC
VPULLUP = (V+), TA = 25°C
VS = 5 V, Sinking
100
100
pA
Short-circuit current
60
mA
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6.9 Switching Characteristics, LM339LV
For VS (Total Supply Voltage) = (V+) – ( GND) = 5 V, VCM = VS / 2, CL = 15 pF at TA = 25°C (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Propagation delay time, high-
to-low
VID = –10 mV; Delay from mid-point of
input to mid-point of output (RP = 2.5 KΩ)
TPD-HL
600
600
20
ns
ns
Propagation delay time, low-to- VID = 10 mV; Delay from mid-point of input
high
TPD-LH
TFALL
to mid-point of output (RP = 2.5 KΩ)
5V Output Fall Time, 80% to
20%
VID = –100 mV
ns
VID = 100 mV (RP = 2.5 KΩ)
FTOGGLE
5V, Toggle Frequency
1
MHz
POWER ON TIME
PON Power on-time
VS = 1.8 V and 5 V, VCM = (GND), VID = –
0.1 V, VPULL-UP = VS / 2, Delay from VS /
2 to VOUT = 0.1 x VS / 2 (RP = 2.5 KΩ)
50
µs
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6.10 Typical Characteristics
TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = GND, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless
otherwise noted.
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
36
34
32
30
28
26
24
22
20
No Load, Output High
125°C
85°C
25°C
-40°C
5V
3.3V
1.8V
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 6-1. Supply Current vs. Supply Voltage
Figure 6-2. Supply Current vs. Temperature
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
125°C
125°C
85°C
25°C
-40°C
85°C
25°C
-40°C
VS=1.8V
VS=3.3V
-0.2
0
0.2 0.4 0.6 0.8
1
Input Voltage (V)
1.2 1.4 1.6 1.8
2
-0.2 0.2 0.6
1
1.4 1.8 2.2 2.6
Input Voltage (V)
3
3.4
Figure 6-3. Supply Current vs. Input Voltage, 1.8V
40
Figure 6-4. Supply Current vs. Input Voltage, 3.3V
1000
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
100
10
1
0.1
125°C
85°C
25°C
-40°C
VS = 5V
VIN = VS/2
0.01
VS=5V
0.002
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-0.5
0
0.5
1
1.5
2
2.5
3
Input Voltage (V)
3.5
4
4.5
5
5.5
Figure 6-6. Input Bias Current vs. Temperature
Figure 6-5. Supply Current vs. Input Voltage, 5V
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6.10 Typical Characteristics (continued)
TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = GND, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless
otherwise noted.
10
1
10
1
100m
10m
1m
100m
10m
1m
125°C
85°C
25°C
-40°C
125°C
85°C
25°C
-40°C
100m
1m 10m
Output Sinking Current (A)
100m
100m
1m 10m
Output Sinking Current (A)
100m
Figure 6-7. Output Sinking Current vs. Output Voltage, 1.8V
Figure 6-8. Output Sinking Current vs. Output Voltage, 3.3V
10
130
120
5V
3.3V
1.8
110
100
90
80
70
60
50
40
30
20
10
0
1
100m
125°C
85°C
25°C
-40°C
10m
1m
100m
1m 10m
Output Sinking Current (A)
100m
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 6-9. Output Sinking Current vs. Output Voltage, 5V
Figure 6-10. Sinking Short Circuit Current vs. Temperature
1k
1k
VS = 5V
VS = 5V
100
100
10
10
125°C
125°C
85°C
25°C
-40°C
85°C
25°C
-40°C
1
1
10p
100p 1n
Output Capacittive Load (F)
10n
10p
100p 1n
Output Capacittive Load (F)
10n
Figure 6-11. Risetime vs. Capacitive Load
Figure 6-12. Falltime vs. Capacitive Load
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6.10 Typical Characteristics (continued)
TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = GND, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless
otherwise noted.
700
650
600
550
500
450
400
350
300
250
200
150
100
50
700
650
600
550
500
450
400
350
300
250
200
150
100
50
-40°C
25°C
85°C
125°C
VS = 1.8V
-40°C
25°C
85°C
125°C
VS = 1.8V
0
0
5 6 78 10
20 30 4050 70 100 200 300 500
Input Overdrive (mV)
1000
5 6 78 10
20 30 4050 70 100 200 300 500
Input Overdrive (mV)
1000
Figure 6-13. Propagation Delay, High to Low, 1.8V
700
Figure 6-14. Propagation Delay, Low to High, 1.8V
700
125°C
85°C
25°C
-40°C
25°C
85°C
VS = 3.3V
VS = 3.3V
650
600
550
500
450
400
350
300
250
200
150
100
50
650
600
550
500
450
400
350
300
250
200
150
100
50
-40°C
125°C
0
0
5 6 78 10
20 30 4050 70 100 200 300 500
Input Overdrive (mV)
1000
5 6 78 10
20 30 4050 70 100 200 300 500
Input Overdrive (mV)
1000
Figure 6-15. Propagation Delay, High to Low, 3.3V
700
Figure 6-16. Propagation Delay, Low to High, 3.3V
700
-40°C
-40°C
25°C
85°C
VS = 5V
650
600
550
500
450
400
350
300
250
200
150
100
50
650
600
550
500
450
400
350
300
250
200
150
100
50
VS = 5V
25°C
85°C
125°C
125°C
0
0
5 6 78 10
20 30 4050 70 100 200 300 500
Input Overdrive (mV)
1000
5 6 78 10
20 30 4050 70 100 200 300 500
Input Overdrive (mV)
1000
Figure 6-17. Propagation Delay, High to Low, 5V
Figure 6-18. Propagation Delay, Low to High, 5V
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6.10 Typical Characteristics (continued)
TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = GND, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless
otherwise noted.
2
1.6
1.2
0.8
0.4
0
2
1.6
1.2
0.8
0.4
0
TA = 125°C
TA = 125°C
-0.4
-0.8
-1.2
-1.6
-2
-0.4
-0.8
-1.2
-1.6
-2
Unit 1
Unit 2
Unit 3
Unit 4
Unit 1
Unit 2
Unit 3
Unit 4
-0.2
0
0.2 0.4 0.6 0.8
1
Input Voltage (V)
1.2 1.4 1.6 1.8
2
-0.5
0
0.5
1
1.5
2
2.5
Input Voltage (V)
3
3.5
4
4.5
5
5.5
Figure 6-19. Offset Voltage vs. Input Votlage at 125°C, 1.8V
Figure 6-20. Offset Voltage vs. Input Votlage at 125°C, 5V
2
2
TA = 25°C
1.6
TA = 25°C
1.6
1.2
0.8
0.4
0
1.2
0.8
0.4
0
-0.4
-0.4
-0.8
-0.8
Unit 1
Unit 2
Unit 3
Unit 4
Unit 1
Unit 2
Unit 3
Unit 4
-1.2
-1.2
-1.6
-2
-1.6
-2
-0.2
0
0.2 0.4 0.6 0.8
1
Input Voltage (V)
1.2 1.4 1.6 1.8
2
-0.5
0
0.5
1
1.5
2
2.5
Input Voltage (V)
3
3.5
4
4.5
5
5.5
Figure 6-21. Offset Voltage vs. Input Votlage at 25°C, 1.8V
Figure 6-22. Offset Voltage vs. Input Votlage at 25°C, 5V
2
2
TA = -40°C
1.6
TA = -40°C
1.6
1.2
0.8
0.4
0
1.2
0.8
0.4
0
-0.4
-0.4
-0.8
-0.8
Unit 1
Unit 2
Unit 3
Unit 4
Unit 1
Unit 2
Unit 3
Unit 4
-1.2
-1.2
-1.6
-2
-1.6
-2
-0.2
0
0.2 0.4 0.6 0.8
1
Input Voltage (V)
1.2 1.4 1.6 1.8
2
-0.5
0
0.5
1
1.5
2
2.5
Input Voltage (V)
3
3.5
4
4.5
5
5.5
Figure 6-23. Offset Voltage vs. Input Votlage at -40°C, 1.8V
Figure 6-24. Offset Voltage vs. Input Votlage at -40°C, 5V
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6.10 Typical Characteristics (continued)
TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = GND, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless
otherwise noted.
2
1.6
1.2
0.8
0.4
0
2
1.6
1.2
0.8
0.4
0
TA = 125°C
Vin = V+
TA = 125°C
Vin = GND
-0.4
-0.8
-1.2
-1.6
-2
-0.4
-0.8
-1.2
-1.6
-2
Unit 1
Unit 2
Unit 3
Unit 4
Unit 1
Unit 2
Unit 3
Unit 4
1.5
2
2.5
3
Supply Voltage (V)
3.5
4
4.5
5
5.5
1.5
2
2.5
3
Supply Voltage (V)
3.5
4
4.5
5
5.5
Figure 6-25. Offset Voltage vs. Supply Voltage at 125°C, VIN=V+ Figure 6-26. Offset Voltage vs. Supply Voltage at 125°C, VIN=0V
2
1.6
1.2
0.8
0.4
0
2
1.6
1.2
0.8
0.4
0
Unit 1
Unit 2
Unit 3
Unit 4
Unit 1
Unit 2
Unit 3
Unit 4
TA = -40°C
Vin = GND
TA = 25°C
Vin = V+
-0.4
-0.8
-1.2
-1.6
-2
-0.4
-0.8
-1.2
-1.6
-2
1.5
2
2.5
3
Supply Voltage (V)
3.5
4
4.5
5
5.5
1.5
2
2.5
3
Supply Voltage (V)
3.5
4
4.5
5
5.5
Figure 6-27. Offset Voltage vs. Supply Voltage at 25°C, VIN=V+
Figure 6-28. Offset Voltage vs. Supply Voltage at 25°C, VIN=0V
2
2
Unit 1
Unit 2
Unit 3
Unit 4
TA = -40°C
1.6
TA = -40°C
1.6
Vin = GND
1.2
0.8
Vin = V+
1.2
0.8
0.4
0
0.4
0
-0.4
-0.4
-0.8
-1.2
-1.6
-2
-0.8
Unit 1
Unit 2
Unit 3
Unit 4
-1.2
-1.6
-2
1.5
2
2.5
3
Supply Voltage (V)
3.5
4
4.5
5
5.5
1.5
2
2.5
3
Supply Voltage (V)
3.5
4
4.5
5
5.5
Figure 6-29. Offset Voltage vs. Supply Voltage at -40°C, VIN=V+ Figure 6-30. Offset Voltage vs. Supply Voltage at -40°C, VIN=0V
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7 Detailed Description
7.1 Overview
The LV Family devices are micro-power comparators with open-drain outputs and improved input offset voltage
that operate down to 1.65 V while only consuming only 25 µA per channel. The LV family are ideally suited for
portable, automotive and industrial applications. An internal power-on reset circuit ensures that the output
remains in a known state during power-up and power-down while fail-safe inputs can tolerate input transients
without damage or false outputs.
7.2 Functional Block Diagram
V+
IN+
IN-
+
-
Output
Control
OUT
V+
SNAPBACK
ESD
CLAMPS
GND
GND
GND
GND
Power-On-Reset
(POR)
Bias
GND
7.3 Feature Description
The LV family devices are micro-power comparators that have low input offset voltages and are capable of
operating at low voltages. The LV family feature a rail-to-rail input stage capable of operating up to 100 mV
beyond the power supply rails. The comparators also feature an open-drain output stage options with Power On
Reset for known start-up conditions.
7.4 Device Functional Modes
7.4.1 Open Drain Output
The LV family features an open-drain (also commonly called open collector) sinking-only output stage enabling
the output logic levels to be pulled up to an external voltage from 0 V up to 5.5 V, independent of the comparator
supply voltage (V+). The open-drain output also allows logical OR'ing of multiple open drain outputs and logic
level translation. TI recommends setting the pull-up resistor current to between 100uA and 1mA. Lower pull-up
resistor values will help increase the rising edge risetime, but at the expense of increasing VOL and higher power
dissipation. The risetime will be dependant on the time constant of the total pull-up resistance and total load
capacitance. Large value pull-up resistors (>1 MΩ) will create an exponential rising edge due to the RC time
constant and increase the risetime.
Unused open drain outputs should be left floating, or can be tied to the GND pin if floating pins are not allowed.
While an individual output can typically sink up to 100 mA, the total combined current for all channels must be
less than 200 mA.
7.4.2 Power-On Reset (POR)
The LV family has an internal Power-on-Reset (POR) circuit for known start-up or power-down conditions. While
the power supply (V+) is ramping up or ramping down, the POR circuitry will be activated for up to 30µs after the
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minimum supply voltage threshold of 1.5V is crossed, or immediately when the supply voltage drops below 1.5V.
When the supply voltage is equal to or greater than the minimum supply voltage, and after the delay period, the
comparator output reflects the state of the differential input (VID).
The POR circuit will keep the output high impedance (HI-Z) during the POR period (ton).
tON
GND
GND + 1.5V
VCC
VOH/2
GND
OUT
Figure 7-1. Power-On Reset Timing Diagram
Note that it is the nature of an open collector output that the output will rise with the pull-up voltage during the
POR period.
A light pull-up (to V+) or pull-down (to GND) resistor can be used to pre-bias the output condition to prevent the
output from floating.
7.4.3 Inputs
7.4.3.1 Rail to Rail Input
The LV family input voltage range extends from 100mV below GND to 100 mV above V+. The differential input
voltage (VID) can be any voltage within these limits. No phase-inversion of the comparator output will occur when
the input pins exceed V+ or GND.
7.4.3.2 Fault Tolerant Inputs
The LV family inputs are fault tolerant up to 5.5V independent of V+. Fault tolerant is defined as maintaining the
same high input impedance when V+ is unpowered or within the recommended operating ranges.
The fault tolerant inputs can be any value between 0 V and 5.5 V, even while V+ is zero or ramping up or down.
This feature avoids power sequencing issues as long as the input voltage range and supply voltage are within
the specified ranges. This is possible since the inputs are not clamped to V+ and the input current maintains its
value even when a higher voltage is applied to the inputs.
As long as one of the input pins remains within the valid input range, and the supply voltage is valid and not in
POR, the output state will be correct.
The following is a summary of input voltage excursions and their outcomes:
1. When both IN- and IN+ are within the specified input voltage range:
a. If IN- is higher than IN+ and the offset voltage, the output is low.
b. If IN- is lower than IN+ and the offset voltage, the output is high.
2. When IN- is outside the specified input voltage range and IN+ is within the specified voltage range, the output
is low.
3. When IN+ is higher than the specified input voltage range and IN- is within the specified input voltage range,
the output is high
4. When IN- and IN+ are both outside the specified input voltage range, the output is indeterminate (random).
Do not operate in this region.
Even with the fault tolerant feature, TI strongly recommends keeping the inputs within the specified input voltage
range during normal system operation to maintain datasheet specifications. Operating outside the specified input
range can cause changes in specifications such as propagation delay, which can lead to unpredictable behavior.
7.4.3.3 Input Protection
The input bias current is typically 5 pA for input voltages between V+ and GND. The comparator inputs are
protected from reverse voltage by the internal ESD diodes connected to GND. As the input voltage goes under
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GND, or above the input Absolute Maximum ratings the protection diodes become forward biased and begin to
conduct causing the input bias current to increase exponentially. Input bias current typically doubles for each
10°C temperature increase.
If the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line,
TI recommends adding a current-limiting resistor in series with the input to limit any transient currents should the
clamps conduct. The current should be limited 10 mA or less. This series resistance can be part of any resistive
input dividers or networks.
7.4.4 ESD Protection
The LV family incorporates internal ESD protection circuits on all pins. The inputs, and the open-drain output,
use a proprietary "snapback" type ESD clamp from each pin to GND, which allows the pins to exceed the supply
voltage (V+). While shown as Zener diodes, snapbacks momentarily "short" and go low impedance (like an
SCR) when the threshold is exceeded, as opposed to clamping to a defined voltage like a Zener. There is no
ESD clamp from the inputs to V+.
The open-drain output protection also consists of a ESD clamp between the output and GND to allow the output
to be pulled above V+ to a maximum of 5.5V. There is no ESD clamp from the output to V+.
If the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line,
TI recommends adding a current-limiting resistor in series with the input to limit any transient currents should the
clamps conduct. The current should be limited 10 mA or less. This series resistance can be part of any resistive
input dividers or networks.
TI does not specify the performance of the ESD clamps and external clamping diodes should be added if the
inputs or output could exceed the maximum ratings as part of normal operation.
7.4.5 Unused Inputs
If a channel is not to be used, DO NOT tie the inputs together. Due to the high equivalent bandwidth and low
offset voltage, tying the inputs directly together can cause high frequency oscillations as the device triggers on
it's own internal wideband noise. Instead, the inputs should be tied to any available voltage that resides within
the specified input voltage range and provides a minimum of 50mV differential voltage. For example, one input
can be grounded and the other input connected to a reference voltage, or even V+ (as long as the input is
directly connected to the V+ pin to avoid transients).
7.4.6 Hysteresis
The LV family does not have internal hysteresis. Due to the wide effective bandwidth and low input offset
voltage, it is possible for the output to "chatter" (oscillate) when the absolute differential voltage near zero, as the
comparator triggers on it's own internal wideband noise. TI recommends that the user add external hysteresis if
slow moving signals are expected. See Section 8.1.2 in the following section.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Basic Comparator Definitions
8.1.1.1 Operation
The basic comparator compares the input voltage (VIN) on one input to a reference voltage (VREF) on the other
input. In the Figure 8-1 example below, if VIN is less than VREF, the output voltage (VO) is logic low (VOL). If VIN is
greater than VREF, the output voltage (VO) is at logic high (VOH). Table 8-1 summarizes the output conditions.
The output logic can be inverted by simply swapping the input pins.
Table 8-1. Output Conditions
Inputs Condition
IN+ > IN-
Output
HIGH (VOH
)
IN+ = IN-
Indeterminate (chatters - see Hysteresis)
LOW (VOL
IN+ < IN-
)
8.1.1.2 Propagation Delay
There is a delay between from when the input crosses the reference voltage and the output responds. This is
called the Propagation Delay. Propagation delay can be different between high-to low and low-to-high input
transitions. This is shown as tpLH and tpHL in Figure 8-1 and is measured from the mid-point of the input to the
midpoint of the output.
V
+ 200mV
V+
REF
Input
+
V
IN
Output
V
OD (+200mV)
V
+ 100mV
REF
REF
œ
V
IN
GND
+
V
REF
V
REF
œ
V
5 100mV
V
OD (-200mV)
V
- 200mV
REF
tpLH
tpHL
V
OH
80%
80%
Output
50%
20%
50%
20%
V
OL
tR
Figure 8-1. Comparator Timing Diagram
tF
8.1.1.3 Overdrive Voltage
The overdrive voltage, VOD, is the amount of input voltage beyond the reference voltage (and not the total input
peak-to-peak voltage). The overdrive voltage is 100mV as shown in the Figure 8-1 example. The overdrive
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voltage can influence the propagation delay (tp). The smaller the overdrive voltage, the longer the propagation
delay, particularly when <100mV. If the fastest speeds are desired, it is recommended to apply the highest
amount of overdrive possible.
The risetime (tr) and falltime (tf) is the time from the 20% and 80% points of the output waveform.
8.1.2 Hysteresis
The basic comparator configuration may oscillate or produce a noisy "chatter" output if the applied differential
input voltage is near the comparator's offset voltage. This usually occurs when the input signal is moving very
slowly across the switching threshold of the comparator.
This problem can be prevented by the addition of hysteresis or positive feedback.
The hysteresis transfer curve is shown in Figure 8-2. This curve is a function of three components: VTH, VOS
and VHYST
,
:
•
•
VTH is the actual set voltage or threshold trip voltage.
VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip
point at which the comparator must respond to change output states.
•
VHYST is the hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise.
V
+ V œ (V
/ 2)
V
TH
+ V
V
+ V + (V
OS
/ 2)
TH
OS
HYST
OS
TH
HYST
Figure 8-2. Hysteresis Transfer Curve
For more information, please see Application Note SBOA219 "Comparator with and without hysteresis circuit".
8.1.2.1 Inverting Comparator With Hysteresis
The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator
supply voltage (VCC), as shown in Figure 8-3.
+V
CC
+5 V
R
1
R
PU
1 MΩ
10 kΩ
5 V
0 V
V
IN
œ
V
O
V
O
V
A
+
V
A2
V
A1
1.67 V
3.33 V
V
IN
R
3
R
2
1 MΩ
1 MΩ
Figure 8-3. Inverting Configuration With Hysteresis
The equivalent resistor networks when the output is high and low are shown in Figure 8-3. Note that RPU should
be considered in series with R3 when the output is high. RPU should be at least 10x less than R3.
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V
High
V Low
O
O
+V
+V
CC
CC
R
R *
3
R
1
1
V
A1
V
A2
R
3
R
R
2
2
* R = R + R
PU
3
3
Figure 8-4. Inverting Configuration Resistor Equivalent Networks
When VIN is less than VA, the output voltage is high (for simplicity, assume VO switches as high as VCC). The
three network resistors can be represented as R1 || R3 in series with R2, as shown in Figure 8-4.
Equation 1 below defines the high-to-low trip voltage (VA1).
R2
VA1 = VCC
´
(R1 || R3) + R2
(1)
When VIN is greater than VA, the output voltage is low. In this case, the three network resistors can be presented
as R2 || R3 in series with R1, as shown in Equation 2.
Use Equation 2 to define the low to high trip voltage (VA2).
R2 || R3
VA2 = VCC
´
R1 + (R2 || R3)
(2)
(3)
Equation 3 defines the total hysteresis provided by the network.
DVA = VA1 - VA2
8.1.2.2 Non-Inverting Comparator With Hysteresis
A noninverting comparator with hysteresis requires a two-resistor network and a voltage reference (VREF) at the
inverting input, as shown in Figure 8-5,
+V
CC
+5 V
R
PU
5 V
0 V
V
œ
REF 2.5 V
V
V
O
V
O
A
V
+
IN
V
V
IN2
IN1
R
1
1.675 V
3.325 V
330 kΩ
V
IN
R
2
1 MΩ
Figure 8-5. Non-Inverting Configuration With Hysteresis
The equivalent resistor networks when the output is high and low are shown in Figure 8-6 Note that RPU should
be considered in series with R2 when the output is high. RPU should be at least 10x less than R2.
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V
Low
IN1
V
High
O
O
+V
+V
CC
*R
R
R
2
1
V
A
= V
V
= V
A REF
REF
R
1
2
* R = R + R
PU
2
2
V
IN2
Figure 8-6. Non-Inverting Configuration Resistor Networks
When VIN is less than VREF,, the output is low. For the output to switch from low to high, VIN must rise above the
VIN1 threshold. Use Equation 4 to calculate VIN1
.
VREF
VIN1 = R1 ´
+ VREF
R2
(4)
When VIN is greater than VREF, the output is high. For the comparator to switch back to a low state, VIN must
drop below VIN2. Use Equation 5 to calculate VIN2
.
VREF (R1 + R2) - VCC ´ R1
VIN2
=
R2
(5)
(6)
The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in Equation 6.
R1
DVIN = VCC
´
R2
For more information, please see Application Notes SNOA997 "Inverting comparator with hysteresis circuit" and
SBOA313 "Non-Inverting Comparator With Hysteresis Circuit".
8.2 Typical Applications
8.2.1 Window Comparator
Window comparators are commonly used to detect undervoltage and overvoltage conditions. Figure 8-7 shows a
simple window comparator circuit. Window comparators require open drain outputs if the outputs are directly
connected together.
3.3 V
RPU
R
1
Low when V > V
IN
TH+
10 MΩ
UV_OV
+
V
TH+
Micro-
Controller
œ
Sensor
Open Drain Output Only!
V
IN
R
2
10 MΩ
Low when V < V
IN
TH-
+
Output high
when V is
IN
œ
V
TH-
within window
R
3
Open Drain Output Only!
10 MΩ
Figure 8-7. Window Comparator
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8.2.1.1 Design Requirements
For this design, follow these design requirements:
•
•
•
•
Alert (logic low output) when an input signal is less than 1.1 V
Alert (logic low output) when an input signal is greater than 2.2 V
Alert signal is active low
Operate from a 3.3-V power supply
8.2.1.2 Detailed Design Procedure
Configure the circuit as shown in Figure 8-7. Connect VCC to a 3.3-V power supply and VEE to ground. Make R1,
R2 and R3 each 10-MΩ resistors. These three resistors are used to create the positive and negative thresholds
for the window comparator (VTH+ and VTH–).
With each resistor being equal, VTH+ is 2.2 V and VTH- is 1.1 V. Large resistor values such as 10-MΩ are used to
minimize power consumption. The resistor values may be recalculated to provide the desired trip point values.
The sensor output voltage is applied to the inverting and noninverting inputs of the two comparators. Using two
open-drain output comparators allows the two comparator outputs to be Wire-OR'ed together.
The respective comparator outputs will be low when the sensor is less than 1.1 V or greater than 2.2 V. The
respective comparator outputs will be high when the sensor is in the range of 1.1 V to 2.2 V (within the
"window"), as shown in Figure 8-8.
8.2.1.3 Application Curve
V
IN
V + = 2.2 V
TH
V
= 1.1 V
THœ
OUT
Figure 8-8. Window Comparator Results
For more information, please see Application note SBOA221 "Window comparator circuit".
8.2.2 Square-Wave Oscillator
Square-wave oscillator can be used as low cost timing reference or system supervisory clock source.
R4
100 kΩ
+
V
t
C1
100 pF
1
+
V
R
PU
10 kΩ
V
C
+
OUT
0
t
2
œ
R1
100 kΩ
R3
100 kΩ
V
A
V
CC
R2
100 kΩ
Figure 8-9. Square-Wave Oscillator
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8.2.2.1 Design Requirements
The square-wave period is determined by the RC time constant of the capacitor C 1 and resistor R 4. The
maximum frequency is limited by propagation delay of the device and the capacitance load at the output. The
low input bias current allows a lower capacitor value and larger resistor value combination for a given oscillator
frequency, which may help to reduce BOM cost and board space. R4 should be over several kilo-ohms to
minimize loading the output.
8.2.2.2 Detailed Design Procedure
The oscillation frequency is determined by the resistor and capacitor values. The following calculation provides
details of the steps.
Figure 8-10. Square-Wave Oscillator Timing Thresholds
First consider the output of Figure Figure 8-9 as high, which indicates the inverted input VC is lower than the
noninverting input (VA). This causes the C1 to be charged through R4, and the voltage VC increases until it is
equal to the noninverting input. The value of VA at the point is calculated by Equation 7.
VCCìR2
R2 + R1IIR3
VA1
=
(7)
if R1 = R2= R3, then VA1 = 2 VCC/ 3
At this time the comparator output trips pulling down the output to the negative rail. The value of VAat this point is
calculated by Equation 8.
VCC(R2IIR3 )
VA2
=
R1+R2IIR3
(8)
if R1 = R2 = R3, then VA2 = VCC/3
The C1 now discharges though the R4, and the voltage VCC decreases until it reaches VA2. At this point, the
output switches back to the starting state. The oscillation period equals to the time duration from for C1 from
2VCC/3 to VCC / 3 then back to 2VCC/3, which is given by R4C1 × ln 2 for each trip. Therefore, the total time
duration is calculated as 2 R4C1 × ln 2.
The oscillation frequency can be obtained by Equation 9:
f = 1/ 2 R4ìC1ìIn2
(9)
8.2.2.3 Application Curve
Figure 8-11 shows the simulated results of an oscillator using the following component values:
•
•
•
R1 = R2 = R3 = R4 = 100 kΩ
C1 = 100 pF, CL = 20 pF
V+ = 5 V, V– = GND
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•
Cstray (not shown) from VA TO GND = 10 pF
Figure 8-11. Square-Wave Oscillator Output Waveform
8.2.3 Adjustable Pulse Width Generator
Figure 8-12 is a variation on the square wave oscillator that allows adjusting the pulse widths.
R4 and R5 provide separate charge and discharge paths for the capacitor C depending on the output state.
R4
1 MΩ
D1
R5
100 kΩ
+
V
D2
t
C1
100 pF
1
+
R
V
PU
10 kΩ
V
V
C
+
OUT
0
t
2
œ
R1
100 kΩ
R3
100 kΩ
A
V
CC
R2
100 kΩ
Figure 8-12. Adjustable Pulse Width Generator
The charge path is set through R5 and D2 when the output is high. Similarly, the discharge path for the capacitor
is set by R4 and D1 when the output is low.
The pulse width t1 is determined by the RC time constant of R5 and C. Thus, the time t2 between the pulses can
be changed by varying R 4, and the pulse width can be altered by R 5. The frequency of the output can be
changed by varying both R4 and R5. At low voltages, the effects of the diode forward drop (0.8 V, or 0.15 V for
Shottky) must be taken into account by altering output high and low voltages in the calculations. RPU should be
at least 10x less than the smallest value of R4 or R5.
8.2.4 Time Delay Generator
The circuit shown in Figure 8-13 provides output signals at a prescribed time interval from a time reference and
automatically resets the output low when the input returns to 0V. This is useful for sequencing a "power on"
signal to trigger a controlled start-up of power supplies.
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+V
RPU not required if using
push-pull output devices
+V
LOGIC3
100 kΩ
10 MΩ
Open
Drain
Output
R
PU
R
100 kΩ
+
V
IN
V
10 kΩ
10 kΩ
10 kΩ
+
V
C
0
+
4
t
t4
0
œ
1
V
3
Input
Gating
Signal
œ
C
+V
LOGIC2
t
t
3
0
100 kΩ
51 kΩ
R
PU
10 MΩ
+
2
œ
V
2
V
V
3
+V
LOGIC1
t
t
2
0
2
51 kΩ
10 MΩ
R
PU
V
C
V
1
+
3
V
1
t
2
t
0
t
1
t
3
t
4
œ
t
t
1
0
51 kΩ
Figure 8-13. Time Delay Generator
Consider the case of VIN = 0. The output of comparator 4 is also at ground, "shorting" the capacitor and holding it
at 0V. This implies that the outputs of comparators 1, 2, and 3 are also at 0V. When an input signal is applied,
the output of open drain comparator 4 goes High-Z and C charges exponentially through R. This is indicated in
the graph. The output voltages of comparators 1, 2, and 3 switch to the high state in sequence when VC rises
above the reference voltages V1, V2 and V3. A small amount of hysteresis has been provided by the 10 kΩ and
10 MΩ resistors to insure fast switching when the RC time constant is chosen to give long delay times. A good
starting point is R = 100 kΩ and C = 0.01 µF to 1 µF.
All outputs will immediately go low when VIN falls to 0V, due to the comparator output going low and immediately
discharging the capacitor.
Comparator 4 must be a open-drain type output (TLV902x), whereas comparators 1 though 3 may be either
open drain or push-pull output, depending on system requirements. R PU is not required for push-pull output
devices.
8.2.5 Logic Level Shifter
The output is the uncommitted drain of the output transistor. Many open-drain outputs can be tied together to
provide an output OR'ing function if desired.
V
LOGIC
V
CC
Logic
In
V
CC
R
PULLUP
+
Logic
Out
0
œ
Open
Drain
Output
R1
V
CC
10 kΩ
V
R2
10 kΩ
LOGIC
0
Figure 8-14. Universal Logic Level Shifter
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The two 10 kΩ resistors bias the input to half of the input logic supply level to set the threshold in the mid-point of
the input logic levels. Only one shared output pull-up resistor is needed and may be connected to any pull-up
voltage between 0 V and 5.5 V. The pullup voltage should match the driven logic input "high" level.
8.2.6 One-Shot Multivibrator
+V
+V
R1
C1
1 MΩ
100 pF
R
PULLUP
+V
IN
V
2
1
+V
0
œ
PW
R2
1 MΩ
+
D1
1N4148
t
0
C2
t
0
t
1
V
D2
1N4148
R4
Figure 8-15. One-Shot Multivibrator
A monostable multivibrator has one stable state in which it can remain indefinitely. It can be triggered externally
to another quasi-stable state. A monostable multivibrator can thus be used to generate a pulse of desired width.
The desired pulse width is set by adjusting the values of C2 and R4. The resistor divider of R1 and R2 can be
used to determine the magnitude of the input trigger pulse. The output will change state when V1 < V2. Diode D2
provides a rapid discharge path for capacitor C2 to reset at the end of the pulse. The diode also prevents the
non-inverting input from being driven below ground.
8.2.7 Bi-Stable Multivibrator
R
R3
PU
R4
100 kΩ
4.7 kΩ
50 kΩ
R1
100 kΩ
+V
S
+
SET
œ
RESET
R
R2
100 kΩ
Figure 8-16. Bi-Stable Multivibrator
A bi-stable multivibrator has two stable states. The reference voltage is set up by the voltage divider of R2 and
R3. A pulse applied to the SET terminal will switch the output of the comparator high. The resistor divider of R1,
R4, and R5 now clamps the non-inverting input to a voltage greater than the reference voltage. A pulse applied to
RESET will now toggle the output low.
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8.2.8 Zero Crossing Detector
+V
R
R3
100 kΩ
R4
100 kΩ
PU
10 kΩ
R1
5 kΩ
R2
5 kΩ
V
3
V
IN
œ
V
2
V
OUT
+
D1
BAT54
V
1
R4
20 MΩ
R5
10 kΩ
R1 = R2 = (R5 / 2)
Figure 8-17. Zero Crossing Detector
A voltage divider of R4 and R5 establishes a reference voltage V1 at the non-inverting input. By making the
series resistance of R1 and R2 equal to R5, the comparator will switch when VIN = 0. Diode D1 insures that V3
clamps near ground. The voltage divider of R2 and R3 then prevents V2 from going below ground. A small
amount of hysteresis is setup to ensure rapid output voltage transitions.
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8.2.9 Pulse Slicer
A Pulse Slicer is a variation of the Zero Crossing Detector and is used to detect the zero crossings on an input
signal with a varying baseline level. This circuit works best with symmetrical waveforms. The RC network of R1
and C1 establishes an mean reference voltage VREF, which tracks the mean amplitude of the VIN signal. The
noninverting input is directly connected to VREF through R2. R2 and R3 are used to produce hysteresis to keep
transitions free of spurious toggles. The time constant is a tradeoff between long-term symmetry and response
time to changes in amplitude.
If the waveform is data, it is recommended that the data be encoded in NRZ (Non-Return to Zero) format to
maintain proper average baseline. Asymmetrical inputs may suffer from timing distortions caused by the
changing VREF average voltage.
V
PU
V
REF
R
PU
470 kꢀ
R1
470 kꢀ
10M ꢀ
R3
+
R2
U1
Output
V
IN
œ
C1
0.01 ꢁF
Figure 8-18. Pulse Slicer
For this design, follow these design requirements:
•
The RC constant value (R2 and C1) must support the targeted data rate in order to maintain a valid tripping
threshold.
•
The hysteresis introduced with R2 and R43 helps to avoid spurious output toggles.
Figure 8-19 shows the results of a 9600 baud data signal riding on a varying baseline.
1.8 V
VIN
1.2 V
4.0 V
VOUT
0.0 V
1.61 V
VREF
1.58 V
0.0
200.0 u
400.0 u
Time
600.0 u
800.0 u
Figure 8-19. Pulse Slicer Waveforms
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9 Power Supply Recommendations
Due to the fast output edges, it is critical to have bypass capacitors on the supply pin to prevent supply ringing
and false triggers and oscillations. Bypass the supply directly at each device with a low ESR 0.1 µF ceramic
bypass capacitor directly between VCC pin and ground pins. Narrow, peak currents will be drawn during the
output transition time, particularly for the push-pull output device. These narrow pulses can cause un-bypassed
supply lines and poor grounds to ring, possibly causing variation that can eat into the input voltage range and
create an inaccurate comparison or even oscillations.
The device may also be powered from "split" supplies (V+, V- and GND), with V- applied to the GND pin.
Input signals must stay within the specified input range (between V+ and V-) for both supply types.
Note that the ouptut will now swing "low" (VOL) to V- potential and not system GND on split supplies.
10 Layout
10.1 Layout Guidelines
For accurate comparator applications it is important maintain a stable power supply with minimized noise and
glitches. Output rise and fall times are in the tens of nanoseconds, and should be treated as high speed logic
devices. The bypass capacitor should be as close to the supply pin as possible and connected to a solid ground
plane, and preferably directly between the VCC and GND pins.
Minimize coupling between outputs and inputs to prevent output oscillations. Do not run output and input traces
in parallel unless there is a VCC or GND trace between output to reduce coupling. When series resistance is
added to inputs, place resistor close to the device. A low value (<100 ohms) resistor may also be added in series
with the output to dampen any ringing or reflections on long, non-impedance controlled traces. For best edge
shapes, controlled impedance traces with back-terminations should be used when routing long distances.
10.2 Layout Example
Ground
Better
0.1mF
VCC
1
2
3
4
8
7
6
5
1OUT
1IN-
VCC
2OUT
2IN-
Input Resistors
Close to device
OK
VCC or GND
1IN+
GND
Ground
2IN+
Figure 10-1. Dual Layout Example
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11 Device and Documentation Support
11.1 Related Documentation
Analog Engineers Circout Cookbook: Amplifers (See Comparators section) - SLYY137
Precision Design, Comparator with Hysteresis Reference Design— TIDU020
Window comparator circuit - SBOA221
Reference Design, Window Comparator Reference Design— TIPD178
Comparator with and without hysteresis circuit - SBOA219
Zero crossing detection using comparator circuit - SNOA999
A Quad of Independently Func Comparators - SNOA654
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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6-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM339LVPWR
LM339LVRTER
LM393LVDGKR
LM393LVDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
WQFN
VSSOP
SOIC
PW
RTE
DGK
D
14
16
8
2000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LM339LV
NIPDAU
SN
L339LV
2IHT
8
NIPDAU
NIPDAU
NIPDAU
L393LV
L393
LM393LVDSGR
LM393LVPWR
WSON
TSSOP
DSG
PW
8
8
L393LV
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Nov-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM339LV, LM393LV :
Automotive : LM339LV-Q1, LM393LV-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM339LVPWR
LM339LVRTER
LM393LVDGKR
LM393LVDR
TSSOP
WQFN
VSSOP
SOIC
PW
RTE
DGK
D
14
16
8
2000
3000
2500
2500
3000
2000
330.0
330.0
330.0
330.0
180.0
330.0
12.4
12.4
12.4
12.4
8.4
6.9
3.3
5.3
6.4
2.3
7.0
5.6
3.3
3.4
5.2
2.3
3.6
1.6
1.1
1.4
2.1
1.15
1.6
8.0
8.0
8.0
8.0
4.0
8.0
12.0
12.0
12.0
12.0
8.0
Q1
Q2
Q1
Q1
Q2
Q1
8
LM393LVDSGR
LM393LVPWR
WSON
TSSOP
DSG
PW
8
8
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Nov-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM339LVPWR
LM339LVRTER
LM393LVDGKR
LM393LVDR
TSSOP
WQFN
VSSOP
SOIC
PW
RTE
DGK
D
14
16
8
2000
3000
2500
2500
3000
2000
853.0
367.0
366.0
367.0
210.0
853.0
449.0
367.0
364.0
367.0
185.0
449.0
35.0
35.0
50.0
35.0
35.0
35.0
8
LM393LVDSGR
LM393LVPWR
WSON
TSSOP
DSG
PW
8
8
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.32
0.18
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
8X
0.4
0.2
PIN 1 ID
8X
0.1
C A B
C
0.05
4218900/D 04/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/D 04/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/D 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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