LM3S102 [TI]
Microcontroller;
| 型号： | LM3S102 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Microcontroller 微控制器 |
| 文件： | 总484页 (文件大小：3882K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NRND: Not recommended for new designs.
TEXAS INSTRUMENTS-PRODUCTION DATA
Stellaris® LM3S102 Microcontroller
DATA SHEET
DS-LM3S102-12972.2532
SPMS006I
Copyright © 2007-2012
Texas Instruments Incorporated
NRND: Not recommended for new designs.
Copyright
Copyright © 2007-2012 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare® are registered trademarks of Texas Instruments
Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the
property of others.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/stellaris
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
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Stellaris® LM3S102 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 19
About This Document .................................................................................................................... 23
Audience .............................................................................................................................................. 23
About This Manual ................................................................................................................................ 23
Related Documents ............................................................................................................................... 23
Documentation Conventions .................................................................................................................. 24
1
Architectural Overview .......................................................................................... 26
Product Features .......................................................................................................... 26
Target Applications ........................................................................................................ 31
High-Level Block Diagram ............................................................................................. 32
Functional Overview ...................................................................................................... 34
1.1
1.2
1.3
1.4
1.4.1 ARM Cortex™-M3 ......................................................................................................... 34
1.4.2 Motor Control Peripherals .............................................................................................. 35
1.4.3 Analog Peripherals ........................................................................................................ 35
1.4.4 Serial Communications Peripherals ................................................................................ 35
1.4.5 System Peripherals ....................................................................................................... 37
1.4.6 Memory Peripherals ...................................................................................................... 37
1.4.7 Additional Features ....................................................................................................... 38
1.4.8 Hardware Details .......................................................................................................... 38
1.4.9 System Block Diagram .................................................................................................. 39
2
2.1
2.2
The Cortex-M3 Processor ...................................................................................... 40
Block Diagram .............................................................................................................. 41
Overview ...................................................................................................................... 42
2.2.1 System-Level Interface .................................................................................................. 42
2.2.2 Integrated Configurable Debug ...................................................................................... 42
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 43
2.2.4 Cortex-M3 System Component Details ........................................................................... 43
2.3
Programming Model ...................................................................................................... 44
2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 44
2.3.2 Stacks .......................................................................................................................... 44
2.3.3 Register Map ................................................................................................................ 45
2.3.4 Register Descriptions .................................................................................................... 46
2.3.5 Exceptions and Interrupts .............................................................................................. 59
2.3.6 Data Types ................................................................................................................... 59
2.4
Memory Model .............................................................................................................. 59
2.4.1 Memory Regions, Types and Attributes ........................................................................... 60
2.4.2 Memory System Ordering of Memory Accesses .............................................................. 61
2.4.3 Behavior of Memory Accesses ....................................................................................... 61
2.4.4 Software Ordering of Memory Accesses ......................................................................... 61
2.4.5 Bit-Banding ................................................................................................................... 63
2.4.6 Data Storage ................................................................................................................ 65
2.4.7 Synchronization Primitives ............................................................................................. 65
2.5
Exception Model ........................................................................................................... 66
2.5.1 Exception States ........................................................................................................... 67
2.5.2 Exception Types ............................................................................................................ 67
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2.5.3 Exception Handlers ....................................................................................................... 70
2.5.4 Vector Table .................................................................................................................. 70
2.5.5 Exception Priorities ....................................................................................................... 71
2.5.6 Interrupt Priority Grouping .............................................................................................. 72
2.5.7 Exception Entry and Return ........................................................................................... 72
2.6
Fault Handling .............................................................................................................. 74
2.6.1 Fault Types ................................................................................................................... 74
2.6.2 Fault Escalation and Hard Faults .................................................................................... 75
2.6.3 Fault Status Registers and Fault Address Registers ........................................................ 76
2.6.4 Lockup ......................................................................................................................... 76
2.7
Power Management ...................................................................................................... 76
2.7.1 Entering Sleep Modes ................................................................................................... 76
2.7.2 Wake Up from Sleep Mode ............................................................................................ 77
2.8
Instruction Set Summary ............................................................................................... 77
3
3.1
Cortex-M3 Peripherals ........................................................................................... 81
Functional Description ................................................................................................... 81
3.1.1 System Timer (SysTick) ................................................................................................. 81
3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................... 82
3.1.3 System Control Block (SCB) .......................................................................................... 84
3.2
3.3
3.4
3.5
Register Map ................................................................................................................ 84
System Timer (SysTick) Register Descriptions ................................................................ 85
NVIC Register Descriptions ........................................................................................... 89
System Control Block (SCB) Register Descriptions .......................................................... 97
4
JTAG Interface ...................................................................................................... 124
Block Diagram ............................................................................................................ 125
Signal Description ....................................................................................................... 125
Functional Description ................................................................................................. 126
4.1
4.2
4.3
4.3.1 JTAG Interface Pins ..................................................................................................... 126
4.3.2 JTAG TAP Controller ................................................................................................... 128
4.3.3 Shift Registers ............................................................................................................ 129
4.3.4 Operational Considerations .......................................................................................... 129
4.4
4.5
Initialization and Configuration ..................................................................................... 131
Register Descriptions .................................................................................................. 131
4.5.1 Instruction Register (IR) ............................................................................................... 131
4.5.2 Data Registers ............................................................................................................ 133
5
5.1
5.2
System Control ..................................................................................................... 135
Signal Description ....................................................................................................... 135
Functional Description ................................................................................................. 135
5.2.1 Device Identification .................................................................................................... 135
5.2.2 Reset Control .............................................................................................................. 136
5.2.3 Power Control ............................................................................................................. 140
5.2.4 Clock Control .............................................................................................................. 140
5.2.5 System Control ........................................................................................................... 143
5.3
5.4
5.5
Initialization and Configuration ..................................................................................... 145
Register Map .............................................................................................................. 145
Register Descriptions .................................................................................................. 146
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6
6.1
6.2
Internal Memory ................................................................................................... 185
Block Diagram ............................................................................................................ 185
Functional Description ................................................................................................. 185
6.2.1 SRAM Memory ............................................................................................................ 185
6.2.2 Flash Memory ............................................................................................................. 186
6.3
Flash Memory Initialization and Configuration ............................................................... 188
6.3.1 Changing Flash Protection Bits .................................................................................... 188
6.3.2 Flash Programming ..................................................................................................... 189
6.4
6.5
6.6
Register Map .............................................................................................................. 190
Flash Register Descriptions (Flash Control Offset) ......................................................... 190
Flash Register Descriptions (System Control Offset) ...................................................... 198
7
General-Purpose Input/Outputs (GPIOs) ........................................................... 202
Block Diagram ............................................................................................................ 203
Signal Description ....................................................................................................... 203
Functional Description ................................................................................................. 206
7.1
7.2
7.3
7.3.1 Data Control ............................................................................................................... 207
7.3.2 Interrupt Control .......................................................................................................... 208
7.3.3 Mode Control .............................................................................................................. 209
7.3.4 Pad Control ................................................................................................................. 209
7.3.5 Identification ............................................................................................................... 209
7.4
7.5
7.6
Initialization and Configuration ..................................................................................... 209
Register Map .............................................................................................................. 210
Register Descriptions .................................................................................................. 212
8
General-Purpose Timers ...................................................................................... 244
Block Diagram ............................................................................................................ 244
Signal Description ....................................................................................................... 245
Functional Description ................................................................................................. 246
8.1
8.2
8.3
8.3.1 GPTM Reset Conditions .............................................................................................. 246
8.3.2 32-Bit Timer Operating Modes ...................................................................................... 246
8.3.3 16-Bit Timer Operating Modes ...................................................................................... 247
8.4
Initialization and Configuration ..................................................................................... 251
8.4.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 251
8.4.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 252
8.4.3 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 252
8.4.4 16-Bit Input Edge Count Mode ..................................................................................... 253
8.4.5 16-Bit Input Edge Timing Mode .................................................................................... 253
8.4.6 16-Bit PWM Mode ....................................................................................................... 254
8.5
8.6
Register Map .............................................................................................................. 254
Register Descriptions .................................................................................................. 255
9
Watchdog Timer ................................................................................................... 280
Block Diagram ............................................................................................................ 281
Functional Description ................................................................................................. 281
Initialization and Configuration ..................................................................................... 282
Register Map .............................................................................................................. 282
Register Descriptions .................................................................................................. 283
9.1
9.2
9.3
9.4
9.5
10
10.1
Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 304
Block Diagram ............................................................................................................ 305
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10.2
10.3
Signal Description ....................................................................................................... 305
Functional Description ................................................................................................. 306
10.3.1 Transmit/Receive Logic ............................................................................................... 306
10.3.2 Baud-Rate Generation ................................................................................................. 306
10.3.3 Data Transmission ...................................................................................................... 307
10.3.4 FIFO Operation ........................................................................................................... 307
10.3.5 Interrupts .................................................................................................................... 308
10.3.6 Loopback Operation .................................................................................................... 309
10.4
10.5
10.6
Initialization and Configuration ..................................................................................... 309
Register Map .............................................................................................................. 310
Register Descriptions .................................................................................................. 311
11
Synchronous Serial Interface (SSI) .................................................................... 344
Block Diagram ............................................................................................................ 344
Signal Description ....................................................................................................... 344
Functional Description ................................................................................................. 345
11.1
11.2
11.3
11.3.1 Bit Rate Generation ..................................................................................................... 345
11.3.2 FIFO Operation ........................................................................................................... 346
11.3.3 Interrupts .................................................................................................................... 346
11.3.4 Frame Formats ........................................................................................................... 346
11.4
11.5
11.6
Initialization and Configuration ..................................................................................... 354
Register Map .............................................................................................................. 355
Register Descriptions .................................................................................................. 356
12
Inter-Integrated Circuit (I2C) Interface ................................................................ 382
Block Diagram ............................................................................................................ 383
Signal Description ....................................................................................................... 383
Functional Description ................................................................................................. 383
12.1
12.2
12.3
12.3.1 I2C Bus Functional Overview ........................................................................................ 384
12.3.2 Available Speed Modes ............................................................................................... 386
12.3.3 Interrupts .................................................................................................................... 386
12.3.4 Loopback Operation .................................................................................................... 387
12.3.5 Command Sequence Flow Charts ................................................................................ 387
12.4
12.5
12.6
12.7
Initialization and Configuration ..................................................................................... 394
Register Map .............................................................................................................. 395
Register Descriptions (I2C Master) ............................................................................... 396
Register Descriptions (I2C Slave) ................................................................................. 409
13
Analog Comparator .............................................................................................. 418
Block Diagram ............................................................................................................ 418
Signal Description ....................................................................................................... 418
Functional Description ................................................................................................. 419
13.1
13.2
13.3
13.3.1 Internal Reference Programming .................................................................................. 420
13.4
13.5
13.6
Initialization and Configuration ..................................................................................... 421
Register Map .............................................................................................................. 421
Register Descriptions .................................................................................................. 422
14
Pin Diagram .......................................................................................................... 430
15
15.1
Signal Tables ........................................................................................................ 432
28-Pin SOIC Package Pin Tables ................................................................................. 432
15.1.1 Signals by Pin Number ................................................................................................ 432
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15.1.2 Signals by Signal Name ............................................................................................... 433
15.1.3 Signals by Function, Except for GPIO ........................................................................... 435
15.1.4 GPIO Pins and Alternate Functions .............................................................................. 436
15.2
48-Pin Package Pin Table ............................................................................................ 436
15.2.1 Signals by Pin Number ................................................................................................ 436
15.2.2 Signals by Signal Name ............................................................................................... 438
15.2.3 Signals by Function, Except for GPIO ........................................................................... 440
15.2.4 GPIO Pins and Alternate Functions .............................................................................. 441
15.3
Connections for Unused Signals ................................................................................... 441
16
Operating Characteristics ................................................................................... 443
17
17.1
Electrical Characteristics .................................................................................... 444
DC Characteristics ...................................................................................................... 444
17.1.1 Maximum Ratings ....................................................................................................... 444
17.1.2 Recommended DC Operating Conditions ...................................................................... 444
17.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 445
17.1.4 GPIO Module Characteristics ....................................................................................... 445
17.1.5 Power Specifications ................................................................................................... 445
17.1.6 Flash Memory Characteristics ...................................................................................... 446
17.2
AC Characteristics ....................................................................................................... 446
17.2.1 Load Conditions .......................................................................................................... 446
17.2.2 Clocks ........................................................................................................................ 447
17.2.3 JTAG and Boundary Scan ............................................................................................ 447
17.2.4 Reset ......................................................................................................................... 449
17.2.5 Sleep Modes ............................................................................................................... 451
17.2.6 General-Purpose I/O (GPIO) ........................................................................................ 451
17.2.7 Synchronous Serial Interface (SSI) ............................................................................... 452
17.2.8 Inter-Integrated Circuit (I2C) Interface ........................................................................... 453
17.2.9 Analog Comparator ..................................................................................................... 454
A
A.1
A.2
Serial Flash Loader .............................................................................................. 455
Serial Flash Loader ..................................................................................................... 455
Interfaces ................................................................................................................... 455
A.2.1 UART ......................................................................................................................... 455
A.2.2 SSI ............................................................................................................................. 455
A.3
Packet Handling .......................................................................................................... 456
A.3.1 Packet Format ............................................................................................................ 456
A.3.2 Sending Packets ......................................................................................................... 456
A.3.3 Receiving Packets ....................................................................................................... 456
A.4
Commands ................................................................................................................. 457
A.4.1 COMMAND_PING (0X20) ............................................................................................ 457
A.4.2 COMMAND_GET_STATUS (0x23) ............................................................................... 457
A.4.3 COMMAND_DOWNLOAD (0x21) ................................................................................. 457
A.4.4 COMMAND_SEND_DATA (0x24) ................................................................................. 458
A.4.5 COMMAND_RUN (0x22) ............................................................................................. 458
A.4.6 COMMAND_RESET (0x25) ......................................................................................... 458
B
Register Quick Reference ................................................................................... 460
C
C.1
Ordering and Contact Information ..................................................................... 475
Ordering Information .................................................................................................... 475
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C.2
C.3
C.4
Part Markings .............................................................................................................. 475
Kits ............................................................................................................................. 476
Support Information ..................................................................................................... 476
D
D.1
Package Information ............................................................................................ 477
28-Pin SOIC Package .................................................................................................. 477
D.1.1 Package Dimensions ................................................................................................... 477
D.2 48-Pin LQFP Package ................................................................................................. 479
D.2.1 Package Dimensions ................................................................................................... 479
D.2.2 Tray Dimensions ......................................................................................................... 481
D.2.3 Tape and Reel Dimensions .......................................................................................... 483
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Stellaris® LM3S102 Microcontroller
List of Figures
Figure 1-1.
Figure 1-2.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 6-1.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 7-4.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 9-1.
Stellaris LM3S102 Microcontroller High-Level Block Diagram ................................. 33
LM3S102 Controller System-Level Block Diagram ................................................. 39
CPU Block Diagram ............................................................................................. 42
TPIU Block Diagram ............................................................................................ 43
Cortex-M3 Register Set ........................................................................................ 45
Bit-Band Mapping ................................................................................................ 64
Data Storage ....................................................................................................... 65
Vector Table ........................................................................................................ 71
Exception Stack Frame ........................................................................................ 73
JTAG Module Block Diagram .............................................................................. 125
Test Access Port State Machine ......................................................................... 129
IDCODE Register Format ................................................................................... 133
BYPASS Register Format ................................................................................... 134
Boundary Scan Register Format ......................................................................... 134
Basic RST Configuration .................................................................................... 137
External Circuitry to Extend Power-On Reset ....................................................... 138
Reset Circuit Controlled by Switch ...................................................................... 138
Main Clock Tree ................................................................................................ 141
Flash Block Diagram .......................................................................................... 185
GPIO Module Block Diagram .............................................................................. 203
GPIO Port Block Diagram ................................................................................... 207
GPIODATA Write Example ................................................................................. 208
GPIODATA Read Example ................................................................................. 208
GPTM Module Block Diagram ............................................................................ 245
16-Bit Input Edge Count Mode Example .............................................................. 249
16-Bit Input Edge Time Mode Example ............................................................... 250
16-Bit PWM Mode Example ................................................................................ 251
WDT Module Block Diagram .............................................................................. 281
Figure 10-1. UART Module Block Diagram ............................................................................. 305
Figure 10-2. UART Character Frame ..................................................................................... 306
Figure 11-1. SSI Module Block Diagram ................................................................................. 344
Figure 11-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 347
Figure 11-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 348
Figure 11-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 348
Figure 11-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 349
Figure 11-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 350
Figure 11-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 350
Figure 11-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 351
Figure 11-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 352
Figure 11-10. MICROWIRE Frame Format (Single Frame) ........................................................ 352
Figure 11-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 353
Figure 11-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 354
Figure 12-1. I2C Block Diagram ............................................................................................. 383
Figure 12-2. I2C Bus Configuration ........................................................................................ 384
Figure 12-3. START and STOP Conditions ............................................................................. 384
Figure 12-4. Complete Data Transfer with a 7-Bit Address ....................................................... 385
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Figure 12-5. R/S Bit in First Byte ............................................................................................ 385
Figure 12-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 385
Figure 12-7. Master Single SEND .......................................................................................... 388
Figure 12-8. Master Single RECEIVE ..................................................................................... 389
Figure 12-9. Master Burst SEND ........................................................................................... 390
Figure 12-10. Master Burst RECEIVE ...................................................................................... 391
Figure 12-11. Master Burst RECEIVE after Burst SEND ............................................................ 392
Figure 12-12. Master Burst SEND after Burst RECEIVE ............................................................ 393
Figure 12-13. Slave Command Sequence ................................................................................ 394
Figure 13-1. Analog Comparator Module Block Diagram ......................................................... 418
Figure 13-2. Structure of Comparator Unit .............................................................................. 419
Figure 13-3. Comparator Internal Reference Structure ............................................................ 420
Figure 14-1. 28-Pin SOIC Package Pin Diagram ..................................................................... 430
Figure 14-2. 48-Pin QFP Package Pin Diagram ...................................................................... 431
Figure 17-1. Load Conditions ................................................................................................ 447
Figure 17-2. JTAG Test Clock Input Timing ............................................................................. 448
Figure 17-3. JTAG Test Access Port (TAP) Timing .................................................................. 448
Figure 17-4. JTAG TRST Timing ............................................................................................ 449
Figure 17-5. External Reset Timing (RST) .............................................................................. 449
Figure 17-6. Power-On Reset Timing ..................................................................................... 450
Figure 17-7. Brown-Out Reset Timing .................................................................................... 450
Figure 17-8. Software Reset Timing ....................................................................................... 450
Figure 17-9. Watchdog Reset Timing ..................................................................................... 451
Figure 17-10. LDO Reset Timing ............................................................................................. 451
Figure 17-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 452
Figure 17-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 453
Figure 17-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 453
Figure 17-14. I2C Timing ......................................................................................................... 454
Figure D-1. Stellaris LM3S102 28-Pin SOIC Package ............................................................ 477
Figure D-2. Stellaris LM3S102 48-Pin LQFP Package ........................................................... 479
Figure D-3. 48-Pin LQFP Tray Dimensions ........................................................................... 481
Figure D-4. 48-Pin LQFP Tape and Reel Dimensions ............................................................. 483
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Stellaris® LM3S102 Microcontroller
List of Tables
Table 1.
Table 2.
Revision History .................................................................................................. 19
Documentation Conventions ................................................................................ 24
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 45
Processor Register Map ....................................................................................... 45
PSR Register Combinations ................................................................................. 51
Memory Map ....................................................................................................... 59
Memory Access Behavior ..................................................................................... 61
SRAM Memory Bit-Banding Regions .................................................................... 63
Peripheral Memory Bit-Banding Regions ............................................................... 63
Exception Types .................................................................................................. 69
Interrupts ............................................................................................................ 69
Exception Return Behavior ................................................................................... 74
Faults ................................................................................................................. 75
Fault Status and Fault Address Registers .............................................................. 76
Cortex-M3 Instruction Summary ........................................................................... 78
Core Peripheral Register Regions ......................................................................... 81
Peripherals Register Map ..................................................................................... 84
Interrupt Priority Levels ...................................................................................... 103
JTAG_SWD_SWO Signals (28SOIC) .................................................................. 125
JTAG_SWD_SWO Signals (48QFP) ................................................................... 126
JTAG Port Pins Reset State ............................................................................... 126
JTAG Instruction Register Commands ................................................................. 131
System Control & Clocks Signals (28SOIC) ......................................................... 135
System Control & Clocks Signals (48QFP) .......................................................... 135
Reset Sources ................................................................................................... 136
Clock Source Options ........................................................................................ 141
Possible System Clock Frequencies Using the SYSDIV Field ............................... 142
System Control Register Map ............................................................................. 145
PLL Mode Control .............................................................................................. 157
Flash Protection Policy Combinations ................................................................. 186
Flash Register Map ............................................................................................ 190
GPIO Pins With Non-Zero Reset Values .............................................................. 204
GPIO Pins and Alternate Functions (28SOIC) ...................................................... 204
GPIO Pins and Alternate Functions (48QFP) ....................................................... 204
GPIO Signals (28SOIC) ..................................................................................... 205
GPIO Signals (48QFP) ....................................................................................... 205
GPIO Pad Configuration Examples ..................................................................... 209
GPIO Interrupt Configuration Example ................................................................ 210
GPIO Register Map ........................................................................................... 211
Available CCP Pins ............................................................................................ 245
General-Purpose Timers Signals (28SOIC) ......................................................... 245
General-Purpose Timers Signals (48QFP) ........................................................... 246
16-Bit Timer With Prescaler Configurations ......................................................... 248
Timers Register Map .......................................................................................... 254
Watchdog Timer Register Map ............................................................................ 282
UART Signals (28SOIC) ..................................................................................... 305
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 6-1.
Table 6-2.
Table 7-1.
Table 7-2.
Table 7-3.
Table 7-4.
Table 7-5.
Table 7-6.
Table 7-7.
Table 7-8.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Table 9-1.
Table 10-1.
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Table 10-2.
Table 10-3.
Table 11-1.
Table 11-2.
Table 11-3.
Table 12-1.
Table 12-2.
Table 12-3.
Table 12-4.
Table 12-5.
Table 13-1.
Table 13-2.
Table 13-3.
Table 13-4.
Table 13-5.
Table 15-1.
Table 15-2.
Table 15-3.
Table 15-4.
Table 15-5.
Table 15-6.
Table 15-7.
Table 15-8.
Table 15-9.
Table 16-1.
Table 16-2.
Table 16-3.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 17-5.
Table 17-6.
Table 17-7.
Table 17-8.
Table 17-9.
UART Signals (48QFP) ...................................................................................... 305
UART Register Map ........................................................................................... 310
SSI Signals (28SOIC) ........................................................................................ 345
SSI Signals (48QFP) .......................................................................................... 345
SSI Register Map .............................................................................................. 355
I2C Signals (28SOIC) ........................................................................................ 383
I2C Signals (48QFP) .......................................................................................... 383
Examples of I2C Master Timer Period versus Speed Mode ................................... 386
Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 395
Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) .................................... 400
Analog Comparators Signals (28SOIC) ............................................................... 419
Analog Comparators Signals (48QFP) ................................................................ 419
Comparator 0 Operating Modes ......................................................................... 420
Internal Reference Voltage and ACREFCTL Field Values ..................................... 420
Analog Comparators Register Map ..................................................................... 422
Signals by Pin Number ....................................................................................... 432
Signals by Signal Name ..................................................................................... 433
Signals by Function, Except for GPIO ................................................................. 435
GPIO Pins and Alternate Functions ..................................................................... 436
Signals by Pin Number ....................................................................................... 436
Signals by Signal Name ..................................................................................... 438
Signals by Function, Except for GPIO ................................................................. 440
GPIO Pins and Alternate Functions ..................................................................... 441
Connections for Unused Signals ......................................................................... 442
Temperature Characteristics ............................................................................... 443
Thermal Characteristics ..................................................................................... 443
ESD Absolute Maximum Ratings ........................................................................ 443
Maximum Ratings .............................................................................................. 444
Recommended DC Operating Conditions ............................................................ 444
LDO Regulator Characteristics ........................................................................... 445
GPIO Module DC Characteristics ........................................................................ 445
Detailed Power Specifications ............................................................................ 446
Flash Memory Characteristics ............................................................................ 446
Phase Locked Loop (PLL) Characteristics ........................................................... 447
Clock Characteristics ......................................................................................... 447
JTAG Characteristics ......................................................................................... 447
Table 17-10. Reset Characteristics ......................................................................................... 449
Table 17-11. Sleep Modes AC Characteristics ......................................................................... 451
Table 17-12. GPIO Characteristics ......................................................................................... 451
Table 17-13. SSI Characteristics ............................................................................................ 452
Table 17-14. I2C Characteristics ............................................................................................. 453
Table 17-15. Analog Comparator Characteristics ..................................................................... 454
Table 17-16. Analog Comparator Voltage Reference Characteristics ........................................ 454
Table C-1.
Part Ordering Information ................................................................................... 475
12
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List of Registers
The Cortex-M3 Processor ............................................................................................................. 40
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Cortex General-Purpose Register 0 (R0) ........................................................................... 47
Cortex General-Purpose Register 1 (R1) ........................................................................... 47
Cortex General-Purpose Register 2 (R2) ........................................................................... 47
Cortex General-Purpose Register 3 (R3) ........................................................................... 47
Cortex General-Purpose Register 4 (R4) ........................................................................... 47
Cortex General-Purpose Register 5 (R5) ........................................................................... 47
Cortex General-Purpose Register 6 (R6) ........................................................................... 47
Cortex General-Purpose Register 7 (R7) ........................................................................... 47
Cortex General-Purpose Register 8 (R8) ........................................................................... 47
Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 47
Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 47
Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 47
Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 47
Register 14: Stack Pointer (SP) ........................................................................................................... 48
Register 15: Link Register (LR) ............................................................................................................ 49
Register 16: Program Counter (PC) ..................................................................................................... 50
Register 17: Program Status Register (PSR) ........................................................................................ 51
Register 18: Priority Mask Register (PRIMASK) .................................................................................... 55
Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 56
Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 57
Register 21: Control Register (CONTROL) ........................................................................................... 58
Cortex-M3 Peripherals ................................................................................................................... 81
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
SysTick Control and Status Register (STCTRL), offset 0x010 ............................................. 86
SysTick Reload Value Register (STRELOAD), offset 0x014 ................................................ 88
SysTick Current Value Register (STCURRENT), offset 0x018 ............................................. 89
Interrupt 0-29 Set Enable (EN0), offset 0x100 .................................................................... 90
Interrupt 0-29 Clear Enable (DIS0), offset 0x180 ................................................................ 91
Interrupt 0-29 Set Pending (PEND0), offset 0x200 ............................................................. 92
Interrupt 0-29 Clear Pending (UNPEND0), offset 0x280 ..................................................... 93
Interrupt 0-29 Active Bit (ACTIVE0), offset 0x300 ............................................................... 94
Interrupt 0-3 Priority (PRI0), offset 0x400 .......................................................................... 95
Register 10: Interrupt 4-7 Priority (PRI1), offset 0x404 .......................................................................... 95
Register 11: Interrupt 8-11 Priority (PRI2), offset 0x408 ......................................................................... 95
Register 12: Interrupt 12-15 Priority (PRI3), offset 0x40C ...................................................................... 95
Register 13: Interrupt 16-19 Priority (PRI4), offset 0x410 ....................................................................... 95
Register 14: Interrupt 20-23 Priority (PRI5), offset 0x414 ....................................................................... 95
Register 15: Interrupt 24-27 Priority (PRI6), offset 0x418 ....................................................................... 95
Register 16: Interrupt 28-29 Priority (PRI7), offset 0x41C ...................................................................... 95
Register 17: Software Trigger Interrupt (SWTRIG), offset 0xF00 ............................................................ 97
Register 18: CPU ID Base (CPUID), offset 0xD00 ................................................................................. 98
Register 19: Interrupt Control and State (INTCTRL), offset 0xD04 ......................................................... 99
Register 20: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 102
Register 21: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 103
Register 22: System Control (SYSCTRL), offset 0xD10 ....................................................................... 105
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Register 23: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 107
Register 24: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 109
Register 25: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 110
Register 26: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 111
Register 27: System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 112
Register 28: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 116
Register 29: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 121
Register 30: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 122
Register 31: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 123
System Control ............................................................................................................................ 135
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Device Identification 0 (DID0), offset 0x000 ..................................................................... 147
Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 .................................. 149
LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 150
Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 151
Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 152
Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 153
Reset Cause (RESC), offset 0x05C ................................................................................ 154
Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 155
XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 158
Register 10: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 159
Register 11: Clock Verification Clear (CLKVCLR), offset 0x150 ............................................................ 160
Register 12: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ................................. 161
Register 13: Device Identification 1 (DID1), offset 0x004 ..................................................................... 162
Register 14: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 164
Register 15: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 165
Register 16: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 166
Register 17: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 168
Register 18: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 169
Register 19: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 170
Register 20: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 171
Register 21: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 172
Register 22: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 173
Register 23: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 175
Register 24: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 177
Register 25: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 179
Register 26: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 180
Register 27: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 181
Register 28: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 182
Register 29: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 183
Register 30: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 184
Internal Memory ........................................................................................................................... 185
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Flash Memory Address (FMA), offset 0x000 .................................................................... 191
Flash Memory Data (FMD), offset 0x004 ......................................................................... 192
Flash Memory Control (FMC), offset 0x008 ..................................................................... 193
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 195
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 196
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 197
USec Reload (USECRL), offset 0x140 ............................................................................ 199
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Register 8:
Register 9:
Flash Memory Protection Read Enable (FMPRE), offset 0x130 ......................................... 200
Flash Memory Protection Program Enable (FMPPE), offset 0x134 .................................... 201
General-Purpose Input/Outputs (GPIOs) ................................................................................... 202
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
GPIO Data (GPIODATA), offset 0x000 ............................................................................ 213
GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 214
GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 215
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 216
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 217
GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 218
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 219
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 220
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 221
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 222
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 224
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 225
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 226
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 227
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 228
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 229
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 230
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 231
Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 232
Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 233
Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 234
Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 235
Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 236
Register 24: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 237
Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 238
Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 239
Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 240
Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 241
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 242
Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 243
General-Purpose Timers ............................................................................................................. 244
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 256
GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 257
GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 259
GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 261
GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 264
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 266
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 267
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 268
GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 270
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 271
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 272
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 273
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 274
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 275
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Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 276
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 277
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 278
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 279
Watchdog Timer ........................................................................................................................... 280
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 284
Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 285
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 286
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 287
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 288
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 289
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 290
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 291
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 292
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 293
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 294
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 295
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 296
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 297
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 298
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 299
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 300
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 301
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 302
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 303
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 304
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
UART Data (UARTDR), offset 0x000 ............................................................................... 312
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 314
UART Flag (UARTFR), offset 0x018 ................................................................................ 316
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 318
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 319
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 320
UART Control (UARTCTL), offset 0x030 ......................................................................... 322
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 324
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 326
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 328
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 329
Register 12: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 330
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 332
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 333
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 334
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 335
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 336
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 337
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 338
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 339
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 340
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 341
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Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 342
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 343
Synchronous Serial Interface (SSI) ............................................................................................ 344
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 357
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 359
SSI Data (SSIDR), offset 0x008 ...................................................................................... 361
SSI Status (SSISR), offset 0x00C ................................................................................... 362
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 364
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 365
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 367
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 368
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 369
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 370
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 371
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 372
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 373
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 374
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 375
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 376
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 377
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 378
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 379
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 380
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 381
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 382
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 397
I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 398
I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 402
I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 403
I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 404
I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 405
I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 406
I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 407
I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 408
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 410
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 411
Register 12: I2C Slave Data (I2CSDR), offset 0x808 ........................................................................... 413
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 414
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 415
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 416
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 417
Analog Comparator ..................................................................................................................... 418
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 423
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 424
Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 425
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 426
Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 427
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Register 6:
Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 428
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Revision History
The revision history table notes changes made between the indicated revisions of the LM3S102
data sheet.
Table 1. Revision History
Date
Revision Description
July 2012
12972.2532
■
Marked 28-pin SOIC package as OBSOLETE.
June 2012
12972.2532
■
In Reset Characteristics table, changed values and units for Internal reset timeout after hardware
reset (R7).
■
■
Removed 48QFN package.
Minor data sheet clarifications and corrections.
November 2011
11107
■
■
Added module-specific pin tables to each chapter in the new Signal Description sections.
In Timer chapter, clarified that in 16-Bit Input Edge Time Mode, the timer is capable of capturing
three types of events: rising edge, falling edge, or both.
■
■
■
In UART chapter, clarified interrupt behavior.
In SSI chapter, corrected SSIClk in the figure "Synchronous Serial Frame Format (Single Transfer)".
In Signal Tables chapter:
–
Corrected pin numbers in table "Connections for Unused Signals" (other pin tables were correct).
■
In Electrical Characteristics chapter:
–
–
Added parameter "Input voltage for a GPIO configured as an analog input" to the "Maximum
Ratings" table.
Corrected Nom values for parameters "TCK clock Low time" and "TCK clock High time" in "JTAG
Characteristics" table.
■
Additional minor data sheet clarifications and corrections.
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Revision History
Table 1. Revision History (continued)
Date
Revision Description
January 2011
9102
■
In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ
to SYSRESREQ.
■
■
■
■
■
Added DEBUG (Debug Priority) bit field to System Handler Priority 3 (SYSPRI3) register.
Added missing bit MMARV to the Configurable Fault Status (FAULTSTAT) register.
Added "Reset Sources" table to System Control chapter.
Removed mention of false-start bit detection in the UART chapter. This feature is not supported.
Added note that specific module clocks must be enabled before that module's registers can be
programmed. There must be a delay of 3 system clocks after the module clock is enabled before
any of that module's registers are accessed.
■
Changed I2C slave register base addresses and offsets to be relative to the I2C module base address
of 0x4002.0000 , so register bases and offsets were changed for all I2C slave registers. Note that
the hw_i2c.h file in the StellarisWare® Driver Library uses a base address of 0x4002.0800 for the
I2C slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that
StellarisWare uses the old slave base address for these offsets.
■
Added specification for maximum input voltage on a non-power pin when the microcontroller is
unpowered (VNON parameter in Maximum Ratings table).
■
■
Additional minor data sheet clarifications and corrections.
September 2010
7783
Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two
new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was
added, including all the Cortex-M3 registers.
■
Changed register names to be consistent with StellarisWare names: the Cortex-M3 Interrupt Control
and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and the
Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0) register.
■
■
Added clarification of instruction execution during Flash operations.
Modified Figure 7-2 on page 207 to clarify operation of the GPIO inputs when used as an alternate
function.
■
Added caution not to apply a Low value to PB7 when debugging; a Low value on the pin causes
the JTAG controller to be reset, resulting in a loss of JTAG communication.
■
■
■
In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.
Added missing table "Connections for Unused Signals" (Table 15-9 on page 442).
In Electrical Characteristics chapter:
–
–
Added ILKG parameter (GPIO input leakage current) to Table 17-4 on page 445.
Corrected values for tCLKRF parameter (SSIClk rise/fall time) in Table 17-13 on page 452.
■
Added dimensions for Tray and Tape and Reel shipping mediums.
June 2010
7393
■
■
■
■
■
Corrected base address for SRAM in architectural overview chapter.
Clarified system clock operation, adding content to “Clock Control” on page 140.
In Signal Tables chapter, added table "Connections for Unused Signals."
In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time.
Additional minor data sheet clarifications and corrections.
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Table 1. Revision History (continued)
Date
Revision Description
April 2010
7004
■
Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
field width to 7 bits.
■
■
■
Added note about RST signal routing.
Clarified the function of the TnSTALL bit in the GPTMCTL register.
Additional minor data sheet clarifications and corrections.
January 2010
6712
■
■
■
■
■
In "System Control" section, clarified Debug Access Port operation after Sleep modes.
Clarified wording on Flash memory access errors.
Added section on Flash interrupts.
Clarified operation of SSI transmit FIFO.
Made these changes to the Operating Characteristics chapter:
–
–
Added storage temperature ratings to "Temperature Characteristics" table
Added "ESD Absolute Maximum Ratings" table
■
Made these changes to the Electrical Characteristics chapter:
–
–
–
In "Flash Memory Characteristics" table, corrected Mass erase time
Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
In "Reset Characteristics" table, corrected supply voltage (VDD) rise time
October 2009
6438
■
■
The reset value for the DID1 register may change, depending on the package.
Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers
because the module resets in 32-bit mode.
■
Made these changes to the Electrical Characteristics chapter:
–
–
Removed VSIH and VSIL parameters from Operating Conditions table.
Changed SSI set up and hold times to be expressed in system clocks, not ns.
■
■
Added 48QFN and 48QFP packages.
Additional minor data sheet clarifications and corrections.
July 2009
5953
■
■
■
Clarified Power-on reset and RST pin operation; added new diagrams.
Added DBG bits missing from FMPRE register. This changes register reset value.
In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added EIR
(Internal voltage reference error) parameter.
■
■
Corrected ordering numbers.
Additional minor data sheet clarifications and corrections.
April 2009
5369
■
■
■
Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 130).
Added "GPIO Module DC Characteristics" table (see Table 17-4 on page 445).
Additional minor data sheet clarifications and corrections.
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Revision History
Table 1. Revision History (continued)
Date
Revision Description
January 2009
4644
■
■
Incorrect bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
Clarification added as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
■
■
Minor corrections to comparator operating mode tables.
Additional minor data sheet clarifications and corrections.
November 2008
October 2008
4283
4149
■
■
Revised High-Level Block Diagram.
Additional minor data sheet clarifications and corrections were made.
■
Added note on clearing interrupts to the Interrupts chapter:
Note:
It may take several processor cycles after a write to clear an interrupt source in order for
NVIC to see the interrupt source de-assert. This means if the interrupt clear is done as
the last action in an interrupt handler, it is possible for the interrupt handler to complete
while NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This can be avoided by either clearing the interrupt source at the
beginning of the interrupt handler or by performing a read or write after the write to clear
the interrupt source (and flush the write buffer)
■
■
Bit 13 and bit 5 of the GPTM Control (GPTMCTL) register should have been marked as reserved
for Stellaris® devices without an ADC module.
Additional minor data sheet clarifications and corrections were made.
June 2008
2972
Started tracking revision history.
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About This Document
This data sheet provides reference information for the LM3S102 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following related documents are available on the Stellaris® web site at www.ti.com/stellaris:
■ Stellaris® Errata
■ ARM® Cortex™-M3 Errata
■ Cortex™-M3/M4 Instruction Set Technical User's Manual
■ Stellaris® Graphics Library User's Guide
■ Stellaris® Peripheral Driver Library User's Guide
The following related documents are also referenced:
■ ARM® Debug Interface V5 Architecture Specification
■ ARM® Embedded Trace Macrocell Architecture Specification
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
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About This Document
Documentation Conventions
This document uses the conventions shown in Table 2 on page 24.
Table 2. Documentation Conventions
Notation
Meaning
General Register Notation
REGISTER
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
bit
A single bit in a register.
bit field
offset 0xnnn
Two or more consecutive and related bits.
A hexadecimal increment to a register's address, relative to that module's base address as specified
in Table 2-4 on page 59.
Register N
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
reserved
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
yy:xx
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
Register Bit/Field
Types
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
RC
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
Software can read this field. Always write the chip reset value.
Software can read or write this field.
RO
R/W
R/WC
R/W1C
Software can read or write this field. Writing to it with any value clears the register.
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1S
W1C
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.
This value in the register bit diagram shows the bit/field value after any reset, unless noted.
WO
Register Bit/Field
Reset Value
0
Bit cleared to 0 on chip reset.
Bit set to 1 on chip reset.
Nondeterministic.
1
-
Pin/Signal Notation
[ ]
Pin alternate function; a pin defaults to the signal without the brackets.
Refers to the physical connection on the package.
pin
signal
Refers to the electrical signal encoding of a pin.
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Table 2. Documentation Conventions (continued)
Notation
Meaning
assert a signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
deassert a signal
Change the value of the signal from the logically True state to the logically False state.
SIGNAL
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
Numbers
X
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
0x
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
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Architectural Overview
1
Architectural Overview
The Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings
high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These
pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit
devices, all in a package with a small footprint.
The LM3S102 microcontroller is targeted for industrial applications, including test and measurement
equipment, factory automation, HVAC and building control, motion control, medical instrumentation,
fire and security, and power/energy.
In addition, the LM3S102 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S102 microcontroller is code-compatible
to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise
needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network. See “Ordering and Contact
Information” on page 475 for ordering information for Stellaris family devices.
1.1
Product Features
The LM3S102 microcontroller includes the following product features:
■ 32-Bit RISC Performance
–
32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
–
System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
–
–
–
–
Thumb®-compatible Thumb-2-only instruction set processor core for high code density
20-MHz operation
Hardware-division and single-cycle-multiplication
Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
–
–
–
14 interrupts with eight priority levels
Unaligned data access, enabling data to be efficiently packed into memory
Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ ARM® Cortex™-M3 Processor Core
Compact core.
–
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Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the
memory size usually associated with 8- and 16-bit devices; typically in the range of a few
kilobytes of memory for microcontroller class applications.
–
–
Rapid application execution through Harvard architecture characterized by separate buses
for instruction and data.
Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
–
–
–
Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
Migration from the ARM7™ processor family for better performance and power efficiency.
Full-featured debug solution
•
•
•
Serial Wire JTAG Debug Port (SWJ-DP)
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
•
•
Instrumentation Trace Macrocell (ITM) for support of printf style debugging
Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
–
–
–
–
–
–
Optimized for single-cycle flash usage
Three sleep modes with clock gating for low power
Single-cycle multiply instruction and hardware divide
Atomic operations
ARM Thumb2 mixed 16-/32-bit instruction set
1.25 DMIPS/MHz
■ JTAG
–
–
–
–
–
IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
Four-bit Instruction Register (IR) chain for storing JTAG instructions
IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
ARM additional instructions: APACC, DPACC and ABORT
Integrated ARM Serial Wire Debug (SWD)
■ Internal Memory
8 KB single-cycle flash
–
•
User-managed flash block protection on a 2-KB block basis
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Architectural Overview
•
•
User-managed flash data programming
User-defined and managed flash-protection block
–
2 KB single-cycle SRAM
■ GPIOs
–
–
–
–
0-18 GPIOs, depending on configuration
5-V-tolerant in input configuration
Fast toggle capable of a change every two clock cycles
Programmable control for GPIO interrupts
•
•
•
Interrupt generation masking
Edge-triggered on rising, falling, or both
Level-sensitive on High or Low values
–
–
–
Bit masking in both read and write operations through address lines
Pins configured as digital inputs are Schmitt-triggered.
Programmable control for GPIO pad configuration
•
•
•
•
•
Weak pull-up or pull-down resistors
2-mA, 4-mA, and 8-mA pad drive for digital communication
Slew rate control for the 8-mA drive
Open drain enables
Digital input enables
■ General-Purpose Timers
–
Two General-Purpose Timer Modules (GPTM), each of which provides two 16-bit
timers/counters. Each GPTM can be configured to operate independently:
•
•
•
As a single 32-bit timer
As one 32-bit Real-Time Clock (RTC) to event capture
For Pulse Width Modulation (PWM)
–
32-bit Timer modes
•
•
•
Programmable one-shot timer
Programmable periodic timer
Real-Time Clock when using an external 32.768-KHz clock as the input
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•
User-enabled stalling when the controller asserts CPU Halt flag during debug
–
16-bit Timer modes
•
General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes
only)
•
•
•
Programmable one-shot timer
Programmable periodic timer
User-enabled stalling when the controller asserts CPU Halt flag during debug
–
–
16-bit Input Capture modes
•
•
Input edge count capture
Input edge time capture
16-bit PWM mode
Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
•
–
–
–
–
–
–
32-bit down counter with a programmable load register
Separate watchdog clock with an enable
Programmable interrupt generation logic with interrupt masking
Lock register protection from runaway software
Reset generation logic with an enable/disable
User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ UART
–
–
–
–
Fully programmable 16C550-type UART
Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
Programmable baud-rate generator allowing speeds up to 1.25 Mbps
Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
–
–
–
–
FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
Standard asynchronous communication bits for start, stop, and parity
Line-break generation and detection
Fully programmable serial interface characteristics
•
5, 6, 7, or 8 data bits
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Architectural Overview
•
•
Even, odd, stick, or no-parity bit generation/detection
1 or 2 stop bit generation
■ Synchronous Serial Interface (SSI)
–
–
–
–
Master or slave operation
Programmable clock bit rate and prescale
Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
–
Programmable data frame size from 4 to 16 bits
–
■ I2C
–
Internal loopback test mode for diagnostic/debug testing
Devices on the I2C bus can be designated as either a master or a slave
•
•
Supports both sending and receiving data as either a master or a slave
Supports simultaneous master and slave operation
–
Four I2C modes
•
•
•
•
Master transmit
Master receive
Slave transmit
Slave receive
–
–
Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
Master and slave interrupt generation
•
Master generates interrupts when a transmit or receive operation completes (or aborts
due to an error)
•
Slave generates interrupts when data has been sent or requested by a master
–
Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ Analog Comparators
–
–
–
One integrated analog comparator
Configurable for output to drive an output pin or generate an interrupt
Compare external pin input to external pin input or to internal programmable voltage reference
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–
Compare a test voltage against any one of these voltages
•
•
•
An individual external reference voltage
A shared single external reference voltage
A shared internal reference voltage
■ Power
–
On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
–
–
–
–
Low-power options on controller: Sleep and Deep-sleep modes
Low-power options for peripherals: software controls shutdown of individual peripherals
User-enabled LDO unregulated voltage detection and automatic reset
3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
–
–
–
–
–
–
Power-on reset (POR)
Reset pin assertion
Brown-out (BOR) detector alerts to system power drops
Software reset
Watchdog timer reset
Internal low drop-out (LDO) regulator output goes unregulated
■ Industrial and extended temperature 28-pin RoHS-compliant SOIC package1
■ Industrial and extended temperature 48-pin RoHS-compliant LQFP package
1.2
Target Applications
■ Factory automation and control
■ Industrial control power devices
■ Building and home automation
■ Stepper motors
■ Brushless DC motors
■ AC induction motors
1OBSOLETE: TI has discontinued production of the 28-pin SOIC package for this device.
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Architectural Overview
1.3
High-Level Block Diagram
Figure 1-1 on page 33 depicts the features on the Stellaris LM3S102 microcontroller.
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Figure 1-1. Stellaris LM3S102 Microcontroller High-Level Block Diagram
JTAG/SWD
ARM®
Cortex™-M3
(20MHz)
System
Control and
Clocks
Flash
(8KB)
DCode bus
ICode bus
(w/ Precis. Osc.)
NVIC
System Bus
LM3S102
SRAM
(2KB)
Bus Matrix
SYSTEM PERIPHERALS
General-
Purpose
Timer (2)
Watchdog
Timer
(1)
GPIOs
(0-18)
SERIAL PERIPHERALS
I2C
(1)
UART
(1)
SSI
(1)
ANALOG PERIPHERALS
Analog
Comparator
(1)
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Architectural Overview
1.4
Functional Overview
The following sections provide an overview of the features of the LM3S102 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 475.
1.4.1
ARM Cortex™-M3
1.4.1.1
Processor Core (see page 40)
All members of the Stellaris product family, including the LM3S102 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
1.4.1.2
1.4.1.3
Memory Map (see page 59)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S102 controller can be found in Table 2-4 on page 59. Register addresses are given as a
hexadecimal increment, relative to the module's base address as shown in the memory map.
System Timer (SysTick) (see page 81)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.4
Nested Vectored Interrupt Controller (NVIC) (see page 82)
The LM3S102 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM® Cortex™-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 14 interrupts.
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1.4.1.5
System Control Block (SCB) (see page 84)
The SCB provides system implementation information and system control, including configuration,
control, and reporting of system exceptions.
1.4.2
Motor Control Peripherals
To enhance motor control, the LM3S102 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1
PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
On the LM3S102, PWM motion control functionality can be achieved through:
■ The motion control features of the general-purpose timers using the CCP pins
CCP Pins (see page 250)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3
Analog Peripherals
For support of analog signals, the LM3S102 microcontroller offers one analog comparator.
1.4.3.1
Analog Comparators (see page 418)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S102 microcontroller provides one analog comparator that can be configured to drive an
output or generate an interrupt .
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts to cause it to start
capturing a sample sequence.
1.4.4
Serial Communications Peripherals
The LM3S102 controller supports both asynchronous and synchronous serial communications with:
■ One fully programmable 16C550-type UART
■ One SSI module
■ One I2C module
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1.4.4.1
UART (see page 304)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S102 controller includes one fully programmable 16C550-type UARTthat supports data
transfer speeds up to 1.25 Mbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.)
Separate 16x8 transmit (TX) and receive (RX) FIFOs reduce CPU interrupt service loading. The
UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2
SSI (see page 344)
Synchronous Serial Interface (SSI) is a four-wire bi-directional full and low-speed communications
interface.
The LM3S102 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3
I2C (see page 382)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking
devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and
diagnostic purposes in product development and manufacture.
The LM3S102 controller includes one I2C module that provides the ability to communicate to other
IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write
and read) data.
Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive,
Slave Transmit, and Slave Receive.
A Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
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Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error). The I2C slave generates
interrupts when data has been sent or requested by a master.
1.4.5
System Peripherals
1.4.5.1
Programmable GPIOs (see page 202)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris GPIO module is comprised of three physical GPIO blocks, each corresponding to an
individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP
for Real-Time Microcontrollers specification) and supports 0-18 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal
Tables” on page 432 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines. Pins configured as digital inputs are
Schmitt-triggered.
1.4.5.2
Two Programmable Timers (see page 244)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris General-Purpose Timer Module (GPTM) contains two GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3
Watchdog Timer (see page 280)
A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The
watchdog timer is used to regain control when a system has failed due to a software error or to the
failure of an external device to respond in the expected way.
The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.6
Memory Peripherals
The LM3S102 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1
SRAM (see page 185)
The LM3S102 static random access memory (SRAM) controller supports 2 KB SRAM. The internal
SRAM of the Stellaris devices starts at base address 0x2000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
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Architectural Overview
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
1.4.6.2
Flash (see page 186)
The LM3S102 Flash controller supports 8 KB of flash memory. The flash is organized as a set of
1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block
to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
1.4.7
Additional Features
1.4.7.1
JTAG TAP Controller (see page 124)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is composed of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO
outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive
programming for the ARM, Stellaris, and unimplemented JTAG instructions.
1.4.7.2
1.4.8
System Control and Clocks (see page 135)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 430
■ “Signal Tables” on page 432
■ “Operating Characteristics” on page 443
■ “Electrical Characteristics” on page 444
■ “Package Information” on page 477
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1.4.9
System Block Diagram
Figure 1-2. LM3S102 Controller System-Level Block Diagram
VDD_3.3V
LDO
VDD_2.5V
LDO
GND
ARM Cortex-M3
(20 MHz)
CM3Core
DCode
ICode
Flash
(8 KB)
NVIC
Debug
Bus
OSC0
OSC1
IOSC PLL
SRAM
(2 KB)
APB Bridge
POR
BOR
Watchdog
Timer
System
Control
RST
& Clocks
GPIO Port A
GPIO Port B
PB7/TRST
PB6/CCP1/C0+
PB5/C0o
Analog
Comparator
PA5/SSITx
PA4/SSIRx
PA3/SSIFss
PA2/SSIClk
PB4/C0-
SSI
PB3/I2CSDA
PB2/I2CSCL
Master
2
I C
Slave
PA1/U0Tx
PA0/U0Rx
UART0
PB1/32KHz
PB0/CCP0
GP Timer1
GPIO Port C
GP Timer0
PC3/TDO/SWO
PC2/TDI
PC1/TMS/SWDIO
PC0/TCK/SWCLK
JTAG
SWD/SWO
LM3S102
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The Cortex-M3 Processor
2
The Cortex-M3 Processor
The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
■ Compact core.
■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■ Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
■ Migration from the ARM7™ processor family for better performance and power efficiency.
■ Full-featured debug solution
–
–
–
Serial Wire JTAG Debug Port (SWJ-DP)
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
–
–
Instrumentation Trace Macrocell (ITM) for support of printf style debugging
Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
■ Optimized for single-cycle flash usage
■ Three sleep modes with clock gating for low power
■ Single-cycle multiply instruction and hardware divide
■ Atomic operations
■ ARM Thumb2 mixed 16-/32-bit instruction set
■ 1.25 DMIPS/MHz
The Stellaris® family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motor control.
This chapter provides information on the Stellaris implementation of the Cortex-M3 processor,
including the programming model, the memory model, the exception model, fault handling, and
power management.
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For technical details on the instruction set, see the Cortex™-M3/M4 Instruction Set Technical User's
Manual.
2.1
Block Diagram
The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor delivers
exceptional power efficiency through an efficient instruction set and extensively optimized design,
providing high-end processing hardware including a range of single-cycle and SIMD multiplication
and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled
system components that reduce processor area while significantly improving interrupt handling and
system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction
set based on Thumb-2 technology, ensuring high code density and reduced program memory
requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a
modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.
The Cortex-M3 processor closely integrates a nested interrupt controller (NVIC), to deliver
industry-leading interrupt performance. The Stellaris NVIC includes a non-maskable interrupt (NMI)
and provides eight interrupt priority levels. The tight integration of the processor core and NVIC
provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency.
The hardware stacking of registers and the ability to suspend load-multiple and store-multiple
operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs
which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces
the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC
integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be
rapidly powered down.
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The Cortex-M3 Processor
Figure 2-1. CPU Block Diagram
Nested
Vectored
Interrupt
Controller
Interrupts
Sleep
Serial
Wire
Output
Trace
Port
ARM
Cortex-M3
CM3 Core
Debug
Instructions Data
Trace
Port
(SWO)
Interface
Unit
Instrumentation
Data
Trace Macrocell
Watchpoint
and Trace
Flash
Patch and
Breakpoint
ROM
Table
Private Peripheral
Bus
Adv. Peripheral
Bus
(internal)
I-code bus
D-code bus
System bus
Bus
Matrix
Serial Wire JTAG
Debug Port
Debug
Access Port
2.2
Overview
2.2.1
System-Level Interface
The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide
high-speed, low-latency memory accesses. The core supports unaligned data accesses and
implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and
thread-safe Boolean data handling.
2.2.2
Integrated Configurable Debug
The Cortex-M3 processor implements a complete hardware debug solution, providing high system
visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire
Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Stellaris
implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and
JTAG debug ports into one module. See the ARM® Debug Interface V5 Architecture Specification
for details on SWJ-DP.
For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace
events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data
trace, and profiling information through a single pin.
The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators
that debuggers can use. The comparators in the FPB also provide remap functions of up to eight
words in the program code in the CODE memory region. This enables applications stored in a
read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory.
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Stellaris® LM3S102 Microcontroller
If a patch is required, the application programs the FPB to remap a number of addresses. When
those addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration.
For more information on the Cortex-M3 debug capabilities, see theARM® Debug Interface V5
Architecture Specification.
2.2.3
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer, as shown in Figure 2-2 on page 43.
Figure 2-2. TPIU Block Diagram
Debug
Serial Wire
Trace Port
(SWO)
ATB
Interface
Trace Out
(serializer)
ATB
Slave
Port
Asynchronous FIFO
APB
Slave
Port
APB
Interface
2.2.4
Cortex-M3 System Component Details
The Cortex-M3 includes the following system components:
■ SysTick
A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer
or as a simple counter (see “System Timer (SysTick)” on page 81).
■ Nested Vectored Interrupt Controller (NVIC)
An embedded interrupt controller that supports low latency interrupt processing (see “Nested
Vectored Interrupt Controller (NVIC)” on page 82).
■ System Control Block (SCB)
The programming model interface to the processor. The SCB provides system implementation
information and system control, including configuration, control, and reporting of system exceptions
(see “System Control Block (SCB)” on page 84).
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The Cortex-M3 Processor
2.3
Programming Model
This section describes the Cortex-M3 programming model. In addition to the individual core register
descriptions, information about the processor modes and privilege levels for software execution and
stacks is included.
2.3.1
Processor Mode and Privilege Levels for Software Execution
The Cortex-M3 has two modes of operation:
■ Thread mode
Used to execute application software. The processor enters Thread mode when it comes out of
reset.
■ Handler mode
Used to handle exceptions. When the processor has finished exception processing, it returns to
Thread mode.
In addition, the Cortex-M3 has two privilege levels:
■ Unprivileged
In this mode, software has the following restrictions:
–
–
–
Limited access to the MSR and MRS instructions and no use of the CPS instruction
No access to the system timer, NVIC, or system control block
Possibly restricted access to memory or peripherals
■ Privileged
In this mode, software can use all the instructions and has access to all resources.
In Thread mode, the CONTROL register (see page 58) controls whether software execution is
privileged or unprivileged. In Handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software
execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor
call to transfer control to privileged software.
2.3.2
Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked
item on the memory. When the processor pushes a new item onto the stack, it decrements the stack
pointer and then writes the item to the new memory location. The processor implements two stacks:
the main stack and the process stack, with a pointer for each held in independent registers (see the
SP register on page 48).
In Thread mode, the CONTROL register (see page 58) controls whether the processor uses the
main stack or the process stack. In Handler mode, the processor always uses the main stack. The
options for processor operations are shown in Table 2-1 on page 45.
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Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode
Thread
Use
Privilege Level
Privileged or unprivileged a
Stack Used
Main stack or process stack a
Applications
Exception handlers
Handler
Always privileged
Main stack
a. See CONTROL (page 58).
2.3.3
Register Map
Figure 2-3 on page 45 shows the Cortex-M3 register set. Table 2-2 on page 45 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.
Figure 2-3. Cortex-M3 Register Set
R0
R1
R2
R3
Low registers
R4
R5
R6
R7
General-purpose registers
R8
R9
High registers
R10
R11
R12
‡Banked version of SP
Stack Pointer
Link Register
SP (R13)
LR (R14)
PC (R15)
PSP‡
MSP‡
Program Counter
PSR
Program status register
Exception mask registers
PRIMASK
FAULTMASK
BASEPRI
CONTROL
Special registers
CONTROL register
Table 2-2. Processor Register Map
See
page
Offset
Name
Type
Reset
Description
-
-
-
-
R0
R1
R2
R3
R/W
R/W
R/W
R/W
-
-
-
-
Cortex General-Purpose Register 0
Cortex General-Purpose Register 1
Cortex General-Purpose Register 2
Cortex General-Purpose Register 3
47
47
47
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The Cortex-M3 Processor
Table 2-2. Processor Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
Cortex General-Purpose Register 4
Cortex General-Purpose Register 5
Cortex General-Purpose Register 6
Cortex General-Purpose Register 7
Cortex General-Purpose Register 8
Cortex General-Purpose Register 9
Cortex General-Purpose Register 10
Cortex General-Purpose Register 11
Cortex General-Purpose Register 12
Stack Pointer
47
47
47
47
47
47
47
47
47
48
49
50
51
55
56
57
58
R5
-
R6
-
R7
-
R8
-
R9
-
R10
-
R11
-
R12
-
SP
-
LR
0xFFFF.FFFF
-
Link Register
PC
Program Counter
PSR
0x0100.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Program Status Register
PRIMASK
FAULTMASK
BASEPRI
CONTROL
Priority Mask Register
Fault Mask Register
Base Priority Mask Register
Control Register
2.3.4
Register Descriptions
This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 45.
The core registers are not memory mapped and are accessed by register name rather than offset.
Note: The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.
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Register 1: Cortex General-Purpose Register 0 (R0)
Register 2: Cortex General-Purpose Register 1 (R1)
Register 3: Cortex General-Purpose Register 2 (R2)
Register 4: Cortex General-Purpose Register 3 (R3)
Register 5: Cortex General-Purpose Register 4 (R4)
Register 6: Cortex General-Purpose Register 5 (R5)
Register 7: Cortex General-Purpose Register 6 (R6)
Register 8: Cortex General-Purpose Register 7 (R7)
Register 9: Cortex General-Purpose Register 8 (R8)
Register 10: Cortex General-Purpose Register 9 (R9)
Register 11: Cortex General-Purpose Register 10 (R10)
Register 12: Cortex General-Purpose Register 11 (R11)
Register 13: Cortex General-Purpose Register 12 (R12)
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed
from either privileged or unprivileged mode.
Cortex General-Purpose Register 0 (R0)
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DATA
DATA
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
31:0
Name
DATA
Type
R/W
Reset
-
Description
Register data.
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The Cortex-M3 Processor
Register 14: Stack Pointer (SP)
The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes
depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear,
this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process
Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value
from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be
accessed in either privileged or unprivileged mode.
Stack Pointer (SP)
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SP
SP
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
31:0
Name
SP
Type
R/W
Reset
-
Description
This field is the address of the stack pointer.
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Register 15: Link Register (LR)
The Link Register (LR) is register R14, and it stores the return information for subroutines, function
calls, and exceptions. LR can be accessed from either privileged or unprivileged mode.
EXC_RETURN is loaded into LR on exception entry. See Table 2-10 on page 74 for the values and
description.
Link Register (LR)
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LINK
LINK
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
31:0
Name
LINK
Type
R/W
Reset
Description
0xFFFF.FFFF This field is the return address.
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The Cortex-M3 Processor
Register 16: Program Counter (PC)
The Program Counter (PC) is register R15, and it contains the current program address. On reset,
the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit
0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register
can be accessed in either privileged or unprivileged mode.
Program Counter (PC)
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PC
PC
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
31:0
Name
PC
Type
R/W
Reset
-
Description
This field is the current program address.
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Register 17: Program Status Register (PSR)
Note: This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the
different functions:
■ Application Program Status Register (APSR), bits 31:27,
■ Execution Program Status Register (EPSR), bits 26:24, 15:10
■ Interrupt Program Status Register (IPSR), bits 5:0
The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register
can be accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or
the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple
instruction. Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine
the operation that faulted (see “Exception Entry and Return” on page 72).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
These registers can be accessed individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example, all of the
registers can be read using PSR with the MRS instruction, or APSR only can be written to using
APSR with the MSR instruction. page 51 shows the possible register combinations for the PSR. See
the MRS and MSR instruction descriptions in the Cortex™-M3/M4 Instruction Set Technical User's
Manual for more information about how to access the program status registers.
Table 2-3. PSR Register Combinations
Register
PSR
Type
R/Wa
RO
R/Wa
R/Wb
Combination
b
,
APSR, EPSR, and IPSR
EPSR and IPSR
APSR and IPSR
APSR and EPSR
IEPSR
IAPSR
EAPSR
a. The processor ignores writes to the IPSR bits.
b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.
Program Status Register (PSR)
Type R/W, reset 0x0100.0000
31
N
30
Z
29
C
28
V
27
Q
26
25
24
23
22
21
20
19
18
17
16
ICI / IT
THUMB
reserved
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICI / IT
reserved
ISRNUM
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
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Bit/Field
31
Name
N
Type
R/W
Reset
0
Description
APSR Negative or Less Flag
Value Description
1
0
The previous operation result was negative or less than.
The previous operation result was positive, zero, greater than,
or equal.
The value of this bit is only meaningful when accessing PSR or APSR.
30
Z
R/W
0
APSR Zero Flag
Value Description
1
0
The previous operation result was zero.
The previous operation result was non-zero.
The value of this bit is only meaningful when accessing PSR or APSR.
APSR Carry or Borrow Flag
29
C
R/W
0
Value Description
1
The previous add operation resulted in a carry bit or the previous
subtract operation did not result in a borrow bit.
0
The previous add operation did not result in a carry bit or the
previous subtract operation resulted in a borrow bit.
The value of this bit is only meaningful when accessing PSR or APSR.
28
V
R/W
0
APSR Overflow Flag
Value Description
1
0
The previous operation resulted in an overflow.
The previous operation did not result in an overflow.
The value of this bit is only meaningful when accessing PSR or APSR.
APSR DSP Overflow and Saturation Flag
Value Description
27
Q
R/W
0
1
0
DSP Overflow or saturation has occurred.
DSP overflow or saturation has not occurred since reset or since
the bit was last cleared.
The value of this bit is only meaningful when accessing PSR or APSR.
This bit is cleared by software using an MRS instruction.
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Bit/Field
26:25
Name
Type
RO
Reset
0x0
Description
ICI / IT
EPSR ICI / IT status
These bits, along with bits 15:10, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When EPSR holds the ICI execution state, bits 26:25 are zero.
The If-Then block contains up to four instructions following an IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M3/M4 Instruction Set Technical User's
Manual for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
24
THUMB
RO
1
EPSR Thumb State
This bit indicates the Thumb state and should always be set.
The following can clear the THUMB bit:
■
■
■
The BLX, BX and POP{PC} instructions
Restoration from the stacked xPSR value on an exception return
Bit 0 of the vector value on an exception entry or reset
Attempting to execute instructions when this bit is clear results in a fault
or lockup. See “Lockup” on page 76 for more information.
The value of this bit is only meaningful when accessing PSR or EPSR.
23:16
15:10
reserved
ICI / IT
RO
RO
0x00
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
EPSR ICI / IT status
These bits, along with bits 26:25, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When an interrupt occurs during the execution of an LDM, STM, PUSH
or POP instruction, the processor stops the load multiple or store multiple
instruction operation temporarily and stores the next register operand
in the multiple operation to bits 15:12. After servicing the interrupt, the
processor returns to the register pointed to by bits 15:12 and resumes
execution of the multiple load or store instruction. When EPSR holds
the ICI execution state, bits 11:10 are zero.
The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M3/M4 Instruction Set Technical User's
Manual for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
9:6
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
5:0
Name
Type
RO
Reset
0x00
Description
ISRNUM
IPSR ISR Number
This field contains the exception type number of the current Interrupt
Service Routine (ISR).
Value
0x00
0x01
0x02
0x03
0x04
0x05
0x06
Description
Thread mode
Reserved
NMI
Hard fault
Memory management fault
Bus fault
Usage fault
0x07-0x0A Reserved
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
...
SVCall
Reserved for Debug
Reserved
PendSV
SysTick
Interrupt Vector 0
Interrupt Vector 1
...
0x2D
Interrupt Vector 29
0x2E-0x3F Reserved
See “Exception Types” on page 67 for more information.
The value of this field is only meaningful when accessing PSR or IPSR.
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Register 18: Priority Mask Register (PRIMASK)
The PRIMASK register prevents activation of all exceptions with programmable priority. Reset,
non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions
should be disabled when they might impact the timing of critical tasks. This register is only accessible
in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and
the CPS instruction may be used to change the value of the PRIMASK register. See the
Cortex™-M3/M4 Instruction Set Technical User's Manual for more information on these instructions.
For more information on exception priority levels, see “Exception Types” on page 67.
Priority Mask Register (PRIMASK)
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PRIMASK
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:1
Name
Type
RO
Reset
Description
reserved
0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
PRIMASK
R/W
0
Priority Mask
Value Description
1
Prevents the activation of all exceptions with configurable
priority.
0
No effect.
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Register 19: Fault Mask Register (FAULTMASK)
The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt
(NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register
is only accessible in privileged mode. The MSR and MRS instructions are used to access the
FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK
register. See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information on
these instructions. For more information on exception priority levels, see “Exception
Types” on page 67.
Fault Mask Register (FAULTMASK)
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FAULTMASK
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:1
Name
Type
RO
Reset
Description
reserved
0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
FAULTMASK
R/W
0
Fault Mask
Value Description
1
0
Prevents the activation of all exceptions except for NMI.
No effect.
The processor clears the FAULTMASK bit on exit from any exception
handler except the NMI handler.
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Register 20: Base Priority Mask Register (BASEPRI)
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority
level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of
critical tasks. This register is only accessible in privileged mode. For more information on exception
priority levels, see “Exception Types” on page 67.
Base Priority Mask Register (BASEPRI)
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
BASEPRI
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
Description
reserved
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5
BASEPRI
R/W
0x0
Base Priority
Any exception that has a programmable priority level with the same or
lower priority as the value of this field is masked. The PRIMASK register
can be used to mask all exceptions with programmable priority levels.
Higher priority exceptions have lower priority levels.
Value Description
0x0 All exceptions are unmasked.
0x1 All exceptions with priority level 1-7 are masked.
0x2 All exceptions with priority level 2-7 are masked.
0x3 All exceptions with priority level 3-7 are masked.
0x4 All exceptions with priority level 4-7 are masked.
0x5 All exceptions with priority level 5-7 are masked.
0x6 All exceptions with priority level 6-7 are masked.
0x7 All exceptions with priority level 7 are masked.
4:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 21: Control Register (CONTROL)
The CONTROL register controls the stack used and the privilege level for software execution when
the processor is in Thread mode. This register is only accessible in privileged mode.
Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the
CONTROL register when in Handler mode. The exception entry and return mechanisms automatically
update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 74).
In an OS environment, threads running in Thread mode should use the process stack and the kernel
and exception handlers should use the main stack. By default, Thread mode uses MSP. To switch
the stack pointer used in Thread mode to PSP, either use the MSR instruction to set the ASP bit, as
detailed in the Cortex™-M3/M4 Instruction Set Technical User's Manual, or perform an exception
return to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 74.
Note: When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction, ensuring that instructions after the ISB execute use the new stack
pointer. See the Cortex™-M3/M4 Instruction Set Technical User's Manual.
Control Register (CONTROL)
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
ASP
TMPL
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
Bit/Field
31:2
Name
Type
RO
Reset
Description
reserved
0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
ASP
R/W
0
Active Stack Pointer
Value Description
1
0
PSP is the current stack pointer.
MSP is the current stack pointer
In Handler mode, this bit reads as zero and ignores writes. The
Cortex-M3 updates this bit automatically on exception return.
0
TMPL
R/W
0
Thread Mode Privilege Level
Value Description
1
0
Unprivileged software can be executed in Thread mode.
Only privileged software can be executed in Thread mode.
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2.3.5
Exceptions and Interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested
Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the
normal flow of software control. The processor uses Handler mode to handle all exceptions except
for reset. See “Exception Entry and Return” on page 72 for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller
(NVIC)” on page 82 for more information.
2.3.6
Data Types
The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports
64-bit data transfer instructions. All instruction and data memory accesses are little endian. See
“Memory Regions, Types and Attributes” on page 60 for more information.
2.4
Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the
bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable
memory.
The memory map for the LM3S102 controller is provided in Table 2-4 on page 59. In this manual,
register addresses are given as a hexadecimal increment, relative to the module’s base address
as shown in the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic
operations to bit data (see “Bit-Banding” on page 63).
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral
registers (see “Cortex-M3 Peripherals” on page 81).
Note: Within the memory map, all reserved space returns a bus fault when read or written.
Table 2-4. Memory Map
Start
End
Description
For details,
see page ...
Memory
0x0000.0000
0x0000.2000
0x2000.0000
0x2000.0800
0x2200.0000
0x0000.1FFF
0x1FFF.FFFF
0x2000.07FF
0x21FF.FFFF
0x2200.FFFF
On-chip Flash
Reserved
190
-
Bit-banded on-chip SRAM
Reserved
185
-
Bit-band alias of bit-banded on-chip SRAM starting at
0x2000.0000
185
-
0x2201.0000
FiRM Peripherals
0x4000.0000
0x4000.1000
0x4000.4000
0x4000.5000
0x4000.6000
0x4000.7000
0x4000.8000
0x3FFF.FFFF
Reserved
0x4000.0FFF
0x4000.3FFF
0x4000.4FFF
0x4000.5FFF
0x4000.6FFF
0x4000.7FFF
0x4000.8FFF
Watchdog timer 0
Reserved
283
-
GPIO Port A
GPIO Port B
GPIO Port C
Reserved
212
212
212
-
SSI0
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Table 2-4. Memory Map (continued)
Start
End
Description
For details,
see page ...
0x4000.9000
0x4000.C000
0x4000.D000
Peripherals
0x4000.BFFF
0x4000.CFFF
0x4001.FFFF
Reserved
UART0
-
311
-
Reserved
0x4002.0000
0x4002.1000
0x4003.0000
0x4003.1000
0x4003.2000
0x4003.C000
0x4003.D000
0x400F.D000
0x400F.E000
0x400F.F000
0x4200.0000
0x4400.0000
Private Peripheral Bus
0xE000.0000
0xE000.1000
0xE000.2000
0xE000.3000
0xE000.E000
0xE000.F000
0xE004.0000
0xE004.1000
0x4002.0FFF
0x4002.FFFF
0x4003.0FFF
0x4003.1FFF
0x4003.BFFF
0x4003.CFFF
0x400F.CFFF
0x400F.DFFF
0x400F.EFFF
0x41FF.FFFF
0x43FF.FFFF
0xDFFF.FFFF
I2C 0
396
Reserved
-
Timer 0
255
Timer 1
255
Reserved
-
Analog Comparators
418
Reserved
-
Flash memory control
190
System control
146
Reserved
-
-
-
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
Reserved
0xE000.0FFF
0xE000.1FFF
0xE000.2FFF
0xE000.DFFF
0xE000.EFFF
0xE003.FFFF
0xE004.0FFF
0xFFFF.FFFF
Instrumentation Trace Macrocell (ITM)
Data Watchpoint and Trace (DWT)
Flash Patch and Breakpoint (FPB)
Reserved
42
42
42
-
Cortex-M3 Peripherals (SysTick, NVIC and SCB)
Reserved
84
-
Trace Port Interface Unit (TPIU)
Reserved
43
-
2.4.1
Memory Regions, Types and Attributes
The memory map splits the memory map into regions. Each region has a defined memory type,
and some regions have additional memory attributes. The memory type and attributes determine
the behavior of accesses to the region.
The memory types are:
■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.
■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.
■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
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An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
2.4.2
Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 61).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.
2.4.3
Behavior of Memory Accesses
Table 2-5 on page 61 shows the behavior of accesses to each region in the memory map. See
“Memory Regions, Types and Attributes” on page 60 for more information on memory types and
the XN attribute. Stellaris devices may have reserved memory areas within the address ranges
shown below (refer to Table 2-4 on page 59 for more information).
Table 2-5. Memory Access Behavior
Address Range
Memory Region Memory Type Execute Description
Never
(XN)
0x0000.0000 - 0x1FFF.FFFF Code
0x2000.0000 - 0x3FFF.FFFF SRAM
Normal
Normal
-
This executable region is for program code.
Data can also be stored here.
-
This executable region is for data. Code
can also be stored here. This region
includes bit band and bit band alias areas
(see Table 2-6 on page 63).
0x4000.0000 - 0x5FFF.FFFF Peripheral
Device
XN
This region includes bit band and bit band
alias areas (see Table 2-7 on page 63).
0x6000.0000 - 0x9FFF.FFFF External RAM
0xA000.0000 - 0xDFFF.FFFF External device
Normal
Device
-
This executable region is for data.
XN
XN
This region is for external device memory.
0xE000.0000- 0xE00F.FFFF Private peripheral Strongly
This region includes the NVIC, system
timer, and system control block.
bus
Ordered
0xE010.0000- 0xFFFF.FFFF Reserved
-
-
-
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M3 has separate buses that can perform
instruction fetches and data accesses simultaneously.
The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch
target addresses.
2.4.4
Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions for the following reasons:
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■ The processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.
■ The processor has multiple bus interfaces.
■ Memory or devices in the memory map have different wait states.
■ Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” on page 61 describes the cases where the memory
system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, software must include memory barrier instructions to force that ordering. The Cortex-M3
has the following memory barrier instructions:
■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions
complete before subsequent memory transactions.
■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.
■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.
Memory barrier instructions can be used in the following situations:
■ Vector table
If the program changes an entry in the vector table and then enables the corresponding exception,
use a DMB instruction between the operations. The DMB instruction ensures that if the exception
is taken immediately after being enabled, the processor uses the new exception vector.
■ Self-modifying code
If a program contains self-modifying code, use an ISB instruction immediately after the code
modification in the program. The ISB instruction ensures subsequent instruction execution uses
the updated program.
■ Memory map switching
If the system contains a memory map switching mechanism, use a DSB instruction after switching
the memory map in the program. The DSB instruction ensures subsequent instruction execution
uses the updated memory map.
■ Dynamic exception priority change
When an exception priority has to change when the exception is pending or active, use DSB
instructions after the change. The change then takes effect on completion of the DSB instruction.
Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require
the use of DMB instructions.
For more information on the memory barrier instructions, see the Cortex™-M3/M4 Instruction Set
Technical User's Manual.
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2.4.5
Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses
to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table
2-6 on page 63. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band
region, as shown in Table 2-7 on page 63. For the specific address range of the bit-band regions,
see Table 2-4 on page 59.
Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in
the SRAM or peripheral bit-band region.
A word access to a bit band address results in a word access to the underlying memory,
and similarly for halfword and byte accesses. This allows bit band accesses to match the
access requirements of the underlying peripheral.
Table 2-6. SRAM Memory Bit-Banding Regions
Address Range
Memory Region
Instruction and Data Accesses
Start
End
0x2000.0000
0x2000.07FF
SRAM bit-band region Direct accesses to this memory range behave as SRAM
memory accesses, but this region is also bit addressable
through bit-band alias.
0x2200.0000
0x2200.FFFF
SRAM bit-band alias Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not remapped.
Table 2-7. Peripheral Memory Bit-Banding Regions
Address Range
Memory Region
Instruction and Data Accesses
Start
End
0x4000.0000
0x400F.FFFF
Peripheral bit-band
region
Direct accesses to this memory range behave as
peripheral memory accesses, but this region is also bit
addressable through bit-band alias.
0x4200.0000
0x43FF.FFFF
Peripheral bit-band alias Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not permitted.
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
bit_word_offset
The position of the target bit in the bit-band memory region.
bit_word_addr
The address of the word in the alias memory region that maps to the targeted bit.
bit_band_base
The starting address of the alias region.
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byte_offset
The number of the byte in the bit-band region that contains the targeted bit.
bit_number
The bit position, 0-7, of the targeted bit.
Figure 2-4 on page 64 shows examples of bit-band mapping between the SRAM bit-band alias
region and the SRAM bit-band region:
■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4)
■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4)
■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000:
0x2200.0000 = 0x2200.0000 + (0*32) + (0*4)
■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000:
0x2200.001C = 0x2200.0000+ (0*32) + (7*4)
Figure 2-4. Bit-Band Mapping
32-MB Alias Region
0x23FF.FFFC
0x2200.001C
0x23FF.FFF8
0x2200.0018
0x23FF.FFF4
0x2200.0014
0x23FF.FFF0
0x23FF.FFEC 0x23FF.FFE8
0x23FF.FFE4
0x2200.0004
0x23FF.FFE0
0x2200.0000
0x2200.0010
0x2200.000C
0x2200.0008
1-MB SRAM Bit-Band Region
7
7
6
6
5
4
3
2
1
1
0
0
7
7
6
6
5
4
3
2
1
0
7
7
6
6
5
4
3
2
1
1
0
0
7
7
6
6
5
4
3
2
1
1
0
0
0x200F.FFFF
0x200F.FFFE
0x200F.FFFD
0x200F.FFFC
5
4
3
2
5
4
3
2
1
0
5
4
3
2
5
4
3
2
0x2000.0003
0x2000.0002
0x2000.0001
0x2000.0000
2.4.5.1
Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
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Bit 0 of the value written to a word in the alias region determines the value written to the targeted
bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a
value with bit 0 clear writes a 0 to the bit-band bit.
Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as
writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band
region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.
2.4.5.2
2.4.6
Directly Accessing a Bit-Band Region
“Behavior of Memory Accesses” on page 61 describes the behavior of direct byte, halfword, or word
accesses to the bit-band regions.
Data Storage
The processor views memory as a linear collection of bytes numbered in ascending order from zero.
For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data
is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the
lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte.
Figure 2-5 on page 65 illustrates how data is stored.
Figure 2-5. Data Storage
Memory
Register
1615
7
0
31
2423
8 7
0
Address A
A+1
B0
B1
B2
B3
lsbyte
B3
B2
B1
B0
A+2
A+3
msbyte
2.4.7
Synchronization Primitives
The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a
non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use these primitives to perform a guaranteed read-modify-write memory
update sequence or for a semaphore mechanism.
A pair of synchronization primitives consists of:
■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests
exclusive access to that location.
■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and
returns a status bit to a register. If this status bit is clear, it indicates that the thread or process
gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates
that the thread or process did not gain exclusive access to the memory and no write was
performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
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■ The word instructions LDREX and STREX
■ The halfword instructions LDREXH and STREXH
■ The byte instructions LDREXB and STREXB
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Modify the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location.
4. Test the returned status bit.
If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no
write was performed, which indicates that the value returned at step 1 might be out of date. The
software must retry the entire read-modify-write sequence.
Software can use the synchronization primitives to implement a semaphore as follows:
1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the
semaphore is free.
2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
address.
3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the
software has claimed the semaphore. However, if the Store-Exclusive failed, another process
might have claimed the semaphore after the software performed step 1.
The Cortex-M3 includes an exclusive access monitor that tags the fact that the processor has
executed a Load-Exclusive instruction. The processor removes its exclusive access tag if:
■ It executes a CLREX instruction.
■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
■ An exception occurs, which means the processor can resolve semaphore conflicts between
different threads.
For more information about the synchronization primitive instructions, see the Cortex™-M3/M4
Instruction Set Technical User's Manual.
2.5
Exception Model
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
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Table 2-8 on page 69 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 14 interrupts (listed in Table 2-9 on page 69).
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn)
registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and
prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting
priority levels into preemption priorities and subpriorities. All the interrupt registers are described in
“Nested Vectored Interrupt Controller (NVIC)” on page 82.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.
Important: After a write to clear an interrupt source, it may take several processor cycles for the
NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the
last action in an interrupt handler, it is possible for the interrupt handler to complete
while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).
See “Nested Vectored Interrupt Controller (NVIC)” on page 82 for more information on exceptions
and interrupts.
2.5.1
Exception States
Each exception is in one of the following states:
■ Inactive. The exception is not active and not pending.
■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
■ Active. An exception that is being serviced by the processor but has not completed.
Note: An exception handler can interrupt the execution of another exception handler. In this
case, both exceptions are in the active state.
■ Active and Pending. The exception is being serviced by the processor, and there is a pending
exception from the same source.
2.5.2
Exception Types
The exception types are:
■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a
special form of exception. When reset is asserted, the operation of the processor stops, potentially
at any point in an instruction. When reset is deasserted, execution restarts from the address
provided by the reset entry in the vector table. Execution restarts as privileged execution in
Thread mode.
■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by
software using the Interrupt Control and State (INTCTRL) register. This exception has the
highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs
cannot be masked or prevented from activation by any other exception or preempted by any
exception other than reset.
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■ Hard Fault. A hard fault is an exception that occurs because of an error during exception
processing, or because an exception cannot be managed by any other exception mechanism.
Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with
configurable priority.
■ Memory Management Fault. A memory management fault is an exception that occurs because
of a memory protection related fault, including access violation and no match. The fixed memory
protection constraints determine this fault, for both instruction and data memory transactions.
This fault is used to abort instruction accesses to Execute Never (XN) memory regions.
■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an
instruction or data memory transaction such as a prefetch fault or a memory access fault. This
fault can be enabled or disabled.
■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:
–
–
–
–
An undefined instruction
An illegal unaligned access
Invalid state on instruction execution
An error on exception return
An unaligned address on a word or halfword memory access or division by zero can cause a
usage fault when the core is properly configured.
■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an
OS environment, applications can use SVC instructions to access OS kernel functions and device
drivers.
■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception
is only active when enabled. This exception does not activate if it is a lower priority than the
current activation.
■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is
triggered using the Interrupt Control and State (INTCTRL) register.
■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches
zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception
using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor
can use this exception as system tick.
■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by
a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to
instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Table 2-9 on page 69 lists the interrupts on the LM3S102 controller.
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-8 on page 69 shows as having
configurable priority (see the SYSHNDCTRL register on page 112 and the DIS0 register on page 91).
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For more information about hard faults, memory management faults, bus faults, and usage faults,
see “Fault Handling” on page 74.
Table 2-8. Exception Types
Exception Type
Vector
Number
Prioritya
Vector Address or
Offsetb
Activation
-
0
-
0x0000.0000
Stack top is loaded from the first
entry of the vector table on reset.
Reset
1
2
-3 (highest)
-2
0x0000.0004
0x0000.0008
Asynchronous
Asynchronous
Non-Maskable Interrupt
(NMI)
Hard Fault
3
4
5
-1
0x0000.000C
0x0000.0010
0x0000.0014
-
Memory Management
Bus Fault
programmablec
programmablec
Synchronous
Synchronous when precise and
asynchronous when imprecise
Usage Fault
-
6
programmablec
-
0x0000.0018
-
Synchronous
Reserved
7-10
SVCall
11
programmablec
programmablec
-
0x0000.002C
0x0000.0030
-
Synchronous
Synchronous
Reserved
Debug Monitor
-
12
13
PendSV
SysTick
Interrupts
14
15
programmablec
programmablec
programmabled
0x0000.0038
0x0000.003C
Asynchronous
Asynchronous
16 and above
0x0000.0040 and above Asynchronous
a. 0 is the default priority for all the programmable priorities.
b. See “Vector Table” on page 70.
c. See SYSPRI1 on page 109.
d. See PRIn registers on page 95.
Table 2-9. Interrupts
Vector Number
Interrupt Number (Bit Vector Address or Description
in Interrupt Registers)
Offset
0-15
-
0x0000.0000 -
0x0000.003C
Processor exceptions
16
17
0
1
0x0000.0040
0x0000.0044
0x0000.0048
-
GPIO Port A
GPIO Port B
GPIO Port C
Reserved
UART0
18
2
19-20
21
3-4
5
0x0000.0054
-
22
6
Reserved
SSI0
23
7
0x0000.005C
0x0000.0060
-
24
8
I2C0
25-33
34
9-17
18
19
20
21
Reserved
Watchdog Timer 0
Timer 0A
Timer 0B
Timer 1A
0x0000.0088
0x0000.008C
0x0000.0090
0x0000.0094
35
36
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Table 2-9. Interrupts (continued)
Vector Number
Interrupt Number (Bit Vector Address or Description
in Interrupt Registers)
Offset
0x0000.0098
-
38
39-40
41
22
23-24
25
Timer 1B
Reserved
0x0000.00A4
-
Analog Comparator 0
Reserved
42-43
44
26-27
28
0x0000.00B0
0x0000.00B4
System Control
Flash Memory Control
45
29
2.5.3
Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
2.5.4
Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 69. Figure 2-6 on page 71 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
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Figure 2-6. Vector Table
Exception number IRQ number Offset
Vector
IRQ29
45
29
0x00B4
.
.
.
.
.
.
.
.
.
0x004C
0x0048
0x0044
0x0040
0x003C
0x0038
18
17
16
15
14
13
12
11
10
9
2
1
IRQ2
IRQ1
0
IRQ0
-1
-2
Systick
PendSV
Reserved
Reserved for Debug
SVCall
-5
0x002C
Reserved
8
7
6
-10
-11
-12
-13
-14
Usage fault
Bus fault
0x0018
0x0014
0x0010
0x000C
0x0008
0x0004
0x0000
5
4
Memory management fault
Hard fault
3
2
NMI
1
Reset
Initial SP value
On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
memory location, in the range 0x0000.0100 to 0x3FFF.FF00 (see “Vector Table” on page 70). Note
that when configuring the VTABLE register, the offset must be aligned on a 256-byte boundary.
2.5.5
Exception Priorities
As Table 2-8 on page 69 shows, all exceptions have an associated priority, with a lower priority
value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard
fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable
priority have a priority of 0. For information about configuring exception priorities, see page 109 and
page 95.
Note: Configurable priority values for the Stellaris implementation are in the range 0-7. This means
that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always
have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means
that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed
before IRQ[0].
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If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same
priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception being
handled, the handler is not preempted, irrespective of the exception number. However, the status
of the new interrupt changes to pending.
2.5.6
Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
grouping divides each interrupt priority register entry into two fields:
■ An upper field that defines the group priority
■ A lower field that defines a subpriority within the group
Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order
in which they are processed. If multiple pending interrupts have the same group priority and
subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
page 103.
2.5.7
Exception Entry and Return
Descriptions of exception handling use the following terms:
■ Preemption. When the processor is executing an exception handler, an exception can preempt
the exception handler if its priority is higher than the priority of the exception being handled. See
“Interrupt Priority Grouping” on page 72 for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See
“Exception Entry” on page 73 more information.
■ Return. Return occurs when the exception handler is completed, and there is no pending
exception with sufficient priority to be serviced and the completed exception handler was not
handling a late-arriving exception. The processor pops the stack and restores the processor
state to the state it had before the interrupt occurred. See “Exception Return” on page 74 for
more information.
■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception
handler, if there is a pending exception that meets the requirements for exception entry, the
stack pop is skipped and control transfers to the new exception handler.
■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs
during state saving for a previous exception, the processor switches to handle the higher priority
exception and initiates the vector fetch for that exception. State saving is not affected by late
arrival because the state saved is the same for both exceptions. Therefore, the state saving
continues uninterrupted. The processor can accept a late arriving exception until the first instruction
of the exception handler of the original exception enters the execute stage of the processor. On
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return from the exception handler of the late-arriving exception, the normal tail-chaining rules
apply.
2.5.7.1
Exception Entry
Exception entry occurs when there is a pending exception with sufficient priority and either the
processor is in Thread mode or the new exception is of higher priority than the exception being
handled, in which case the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers
(see PRIMASK on page 55, FAULTMASK on page 56, and BASEPRI on page 57). An exception
with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred to as
stacking and the structure of eight data words is referred to as stack frame.
Figure 2-7. Exception Stack Frame
...
Pre-IRQ top of stack
{aligner}
xPSR
PC
LR
R12
R3
R2
R1
R0
IRQ top of stack
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. Unless
stack alignment is disabled, the stack frame is aligned to a double-word address. If the STKALIGN
bit of the Configuration Control (CCR) register is set, stack align adjustment is performed during
stacking.
The stack frame includes the return address, which is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception
handler start address from the vector table. When stacking is complete, the processor starts executing
the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR,
indicating which stack pointer corresponds to the stack frame and what operation mode the processor
was in before the entry occurred.
If no higher-priority exception occurs during exception entry, the processor starts executing the
exception handler and automatically changes the status of the corresponding pending interrupt to
active.
If another higher-priority exception occurs during exception entry, known as late arrival, the processor
starts executing the exception handler for this exception and does not change the pending status
of the earlier exception.
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2.5.7.2
Exception Return
Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:
■ An LDM or POP instruction that loads the PC
■ A BX instruction using any register
■ An LDR instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies
on this value to detect when the processor has completed an exception handler. The lowest four
bits of this value provide information on the return stack and processor mode. Table 2-10 on page 74
shows the EXC_RETURN values with a description of the exception return behavior.
EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 2-10. Exception Return Behavior
EXC_RETURN[31:0]
0xFFFF.FFF0
Description
Reserved
0xFFFF.FFF1
Return to Handler mode.
Exception return uses state from MSP.
Execution uses MSP after return.
0xFFFF.FFF2 - 0xFFFF.FFF8
0xFFFF.FFF9
Reserved
Return to Thread mode.
Exception return uses state from MSP.
Execution uses MSP after return.
0xFFFF.FFFA - 0xFFFF.FFFC
0xFFFF.FFFD
Reserved
Return to Thread mode.
Exception return uses state from PSP.
Execution uses PSP after return.
0xFFFF.FFFE - 0xFFFF.FFFF
Reserved
2.6
Fault Handling
Faults are a subset of the exceptions (see “Exception Model” on page 66). The following conditions
generate a fault:
■ A bus error on an instruction fetch or vector table load or a data access.
■ An internally detected error such as an undefined instruction or an attempt to change state with
a BX instruction.
■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN).
2.6.1
Fault Types
Table 2-11 on page 75 shows the types of fault, the handler used for the fault, the corresponding
fault status register, and the register bit that indicates the fault has occurred. See page 116 for more
information about the fault status registers.
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Table 2-11. Faults
Fault
Handler
Fault Status Register
Bit Name
VECT
Bus error on a vector read
Fault escalated to a hard fault
Hard fault
Hard fault
Hard Fault Status (HFAULTSTAT)
Hard Fault Status (HFAULTSTAT)
FORCED
IERR a
Default memory mismatch on
instruction access
Memory management Memory Management Fault Status
fault
(MFAULTSTAT)
Bus error during exception stacking Bus fault
Bus error during exception unstacking Bus fault
Bus error during instruction prefetch Bus fault
Bus Fault Status (BFAULTSTAT)
Bus Fault Status (BFAULTSTAT)
Bus Fault Status (BFAULTSTAT)
Bus Fault Status (BFAULTSTAT)
Bus Fault Status (BFAULTSTAT)
Usage Fault Status (UFAULTSTAT)
Usage Fault Status (UFAULTSTAT)
Usage Fault Status (UFAULTSTAT)
BSTKE
BUSTKE
IBUS
Precise data bus error
Bus fault
PRECISE
IMPRE
NOCP
Imprecise data bus error
Attempt to access a coprocessor
Undefined instruction
Bus fault
Usage fault
Usage fault
UNDEF
INVSTAT
Attempt to enter an invalid instruction Usage fault
set state b
Invalid EXC_RETURN value
Illegal unaligned load or store
Divide by 0
Usage fault
Usage fault
Usage fault
Usage Fault Status (UFAULTSTAT)
Usage Fault Status (UFAULTSTAT)
Usage Fault Status (UFAULTSTAT)
INVPC
UNALIGN
DIV0
a. Occurs on an access to an XN region.
b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction
with ICI continuation.
2.6.2
Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on
page 109). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on
page 112).
Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another
fault handler as described in “Exception Model” on page 66.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself because it must have the same priority
as the current priority level.
■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This
situation happens because the handler for the new fault cannot preempt the currently executing
fault handler.
■ An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
■ A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even
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though the stack push for the handler failed. The fault handler operates but the stack contents are
corrupted.
Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
2.6.3
Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused the
fault, as shown in Table 2-12 on page 76.
Table 2-12. Fault Status and Fault Address Registers
Handler
Status Register Name
Address Register Name
Register Description
Hard fault
Hard Fault Status (HFAULTSTAT)
-
page 121
Memory management Memory Management Fault Status
Memory Management Fault page 116
fault
(MFAULTSTAT)
Address (MMADDR)
page 122
Bus fault
Bus Fault Status (BFAULTSTAT)
Bus Fault Address
(FAULTADDR)
page 116
page 123
Usage fault
Usage Fault Status (UFAULTSTAT)
-
page 116
2.6.4
Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault
handlers. When the processor is in the lockup state, it does not execute any instructions. The
processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger.
Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the
processor to leave the lockup state.
2.7
Power Management
The Cortex-M3 processor sleep modes reduce power consumption:
■ Sleep mode stops the processor clock.
■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory.
The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used
(see page 105). For more information about the behavior of the sleep modes, see “System
Control” on page 143.
This section describes the mechanisms for entering sleep mode and the conditions for waking up
from sleep mode, both of which apply to Sleep mode and Deep-sleep mode.
2.7.1
Entering Sleep Modes
This section describes the mechanisms software can use to put the processor into one of the sleep
modes.
The system can generate spurious wake-up events, for example a debug operation wakes up the
processor. Therefore, software must be able to put the processor back into sleep mode after such
an event. A program might have an idle loop to put the processor back to sleep mode.
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2.7.1.1
2.7.1.2
Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up
condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 77). When the processor
executes a WFI instruction, it stops executing instructions and enters sleep mode. See the
Cortex™-M3/M4 Instruction Set Technical User's Manual for more information.
Wait for Event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit
event register. When the processor executes a WFE instruction, it checks the event register. If the
register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1,
the processor clears the register and continues executing instructions without entering sleep mode.
If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction.
Typically, this situation occurs if an SEV instruction has been executed. Software cannot access
this register directly.
See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information.
2.7.1.3
Sleep-on-Exit
If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution
of all exception handlers, it returns to Thread mode and immediately enters sleep mode. This
mechanism can be used in applications that only require the processor to run when an exception
occurs.
2.7.2
Wake Up from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep
mode.
2.7.2.1
Wake Up from WFI or Sleep-on-Exit
Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority
to cause exception entry. Some embedded systems might have to execute system restore tasks
after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler
can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives
that is enabled and has a higher priority than current exception priority, the processor wakes up but
does not execute the interrupt handler until the processor clears PRIMASK. For more information
about PRIMASK and FAULTMASK, see page 55 and page 56.
2.7.2.2
Wake Up from WFE
The processor wakes up if it detects an exception with sufficient priority to cause exception entry.
In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 105.
2.8
Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-13 on page 78 lists the
supported instructions.
Note: In Table 2-13 on page 78:
■ Angle brackets, <>, enclose alternative forms of the operand
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■ Braces, {}, enclose optional operands
■ The Operands column is not exhaustive
■ Op2 is a flexible second operand that can be either a register or a constant
■ Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in
the Cortex™-M3/M4 Instruction Set Technical User's Manual.
Table 2-13. Cortex-M3 Instruction Summary
Mnemonic
ADC, ADCS
ADD, ADDS
ADD, ADDW
ADR
Operands
Brief Description
Add with carry
Add
Flags
{Rd,} Rn, Op2
{Rd,} Rn, Op2
{Rd,} Rn , #imm12
Rd, label
{Rd,} Rn, Op2
Rd, Rm, <Rs|#n>
label
N,Z,C,V
N,Z,C,V
Add
N,Z,C,V
Load PC-relative address
Logical AND
-
AND, ANDS
ASR, ASRS
B
N,Z,C
Arithmetic shift right
Branch
N,Z,C
-
BFC
Rd, #lsb, #width
Rd, Rn, #lsb, #width
{Rd,} Rn, Op2
#imm
Bit field clear
-
BFI
Bit field insert
-
BIC, BICS
BKPT
Bit clear
N,Z,C
Breakpoint
-
BL
label
Branch with link
Branch indirect with link
Branch indirect
Compare and branch if non-zero
Compare and branch if zero
Clear exclusive
Count leading zeros
Compare negative
Compare
-
BLX
Rm
-
BX
Rm
-
CBNZ
Rn, label
Rn, label
-
-
CBZ
-
CLREX
CLZ
-
Rd, Rm
-
CMN
Rn, Op2
N,Z,C,V
N,Z,C,V
-
CMP
Rn, Op2
CPSID
i
Change processor state, disable
interrupts
CPSIE
i
Change processor state, enable
interrupts
-
DMB
-
Data memory barrier
-
DSB
-
Data synchronization barrier
Exclusive OR
-
EOR, EORS
{Rd,} Rn, Op2
N,Z,C
ISB
-
Instruction synchronization barrier
If-Then condition block
-
-
-
-
IT
-
LDM
Rn{!}, reglist
Rn{!}, reglist
Load multiple registers, increment after
LDMDB, LDMEA
Load multiple registers, decrement
before
LDMFD, LDMIA
LDR
Rn{!}, reglist
Load multiple registers, increment after
Load register with word
-
-
-
-
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, Rt2, [Rn, #offset]
LDRB, LDRBT
LDRD
Load register with byte
Load register with two bytes
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Table 2-13. Cortex-M3 Instruction Summary (continued)
Mnemonic
LDREX
Operands
Brief Description
Flags
Rt, [Rn, #offset]
Rt, [Rn]
Load register exclusive
Load register exclusive with byte
Load register exclusive with halfword
Load register with halfword
Load register with signed byte
Load register with signed halfword
Load register with word
Logical shift left
-
LDREXB
-
LDREXH
Rt, [Rn]
-
LDRH, LDRHT
LDRSB, LDRSBT
LDRSH, LDRSHT
LDRT
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rd, Rm, <Rs|#n>
Rd, Rm, <Rs|#n>
Rd, Rn, Rm, Ra
Rd, Rn, Rm, Ra
Rd, Op2
-
-
-
-
LSL, LSLS
LSR, LSRS
MLA
N,Z,C
Logical shift right
N,Z,C
Multiply with accumulate, 32-bit result
Multiply and subtract, 32-bit result
Move
-
MLS
-
MOV, MOVS
MOV, MOVW
MOVT
N,Z,C
Rd, #imm16
Move 16-bit constant
N,Z,C
Rd, #imm16
Move top
-
-
MRS
Rd, spec_reg
Move from special register to general
register
MSR
spec_reg, Rm
Move from general register to special
register
N,Z,C,V
MUL, MULS
MVN, MVNS
NOP
{Rd,} Rn, Rm
Rd, Op2
-
Multiply, 32-bit result
Move NOT
N,Z
N,Z,C
No operation
-
ORN, ORNS
ORR, ORRS
POP
{Rd,} Rn, Op2
{Rd,} Rn, Op2
reglist
reglist
Rd, Rn
Logical OR NOT
N,Z,C
Logical OR
N,Z,C
Pop registers from stack
Push registers onto stack
Reverse bits
-
-
-
-
-
-
PUSH
RBIT
REV
Rd, Rn
Reverse byte order in a word
Reverse byte order in each halfword
REV16
Rd, Rn
REVSH
Rd, Rn
Reverse byte order in bottom halfword
and sign extend
ROR, RORS
RRX, RRXS
RSB, RSBS
SBC, SBCS
SBFX
Rd, Rm, <Rs|#n>
Rd, Rm
Rotate right
N,Z,C
Rotate right with extend
Reverse subtract
Subtract with carry
Signed bit field extract
Signed divide
N,Z,C
{Rd,} Rn, Op2
{Rd,} Rn, Op2
Rd, Rn, #lsb, #width
{Rd,} Rn, Rm
-
N,Z,C,V
N,Z,C,V
-
-
-
-
SDIV
SEV
Send event
SMLAL
RdLo, RdHi, Rn, Rm
Signed multiply with accumulate
(32x32+64), 64-bit result
SMULL
SSAT
STM
RdLo, RdHi, Rn, Rm
Rd, #n, Rm {,shift #s}
Rn{!}, reglist
Signed multiply (32x32), 64-bit result
Signed saturate
-
Q
Store multiple registers, increment after -
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Table 2-13. Cortex-M3 Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
STMDB, STMEA
Rn{!}, reglist
Store multiple registers, decrement
before
-
STMFD, STMIA
STR
Rn{!}, reglist
Store multiple registers, increment after -
Rt, [Rn {, #offset}]
Rt, [Rn {, #offset}]
Rt, Rt2, [Rn {, #offset}]
Rt, Rt, [Rn {, #offset}]
Rd, Rt, [Rn]
Store register word
Store register byte
-
STRB, STRBT
STRD
-
Store register two words
Store register exclusive
Store register exclusive byte
Store register exclusive halfword
Store register halfword
Store register signed byte
Store register signed halfword
Store register word
Subtract
-
STREX
-
STREXB
STREXH
STRH, STRHT
STRSB, STRSBT
STRSH, STRSHT
STRT
-
Rd, Rt, [Rn]
-
Rt, [Rn {, #offset}]
Rt, [Rn {, #offset}]
Rt, [Rn {, #offset}]
Rt, [Rn {, #offset}]
{Rd,} Rn, Op2
-
-
-
-
SUB, SUBS
SUB, SUBW
SVC
N,Z,C,V
{Rd,} Rn, #imm12
#imm
Subtract 12-bit constant
Supervisor call
N,Z,C,V
-
SXTB
{Rd,} Rm {,ROR #n}
{Rd,} Rm {,ROR #n}
[Rn, Rm]
Sign extend a byte
-
SXTH
Sign extend a halfword
Table branch byte
-
TBB
-
TBH
[Rn, Rm, LSL #1]
Rn, Op2
Table branch halfword
Test equivalence
-
TEQ
N,Z,C
TST
Rn, Op2
Test
N,Z,C
UBFX
Rd, Rn, #lsb, #width
{Rd,} Rn, Rm
Unsigned bit field extract
Unsigned divide
-
-
-
UDIV
UMLAL
RdLo, RdHi, Rn, Rm
Unsigned multiply with accumulate
(32x32+32+32), 64-bit result
UMULL
USAT
UXTB
UXTH
WFE
RdLo, RdHi, Rn, Rm
Unsigned multiply (32x 2), 64-bit result
Unsigned Saturate
-
Rd, #n, Rm {,shift #s}
Q
-
{Rd,} Rm, {,ROR #n}
Zero extend a Byte
{Rd,} Rm, {,ROR #n}
Zero extend a Halfword
Wait for event
-
-
-
-
WFI
Wait for interrupt
-
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3
Cortex-M3 Peripherals
This chapter provides information on the Stellaris® implementation of the Cortex-M3 processor
peripherals, including:
■ SysTick (see page 81)
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible
control mechanism.
■ Nested Vectored Interrupt Controller (NVIC) (see page 82)
–
–
–
Facilitates low-latency exception and interrupt handling
Controls power management
Implements system control registers
■ System Control Block (SCB) (see page 84)
Provides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
Table 3-1 on page 81 shows the address map of the Private Peripheral Bus (PPB). Some peripheral
register regions are split into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions
Address
Core Peripheral
Description (see page ...)
0xE000.E010-0xE000.E01F
System Timer
81
82
0xE000.E100-0xE000.E4EF
0xE000.EF00-0xE000.EF03
Nested Vectored Interrupt Controller
0xE000.ED00-0xE000.ED3F
0xE000.ED90-0xE000.ED93
System Control Block
MPU Type Register
84
Reads as zero, indicated the
MPU is not implementeda
a. Software can read the MPU Type Register at 0xE000.ED90 to test for the presence of a memory protection unit (MPU).
3.1
Functional Description
This chapter provides information on the Stellaris implementation of the Cortex-M3 processor
peripherals: SysTick, NVIC, SCB and MPU.
3.1.1
System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example as:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter used to measure time to completion and time used.
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■ An internal clock source control based on missing/meeting durations. The COUNT bit in the
STCTRL control and status register can be used to determine if an action completed within a
set duration, as part of a dynamic clock management control loop.
The timer consists of three registers:
■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock,
enable the counter, enable the SysTick interrupt, and determine counter status.
■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the
counter's wrap value.
■ SysTick Current Value (STCURRENT): The current value of the counter.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the STRELOAD register on the next clock edge, then decrements on subsequent
clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter
reaches zero, the COUNT status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does
not trigger the SysTick exception logic. On a read, the current value is the value of the register at
the time the register is accessed.
The SysTick counter runs on the system clock. If this clock signal is stopped for low power mode,
the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick
registers.
Note: When the processor is halted for debugging, the counter does not decrement.
3.1.2
Nested Vectored Interrupt Controller (NVIC)
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:
■ 14 interrupts.
■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower
priority, so level 0 is the highest interrupt priority.
■ Low-latency exception and interrupt handling.
■ Level and pulse detection of interrupt signals.
■ Dynamic reprioritization of interrupts.
■ Grouping of priority values into group priority and subpriority fields.
■ Interrupt tail-chaining.
■ An external Non-maskable interrupt (NMI).
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead, providing low latency exception handling.
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3.1.2.1
Level-Sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described
as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically
this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A
pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor
clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt
(see “Hardware and Software Control of Interrupts” on page 83 for more information). For a
level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR,
the interrupt becomes pending again, and the processor must execute its ISR again. As a result,
the peripheral can hold the interrupt signal asserted until it no longer needs servicing.
3.1.2.2
Hardware and Software Control of Interrupts
The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:
■ The NVIC detects that the interrupt signal is High and the interrupt is not active.
■ The NVIC detects a rising edge on the interrupt signal.
■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit
in the PEND0 register on page 92 or SWTRIG on page 97.
A pending interrupt remains pending until one of the following:
■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending
to active. Then:
–
–
For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples
the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending,
which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the
interrupt changes to inactive.
For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed
the state of the interrupt changes to pending and active. In this case, when the processor
returns from the ISR the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the processor
returns from the ISR the state of the interrupt changes to inactive.
■ Software writes to the corresponding interrupt clear-pending register bit
–
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.
–
For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending
or to active, if the state was active and pending.
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3.1.3
System Control Block (SCB)
The System Control Block (SCB) provides system implementation information and system control,
including configuration, control, and reporting of the system exceptions.
3.2
Register Map
Table 3-2 on page 84 lists the Cortex-M3 Peripheral SysTick, NVIC and SCB registers. The offset
listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base
address of 0xE000.E000.
Note: Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.
Table 3-2. Peripherals Register Map
See
page
Offset
Name
Type
Reset
Description
System Timer (SysTick) Registers
0x010
0x014
0x018
STCTRL
R/W
R/W
0x0000.0000
0x0000.0000
0x0000.0000
SysTick Control and Status Register
SysTick Reload Value Register
SysTick Current Value Register
86
88
89
STRELOAD
STCURRENT
R/WC
Nested Vectored Interrupt Controller (NVIC) Registers
0x100
0x180
0x200
0x280
0x300
0x400
0x404
0x408
0x40C
0x410
0x414
0x418
0x41C
0xF00
EN0
R/W
R/W
R/W
R/W
RO
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Interrupt 0-29 Set Enable
Interrupt 0-29 Clear Enable
Interrupt 0-29 Set Pending
Interrupt 0-29 Clear Pending
Interrupt 0-29 Active Bit
Interrupt 0-3 Priority
90
91
92
93
94
95
95
95
95
95
95
95
95
97
DIS0
PEND0
UNPEND0
ACTIVE0
PRI0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO
PRI1
Interrupt 4-7 Priority
PRI2
Interrupt 8-11 Priority
PRI3
Interrupt 12-15 Priority
Interrupt 16-19 Priority
Interrupt 20-23 Priority
Interrupt 24-27 Priority
Interrupt 28-29 Priority
Software Trigger Interrupt
PRI4
PRI5
PRI6
PRI7
SWTRIG
System Control Block (SCB) Registers
0xD00
0xD04
0xD08
CPUID
RO
R/W
R/W
0x410F.C231
0x0000.0000
0x0000.0000
CPU ID Base
98
99
INTCTRL
VTABLE
Interrupt Control and State
Vector Table Offset
102
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Table 3-2. Peripherals Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0xD0C
0xD10
0xD14
0xD18
0xD1C
0xD20
0xD24
0xD28
0xD2C
0xD34
0xD38
APINT
R/W
R/W
0xFA05.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
-
Application Interrupt and Reset Control
System Control
103
105
107
109
110
111
112
116
121
122
123
SYSCTRL
CFGCTRL
SYSPRI1
R/W
Configuration and Control
System Handler Priority 1
System Handler Priority 2
System Handler Priority 3
System Handler Control and State
Configurable Fault Status
Hard Fault Status
R/W
SYSPRI2
R/W
SYSPRI3
R/W
SYSHNDCTRL
FAULTSTAT
HFAULTSTAT
MMADDR
FAULTADDR
R/W
R/W1C
R/W1C
R/W
Memory Management Fault Address
Bus Fault Address
R/W
-
3.3
System Timer (SysTick) Register Descriptions
This section lists and describes the System Timer registers, in numerical order by address offset.
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Register 1: SysTick Control and Status Register (STCTRL), offset 0x010
Note: This register can only be accessed from privileged mode.
The SysTick STCTRL register enables the SysTick features.
SysTick Control and Status Register (STCTRL)
Base 0xE000.E000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
COUNT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CLK_SRC INTEN ENABLE
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:17
Name
Type
RO
Reset
0x000
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
COUNT
RO
0
Count Flag
Value
0
Description
The SysTick timer has not counted to 0 since the last time
this bit was read.
1
The SysTick timer has counted to 0 since the last time
this bit was read.
This bit is cleared by a read of the register or if the STCURRENT register
is written with any value.
If read by the debugger using the DAP, this bit is cleared only if the
MasterType bit in the AHB-AP Control Register is clear. Otherwise,
the COUNT bit is not changed by the debugger read. See the ARM®
Debug Interface V5 Architecture Specification for more information on
MasterType.
15:3
2
reserved
RO
0x000
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CLK_SRC
R/W
Clock Source
Value Description
0
External reference clock. (Not implemented for most Stellaris
microcontrollers.)
1
System clock
Because an external reference clock is not implemented, this bit must
be set in order for SysTick to operate.
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Bit/Field
1
Name
Type
R/W
Reset
0
Description
INTEN
Interrupt Enable
Value
0
Description
Interrupt generation is disabled. Software can use the
COUNT bit to determine if the counter has ever reached 0.
1
An interrupt is generated to the NVIC when SysTick counts
to 0.
0
ENABLE
R/W
0
Enable
Value
Description
0
1
The counter is disabled.
Enables SysTick to operate in a multi-shot way. That is, the
counter loads the RELOAD value and begins counting down.
On reaching 0, the COUNT bit is set and an interrupt is
generated if enabled by INTEN. The counter then loads the
RELOAD value again and begins counting.
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Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014
Note: This register can only be accessed from privileged mode.
The STRELOAD register specifies the start value to load into the SysTick Current Value
(STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and
0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the
COUNT bit are activated when counting from 1 to 0.
SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock
pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required
every 100 clock pulses, 99 must be written into the RELOAD field.
SysTick Reload Value Register (STRELOAD)
Base 0xE000.E000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
RELOAD
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RELOAD
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:24
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:0
RELOAD
R/W
0x00.0000 Reload Value
Value to load into the SysTick Current Value (STCURRENT) register
when the counter reaches 0.
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Register 3: SysTick Current Value Register (STCURRENT), offset 0x018
Note: This register can only be accessed from privileged mode.
The STCURRENT register contains the current value of the SysTick counter.
SysTick Current Value Register (STCURRENT)
Base 0xE000.E000
Offset 0x018
Type R/WC, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
CURRENT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CURRENT
Type
Reset
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
Bit/Field
31:24
Name
Type
Reset
0x00
Description
reserved
RO
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:0
CURRENT
R/WC
0x00.0000 Current Value
This field contains the current value at the time the register is accessed.
No read-modify-write protection is provided, so change with care.
This register is write-clear. Writing to it with any value clears the register.
Clearing this register also clears the COUNT bit of the STCTRL register.
3.4
NVIC Register Descriptions
This section lists and describes the NVIC registers, in numerical order by address offset.
The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended
while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any
other unprivileged mode access causes a bus fault.
Ensure software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers.
An interrupt can enter the pending state even if it is disabled.
Before programming the VTABLE register to relocate the vector table, ensure the vector table
entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such
as interrupts. For more information, see page 102.
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Register 4: Interrupt 0-29 Set Enable (EN0), offset 0x100
Note: This register can only be accessed from privileged mode.
The EN0 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to
Interrupt 0; bit 29 corresponds to Interrupt 29.
See Table 2-9 on page 69 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 0-29 Set Enable (EN0)
Base 0xE000.E000
Offset 0x100
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
INT
Type
Reset
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:30
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29:0
INT
R/W
0x000.0000 Interrupt Enable
Value
0
Description
On a read, indicates the interrupt is disabled.
On a write, no effect.
1
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
A bit can only be cleared by setting the corresponding INT[n] bit in
the DISn register.
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Register 5: Interrupt 0-29 Clear Enable (DIS0), offset 0x180
Note: This register can only be accessed from privileged mode.
The DIS0 register disables interrupts. Bit 0 corresponds to Interrupt 0; bit 29 corresponds to Interrupt
29.
See Table 2-9 on page 69 for interrupt assignments.
Interrupt 0-29 Clear Enable (DIS0)
Base 0xE000.E000
Offset 0x180
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
INT
Type
Reset
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:30
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29:0
INT
R/W
0x000.0000 Interrupt Disable
Value Description
0
On a read, indicates the interrupt is disabled.
On a write, no effect.
1
On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN0
register, disabling interrupt [n].
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Register 6: Interrupt 0-29 Set Pending (PEND0), offset 0x200
Note: This register can only be accessed from privileged mode.
The PEND0 register forces interrupts into the pending state and shows which interrupts are pending.
Bit 0 corresponds to Interrupt 0; bit 29 corresponds to Interrupt 29.
See Table 2-9 on page 69 for interrupt assignments.
Interrupt 0-29 Set Pending (PEND0)
Base 0xE000.E000
Offset 0x200
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
INT
Type
Reset
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:30
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29:0
INT
R/W
0x000.0000 Interrupt Set Pending
Value
0
Description
On a read, indicates that the interrupt is not pending.
On a write, no effect.
1
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
If the corresponding interrupt is already pending, setting a bit has no
effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND0 register.
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Register 7: Interrupt 0-29 Clear Pending (UNPEND0), offset 0x280
Note: This register can only be accessed from privileged mode.
The UNPEND0 register shows which interrupts are pending and removes the pending state from
interrupts. Bit 0 corresponds to Interrupt 0; bit 29 corresponds to Interrupt 29.
See Table 2-9 on page 69 for interrupt assignments.
Interrupt 0-29 Clear Pending (UNPEND0)
Base 0xE000.E000
Offset 0x280
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
INT
Type
Reset
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:30
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29:0
INT
R/W
0x000.0000 Interrupt Clear Pending
Value Description
0
On a read, indicates that the interrupt is not pending.
On a write, no effect.
1
On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND0
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
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Register 8: Interrupt 0-29 Active Bit (ACTIVE0), offset 0x300
Note: This register can only be accessed from privileged mode.
The ACTIVE0 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 0; bit 29
corresponds to Interrupt 29.
See Table 2-9 on page 69 for interrupt assignments.
Caution – Do not manually set or clear the bits in this register.
Interrupt 0-29 Active Bit (ACTIVE0)
Base 0xE000.E000
Offset 0x300
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
INT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:30
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29:0
INT
RO
0x000.0000 Interrupt Active
Value Description
0
1
The corresponding interrupt is not active.
The corresponding interrupt is active, or active and pending.
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Register 9: Interrupt 0-3 Priority (PRI0), offset 0x400
Register 10: Interrupt 4-7 Priority (PRI1), offset 0x404
Register 11: Interrupt 8-11 Priority (PRI2), offset 0x408
Register 12: Interrupt 12-15 Priority (PRI3), offset 0x40C
Register 13: Interrupt 16-19 Priority (PRI4), offset 0x410
Register 14: Interrupt 20-23 Priority (PRI5), offset 0x414
Register 15: Interrupt 24-27 Priority (PRI6), offset 0x418
Register 16: Interrupt 28-29 Priority (PRI7), offset 0x41C
Note: This register can only be accessed from privileged mode.
The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible.
Each register holds four priority fields that are assigned to interrupts as follows:
PRIn Register Bit Field
Bits 31:29
Interrupt
Interrupt [4n+3]
Interrupt [4n+2]
Interrupt [4n+1]
Interrupt [4n]
Bits 23:21
Bits 15:13
Bits 7:5
See Table 2-9 on page 69 for interrupt assignments.
Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP
field in the Application Interrupt and Reset Control (APINT) register (see page 103) indicates the
position of the binary point that splits the priority and subpriority fields.
These registers can only be accessed from privileged mode.
Interrupt 0-3 Priority (PRI0)
Base 0xE000.E000
Offset 0x400
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTD
reserved
INTC
reserved
Type
Reset
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTB
reserved
INTA
reserved
Type
Reset
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:29
Name
INTD
Type
R/W
Reset
0x0
Description
Interrupt Priority for Interrupt [4n+3]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+3], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
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Bit/Field
28:24
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21
INTC
R/W
0x0
Interrupt Priority for Interrupt [4n+2]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+2], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
20:16
15:13
reserved
INTB
RO
0x0
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
Interrupt Priority for Interrupt [4n+1]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+1], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
12:8
7:5
reserved
INTA
RO
0x0
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
Interrupt Priority for Interrupt [4n]
This field holds a priority value, 0-7, for the interrupt with the number
[4n], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
4:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 17: Software Trigger Interrupt (SWTRIG), offset 0xF00
Note: Only privileged software can enable unprivileged access to the SWTRIG register.
Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI).
See Table 2-9 on page 69 for interrupt assignments.
When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 107) is
set, unprivileged software can access the SWTRIG register.
Software Trigger Interrupt (SWTRIG)
Base 0xE000.E000
Offset 0xF00
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
INTID
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
WO
0
WO
0
WO
0
WO
0
Bit/Field
31:5
Name
Type
Reset
Description
reserved
RO
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4:0
INTID
WO
0x00
Interrupt ID
This field holds the interrupt ID of the required SGI. For example, a value
of 0x3 generates an interrupt on IRQ3.
3.5
System Control Block (SCB) Register Descriptions
This section lists and describes the System Control Block (SCB) registers, in numerical order by
address offset. The SCB registers can only be accessed from privileged mode.
All registers must be accessed with aligned word accesses except for the FAULTSTAT and
SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to system control block registers.
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Register 18: CPU ID Base (CPUID), offset 0xD00
Note: This register can only be accessed from privileged mode.
The CPUID register contains the ARM® Cortex™-M3 processor part number, version, and
implementation information.
CPU ID Base (CPUID)
Base 0xE000.E000
Offset 0xD00
Type RO, reset 0x410F.C231
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IMP
VAR
CON
REV
Type
Reset
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PARTNO
Type
Reset
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
Bit/Field
31:24
Name
Type
RO
Reset
0x41
Description
IMP
Implementer Code
Value Description
0x41 ARM
23:20
VAR
RO
0x0
Variant Number
Value Description
0x0 The rn value in the rnpn product revision identifier, for example,
the 0 in r0p1.
19:16
15:4
3:0
CON
RO
RO
RO
0xF
0xC23
0x1
Constant
Value Description
0xF Always reads as 0xF.
PARTNO
Part Number
Value Description
0xC23 Cortex-M3 processor.
REV
Revision Number
Value Description
0x1 The pn value in the rnpn product revision identifier, for example,
the 1 in r0p1.
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Register 19: Interrupt Control and State (INTCTRL), offset 0xD04
Note: This register can only be accessed from privileged mode.
The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and
clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate
the exception number of the exception being processed, whether there are preempted active
exceptions, the exception number of the highest priority pending exception, and whether any interrupts
are pending.
When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and
UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits.
Interrupt Control and State (INTCTRL)
Base 0xE000.E000
Offset 0xD04
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
UNPENDSV PENDSTSET PENDSTCLR reserved
NMISET
reserved
PENDSV
ISRPRE ISRPEND
reserved
VECPEND
Type
Reset
R/W
0
RO
0
RO
0
R/W
0
WO
0
R/W
0
WO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VECPEND
RETBASE
reserved
VECACT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31
Name
Type
Reset
0
Description
NMISET
R/W
NMI Set Pending
Value Description
0
On a read, indicates an NMI exception is not pending.
On a write, no effect.
1
On a read, indicates an NMI exception is pending.
On a write, changes the NMI exception state to pending.
Because NMI is the highest-priority exception, normally the processor
enters the NMI exception handler as soon as it registers the setting of
this bit, and clears this bit on entering the interrupt handler. A read of
this bit by the NMI exception handler returns 1 only if the NMI signal is
reasserted while the processor is executing that handler.
30:29
28
reserved
PENDSV
RO
0x0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
PendSV Set Pending
Value Description
0
On a read, indicates a PendSV exception is not pending.
On a write, no effect.
1
On a read, indicates a PendSV exception is pending.
On a write, changes the PendSV exception state to pending.
Setting this bit is the only way to set the PendSV exception state to
pending. This bit is cleared by writing a 1 to the UNPENDSV bit.
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Bit/Field
27
Name
UNPENDSV
Type
WO
Reset
0
Description
PendSV Clear Pending
Value Description
0
1
On a write, no effect.
On a write, removes the pending state from the PendSV
exception.
This bit is write only; on a register read, its value is unknown.
SysTick Set Pending
26
PENDSTSET
R/W
0
Value Description
0
On a read, indicates a SysTick exception is not pending.
On a write, no effect.
1
On a read, indicates a SysTick exception is pending.
On a write, changes the SysTick exception state to pending.
This bit is cleared by writing a 1 to the PENDSTCLR bit.
SysTick Clear Pending
25
PENDSTCLR
WO
0
Value Description
0
1
On a write, no effect.
On a write, removes the pending state from the SysTick
exception.
This bit is write only; on a register read, its value is unknown.
24
23
reserved
ISRPRE
RO
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Debug Interrupt Handling
Value Description
0
1
The release from halt does not take an interrupt.
The release from halt takes an interrupt.
This bit is only meaningful in Debug mode and reads as zero when the
processor is not in Debug mode.
22
ISRPEND
RO
0
Interrupt Pending
Value Description
0
1
No interrupt is pending.
An interrupt is pending.
This bit provides status for all interrupts excluding NMI and Faults.
21:18
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
17:12
Name
Type
RO
Reset
0x00
Description
VECPEND
Interrupt Pending Vector Number
This field contains the exception number of the highest priority pending
enabled exception. The value indicated by this field includes the effect
of the BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.
Value
0x00
0x01
0x02
0x03
0x04
0x05
0x06
Description
No exceptions are pending
Reserved
NMI
Hard fault
Memory management fault
Bus fault
Usage fault
0x07-0x0A Reserved
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
...
SVCall
Reserved for Debug
Reserved
PendSV
SysTick
Interrupt Vector 0
Interrupt Vector 1
...
0x2D
Interrupt Vector 29
0x2E-0x3F Reserved
11
RETBASE
RO
0
Return to Base
Value Description
0
1
There are preempted active exceptions to execute.
There are no active exceptions, or the currently executing
exception is the only active exception.
This bit provides status for all interrupts excluding NMI and Faults. This
bit only has meaning if the processor is currently executing an ISR (the
Interrupt Program Status (IPSR) register is non-zero).
10:6
5:0
reserved
VECACT
RO
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00
Interrupt Pending Vector Number
This field contains the active exception number. The exception numbers
can be found in the description for the VECPEND field. If this field is clear,
the processor is in Thread mode. This field contains the same value as
the ISRNUM field in the IPSR register.
Subtract 16 from this value to obtain the IRQ number required to index
into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn),
Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn),
and Interrupt Priority (PRIn) registers (see page 51).
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Register 20: Vector Table Offset (VTABLE), offset 0xD08
Note: This register can only be accessed from privileged mode.
The VTABLE register indicates the offset of the vector table base address from memory address
0x0000.0000.
Vector Table Offset (VTABLE)
Base 0xE000.E000
Offset 0xD08
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
BASE
OFFSET
Type
Reset
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OFFSET
reserved
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:30
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29
BASE
R/W
0
Vector Table Base
Value Description
0
1
The vector table is in the code memory region.
The vector table is in the SRAM memory region.
28:8
7:0
OFFSET
reserved
R/W
RO
0x000.00
0x00
Vector Table Offset
When configuring the OFFSET field, the offset must be aligned to the
number of exception entries in the vector table. Because there are 29
interrupts, the offset must be aligned on a 256-byte boundary.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 21: Application Interrupt and Reset Control (APINT), offset 0xD0C
Note: This register can only be accessed from privileged mode.
The APINT register provides priority grouping control for the exception model, endian status for
data accesses, and reset control of the system. To write to this register, 0x05FA must be written to
the VECTKEY field, otherwise the write is ignored.
The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the
Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table
3-3 on page 103 shows how the PRIGROUP value controls this split. The bit numbers in the Group
Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the
INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29.
Note: Determining preemption of an exception uses only the group priority field.
Table 3-3. Interrupt Priority Levels
PRIGROUP Bit Field Binary Pointa
Group Priority Field Subpriority Field
Group
Subpriorities
Priorities
0x0 - 0x4
0x5
bxxx.
bxx.y
bx.yy
b.yyy
[7:5]
[7:6]
[7]
None
[5]
8
4
2
1
1
2
4
8
0x6
[6:5]
[7:5]
0x7
None
a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit.
Application Interrupt and Reset Control (APINT)
Base 0xE000.E000
Offset 0xD0C
Type R/W, reset 0xFA05.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VECTKEY
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VECTCLRACT
ENDIANESS
SYSRESREQ
VECTRESET
reserved
PRIGROUP
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
WO
0
WO
0
Bit/Field
31:16
Name
Type
R/W
Reset
Description
VECTKEY
0xFA05
Register Key
This field is used to guard against accidental writes to this register.
0x05FA must be written to this field in order to change the bits in this
register. On a read, 0xFA05 is returned.
15
ENDIANESS
reserved
RO
RO
0
Data Endianess
The Stellaris implementation uses only little-endian mode so this is
cleared to 0.
14:11
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
10:8
Name
Type
R/W
Reset
0x0
Description
PRIGROUP
Interrupt Priority Grouping
This field determines the split of group priority from subpriority (see
Table 3-3 on page 103 for more information).
7:3
2
reserved
RO
0x0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SYSRESREQ
WO
System Reset Request
Value Description
0
1
No effect.
Resets the core and all on-chip peripherals except the Debug
interface.
This bit is automatically cleared during the reset of the core and reads
as 0.
1
0
VECTCLRACT
VECTRESET
WO
WO
0
0
Clear Active NMI / Fault
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
System Reset
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
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Register 22: System Control (SYSCTRL), offset 0xD10
Note: This register can only be accessed from privileged mode.
The SYSCTRL register controls features of entry to and exit from low-power state.
System Control (SYSCTRL)
Base 0xE000.E000
Offset 0xD10
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SEVONPEND reserved SLEEPDEEP SLEEPEXIT reserved
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
R/W
0
R/W
0
RO
0
Bit/Field
31:5
Name
Type
Reset
Description
reserved
RO
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
SEVONPEND
R/W
0
Wake Up on Pending
Value Description
0
Only enabled interrupts or events can wake up the processor;
disabled interrupts are excluded.
1
Enabled events and all interrupts, including disabled interrupts,
can wake up the processor.
When an event or interrupt enters the pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for an
event, the event is registered and affects the next WFE.
The processor also wakes up on execution of a SEV instruction or an
external event.
3
2
reserved
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SLEEPDEEP
R/W
Deep Sleep Enable
Value Description
0
1
Use Sleep mode as the low power mode.
Use Deep-sleep mode as the low power mode.
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Bit/Field
1
Name
SLEEPEXIT
Type
R/W
Reset
0
Description
Sleep on ISR Exit
Value Description
0
When returning from Handler mode to Thread mode, do not
sleep when returning to Thread mode.
1
When returning from Handler mode to Thread mode, enter sleep
or deep sleep on return from an ISR.
Setting this bit enables an interrupt-driven application to avoid returning
to an empty main application.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 23: Configuration and Control (CFGCTRL), offset 0xD14
Note: This register can only be accessed from privileged mode.
The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault
and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero
and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 97).
Configuration and Control (CFGCTRL)
Base 0xE000.E000
Offset 0xD14
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STKALIGN BFHFNMIGN
UNALIGNED reserved MAINPEND
BASETHR
reserved
reserved
DIV0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
Bit/Field
31:10
Name
Type
RO
Reset
Description
reserved
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9
STKALIGN
R/W
0
Stack Alignment on Exception Entry
Value Description
0
1
The stack is 4-byte aligned.
The stack is 8-byte aligned.
On exception entry, the processor uses bit 9 of the stacked PSR to
indicate the stack alignment. On return from the exception, it uses this
stacked bit to restore the correct stack alignment.
8
BFHFNMIGN
R/W
0
Ignore Bus Fault in NMI and Fault
This bit enables handlers with priority -1 or -2 to ignore data bus faults
caused by load and store instructions. The setting of this bit applies to
the hard fault, NMI, and FAULTMASK escalated handlers.
Value Description
0
Data bus faults caused by load and store instructions cause a
lock-up.
1
Handlers running at priority -1 and -2 ignore data bus faults
caused by load and store instructions.
Set this bit only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.
7:5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
4
Name
Type
R/W
Reset
0
Description
DIV0
Trap on Divide by 0
This bit enables faulting or halting when the processor executes an
SDIV or UDIV instruction with a divisor of 0.
Value Description
0
Do not trap on divide by 0. A divide by zero returns a quotient
of 0.
1
Trap on divide by 0.
3
UNALIGNED
R/W
0
Trap on Unaligned Access
Value Description
0
1
Do not trap on unaligned halfword and word accesses.
Trap on unaligned halfword and word accesses. An unaligned
access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of whether UNALIGNED is set.
2
1
reserved
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MAINPEND
R/W
Allow Main Interrupt Trigger
Value Description
0
1
Disables unprivileged software access to the SWTRIG register.
Enables unprivileged software access to the SWTRIG register
(see page 97).
0
BASETHR
R/W
0
Thread State Control
Value Description
0
The processor can enter Thread mode only when no exception
is active.
1
The processor can enter Thread mode from any level under the
control of an EXC_RETURN value (see “Exception
Return” on page 74 for more information).
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Register 24: System Handler Priority 1 (SYSPRI1), offset 0xD18
Note: This register can only be accessed from privileged mode.
The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault and bus fault exception
handlers. This register is byte-accessible.
System Handler Priority 1 (SYSPRI1)
Base 0xE000.E000
Offset 0xD18
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
USAGE
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BUS
reserved
Type
Reset
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:24
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21
USAGE
R/W
0x0
Usage Fault Priority
This field configures the priority level of the usage fault. Configurable
priority values are in the range 0-7, with lower values having higher
priority.
20:16
15:13
reserved
BUS
RO
0x0
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
Bus Fault Priority
This field configures the priority level of the bus fault. Configurable priority
values are in the range 0-7, with lower values having higher priority.
12:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 25: System Handler Priority 2 (SYSPRI2), offset 0xD1C
Note: This register can only be accessed from privileged mode.
The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is
byte-accessible.
System Handler Priority 2 (SYSPRI2)
Base 0xE000.E000
Offset 0xD1C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SVC
reserved
Type
Reset
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:29
Name
SVC
Type
R/W
Reset
0x0
Description
SVCall Priority
This field configures the priority level of SVCall. Configurable priority
values are in the range 0-7, with lower values having higher priority.
28:0
reserved
RO
0x000.0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 26: System Handler Priority 3 (SYSPRI3), offset 0xD20
Note: This register can only be accessed from privileged mode.
The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV
handlers. This register is byte-accessible.
System Handler Priority 3 (SYSPRI3)
Base 0xE000.E000
Offset 0xD20
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TICK
reserved
PENDSV
reserved
Type
Reset
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DEBUG
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:29
Name
TICK
Type
Reset
0x0
Description
R/W
SysTick Exception Priority
This field configures the priority level of the SysTick exception.
Configurable priority values are in the range 0-7, with lower values
having higher priority.
28:24
23:21
reserved
PENDSV
RO
0x0
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
PendSV Priority
This field configures the priority level of PendSV. Configurable priority
values are in the range 0-7, with lower values having higher priority.
20:8
7:5
reserved
DEBUG
RO
0x000
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
Debug Priority
This field configures the priority level of Debug. Configurable priority
values are in the range 0-7, with lower values having higher priority.
4:0
reserved
RO
0x0.0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 27: System Handler Control and State (SYSHNDCTRL), offset 0xD24
Note: This register can only be accessed from privileged mode.
The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the
usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status
of the system handlers.
If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as
a hard fault.
This register can be modified to change the pending or active status of system exceptions. An OS
kernel can write to the active bits to perform a context switch that changes the current exception
type.
Caution – Software that changes the value of an active bit in this register without correct adjustment
to the stacked content can cause the processor to generate a fault exception. Ensure software that writes
to this register retains and subsequently restores the current active status.
If the value of a bit in this register must be modified after enabling the system handlers, a
read-modify-write procedure must be used to ensure that only the required bit is modified.
System Handler Control and State (SYSHNDCTRL)
Base 0xE000.E000
Offset 0xD24
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
USAGE
BUS
MEM
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
reserved
SVC
BUSP
MEMP USAGEP
TICK
PNDSV
MON
SVCA
reserved
USGA
BUSA
MEMA
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
RO
0
R/W
0
R/W
0
Bit/Field
31:19
Name
Type
Reset
0x000
Description
reserved
RO
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
18
USAGE
R/W
0
Usage Fault Enable
Value Description
0
1
Disables the usage fault exception.
Enables the usage fault exception.
17
BUS
R/W
0
Bus Fault Enable
Value Description
0
1
Disables the bus fault exception.
Enables the bus fault exception.
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Bit/Field
16
Name
MEM
Type
R/W
Reset
0
Description
Memory Management Fault Enable
Value Description
0
1
Disables the memory management fault exception.
Enables the memory management fault exception.
15
14
13
12
11
SVC
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
SVC Call Pending
Value Description
0
1
An SVC call exception is not pending.
An SVC call exception is pending.
This bit can be modified to change the pending status of the SVC call
exception.
BUSP
Bus Fault Pending
Value Description
0
1
A bus fault exception is not pending.
A bus fault exception is pending.
This bit can be modified to change the pending status of the bus fault
exception.
MEMP
USAGEP
TICK
Memory Management Fault Pending
Value Description
0
1
A memory management fault exception is not pending.
A memory management fault exception is pending.
This bit can be modified to change the pending status of the memory
management fault exception.
Usage Fault Pending
Value Description
0
1
A usage fault exception is not pending.
A usage fault exception is pending.
This bit can be modified to change the pending status of the usage fault
exception.
SysTick Exception Active
Value Description
0
1
A SysTick exception is not active.
A SysTick exception is active.
This bit can be modified to change the active status of the SysTick
exception, however, see the Caution above before setting this bit.
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Bit/Field
10
Name
Type
R/W
Reset
0
Description
PNDSV
PendSV Exception Active
Value Description
0
1
A PendSV exception is not active.
A PendSV exception is active.
This bit can be modified to change the active status of the PendSV
exception, however, see the Caution above before setting this bit.
9
8
reserved
MON
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
Debug Monitor Active
Value Description
0
1
The Debug monitor is not active.
The Debug monitor is active.
7
SVCA
R/W
0
SVC Call Active
Value Description
0
1
SVC call is not active.
SVC call is active.
This bit can be modified to change the active status of the SVC call
exception, however, see the Caution above before setting this bit.
6:4
3
reserved
USGA
RO
0x0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
Usage Fault Active
Value Description
0
1
Usage fault is not active.
Usage fault is active.
This bit can be modified to change the active status of the usage fault
exception, however, see the Caution above before setting this bit.
2
1
reserved
BUSA
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
Bus Fault Active
Value Description
0
1
Bus fault is not active.
Bus fault is active.
This bit can be modified to change the active status of the bus fault
exception, however, see the Caution above before setting this bit.
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Bit/Field
0
Name
Type
R/W
Reset
0
Description
MEMA
Memory Management Fault Active
Value Description
0
1
Memory management fault is not active.
Memory management fault is active.
This bit can be modified to change the active status of the memory
management fault exception, however, see the Caution above before
setting this bit.
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Register 28: Configurable Fault Status (FAULTSTAT), offset 0xD28
Note: This register can only be accessed from privileged mode.
The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage
fault. Each of these functions is assigned to a subregister as follows:
■ Usage Fault Status (UFAULTSTAT), bits 31:16
■ Bus Fault Status (BFAULTSTAT), bits 15:8
■ Memory Management Fault Status (MFAULTSTAT), bits 7:0
FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows:
■ The complete FAULTSTAT register, with a word access to offset 0xD28
■ The MFAULTSTAT, with a byte access to offset 0xD28
■ The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28
■ The BFAULTSTAT, with a byte access to offset 0xD29
■ The UFAULTSTAT, with a halfword access to offset 0xD2A
Bits are cleared by writing a 1 to them.
In a fault handler, the true faulting address can be determined by:
1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address
(FAULTADDR) value.
2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the
MMADDR or FAULTADDR contents are valid.
Software must follow this sequence because another higher priority exception might change the
MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current
fault handler, the other fault might change the MMADDR or FAULTADDR value.
Configurable Fault Status (FAULTSTAT)
Base 0xE000.E000
Offset 0xD28
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
DIV0
UNALIGN
reserved
NOCP
INVPC INVSTAT UNDEF
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BFARV
reserved
BSTKE BUSTKE IMPRE PRECISE
IBUS
MMARV
reserved
IERR
Type
Reset
R/W1C
0
RO
0
RO
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
Bit/Field
31:26
Name
reserved
Type
RO
Reset
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
25
Name
DIV0
Type
Reset
0
Description
R/W1C
Divide-by-Zero Usage Fault
Value Description
0
No divide-by-zero fault has occurred, or divide-by-zero trapping
is not enabled.
1
The processor has executed an SDIV or UDIV instruction with
a divisor of 0.
When this bit is set, the PC value stacked for the exception return points
to the instruction that performed the divide by zero.
Trapping on divide-by-zero is enabled by setting the DIV0 bit in the
Configuration and Control (CFGCTRL) register (see page 107).
This bit is cleared by writing a 1 to it.
Unaligned Access Usage Fault
Value Description
24
UNALIGN
R/W1C
0
0
No unaligned access fault has occurred, or unaligned access
trapping is not enabled.
1
The processor has made an unaligned memory access.
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of the configuration of this bit.
Trapping on unaligned access is enabled by setting the UNALIGNED bit
in the CFGCTRL register (see page 107).
This bit is cleared by writing a 1 to it.
23:20
19
reserved
NOCP
RO
0x00
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W1C
No Coprocessor Usage Fault
Value Description
0
A usage fault has not been caused by attempting to access a
coprocessor.
1
The processor has attempted to access a coprocessor.
This bit is cleared by writing a 1 to it.
Invalid PC Load Usage Fault
Value Description
18
INVPC
R/W1C
0
0
A usage fault has not been caused by attempting to load an
invalid PC value.
1
The processor has attempted an illegal load of EXC_RETURN
to the PC as a result of an invalid context or an invalid
EXC_RETURN value.
When this bit is set, the PC value stacked for the exception return points
to the instruction that tried to perform the illegal load of the PC.
This bit is cleared by writing a 1 to it.
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Bit/Field
17
Name
Type
Reset
0
Description
INVSTAT
UNDEF
BFARV
R/W1C
Invalid State Usage Fault
Value Description
0
1
A usage fault has not been caused by an invalid state.
The processor has attempted to execute an instruction that
makes illegal use of the EPSR register.
When this bit is set, the PC value stacked for the exception return points
to the instruction that attempted the illegal use of the Execution
Program Status Register (EPSR) register.
This bit is not set if an undefined instruction uses the EPSR register.
This bit is cleared by writing a 1 to it.
16
R/W1C
0
Undefined Instruction Usage Fault
Value Description
0
1
A usage fault has not been caused by an undefined instruction.
The processor has attempted to execute an undefined
instruction.
When this bit is set, the PC value stacked for the exception return points
to the undefined instruction.
An undefined instruction is an instruction that the processor cannot
decode.
This bit is cleared by writing a 1 to it.
Bus Fault Address Register Valid
Value Description
15
R/W1C
0
0
The value in the Bus Fault Address (FAULTADDR) register
is not a valid fault address.
1
The FAULTADDR register is holding a valid fault address.
This bit is set after a bus fault, where the address is known. Other faults
can clear this bit, such as a memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority,
the hard fault handler must clear this bit. This action prevents problems
if returning to a stacked active bus fault handler whose FAULTADDR
register value has been overwritten.
This bit is cleared by writing a 1 to it.
14:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
12
Name
Type
Reset
0
Description
BSTKE
R/W1C
Stack Bus Fault
Value Description
0
1
No bus fault has occurred on stacking for exception entry.
Stacking for an exception entry has caused one or more bus
faults.
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the FAULTADDR register.
This bit is cleared by writing a 1 to it.
11
BUSTKE
R/W1C
0
Unstack Bus Fault
Value Description
0
No bus fault has occurred on unstacking for a return from
exception.
1
Unstacking for a return from exception has caused one or more
bus faults.
This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
FAULTADDR register.
This bit is cleared by writing a 1 to it.
Imprecise Data Bus Error
Value Description
10
IMPRE
R/W1C
0
0
1
An imprecise data bus error has not occurred.
A data bus error has occurred, but the return address in the
stack frame is not related to the instruction that caused the error.
When this bit is set, a fault address is not written to the FAULTADDR
register.
This fault is asynchronous. Therefore, if the fault is detected when the
priority of the current process is higher than the bus fault priority, the
bus fault becomes pending and becomes active only when the processor
returns from all higher-priority processes. If a precise fault occurs before
the processor enters the handler for the imprecise bus fault, the handler
detects that both the IMPRE bit is set and one of the precise fault status
bits is set.
This bit is cleared by writing a 1 to it.
9
PRECISE
R/W1C
0
Precise Data Bus Error
Value Description
0
1
A precise data bus error has not occurred.
A data bus error has occurred, and the PC value stacked for
the exception return points to the instruction that caused the
fault.
When this bit is set, the fault address is written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.
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Bit/Field
8
Name
Type
Reset
0
Description
IBUS
R/W1C
Instruction Bus Error
Value Description
0
1
An instruction bus error has not occurred.
An instruction bus error has occurred.
The processor detects the instruction bus error on prefetching an
instruction, but sets this bit only if it attempts to issue the faulting
instruction.
When this bit is set, a fault address is not written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.
Memory Management Fault Address Register Valid
Value Description
7
MMARV
R/W1C
0
0
The value in the Memory Management Fault Address
(MMADDR) register is not a valid fault address.
1
The MMADDR register is holding a valid fault address.
If a memory management fault occurs and is escalated to a hard fault
because of priority, the hard fault handler must clear this bit. This action
prevents problems if returning to a stacked active memory management
fault handler whose MMADDR register value has been overwritten.
This bit is cleared by writing a 1 to it.
6:1
0
reserved
IERR
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W1C
Instruction Access Violation
Value Description
0
1
An instruction access violation has not occurred.
The processor attempted an instruction fetch from a location
that does not permit execution.
This fault occurs on any access to an XN region.
When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
not written to the MMADDR register.
This bit is cleared by writing a 1 to it.
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Register 29: Hard Fault Status (HFAULTSTAT), offset 0xD2C
Note: This register can only be accessed from privileged mode.
The HFAULTSTAT register gives information about events that activate the hard fault handler.
Bits are cleared by writing a 1 to them.
Hard Fault Status (HFAULTSTAT)
Base 0xE000.E000
Offset 0xD2C
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DBG
FORCED
reserved
Type
Reset
R/W1C
0
R/W1C
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
reserved
VECT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
RO
0
Bit/Field
31
Name
DBG
Type
Reset
0
Description
R/W1C
Debug Event
This bit is reserved for Debug use. This bit must be written as a 0,
otherwise behavior is unpredictable.
30
FORCED
R/W1C
0
Forced Hard Fault
Value Description
0
1
No forced hard fault has occurred.
A forced hard fault has been generated by escalation of a fault
with configurable priority that cannot be handled, either because
of priority or because it is disabled.
When this bit is set, the hard fault handler must read the other fault
status registers to find the cause of the fault.
This bit is cleared by writing a 1 to it.
29:2
1
reserved
VECT
RO
0x00
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W1C
Vector Table Read Fault
Value Description
0
1
No bus fault has occurred on a vector table read.
A bus fault occurred on a vector table read.
This error is always handled by the hard fault handler.
When this bit is set, the PC value stacked for the exception return points
to the instruction that was preempted by the exception.
This bit is cleared by writing a 1 to it.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 30: Memory Management Fault Address (MMADDR), offset 0xD34
Note: This register can only be accessed from privileged mode.
The MMADDR register contains the address of the location that generated a memory management
fault. When an unaligned access faults, the address in the MMADDR register is the actual address
that faulted. Because a single read or write instruction can be split into multiple aligned accesses,
the fault address can be any address in the range of the requested access size. Bits in the Memory
Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether
the value in the MMADDR register is valid (see page 116).
Memory Management Fault Address (MMADDR)
Base 0xE000.E000
Offset 0xD34
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
31:0
Name
ADDR
Type
R/W
Reset
-
Description
Fault Address
When the MMARV bit of MFAULTSTAT is set, this field holds the address
of the location that generated the memory management fault.
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Register 31: Bus Fault Address (FAULTADDR), offset 0xD38
Note: This register can only be accessed from privileged mode.
The FAULTADDR register contains the address of the location that generated a bus fault. When
an unaligned access faults, the address in the FAULTADDR register is the one requested by the
instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT)
register indicate the cause of the fault and whether the value in the FAULTADDR register is valid
(see page 116).
Bus Fault Address (FAULTADDR)
Base 0xE000.E000
Offset 0xD38
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
31:0
Name
ADDR
Type
R/W
Reset
-
Description
Fault Address
When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the
address of the location that generated the bus fault.
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JTAG Interface
4
JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially
into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
The Stellaris® JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO
outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive
programming for the ARM, Stellaris, and unimplemented JTAG instructions.
The Stellaris JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM
JTAG controller.
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4.1
Block Diagram
Figure 4-1. JTAG Module Block Diagram
TRST
TCK
TAP Controller
TMS
TDI
Instruction Register (IR)
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TDO
Cortex-M3
Debug
Port
4.2
Signal Description
Table 4-1 on page 125 and Table 4-2 on page 126 list the external signals of the JTAG/SWD controller
and describe the function of each. The JTAG/SWD controller signals are alternate functions for
some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function.
The column in the table below titled "Pin Assignment" lists the GPIO pin placement for the JTAG/SWD
controller signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register
(page 222) is set to choose the JTAG/SWD function. For more information on configuring GPIOs,
see “General-Purpose Input/Outputs (GPIOs)” on page 202.
Table 4-1. JTAG_SWD_SWO Signals (28SOIC)
Pin Name
SWCLK
SWDIO
SWO
Pin Number
Pin Type
Buffer Typea Description
28
27
25
28
26
25
27
1
I
I/O
O
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
JTAG/SWD CLK.
JTAG TMS and SWDIO.
JTAG TDO and SWO.
JTAG/SWD CLK.
TCK
TDI
I
JTAG TDI.
TDO
O
I/O
I
JTAG TDO and SWO.
JTAG TMS and SWDIO.
JTAG TRST.
TMS
TRST
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
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Table 4-2. JTAG_SWD_SWO Signals (48QFP)
Pin Name
SWCLK
SWDIO
SWO
Pin Number
Pin Type
Buffer Typea Description
40
39
37
40
38
37
39
41
I
I/O
O
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
JTAG/SWD CLK.
JTAG TMS and SWDIO.
JTAG TDO and SWO.
JTAG/SWD CLK.
TCK
TDI
I
JTAG TDI.
TDO
O
I/O
I
JTAG TDO and SWO.
JTAG TMS and SWDIO.
JTAG TRST.
TMS
TRST
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
4.3
Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 125. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and
TMS inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel
load registers. The current state of the TAP controller also determines whether the Instruction
Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 4-4 on page 131 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 447 for JTAG timing diagrams.
4.3.1
JTAG Interface Pins
The JTAG interface consists of five standard pins: TRST,TCK, TMS, TDI, and TDO. These pins and
their associated reset state are given in Table 4-3 on page 126. Detailed information on each pin
follows.
Table 4-3. JTAG Port Pins Reset State
Pin Name
TRST
TCK
Data Direction
Input
Internal Pull-Up Internal Pull-Down Drive Strength
Drive Value
N/A
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
Disabled
Disabled
N/A
N/A
Input
N/A
TMS
Input
N/A
N/A
TDI
Input
N/A
N/A
TDO
Output
2-mA driver
High-Z
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4.3.1.1
Test Reset Input (TRST)
The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP
controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the
Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters
the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction,
IDCODE.
By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled
on PB7/TRST; otherwise JTAG communication could be lost.
4.3.1.2
Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers
that are daisy-chained together can synchronously communicate serial test data between
components. During normal operation, TCK is driven by a free-running clock with a nominal 50%
duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK
is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction
and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
4.3.1.3
Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered.
Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can
be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine
can be seen in its entirety in Figure 4-2 on page 129.
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost.
4.3.1.4
Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling
edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost.
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JTAG Interface
4.3.1.5
Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states.
4.3.2
JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 4-2 on page 129. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR)
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state, please
refer to IEEE Standard 1149.1.
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Figure 4-2. Test Access Port State Machine
Test Logic Reset
0
1
0
Run Test Idle
Select DR Scan
0
Select IR Scan
1
1
1
0
Capture DR
0
Capture IR
1
1
0
Shift DR
1
Shift IR
0
1
0
1
Exit 1 DR
0
Exit 1 IR
1
0
Pause DR
1
Pause IR
0
0
1
Exit 2 DR
1
Exit 2 IR
0
0
1
Update DR
Update IR
1
0
1
0
4.3.3
4.3.4
Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 131.
Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.
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4.3.4.1
GPIO Functionality
When the microcontroller is reset with either a POR or RST, the JTAG port pins default to their JTAG
configurations. The default configuration includes enabling the pull-up resistors (setting GPIOPUR
to 1 for PB7 and PC[3:0]) and enabling the alternate hardware function (setting GPIOAFSEL to
1 for PB7 and PC[3:0]) on the JTAG pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG port for debugging or
board-level testing, this provides five more GPIOs for use in the design.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris
microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their
GPIO functionality, the debugger may not have enough time to connect and halt the controller before
the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided
with a software routine that restores JTAG functionality based on an external or software trigger.
4.3.4.2
Communication with JTAG/SWD
Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.
4.3.4.3
ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the
TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR,
Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR, Run Test Idle, Select DR,
Select IR, and Test-Logic-Reset states.
Stepping through the JTAG TAP Instruction Register (IR) load sequences of the TAP state machine
twice without shifting in a new instruction enables the SWD interface and disables the JTAG interface.
For more information on this operation and the SWD interface, see the ARM® Debug Interface V5
Architecture Specification.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occurring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
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4.4
Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. This is done by enabling the five JTAG
pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to
enabling the alternate functions, any other changes to the GPIO pad configurations on the five JTAG
pins (PB7 andPC[3:0]) should be reverted to their default settings.
4.5
Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The registers
can be broken down into two main categories: Instruction Registers and Data Registers.
4.5.1
Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG
TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 4-4 on page 131. A detailed explanation of each instruction, along
with its associated Data Register, follows.
Table 4-4. JTAG Instruction Register Commands
IR[3:0]
Instruction
Description
0000
EXTEST
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
0001
0010
INTEST
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction into the controller.
SAMPLE / PRELOAD Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
1000
1010
1011
1110
ABORT
DPACC
APACC
IDCODE
Shifts data into the ARM Debug Port Abort Register.
Shifts data into and out of the ARM DP Access Register.
Shifts data into and out of the ARM AC Access Register.
Loads manufacturing information defined by the IEEE Standard 1149.1
into the IDCODE chain and shifts it out.
1111
BYPASS
Reserved
Connects TDI to TDO through a single Shift Register chain.
All Others
Defaults to the BYPASS instruction to ensure that TDI is always connected
to TDO.
4.5.1.1
EXTEST Instruction
The EXTEST instruction is not associated with its own Data Register chain. The EXTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. This allows
tests to be developed that drive known values out of the controller, which can be used to verify
connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan
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Data Register can be accessed to sample and shift out the current data and load new data into the
Boundary Scan Data Register.
4.5.1.2
INTEST Instruction
The INTEST instruction is not associated with its own Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows tests
to be developed that drive known values into the controller, which can be used for testing. It is
important to note that although the RST input pin is on the Boundary Scan Data Register chain, it
is only observable. While the INTEXT instruction is present in the Instruction Register, the Boundary
Scan Data Register can be accessed to sample and shift out the current data and load new data
into the Boundary Scan Data Register.
4.5.1.3
SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data
Register” on page 134 for more information.
4.5.1.4
4.5.1.5
ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. Please see the “ABORT Data Register” on page 134 for more
information.
DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 134 for more information.
4.5.1.6
APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
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register allows read and write access to internal components and buses through the Debug Port.
Please see “APACC Data Register” on page 134 for more information.
4.5.1.7
IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, TRST is asserted, or the
Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 133 for more
information.
4.5.1.8
BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 133 for
more information.
4.5.2
Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan,
APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed
in the following sections.
4.5.2.1
IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-3 on page 133. The standard requires that every JTAG-compliant device implement either
the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x1BA0.0477. This allows the debuggers to automatically configure
themselves to work correctly with the Cortex-M3 during debug.
Figure 4-3. IDCODE Register Format
31
28 27
12 11
1 0
TDI
TDO
Version
Part Number
Manufacturer ID
1
4.5.2.2
BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-4 on page 134. The standard requires that every JTAG-compliant device implement either
the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
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Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default instruction.
Figure 4-4. BYPASS Register Format
0
TDI
TDO
0
4.5.2.3
Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 4-5 on page 134. Each GPIO
pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 4-5. Boundary Scan Register Format
O
U
T
O
U
T
O
U
T
O
U
T
TDI
TDO
I
N
O
E
I
N
O
E
I
I
N
O
E
I
N
O
E
...
...
N
GPIO PB6
GPIO m
RST
GPIO m+1
GPIO n
4.5.2.4
4.5.2.5
4.5.2.6
APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
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5
System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.
5.1
Signal Description
Table 5-1 on page 135 and Table 5-2 on page 135 list the external signals of the System Control
module and describe the function of each. The NMI signal is the alternate function for and functions
as a GPIO after reset. under commit protection and require a special process to be configured as
any alternate function or to subsequently return to the GPIO function. The column in the table below
titled "Pin Assignment" lists the GPIO pin placement for the NMI signal. The AFSEL bit in the GPIO
Alternate Function Select (GPIOAFSEL) register (page 222) should be set to choose the NMI
function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 202. The remaining signals (with the word "fixed" in the Pin Assignment column)
have a fixed pin assignment and function.
Table 5-1. System Control & Clocks Signals (28SOIC)
Pin Name
Pin Number
Pin Type
Buffer Typea Description
OSC0
9
I
Analog
Analog
TTL
Main oscillator crystal input or an external clock reference
input.
OSC1
RST
10
5
O
I
Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
System reset input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 5-2. System Control & Clocks Signals (48QFP)
Pin Name
Pin Number
Pin Type
Buffer Typea Description
OSC0
9
I
Analog
Analog
TTL
Main oscillator crystal input or an external clock reference
input.
OSC1
RST
10
5
O
I
Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
System reset input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
5.2
Functional Description
The System Control module provides the following capabilities:
■ Device identification (see “Device Identification” on page 135)
■ Local control, such as reset (see “Reset Control” on page 136), power (see “Power
Control” on page 140) and clock control (see “Clock Control” on page 140)
■ System control (Run, Sleep, and Deep-Sleep modes); see “System Control” on page 143
5.2.1
Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers.
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5.2.2
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
5.2.2.1
Reset Sources
The controller has six sources of reset:
1. External reset input pin (RST) assertion; see “External RST Pin” on page 137.
2. Power-on reset (POR); see “Power-On Reset (POR)” on page 136.
3. Internal brown-out (BOR) detector; see “Brown-Out Reset (BOR)” on page 138.
4. Software-initiated reset (with the software reset registers); see “Software Reset” on page 139.
5. A watchdog timer reset condition violation; see “Watchdog Timer Reset” on page 139.
6. Internal low drop-out (LDO) regulator output.
Table 5-3 provides a summary of results of the various reset operations.
Table 5-3. Reset Sources
Reset Source
Power-On Reset
RST
Core Reset?
JTAG Reset?
On-Chip Peripherals Reset?
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Pin Config Only
Brown-Out Reset
No
No
Software System Request
Reseta
Software Peripheral Reset
Watchdog Reset
LDO Reset
No
Yes
Yes
No
No
No
Yesb
Yes
Yes
a. By using the SYSRESREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control (APINT) register
b. Programmable on a module-by-module basis using the Software Reset Control Registers.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences,except when an external reset
is the cause, and then all the other bits in the RESC register are cleared.
Note: The main oscillator is used for external resets and power-on resets; the internal oscillator
is used during the internal process by internal reset and clock verification circuitry.
5.2.2.2
Power-On Reset (POR)
Note: The power-on reset also resets the JTAG controller. An external reset does not.
The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates
a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a
threshold value (VTH). The microcontroller must be operating within the specified operating parameters
when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the microcontroller
must reach 3.0 V within 10 msec of VDD crossing 2.0 V to guarantee proper operation. For applications
that require the use of an external reset signal to hold the microcontroller in reset longer than the
internal POR, the RST input may be used as discussed in “External RST Pin” on page 137.
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The Power-On Reset sequence is as follows:
1. The microcontroller waits for internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset
timing is shown in Figure 17-6 on page 450.
5.2.2.3
External RST Pin
Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be
sure to place any components connected to the RST signal as close to the microcontroller
as possible.
If the application only uses the internal POR circuit, the RST input must be connected to the power
supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 137.
Figure 5-1. Basic RST Configuration
VDD
Stellaris®
RPU
RST
RPU = 0 to 100 kΩ
The external reset pin (RST) resets the microcontroller including the core and all the on-chip
peripherals except the JTAG TAP controller (see “JTAG Interface” on page 124). The external reset
sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted
(see “Reset” on page 449).
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 5-2 on page 138.
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Figure 5-2. External Circuitry to Extend Power-On Reset
VDD
Stellaris®
RPU
RST
C1
RPU = 1 kΩ to 100 kΩ
C1 = 1 nF to 10 µF
If the application requires the use of an external reset switch, Figure 5-3 on page 138 shows the
proper circuitry to use.
Figure 5-3. Reset Circuit Controlled by Switch
VDD
Stellaris®
RPU
RST
RS
C1
Typical RPU = 10 kΩ
Typical RS = 470 Ω
C1 = 10 nF
The RPU and C1 components define the power-on delay.
The external reset timing is shown in Figure 17-5 on page 449.
5.2.2.4
Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops
below a brown-out threshold voltage (VBTH). The circuit is provided to guard against improper
operation of logic and peripherals that operate off the power supply voltage (VDD) and not the LDO
voltage. If a brown-out condition is detected, the system may generate a controller interrupt or a
system reset. The BOR circuit has a digital filter that protects against noise-related detection for the
interrupt condition. This feature may be optionally enabled.
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
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The brown-out reset sequence is as follows:
1. When VDD drops below VBTH, an internal BOR condition is set.
2. If the BORWT bit in the PBORCTL register is set and BORIOR is not set, the BOR condition is
resampled, after a delay specified by BORTIM, to determine if the original condition was caused
by noise. If the BOR condition is not met the second time, then no further action is taken.
3. If the BOR condition exists, an internal reset is asserted.
4. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
5. The internal BOR condition is reset after 500 µs to prevent another BOR condition from being
set before software has a chance to investigate the original cause.
The internal Brown-Out Reset timing is shown in Figure 17-7 on page 450.
5.2.2.5
Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 143). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
The software-initiated system reset timing is shown in Figure 17-8 on page 450.
5.2.2.6
Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
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1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
The watchdog reset timing is shown in Figure 17-9 on page 451.
5.2.2.7
Low Drop-Out (LDO)
A reset can be initiated when the internal low drop-out (LDO) regulator output goes unregulated.
This is initially disabled and may be enabled by software. LDO is controlled with the LDO Power
Control (LDOPCTL) register. The LDO reset sequence is as follows:
1. LDO goes unregulated and the LDOARST bit in the LDOARST register is set.
2. An internal reset is asserted.
3. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
The LDO reset timing is shown in Figure 17-10 on page 451.
5.2.3
Power Control
The Stellaris® microcontroller provides an integrated LDO regulator that is used to provide power
to the majority of the controller's internal logic. For power reduction, the LDO regulator provides
software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range
of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of
the VADJ field in the LDO Power Control (LDOPCTL) register.
5.2.4
Clock Control
System control determines the control of clocks in this part.
5.2.4.1
Fundamental Clock Sources
There are multiple clock sources for use in the device:
■ Internal Oscillator (IOSC). The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. The crystal value
allowed depends on whether the main oscillator is used as the clock reference source to the
PLL. If so, the crystal must be one of the supported frequencies between 3.579545 MHz through
8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit field
in the RCC register (see page 155).
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The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The
frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
Table 5-4 on page 141 shows how the various clock sources can be used in a system.
Table 5-4. Clock Source Options
Clock Source
Drive PLL?
Used as SysClk?
BYPASS = 0, OSCSRC = 0x1 Yes
Internal Oscillator (12 MHz)
Yes
BYPASS = 1, OSCSRC = 0x1
BYPASS = 1, OSCSRC = 0x2
Internal Oscillator divide by 4 (3 Yes
MHz)
BYPASS = 0, OSCSRC = 0x2 Yes
Main Oscillator
Yes
BYPASS = 0, OSCSRC = 0x0 Yes
BYPASS = 1, OSCSRC = 0x0
5.2.4.2
Clock Configuration
Nearly all of the control for the clocks is provided by the Run-Mode Clock Configuration (RCC)
register. This register controls the following clock functionality:
■ Source of clocks in sleep and deep-sleep modes
■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
■ Crystal input selection
Figure 5-4 on page 141 shows the logic for the main clock tree. The peripheral blocks are driven by
the system clock signal and can be individually enabled/disabled.
Figure 5-4. Main Clock Tree
USESYSDIVa
OSC1
OSC2
Main
Osc
1-8 MHz
System Clock
SYSDIVa
PLL
(200 MHz
output)
Internal
Osc
12 MHz
÷4
OSCSRCa
OENa
XTALa
BYPASSa
PWRDNa
a. These are bit fields within the Run-Mode Clock Configuration (RCC) register.
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). Table 5-5 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
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The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 5-4 on page 141.
Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field
SYSDIV
Divisor Frequency
Frequency (BYPASS=1)
StellarisWare Parametera
(BYPASS=0)
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
/1
/2
reserved
Clock source frequency/2
Clock source frequency/2
Clock source frequency/3
Clock source frequency/4
Clock source frequency/5
Clock source frequency/6
Clock source frequency/7
Clock source frequency/8
Clock source frequency/9
Clock source frequency/10
Clock source frequency/11
Clock source frequency/12
Clock source frequency/13
Clock source frequency/14
Clock source frequency/15
Clock source frequency/16
SYSCTL_SYSDIV_1b
SYSCTL_SYSDIV_2
SYSCTL_SYSDIV_3
SYSCTL_SYSDIV_4
SYSCTL_SYSDIV_5
SYSCTL_SYSDIV_6
SYSCTL_SYSDIV_7
SYSCTL_SYSDIV_8
SYSCTL_SYSDIV_9
SYSCTL_SYSDIV_10
SYSCTL_SYSDIV_11
SYSCTL_SYSDIV_12
SYSCTL_SYSDIV_13
SYSCTL_SYSDIV_14
SYSCTL_SYSDIV_15
SYSCTL_SYSDIV_16
reserved
/3
reserved
/4
reserved
/5
reserved
/6
reserved
/7
reserved
/8
reserved
/9
reserved
/10
/11
/12
/13
/14
/15
/16
20 MHz
18.18 MHz
16.67 MHz
15.38 MHz
14.29 MHz
13.33 MHz
12.5 MHz (default)
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
5.2.4.3
Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 155) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
5.2.4.4
Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software configures the main PLL input reference clock source, specifies the output divisor
to set the system clock frequency, and enables the main PLL to drive the output.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 158). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 155)
describes the available crystal choices and default programming of the PLLCFG register. Any time
the XTAL field changes, the new settings are translated and the internal PLL settings are updated.
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5.2.4.5
5.2.4.6
PLL Modes
The PLL has two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC register fields (see page 155).
PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
17-7 on page 447). During the relock time, the affected PLL is not usable as a clock reference.
PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). Hardware is provided to keep
the PLL from being used as a system clock until the TREADY condition is met after one of the two
changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC register is switched to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the controller from the oscillator selected by the RCC register
until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software can use
many methods to ensure that the system is clocked from the main PLL, including periodically polling
the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock interrupt.
5.2.4.7
Clock Verification Timers
There are three identical clock verification circuits that can be enabled though software. The circuit
checks the faster clock by a slower clock using timers:
■ The main oscillator checks the PLL.
■ The main oscillator checks the internal oscillator.
■ The internal oscillator divided by 64 checks the main oscillator.
If the verification timer function is enabled and a failure is detected, the main clock tree is immediately
switched to a working clock and an interrupt is generated to the controller. Software can then
determine the course of action to take. The actual failure indication and clock switching does not
clear without a write to the CLKVCLR register, an external reset, or a POR reset. The clock
verification timers are controlled by the PLLVER , IOSCVER , and MOSCVER bits in the RCC register.
5.2.5
System Control
For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
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System Control
mode, respectively. The DC1 , DC2 and DC4 registers act as a write mask for the RCGCn , SCGCn,
and DCGCn registers.
There are three levels of operation for the device defined as:
■ Run Mode. In Run mode, the controller actively executes code. Run mode provides normal
operation of the processor and all of the peripherals that are currently enabled by the RCGCn
registers. The system clock can be any of the available clock sources including the PLL.
■ Sleep Mode. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the
processor and the memory subsystem are not clocked and therefore no longer execute code.
Sleep mode is entered by the Cortex-M3 core executing a WFI(Wait for Interrupt)
instruction. Any properly configured interrupt event in the system will bring the processor back
into Run mode. See “Power Management” on page 76 for more details.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
■ Deep-Sleep Mode. In Deep-Sleep mode, the clock frequency of the active peripherals may
change (depending on the Run mode clock configuration) in addition to the processor clock being
stopped. An interrupt returns the device to Run mode from one of the sleep modes. Deep-Sleep
mode is entered by first writing the Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system
control register and then executing a WFI instruction. Any properly configured interrupt event in
the system will bring the processor back into Run mode. See “Power Management” on page 76
for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the
WFI instruction, hardware will power the PLL down. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of
Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep
duration.
Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a
low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their run mode configuration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power-cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.
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5.3
Initialization and Configuration
The PLL is configured using direct register writes to the RCC register. The steps required to
successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source and allows
for the new PLL configuration to be validated before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN and OEN
bits in RCC. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN and OEN bits powers and enables the PLL and its
output.
3. Select the desired system divider (SYSDIV) in RCC and set the USESYS bit in RCC. The SYSDIV
field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC.
Note: If the BYPASS bit is cleared before the PLL locks, it is possible to render the device unusable.
5.4
Register Map
Table 5-6 on page 145 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Table 5-6. System Control Register Map
See
page
Offset
Name
Type
Reset
Description
0x000
0x004
0x008
0x010
0x014
0x018
0x01C
0x030
0x034
0x040
0x044
0x048
DID0
RO
RO
-
Device Identification 0
Device Identification 1
Device Capabilities 0
147
162
164
165
166
168
169
149
150
182
183
184
DID1
-
DC0
RO
0x0007.0003
0x0000.901F
0x0103.1011
0x8300.01C0
0x0000.0007
0x0000.7FFD
0x0000.0000
0x00000000
0x00000000
0x00000000
DC1
RO
Device Capabilities 1
DC2
RO
Device Capabilities 2
DC3
RO
Device Capabilities 3
DC4
RO
Device Capabilities 4
PBORCTL
LDOPCTL
SRCR0
SRCR1
SRCR2
R/W
R/W
R/W
R/W
R/W
Power-On and Brown-Out Reset Control
LDO Power Control
Software Reset Control 0
Software Reset Control 1
Software Reset Control 2
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System Control
Table 5-6. System Control Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0x050
0x054
0x058
0x05C
0x060
0x064
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x144
0x150
0x160
RIS
RO
R/W
R/W1C
R/W
R/W
RO
0x0000.0000
0x0000.0000
0x0000.0000
-
Raw Interrupt Status
151
152
153
154
155
158
170
173
179
171
175
180
172
177
181
159
160
161
IMC
Interrupt Mask Control
MISC
Masked Interrupt Status and Clear
Reset Cause
RESC
RCC
0x0780.3AC0
-
Run-Mode Clock Configuration
PLLCFG
RCGC0
RCGC1
RCGC2
SCGC0
SCGC1
SCGC2
DCGC0
DCGC1
DCGC2
DSLPCLKCFG
CLKVCLR
LDOARST
XTAL to PLL Translation
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00000040
0x00000000
0x00000000
0x00000040
0x00000000
0x00000000
0x00000040
0x00000000
0x00000000
0x0780.0000
0x0000.0000
0x0000.0000
Run Mode Clock Gating Control Register 0
Run Mode Clock Gating Control Register 1
Run Mode Clock Gating Control Register 2
Sleep Mode Clock Gating Control Register 0
Sleep Mode Clock Gating Control Register 1
Sleep Mode Clock Gating Control Register 2
Deep Sleep Mode Clock Gating Control Register 0
Deep Sleep Mode Clock Gating Control Register 1
Deep Sleep Mode Clock Gating Control Register 2
Deep Sleep Clock Configuration
Clock Verification Clear
Allow Unregulated LDO to Reset the Part
5.5
Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
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Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the microcontroller. Each microcontroller is uniquely identified
by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1
register.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
VER
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MAJOR
MINOR
Type
Reset
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
Bit/Field
31
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30:28
VER
RO
0x0
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows:
Value Description
0x0 Initial DID0 register format definition for Stellaris®
Sandstorm-class devices.
27:16
15:8
reserved
MAJOR
RO
RO
0x0
-
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Major Revision
This field specifies the major revision number of the device. The major
revision reflects changes to base layers of the design. The major revision
number is indicated in the part number as a letter (A for first revision, B
for second, and so on). This field is encoded as follows:
Value Description
0x0 Revision A (initial device)
0x1 Revision B (first base layer revision)
0x2 Revision C (second base layer revision)
and so on.
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Bit/Field
7:0
Name
Type
RO
Reset
-
Description
MINOR
Minor Revision
This field specifies the minor revision number of the device. The minor
revision reflects changes to the metal layers of the design. The MINOR
field value is reset when the MAJOR field is changed. This field is numeric
and is encoded as follows:
Value Description
0x0 Initial device, or a major revision update.
0x1 First metal layer change.
0x2 Second metal layer change.
and so on.
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Register 2: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Power-On and Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BORTIM
BORIOR BORWT
Type
Reset
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
R/W
1
Bit/Field
31:16
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:2
BORTIM
R/W
0x1FFF
BOR Time Delay
This field specifies the number of internal oscillator clocks delayed before
the BOR output is resampled if the BORWT bit is set.
The width of this field is derived by the t BOR width of 500 μs and the
internal oscillator (IOSC) frequency of 12 MHz ± 30%. At +30%, the
counter value has to exceed 7,800.
1
0
BORIOR
BORWT
R/W
R/W
0
1
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.
BOR Wait and Check for Noise
This bit specifies the response to a brown-out signal assertion if BORIOR
is not set.
If BORWT is set to 1 and BORIOR is cleared to 0, the controller waits
BORTIM IOSC periods and resamples the BOR output. If still asserted,
a BOR interrupt is signalled. If no longer asserted, the initial assertion
is suppressed (attributable to noise).
If BORWT is 0, BOR assertions do not resample the output and any
condition is reported immediately if enabled.
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System Control
Register 3: LDO Power Control (LDOPCTL), offset 0x034
The VADJ field in this register adjusts the on-chip output voltage (VOUT).
LDO Power Control (LDOPCTL)
Base 0x400F.E000
Offset 0x034
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
VADJ
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:6
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:0
VADJ
R/W
0x0
LDO Output Voltage
This field sets the on-chip output voltage. The programming values for
the VADJ field are provided below.
Value
0x00
0x01
0x02
0x03
0x04
0x05
VOUT (V)
2.50
2.45
2.40
2.35
2.30
2.25
0x06-0x3F Reserved
0x1B
0x1C
0x1D
0x1E
0x1F
2.75
2.70
2.65
2.60
2.55
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Register 4: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PLLLRIS CLRIS
IOFRIS MOFRIS LDORIS BORRIS PLLFRIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:7
Name
Type
Reset
0
Description
reserved
RO
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
5
4
3
2
1
PLLLRIS
CLRIS
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
PLL Lock Raw Interrupt Status
This bit is set when the PLL TREADY Timer asserts.
Current Limit Raw Interrupt Status
This bit is set if the LDO’s CLE output asserts.
IOFRIS
MOFRIS
LDORIS
BORRIS
Internal Oscillator Fault Raw Interrupt Status
This bit is set if an internal oscillator fault is detected.
Main Oscillator Fault Raw Interrupt Status
This bit is set if a main oscillator fault is detected.
LDO Power Unregulated Raw Interrupt Status
This bit is set if a LDO voltage is unregulated.
Brown-Out Reset Raw Interrupt Status
This bit is the raw interrupt status for any brown-out conditions. If set,
a brown-out condition is currently active. This is an unregistered signal
from the brown-out detection circuit. An interrupt is reported if the BORIM
bit in the IMC register is set and the BORIOR bit in the PBORCTL register
is cleared.
0
PLLFRIS
RO
0
PLL Fault Raw Interrupt Status
This bit is set if a PLL fault is detected (stops oscillating).
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System Control
Register 5: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PLLLIM
CLIM
IOFIM
MOFIM
LDOIM
BORIM
PLLFIM
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:7
Name
Type
Reset
0
Description
reserved
RO
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
5
4
3
2
1
0
PLLLIM
R/W
0
0
0
0
0
0
0
PLL Lock Interrupt Mask
This bit specifies whether a PLL Lock interrupt is promoted to a controller
interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set;
otherwise, an interrupt is not generated.
CLIM
IOFIM
R/W
R/W
R/W
R/W
R/W
R/W
Current Limit Interrupt Mask
This bit specifies whether a current limit detection is promoted to a
controller interrupt. If set, an interrupt is generated if CLRIS is set;
otherwise, an interrupt is not generated.
Internal Oscillator Fault Interrupt Mask
This bit specifies whether an internal oscillator fault detection is promoted
to a controller interrupt. If set, an interrupt is generated if IOFRIS is set;
otherwise, an interrupt is not generated.
MOFIM
LDOIM
BORIM
PLLFIM
Main Oscillator Fault Interrupt Mask
This bit specifies whether a main oscillator fault detection is promoted
to a controller interrupt. If set, an interrupt is generated if MOFRIS is set;
otherwise, an interrupt is not generated.
LDO Power Unregulated Interrupt Mask
This bit specifies whether an LDO unregulated power situation is
promoted to a controller interrupt. If set, an interrupt is generated if
LDORIS is set; otherwise, an interrupt is not generated.
Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.
PLL Fault Interrupt Mask
This bit specifies whether a PLL fault detection is promoted to a controller
interrupt. If set, an interrupt is generated if PLLFRIS is set; otherwise,
an interrupt is not generated.
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Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
On a read, this register gives the current masked status value of the corresponding interrupt. All of
the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register
(see page 151).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
reserved
PLLLMIS CLMIS
IOFMIS MOFMIS LDOMIS BORMIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
RO
0
Bit/Field
31:7
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
5
4
3
2
1
PLLLMIS
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
0
0
0
0
0
0
PLL Lock Masked Interrupt Status
This bit is set when the PLL TREADY timer asserts. The interrupt is cleared
by writing a 1 to this bit.
CLMIS
IOFMIS
MOFMIS
LDOMIS
BORMIS
Current Limit Masked Interrupt Status
This bit is set if the LDO’s CLE output asserts. The interrupt is cleared
by writing a 1 to this bit.
Internal Oscillator Fault Masked Interrupt Status
This bit is set if an internal oscillator fault is detected. The interrupt is
cleared by writing a 1 to this bit.
Main Oscillator Fault Masked Interrupt Status
This bit is set if a main oscillator fault is detected. The interrupt is cleared
by writing a 1 to this bit.
LDO Power Unregulated Masked Interrupt Status
This bit is set if LDO power is unregulated. The interrupt is cleared by
writing a 1 to this bit.
BOR Masked Interrupt Status
This bit is the masked interrupt status for any brown-out conditions. If
set, a brown-out condition was detected. An interrupt is reported if the
BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL
register is cleared. The interrupt is cleared by writing a 1 to this bit.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 7: Reset Cause (RESC), offset 0x05C
This field specifies the cause of the reset event to software. The reset value is determined by the
cause of the reset. When an external reset is the cause (EXT is set), all other reset bits are cleared.
However, if the reset is due to any other cause, the remaining bits are sticky, allowing software to
see all causes.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
LDO
SW
WDT
BOR
POR
EXT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
31:6
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
LDO
R/W
-
LDO Reset
When set, indicates the LDO circuit has lost regulation and has
generated a reset event.
4
3
2
1
0
SW
WDT
BOR
POR
EXT
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
Software Reset
When set, indicates a software reset is the cause of the reset event.
Watchdog Timer Reset
When set, indicates a watchdog reset is the cause of the reset event.
Brown-Out Reset
When set, indicates a brown-out reset is the cause of the reset event.
Power-On Reset
When set, indicates a power-on reset is the cause of the reset event.
External Reset
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
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Stellaris® LM3S102 Microcontroller
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x0780.3AC0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
USESYSDIV
reserved
ACG
SYSDIV
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PWRDN
OEN
BYPASS PLLVER
XTAL
OSCSRC
IOSCVER MOSCVER IOSCDIS MOSCDIS
Type
Reset
RO
0
RO
0
R/W
1
R/W
1
R/W
1
R/W
0
R/W
1
R/W
0
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:28
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27
ACG
R/W
0
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
26:23
SYSDIV
R/W
0xF
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS
bit in this register is configured). See Table 5-5 on page 142 for bit
encodings.
The PLL VCO frequency is 200 MHz.
If the SYSDIV value is less than MINSYSDIV (see page 165), and the
PLL is being used, then the MINSYSDIV value is used as the divisor.
If the PLL is not being used, the SYSDIV value can be less than
MINSYSDIV.
22
USESYSDIV
R/W
0
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2 field
in the RCC2 register is used as the system clock divider rather than the
SYSDIV field in this register.
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System Control
Bit/Field
21:14
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
12
PWRDN
OEN
R/W
R/W
1
1
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL. See Table 5-7 on page 157 for PLL mode control.
PLL Output Enable
This bit specifies whether the PLL output driver is enabled. If cleared,
the driver transmits the PLL clock to the output. Otherwise, the PLL
clock does not oscillate outside the PLL module.
Note:
Both PWRDN and OEN must be cleared to run the PLL.
11
BYPASS
R/W
1
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
See Table 5-5 on page 142 for programming guidelines.
10
PLLVER
XTAL
R/W
R/W
0
PLL Verification
This bit controls the PLL verification timer function. If set, the verification
timer is enabled and an interrupt is generated if the PLL becomes
inoperative. Otherwise, the verification timer is not enabled.
9:6
0xB
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below.
Value Crystal Frequency (MHz) Not Crystal Frequency (MHz) Using
Using the PLL
the PLL
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
1.000
reserved
reserved
reserved
reserved
1.8432
2.000
2.4576
3.579545 MHz
3.6864 MHz
4 MHz
4.096 MHz
4.9152 MHz
5 MHz
5.12 MHz
6 MHz (reset value)
6.144 MHz
7.3728 MHz
8 MHz
8.192 MHz
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Stellaris® LM3S102 Microcontroller
Bit/Field
5:4
Name
Type
R/W
Reset
0x0
Description
OSCSRC
Oscillator Source
Selects the input source for the OSC. The values are:
Value Input Source
0x0 MOSC
Main oscillator (default)
0x1 IOSC
Internal oscillator
0x2 IOSC/4
Internal oscillator / 4 (this is necessary if used as input to PLL)
0x3 reserved
3
2
IOSCVER
R/W
R/W
0
0
Internal Oscillator Verification Timer
This bit controls the internal oscillator verification timer function. If set,
the verification timer is enabled and an interrupt is generated if the timer
becomes inoperative. Otherwise, the verification timer is not enabled.
MOSCVER
Main Oscillator Verification Timer
This bit controls the main oscillator verification timer function. If set, the
verification timer is enabled and an interrupt is generated if the timer
becomes inoperative. Otherwise, the verification timer is not enabled.
1
0
IOSCDIS
R/W
R/W
0
0
Internal Oscillator Disable
0: Internal oscillator (IOSC) is enabled.
1: Internal oscillator is disabled.
MOSCDIS
Main Oscillator Disable
0: Main oscillator is enabled (default).
1: Main oscillator is disabled .
Table 5-7. PLL Mode Control
PWRDN
OEN
Mode
1
0
X
0
Power down
Normal
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System Control
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 155).
The PLL frequency is calculated using the PLLCFG field values, as follows:
PLLFreq = OSCFreq * (F + 2) / (R + 2)
XTAL to PLL Translation (PLLCFG)
Base 0x400F.E000
Offset 0x064
Type RO, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
F
8
7
6
5
4
3
2
1
0
OD
R
Type
Reset
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
Bit/Field
31:16
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:14
OD
RO
-
PLL OD Value
This field specifies the value supplied to the PLL’s OD input.
Value Description
0x0 Divide by 1
0x1 Divide by 2
0x2 Divide by 4
0x3 Reserved
13:5
4:0
F
RO
RO
-
-
PLL F Value
This field specifies the value supplied to the PLL’s F input.
R
PLL R Value
This field specifies the value supplied to the PLL’s R input.
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Stellaris® LM3S102 Microcontroller
Register 10: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register is used to automatically switch from the main oscillator to the internal oscillator when
entering Deep-Sleep mode. The system clock source is the main oscillator by default. When this
register is set, the internal oscillator is powered up and the main oscillator is powered down. When
the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency
it had at the onset of Deep-Sleep mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IOSC
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:1
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
IOSC
R/W
0
IOSC Clock Source
When set, forces IOSC to be clock source during Deep-Sleep (overrides
DSOSCSRC field if set)
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System Control
Register 11: Clock Verification Clear (CLKVCLR), offset 0x150
This register is provided as a means of clearing the clock verification circuits by software. Since the
clock verification circuits force a known good clock to control the process, the controller is allowed
the opportunity to solve the problem and clear the verification fault. This register clears all clock
verification faults. To clear a clock verification fault, the VERCLR bit must be set and then cleared
by software. This bit is not self-clearing.
Clock Verification Clear (CLKVCLR)
Base 0x400F.E000
Offset 0x150
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
VERCLR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:1
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
VERCLR
R/W
0
Clock Verification Clear
Clears clock verification faults.
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Stellaris® LM3S102 Microcontroller
Register 12: Allow Unregulated LDO to Reset the Part (LDOARST), offset
0x160
This register is provided as a means of allowing the LDO to reset the part if the voltage goes
unregulated. Use this register to choose whether to automatically reset the part if the LDO goes
unregulated, based on the design tolerance for LDO fluctuation.
Allow Unregulated LDO to Reset the Part (LDOARST)
Base 0x400F.E000
Offset 0x160
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
LDOARST
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:1
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
LDOARST
R/W
0
LDO Reset
When set, allows unregulated LDO output to reset the part.
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System Control
Register 13: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, pin count, and package
type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the
DID0 register and the PARTNO field in the DID1 register.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VER
FAM
PARTNO
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TEMP
PKG
ROHS
QUAL
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
1
RO
-
RO
-
Bit/Field
31:28
Name
VER
Type
RO
Reset
0x0
Description
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
0x0 Initial DID1 register format definition, indicating a Stellaris
LM3Snnn device.
27:24
FAM
RO
0x0
Family
This field provides the family identification of the device within the
Luminary Micro product portfolio. The value is encoded as follows (all
other encodings are reserved):
Value Description
0x0 Stellaris family of microcontollers, that is, all devices with
external part numbers starting with LM3S.
23:16
PARTNO
RO
0x02
Part Number
This field provides the part number of the device within the family. The
value is encoded as follows (all other encodings are reserved):
Value Description
0x02 LM3S102
15:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S102 Microcontroller
Bit/Field
7:5
Name
TEMP
Type
RO
Reset
-
Description
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0 Commercial temperature range (0°C to 70°C)
0x1 Industrial temperature range (-40°C to 85°C)
0x2 Extended temperature range (-40°C to 105°C)
4:3
PKG
RO
-
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
Value Description
0x0 28-pin SOIC package
0x1 48-pin LQFP package
0x3 48-pin QFN package
2
ROHS
QUAL
RO
RO
1
-
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
1:0
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0 Engineering Sample (unqualified)
0x1 Pilot Production (unqualified)
0x2 Fully Qualified
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System Control
Register 14: Device Capabilities 0 (DC0), offset 0x008
This register is predefined by the part and can be used to verify features.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x0007.0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SRAMSZ
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FLASHSZ
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
Bit/Field
31:16
Name
Type
RO
Reset
Description
SRAM Size
SRAMSZ
FLASHSZ
0x0007
Indicates the size of the on-chip SRAM memory.
Value Description
0x0007 2 KB of SRAM
15:0
RO
0x0003
Flash Size
Indicates the size of the on-chip flash memory.
Value Description
0x0003 8 KB of Flash
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Stellaris® LM3S102 Microcontroller
Register 15: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: PWM, ADC,
Watchdog timer, and debug capabilities. This register also indicates the maximum clock frequency
and maximum ADC sample rate. The format of this register is consistent with the RCGC0, SCGC0,
and DCGC0 clock control registers and the SRCR0 software reset control register.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0000.901F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MINSYSDIV
reserved
PLL
WDT
SWO
SWD
JTAG
Type
Reset
RO
1
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
31:16
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:12
MINSYSDIV
RO
0x9
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
0x9 Specifies a 20-MHz clock with a PLL divider of 10.
11:5
4
reserved
PLL
RO
RO
0
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
3
2
WDT
SWO
RO
RO
1
1
Watchdog Timer Present
When set, indicates that a watchdog timer is present.
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
1
0
SWD
JTAG
RO
RO
1
1
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
JTAG Present
When set, indicates that the JTAG debugger interface is present.
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System Control
Register 16: Device Capabilities 2 (DC2), offset 0x014
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register
is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software
reset control register.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x0103.1011
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
COMP0
reserved
TIMER1 TIMER0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
I2C0
reserved
SSI0
reserved
UART0
Type
Reset
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
1
Bit/Field
31:25
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
24
COMP0
reserved
RO
RO
1
0
Analog Comparator 0 Present
When set, indicates that analog comparator 0 is present.
23:18
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17
16
TIMER1
TIMER0
reserved
RO
RO
RO
1
1
0
Timer 1 Present
When set, indicates that General-Purpose Timer module 1 is present.
Timer 0 Present
When set, indicates that General-Purpose Timer module 0 is present.
15:13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
RO
RO
1
0
I2C Module 0 Present
When set, indicates that I2C module 0 is present.
11:5
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
SSI0
RO
RO
1
0
SSI0 Present
When set, indicates that SSI module 0 is present.
3:1
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S102 Microcontroller
Bit/Field
0
Name
Type
RO
Reset
1
Description
UART0
UART0 Present
When set, indicates that UART module 0 is present.
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System Control
Register 17: Device Capabilities 3 (DC3), offset 0x018
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0x8300.01C0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
32KHZ
reserved
CCP1
CCP0
reserved
Type
Reset
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
C0O
C0PLUS C0MINUS
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31
Name
Type
RO
Reset
1
Description
32KHz Input Clock Available
32KHZ
When set, indicates the 32KHz pin or an even CCP pin is present and
can be used as a 32-KHz input clock.
30:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
24
CCP1
CCP0
RO
RO
RO
1
1
0
CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin 1 is present.
CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin 0 is present.
23:9
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
7
C0O
RO
RO
RO
RO
1
1
1
0
C0o Pin Present
When set, indicates that the analog comparator 0 output pin is present.
C0PLUS
C0MINUS
reserved
C0+ Pin Present
When set, indicates that the analog comparator 0 (+) input pin is present.
6
C0- Pin Present
When set, indicates that the analog comparator 0 (-) input pin is present.
5:0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
168
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Stellaris® LM3S102 Microcontroller
Register 18: Device Capabilities 4 (DC4), offset 0x01C
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of GPIOs in the specific device. The format of this register is
consistent with the RCGC2, SCGC2, and DCGC2 clock control registers and the SRCR2 software
reset control register.
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x0000.0007
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
GPIOC
GPIOB
GPIOA
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
Bit/Field
31:3
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
1
0
GPIOC
GPIOB
GPIOA
RO
RO
RO
1
1
1
GPIO Port C Present
When set, indicates that GPIO Port C is present.
GPIO Port B Present
When set, indicates that GPIO Port B is present.
GPIO Port A Present
When set, indicates that GPIO Port A is present.
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System Control
Register 19: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
Type R/W, reset 0x00000040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WDT
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
Bit/Field
31:4
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT
R/W
RO
0
0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
2:0
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S102 Microcontroller
Register 20: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WDT
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
Bit/Field
31:4
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT
R/W
RO
0
0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
2:0
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 21: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WDT
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
Bit/Field
31:4
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT
R/W
RO
0
0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
2:0
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S102 Microcontroller
Register 22: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
COMP0
reserved
TIMER1 TIMER0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
I2C0
reserved
SSI0
reserved
UART0
Type
Reset
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:25
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
24
COMP0
R/W
0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
23:18
17
reserved
TIMER1
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16
TIMER0
reserved
R/W
RO
0
0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
15:13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
12
Name
I2C0
Type
R/W
Reset
0
Description
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
11:5
4
reserved
SSI0
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3:1
0
reserved
UART0
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
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Stellaris® LM3S102 Microcontroller
Register 23: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
COMP0
reserved
TIMER1 TIMER0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
I2C0
reserved
SSI0
reserved
UART0
Type
Reset
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:25
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
24
COMP0
R/W
0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
23:18
17
reserved
TIMER1
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16
TIMER0
R/W
0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
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System Control
Bit/Field
15:13
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
11:5
4
reserved
SSI0
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3:1
0
reserved
UART0
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
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Stellaris® LM3S102 Microcontroller
Register 24: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
COMP0
reserved
TIMER1 TIMER0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
I2C0
reserved
SSI0
reserved
UART0
Type
Reset
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:25
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
24
COMP0
R/W
0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
23:18
17
reserved
TIMER1
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16
TIMER0
R/W
0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
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System Control
Bit/Field
15:13
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
11:5
4
reserved
SSI0
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3:1
0
reserved
UART0
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
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Stellaris® LM3S102 Microcontroller
Register 25: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
GPIOC
GPIOB
GPIOA
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:3
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
1
0
GPIOC
R/W
R/W
R/W
0
0
0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
GPIOB
GPIOA
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
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System Control
Register 26: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 2 (SCGC2)
Base 0x400F.E000
Offset 0x118
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
GPIOC
GPIOB
GPIOA
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:3
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
1
0
GPIOC
R/W
R/W
R/W
0
0
0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
GPIOB
GPIOA
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
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Stellaris® LM3S102 Microcontroller
Register 27: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
GPIOC
GPIOB
GPIOA
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:3
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
1
0
GPIOC
R/W
R/W
R/W
0
0
0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
GPIOB
GPIOA
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
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System Control
Register 28: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WDT
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
Bit/Field
31:4
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT
R/W
RO
0
0
WDT Reset Control
Reset control for Watchdog unit.
2:0
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S102 Microcontroller
Register 29: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
COMP0
reserved
TIMER1 TIMER0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
I2C0
reserved
SSI0
reserved
UART0
Type
Reset
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:25
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
24
COMP0
reserved
R/W
RO
0
0
Analog Comp 0 Reset Control
Reset control for analog comparator 0.
23:18
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17
16
TIMER1
TIMER0
reserved
R/W
R/W
RO
0
0
0
Timer 1 Reset Control
Reset control for General-Purpose Timer module 1.
Timer 0 Reset Control
Reset control for General-Purpose Timer module 0.
15:13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
RO
0
0
I2C0 Reset Control
Reset control for I2C unit 0.
11:5
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
SSI0
R/W
RO
0
0
SSI0 Reset Control
Reset control for SSI unit 0.
3:1
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
UART0
R/W
0
UART0 Reset Control
Reset control for UART unit 0.
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System Control
Register 30: Software Reset Control 2 (SRCR2), offset 0x048
Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
GPIOC
GPIOB
GPIOA
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:3
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
1
0
GPIOC
GPIOB
GPIOA
R/W
R/W
R/W
0
0
0
Port C Reset Control
Reset control for GPIO Port C.
Port B Reset Control
Reset control for GPIO Port B.
Port A Reset Control
Reset control for GPIO Port A.
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Stellaris® LM3S102 Microcontroller
6
Internal Memory
The LM3S102 microcontroller comes with 2 KB of bit-banded SRAM and 8 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.
6.1
Block Diagram
Figure 6-1 on page 185 illustrates the Flash functions. The dashed boxes in the figure indicate
registers residing in the System Control module rather than the Flash Control module.
Figure 6-1. Flash Block Diagram
Icode Bus
Flash Control
Cortex-M3
FMA
FMD
Dcode Bus
Flash Array
FMC
FCRIS
FCIM
FCMISC
Flash Protection
Bridge
FMPRE
FMPPE
Flash Timing
USECRL
SRAM Array
6.2
Functional Description
This section describes the functionality of the SRAM and Flash memories.
6.2.1
SRAM Memory
The internal SRAM of the Stellaris® devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor,
certain regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
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0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, see “Bit-Banding” on page 63.
6.2.2
Flash Memory
The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be
programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB
blocks that can be individually protected. The protection allows blocks to be marked as read-only
or execute-only, providing different levels of code protection. Read-only blocks cannot be erased
or programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
See also “Serial Flash Loader” on page 455 for a preprogrammed flash-resident utility used to
download code to the flash memory of a device without the use of a debug interface.
6.2.2.1
Flash Memory Timing
The timing for the flash is automatically handled by the flash controller. However, in order to do so,
it must know the clock rate of the system in order to time its internal signals properly. The number
of clock cycles per microsecond must be provided to the flash controller for it to accomplish this
timing. It is software's responsibility to keep the flash controller updated with this information via the
USec Reload (USECRL) register.
On reset, the USECRL register is loaded with a value that configures the flash timing so that it works
with the maximum clock rate of the part. If software changes the system operating frequency, the
new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash
modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value
of 0x13 (20-1) must be written to the USECRL register.
6.2.2.2
Flash Memory Protection
The user is provided two forms of flash protection per 2-KB flash blocks in two 32-bit wide
registers.The protection policy for each form is controlled by individual bits (per policy per block) in
the FMPPEn and FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed
(written) or erased. If cleared, the block may not be changed.
■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may
be executed or read by software or debuggers. If a bit is cleared, the corresponding block may
only be executed, and contents of the memory block are prohibited from being read as data.
The policies may be combined as shown in Table 6-1 on page 186.
Table 6-1. Flash Protection Policy Combinations
FMPPEn
FMPREn
Protection
0
0
Execute-only protection. The block may only be executed and may not be written or erased.
This mode is used to protect code.
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Table 6-1. Flash Protection Policy Combinations (continued)
FMPPEn
FMPREn
Protection
1
0
The block may be written, erased or executed, but not read. This combination is unlikely to
be used.
0
1
1
1
Read-only protection. The block may be read or executed but may not be written or erased.
This mode is used to lock the block from further modification while allowing any read or
execute access.
No protection. The block may be written, erased, executed or read.
A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited
and generates a bus fault. A Flash memory access that attempts to program or erase a
program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt
(by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software
developers of poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. These settings create a policy of open access and programmability. The register bits may
be changed by clearing the specific register bit. The changes are not permanent until the register
is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a
0 and not committed, it may be restored by executing a power-on reset sequence. The changes
are committed using the Flash Memory Control (FMC) register.
6.2.2.3
Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:
■ Programming Interrupt - signals when a program or erase action is complete.
■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block
of memory that is protected by its corresponding FMPPEn bit.
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 196) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 195).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the
corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register
(see page 197).
6.2.2.4
Flash Memory Protection by Disabling Debug Access
Flash memory may also be protected by permanently disabling access to the Debug Access Port
(DAP) through the JTAG and SWD interfaces. Access is disabled by clearing the DBG field of the
FMPRE register.
If the DBG field in the Flash Memory Protection Read Enable (FMPRE) register is programmed
to 0x2, access to the DAP is enabled through the JTAG and SWD interfaces. If clear, access to the
DAP is disabled. The DBG field programming becomes permanent and irreversible after a commit
sequence is performed.
In the initial state provided from the factory, access is enabled in order to facilitate code development
and debug. Access to the DAP may be disabled at the end of the manufacturing flow, once all tests
have passed and software has been loaded. This change does not take effect until the next power-up
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of the device. Note that it is recommended that disabling access to the DAP be combined with a
mechanism for providing end-user installable updates (if necessary) such as the Stellaris boot loader.
Important: Once the DBG field is cleared and committed, this field can never be restored to the
factory-programmed value—which means the JTAG/SWD interface to the debug module
can never be re-enabled. This sequence does NOT disable the JTAG controller, it only
disables the access of the DAP through the JTAG or SWD interfaces. The JTAG interface
remains functional and access to the Test Access Port remains enabled, allowing the
user to execute the IEEE JTAG-defined instructions (for example, to perform boundary
scan operations).
When using the FMPRE bits to protect Flash memory from being read as data (to mark sets of 2-KB
blocks of Flash memory as execute-only), these one-time-programmable bits should be written at
the same time that the debug disable bits are programmed. Mechanisms to execute the one-time
code sequence to disable all debug access include:
■ Selecting the debug disable option in the Stellaris boot loader
■ Loading the debug disable sequence into SRAM and running it once from SRAM after
programming the final end application code into Flash memory
6.3
Flash Memory Initialization and Configuration
This section shows examples for using the flash controller to perform various operations on the
contents of the flash memory.
6.3.1
Changing Flash Protection Bits
As discussed in “Flash Memory Protection” on page 186, changes to the protection bits must be
committed before they take effect. The sequence below is used change and commit a block protection
bit in the FMPRE or FMPPE registers. The sequence to change and commit a bit in software is as
follows:
1. The Flash Memory Protection Read Enable (FMPRE) and Flash Memory Protection Program
Enable (FMPPE) registers are written, changing the intended bit(s). The action of these changes
can be tested by software while in this state.
2. The Flash Memory Address (FMA) register (see page 191) bit 0 is set to 1 if the FMPPE register
is to be committed; otherwise, a 0 commits the FMPRE register.
3. The Flash Memory Control (FMC) register (see page 193) is written with the COMT bit set. This
initiates a write sequence and commits the changes.
There is a special sequence to change and commit the DBG bits in the Flash Memory Protection
Read Enable (FMPRE) register. This sequence also sets and commits any changes from 1 to 0 in
the block protection bits (for execute-only) in the FMPRE register.
1. The Flash Memory Protection Read Enable (FMPRE) register is written, changing the intended
bit(s). The action of these changes can be tested by software while in this state.
2. The Flash Memory Address (FMA) register (see page 191) is written with a value of 0x900.
3. The Flash Memory Control (FMC) register (see page 193) is written with the COMT bit set. This
initiates a write sequence and commits the changes.
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Below is an example code sequence to permanently disable the JTAG and SWD interface to the
debug module using DriverLib:
#include "hw_types.h"
#include "hw_flash.h"
void
permanently_disable_jtag_swd(void)
{
//
// Clear the DBG field of the FMPRE register. Note that the value
// used in this instance does not affect the state of the BlockN
// bits, but were the value different, all bits in the FMPRE are
// affected by this function!
//
HWREG(FLASH_FMPRE) &= 0x3fffffff;
//
// The following sequence activates the one-time
// programming of the FMPRE register.
//
HWREG(FLASH_FMA) = 0x900;
HWREG(FLASH_FMC) = (FLASH_FMC_WRKEY | FLASH_FMC_COMT);
//
// Wait until the operation is complete.
//
while (HWREG(FLASH_FMC) & FLASH_FMC_COMT)
{
}
}
6.3.2
Flash Programming
The Stellaris devices provide a user-friendly interface for flash programming. All erase/program
operations are handled via three registers: FMA, FMD, and FMC.
During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory
is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation
is complete. If instruction execution is required during a Flash memory operation, the code that is
executing must be placed in SRAM and executed from there while the flash operation is in progress.
6.3.2.1
To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register.
4. Poll the FMC register until the WRITE bit is cleared.
To perform an erase of a 1-KB page
6.3.2.2
1. Write the page address to the FMA register.
2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register.
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3. Poll the FMC register until the ERASE bit is cleared.
6.3.2.3
To perform a mass erase of the flash
1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register.
2. Poll the FMC register until the MERASE bit is cleared.
6.4
Register Map
Table 6-2 on page 190 lists the Flash memory and control registers. The offset listed is a hexadecimal
increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC register
offsets are relative to the Flash memory control base address of 0x400F.D000. The Flash memory
protection register offsets are relative to the System Control base address of 0x400F.E000.
Table 6-2. Flash Register Map
See
page
Offset
Name
Type
Reset
Description
Flash Memory Control Registers (Flash Control Offset)
0x000
0x004
0x008
0x00C
0x010
0x014
FMA
R/W
R/W
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Flash Memory Address
191
192
193
195
196
197
FMD
Flash Memory Data
FMC
R/W
Flash Memory Control
FCRIS
FCIM
FCMISC
RO
Flash Controller Raw Interrupt Status
Flash Controller Interrupt Mask
Flash Controller Masked Interrupt Status and Clear
R/W
R/W1C
Flash Memory Protection Registers (System Control Offset)
0x130
0x134
0x140
FMPRE
FMPPE
USECRL
R/W
R/W
R/W
0x8000.000F
0x0000.000F
0x13
Flash Memory Protection Read Enable
Flash Memory Protection Program Enable
USec Reload
200
201
199
6.5
Flash Register Descriptions (Flash Control Offset)
This section lists and describes the Flash Memory registers, in numerical order by address offset.
Registers in this section are relative to the Flash control base address of 0x400F.D000.
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Register 1: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and specifies
which page is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OFFSET
Type
Reset
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:13
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12:0
OFFSET
R/W
0x0
Address Offset
Address offset in flash where operation is performed.
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Register 2: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during the erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DATA
DATA
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:0
Name
DATA
Type
R/W
Reset
0x0
Description
Data Value
Data value for write operation.
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Register 3: Flash Memory Control (FMC), offset 0x008
When this register is written, the flash controller initiates the appropriate access cycle for the location
specified by the Flash Memory Address (FMA) register (see page 191). If the access is a write
access, the data contained in the Flash Memory Data (FMD) register (see page 192) is written.
This is the final register written and initiates the memory operation. There are four control bits in the
lower byte of this register that, when set, initiate the memory operation. The most used of these
register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WRKEY
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
COMT MERASE ERASE
WRITE
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:16
Name
WRKEY
Type
WO
Reset
0x0
Description
Flash Write Key
This field contains a write key, which is used to minimize the incidence
of accidental flash writes. The value 0xA442 must be written into this
field for a write to occur. Writes to the FMC register without this WRKEY
value are ignored. A read of this field returns the value 0.
15:4
3
reserved
COMT
RO
0x0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
Commit Register Value
Commit (write) of register value to nonvolatile storage. A write of 0 has
no effect on the state of this bit.
If read, the state of the previous commit access is provided. If the
previous commit access is complete, a 0 is returned; otherwise, if the
commit access is not complete, a 1 is returned.
This can take up to 50 μs.
2
MERASE
R/W
0
Mass Erase Flash Memory
If this bit is set, the flash main memory of the device is all erased. A
write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is provided. If the
previous mass erase access is complete, a 0 is returned; otherwise, if
the previous mass erase access is not complete, a 1 is returned.
This can take up to 250 ms.
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Bit/Field
1
Name
Type
R/W
Reset
0
Description
ERASE
Erase a Page of Flash Memory
If this bit is set, the page of flash main memory as specified by the
contents of FMA is erased. A write of 0 has no effect on the state of this
bit.
If read, the state of the previous erase access is provided. If the previous
erase access is complete, a 0 is returned; otherwise, if the previous
erase access is not complete, a 1 is returned.
This can take up to 25 ms.
0
WRITE
R/W
0
Write a Word into Flash Memory
If this bit is set, the data stored in FMD is written into the location as
specified by the contents of FMA. A write of 0 has no effect on the state
of this bit.
If read, the state of the previous write update is provided. If the previous
write access is complete, a 0 is returned; otherwise, if the write access
is not complete, a 1 is returned.
This can take up to 50 µs.
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Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled
if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PRIS
ARIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:2
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PRIS
RO
0
Programming Raw Interrupt Status
This bit provides status on programming cycles which are write or erase
actions generated through the FMC register bits (see page 193).
Value Description
1
0
The programming cycle has completed.
The programming cycle has not completed.
This status is sent to the interrupt controller when the PMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register.
0
ARIS
RO
0
Access Raw Interrupt Status
Value Description
1
A program or erase action was attempted on a block of Flash
memory that contradicts the protection policy for that block as
set in the FMPPEn registers.
0
No access has tried to improperly program or erase the Flash
memory.
This status is sent to the interrupt controller when the AMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register.
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Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PMASK AMASK
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
Bit/Field
31:2
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PMASK
R/W
0
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the interrupt controller.
Value Description
1
An interrupt is sent to the interrupt controller when the PRIS bit
is set.
0
The PRIS interrupt is suppressed and not sent to the interrupt
controller.
0
AMASK
R/W
0
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
interrupt controller.
Value Description
1
An interrupt is sent to the interrupt controller when the ARIS bit
is set.
0
The ARIS interrupt is suppressed and not sent to the interrupt
controller.
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Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PMISC
AMISC
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
Bit/Field
31:2
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PMISC
R/W1C
0
Programming Masked Interrupt Status and Clear
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because a programming cycle completed.
Writing a 1 to this bit clears PMISC and also the PRIS bit in the
FCRIS register (see page 195).
0
When read, a 0 indicates that a programming cycle complete
interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
AMISC
R/W1C
0
Access Masked Interrupt Status and Clear
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because a program or erase action was attempted on
a block of Flash memory that contradicts the protection policy
for that block as set in the FMPPEn registers.
Writing a 1 to this bit clears AMISC and also the ARIS bit in the
FCRIS register (see page 195).
0
When read, a 0 indicates that no improper accesses have
occurred.
A write of 0 has no effect on the state of this bit.
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Internal Memory
6.6
Flash Register Descriptions (System Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the System Control base address of
0x400F.E000.
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Register 7: USec Reload (USECRL), offset 0x140
Note: Offset is relative to System Control base address of 0x400F.E000
This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.
The internal flash has specific minimum and maximum requirements on the length of time the high
voltage write pulse can be applied. It is required that this register contain the operating frequency
(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this
value if the clocking conditions are changed for a flash erase/program operation.
USec Reload (USECRL)
Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x13
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
USEC
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
1
R/W
1
Bit/Field
31:8
Name
Type
RO
Reset
0x0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
USEC
R/W
0x13
Microsecond Reload Value
MHz -1 of the controller clock when the flash is being erased or
programmed.
If the maximum system frequency is being used, USEC should be set to
0x13 (19 MHz) whenever the flash is being erased or programmed.
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Internal Memory
Register 8: Flash Memory Protection Read Enable (FMPRE), offset 0x130
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (see the FMPPE registers
for the execute-only protection bits). This register is loaded during the power-on reset sequence.
The factory settingsare a value of 1 for all implemented banks. This implements a policy of open
access and programmability. The register bits may be changed by writing the specific register bit.
However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may
NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at
which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it
may be restored by executing a power-on reset sequence. For additional information, see the “Flash
Memory Protection” section.
Flash Memory Protection Read Enable (FMPRE)
Base 0x400F.E000
Offset 0x130
Type R/W, reset 0x8000.000F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DBG
READ_ENABLE
Type
Reset
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
31:30
Name
DBG
Type
R/W
Reset
0x2
Description
User Controlled Debug Enable
Each bit position maps 2 Kbytes of Flash to be read-enabled.
Value Description
0x2 Debug access allowed
29:0
READ_ENABLE
R/W
0x0000000F Flash Read Enable
Each bit position maps 2 Kbytes of Flash to be read-enabled.
Value
Description
0x0000000F Enables 8 KB of flash.
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Register 9: Flash Memory Protection Program Enable (FMPPE), offset 0x134
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (see the FMPRE
registers for the read-only protection bits). This register is loaded during the power-on reset sequence.
The factory settings are a value of 1 for all implemented banks. This implements a policy of open
access and programmability. The register bits may be changed by writing the specific register bit.
However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may
NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at
which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it
may be restored by executing a power-on reset sequence. For additional information, see the “Flash
Memory Protection” section.
Flash Memory Protection Program Enable (FMPPE)
Base 0x400F.E000
Offset 0x134
Type R/W, reset 0x0000.000F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PROG_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PROG_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
31:0
Name
PROG_ENABLE
Type
R/W
Reset
Description
0x0000000F Flash Programming Enable
Each bit position maps 2 Kbytes of Flash to be write-enabled.
Value
Description
0x0000000F Enables 8 KB of flash.
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General-Purpose Input/Outputs (GPIOs)
7
General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of three physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C). The GPIO module supports 0-18 programmable input/output
pins, depending on the peripherals being used.
The GPIO module has the following features:
■ 0-18 GPIOs, depending on configuration
■ 5-V-tolerant in input configuration
■ Fast toggle capable of a change every two clock cycles
■ Programmable control for GPIO interrupts
–
–
–
Interrupt generation masking
Edge-triggered on rising, falling, or both
Level-sensitive on High or Low values
■ Bit masking in both read and write operations through address lines
■ Pins configured as digital inputs are Schmitt-triggered.
■ Programmable control for GPIO pad configuration
–
–
–
–
–
Weak pull-up or pull-down resistors
2-mA, 4-mA, and 8-mA pad drive for digital communication
Slew rate control for the 8-mA drive
Open drain enables
Digital input enables
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7.1
Block Diagram
Figure 7-1. GPIO Module Block Diagram
U0Rx
U0Tx
PA0
PA1
PA2
PA3
PA4
PA5
UART0
SSI
SSIClk
SSIFss
SSIRx
SSITx
CCP1
CCP0
Timer 0
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
32KHz
Timer 1
I2CSCL
I2CSDA
I2C
C0-
Analog
Comparator
C0o
C0+
TCK/SWCLK
TMS/SWDIO
TRST
PC0
PC1
PC2
PC3
JTAG
TDI
TDO/SWO
7.2
Signal Description
GPIO signals have alternate hardware functions. Table 7-4 on page 205 and Table 7-5 on page 205
list the GPIO pins and their digital alternate functions. Other analog signals are 5-V tolerant and are
connected directly to their circuitry (C0-, C0+). These signals are configured by clearing the DEN
bit in the GPIO Digital Enable (GPIODEN) register. The digital alternate hardware functions are
enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and
GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL)
register to the numeric enoding shown in the table below. Note that each pin must be programmed
individually; no type of grouping is implied by the columns in the table.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
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General-Purpose Input/Outputs (GPIOs)
four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting
RST puts the pins back to their default state.
Table 7-1. GPIO Pins With Non-Zero Reset Values
GPIO Pins
PA[1:0]
Default State
UART0
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR GPIOPCTL
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0x1
0x1
0x1
0x3
PA[5:2]
SSI0
PB[3:2]
PC[3:0]
I2C0
JTAG/SWD
Table 7-2. GPIO Pins and Alternate Functions (28SOIC)
IO
Pin Number
Multiplexed Function
U0Rx
Multiplexed Function
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
11
12
13
14
15
16
19
20
23
24
4
U0Tx
SSIClk
SSIFss
SSIRx
SSITx
CCP0
32KHz
I2CSCL
I2CSDA
C0-
3
C0o
2
C0+
CCP1
1
TRST
28
27
26
25
TCK
SWCLK
SWDIO
TMS
TDI
TDO
SWO
Table 7-3. GPIO Pins and Alternate Functions (48QFP)
IO
Pin Number
Multiplexed Function
U0Rx
Multiplexed Function
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
17
18
19
20
21
22
29
30
33
34
U0Tx
SSIClk
SSIFss
SSIRx
SSITx
CCP0
32KHz
I2CSCL
I2CSDA
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Table 7-3. GPIO Pins and Alternate Functions (48QFP) (continued)
IO
Pin Number
Multiplexed Function
Multiplexed Function
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
44
43
42
41
40
39
38
37
C0-
C0o
C0+
TRST
TCK
TMS
TDI
TDO
CCP1
SWCLK
SWDIO
SWO
Table 7-4. GPIO Signals (28SOIC)
Pin Name
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
Pin Number
Pin Type
I/O
Buffer Typea Description
11
12
13
14
15
16
19
20
23
24
4
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
GPIO port A bit 0.
GPIO port A bit 1.
GPIO port A bit 2.
GPIO port A bit 3.
GPIO port A bit 4.
GPIO port A bit 5.
GPIO port B bit 0.
GPIO port B bit 1.
GPIO port B bit 2.
GPIO port B bit 3.
GPIO port B bit 4.
GPIO port B bit 5.
GPIO port B bit 6.
GPIO port B bit 7.
GPIO port C bit 0.
GPIO port C bit 1.
GPIO port C bit 2.
GPIO port C bit 3.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3
I/O
2
I/O
1
I/O
28
27
26
25
I/O
I/O
I/O
I/O
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 7-5. GPIO Signals (48QFP)
Pin Name
PA0
Pin Number
Pin Type
I/O
Buffer Typea Description
17
18
19
20
21
22
29
30
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
GPIO port A bit 0.
GPIO port A bit 1.
GPIO port A bit 2.
GPIO port A bit 3.
GPIO port A bit 4.
GPIO port A bit 5.
GPIO port B bit 0.
GPIO port B bit 1.
PA1
I/O
PA2
I/O
PA3
I/O
PA4
I/O
PA5
I/O
PB0
I/O
PB1
I/O
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Table 7-5. GPIO Signals (48QFP) (continued)
Pin Name
PB2
Pin Number
Pin Type
I/O
Buffer Typea Description
33
34
44
43
42
41
40
39
38
37
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
GPIO port B bit 2.
PB3
I/O
GPIO port B bit 3.
GPIO port B bit 4.
GPIO port B bit 5.
GPIO port B bit 6.
GPIO port B bit 7.
GPIO port C bit 0.
GPIO port C bit 1.
GPIO port C bit 2.
GPIO port C bit 3.
PB4
I/O
PB5
I/O
PB6
I/O
PB7
I/O
PC0
I/O
PC1
I/O
PC2
I/O
PC3
I/O
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
7.3
Functional Description
Important: All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the exception
of the five JTAG pins (PB7 and PC[3:0]). The JTAG pins default to their JTAG
functionality (GPIOAFSEL=1). A Power-On-Reset (POR) or asserting an external reset
(RST) puts both groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a Low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
7-2 on page 207). The LM3S102 microcontroller contains three ports and thus three of these physical
GPIO blocks.
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Figure 7-2. GPIO Port Block Diagram
Mode
Control
GPIOAFSEL
Alternate Input
Pad Input
Alternate Output
Alternate Output Enable
Digital
I/O Pad
Pad Output
Package I/O Pin
GPIO Input
Data
Control
GPIO Output
GPIODATA
GPIODIR
Pad Output Enable
GPIO Output Enable
Interrupt
Control
Pad
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
GPIOIS
Interrupt
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Identification Registers
GPIOPeriphID0 GPIOPeriphID4
GPIOPeriphID1 GPIOPeriphID5
GPIOPeriphID2 GPIOPeriphID6
GPIOPeriphID3 GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
7.3.1
Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
7.3.1.1
Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 214) is used to configure each individual pin as
an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and
the corresponding data register bit will capture and store the value on the GPIO port. When the data
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.
7.3.1.2
Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 213) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
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During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 7-3 on page 208, where u is data unchanged by the write.
Figure 7-3. GPIODATA Write Example
9
0
8
0
7
1
6
0
5
0
4
1
3
1
2
0
1
0
0
0
ADDR[9:2]
0x098
1
1
1
0
1
0
1
1
0xEB
u
7
u
6
1
5
u
4
u
3
0
2
1
1
u
0
GPIODATA
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 7-4 on page 208.
Figure 7-4. GPIODATA Read Example
9
0
8
0
7
1
6
1
5
0
4
0
3
0
2
1
1
0
0
0
ADDR[9:2]
0x0C4
1
0
1
1
1
1
1
0
GPIODATA
0
7
0
6
1
5
1
4
0
3
0
2
0
1
0
0
Returned Value
7.3.2
Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
■ GPIO Interrupt Sense (GPIOIS) register (see page 215)
■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 216)
■ GPIO Interrupt Event (GPIOIEV) register (see page 217)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 218).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 219 and page 220). As the name implies, the GPIOMIS register only shows interrupt
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conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a
GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR)
register (see page 221).
When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.
7.3.3
7.3.4
Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 222), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.
Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital enable.
7.3.5
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
7.4
Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) default to general-purpose input mode
(GPIODIR=0 and GPIOAFSEL=0). Table 7-6 on page 209 shows all possible configurations of the
GPIO pads and the control register settings required to achieve them. Table 7-7 on page 210 shows
how a rising edge interrupt would be configured for pin 2 of a GPIO port.
Table 7-6. GPIO Pad Configuration Examples
GPIO Register Bit Valuea
Configuration
AFSEL
DIR
ODR
DEN
PUR
PDR
DR2R
DR4R
DR8R
SLR
Digital Input (GPIO)
Digital Output (GPIO)
0
0
0
0
1
1
0
1
?
?
X
?
?
X
?
?
X
?
?
X
0
1
1
1
?
?
?
?
Open Drain Output
(GPIO)
X
X
Open Drain
1
1
1
X
X
X
1
0
0
1
1
1
X
?
?
X
?
?
?
X
?
?
X
?
?
X
?
?
X
?
Input/Output (I2C)
Digital Input (Timer
CCP)
Digital Output (Timer
PWM)
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Table 7-6. GPIO Pad Configuration Examples (continued)
GPIO Register Bit Valuea
Configuration
AFSEL
DIR
ODR
DEN
PUR
PDR
DR2R
DR4R
DR8R
SLR
Digital Input/Output
(SSI)
1
X
X
0
0
1
?
?
?
?
?
?
?
Digital Input/Output
(UART)
1
0
1
0
0
0
1
0
1
?
0
?
?
0
?
?
X
?
?
X
?
?
X
?
Analog Input
(Comparator)
X
?
Digital Output
(Comparator)
X
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
Table 7-7. GPIO Interrupt Configuration Example
Desired
Interrupt
Event
Pin 2 Bit Valuea
7
6
5
4
3
2
1
0
Register
Trigger
GPIOIS
0=edge
1=level
X
X
X
X
X
X
X
X
X
0
0
X
X
X
GPIOIBE
0=single
edge
X
X
1=both
edges
GPIOIEV
GPIOIM
0=Low level,
or negative
edge
X
0
X
0
X
0
X
X
0
1
1
X
0
X
1=High level,
or positive
edge
0=masked
0
0
1=not
masked
a. X=Ignored (don’t care bit)
7.5
Register Map
Table 7-8 on page 211 lists the GPIO registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that GPIO port’s base address:
■ GPIO Port A: 0x4000.4000
■ GPIO Port B: 0x4000.5000
■ GPIO Port C: 0x4000.6000
Note that the GPIO module clock must be enabled before the registers can be programmed (see
page 179). There must be a delay of 3 system clocks after the GPIO module clock is enabled before
any GPIO module registers are accessed.
Important: The GPIO registers in this chapter are duplicated in each GPIO block; however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
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cases, writing to those unconnected bits has no effect, and reading those unconnected
bits returns no meaningful data.
Note: The default reset value for the GPIOAFSEL register is 0x0000.0000 for all GPIO pins, with
the exception of the five JTAG pins (PB7 and PC[3:0]). These five pins default to JTAG
functionality. Because of this, the default reset value of GPIOAFSEL for GPIO Port B is
0x0000.0080 while the default reset value for Port C is 0x0000.000F.
Table 7-8. GPIO Register Map
See
page
Offset
Name
Type
Reset
Description
0x000
0x400
0x404
0x408
0x40C
0x410
0x414
0x418
0x41C
0x420
0x500
0x504
0x508
0x50C
0x510
0x514
0x518
0x51C
0xFD0
0xFD4
0xFD8
0xFDC
0xFE0
0xFE4
0xFE8
0xFEC
0xFF0
GPIODATA
GPIODIR
R/W
R/W
R/W
R/W
R/W
R/W
RO
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
-
GPIO Data
213
214
215
216
217
218
219
220
221
222
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
GPIO Direction
GPIOIS
GPIO Interrupt Sense
GPIOIBE
GPIO Interrupt Both Edges
GPIO Interrupt Event
GPIOIEV
GPIOIM
GPIO Interrupt Mask
GPIORIS
GPIO Raw Interrupt Status
GPIO Masked Interrupt Status
GPIO Interrupt Clear
GPIOMIS
RO
GPIOICR
W1C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
GPIOAFSEL
GPIODR2R
GPIODR4R
GPIODR8R
GPIOODR
GPIO Alternate Function Select
GPIO 2-mA Drive Select
GPIO 4-mA Drive Select
GPIO 8-mA Drive Select
GPIO Open Drain Select
GPIO Pull-Up Select
0x0000.00FF
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.00FF
0x0000.0000
0x0000.0000
0x0000.00FF
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0061
0x0000.0000
0x0000.0018
0x0000.0001
0x0000.000D
GPIOPUR
GPIOPDR
GPIO Pull-Down Select
GPIOSLR
GPIO Slew Rate Control Select
GPIO Digital Enable
GPIODEN
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPCellID0
GPIO Peripheral Identification 4
GPIO Peripheral Identification 5
GPIO Peripheral Identification 6
GPIO Peripheral Identification 7
GPIO Peripheral Identification 0
GPIO Peripheral Identification 1
GPIO Peripheral Identification 2
GPIO Peripheral Identification 3
GPIO PrimeCell Identification 0
RO
RO
RO
RO
RO
RO
RO
RO
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Table 7-8. GPIO Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0xFF4
0xFF8
0xFFC
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
RO
RO
RO
0x0000.00F0
0x0000.0005
0x0000.00B1
GPIO PrimeCell Identification 1
GPIO PrimeCell Identification 2
GPIO PrimeCell Identification 3
241
242
243
7.6
Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.
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Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 214).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DATA
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DATA
R/W
0x00
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and the data written to the
registers are masked by the eight address lines ipaddr[9:2]. Reads
from this register return its current state. Writes to this register only affect
bits that are not masked by ipaddr[9:2] and are configured as
outputs. See “Data Register Operation” on page 207 for examples of
reads and writes.
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Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure
the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are
cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x400
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DIR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DIR
R/W
0x00
GPIO Data Direction
The DIR values are defined as follows:
Value Description
0
1
Pins are inputs.
Pins are outputs.
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Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the
corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits
are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x404
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IS
R/W
0x00
GPIO Interrupt Sense
The IS values are defined as follows:
Value Description
0
1
Edge on corresponding pin is detected (edge-sensitive).
Level on corresponding pin is detected (level-sensitive).
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Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 215) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 217). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x408
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IBE
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IBE
R/W
0x00
GPIO Interrupt Both Edges
The IBE values are defined as follows:
Value Description
0
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 217).
1
Both edges on the corresponding pin trigger an interrupt.
Note:
Single edge is determined by the corresponding bit
in GPIOIEV.
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Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value
in the GPIO Interrupt Sense (GPIOIS) register (see page 215). Clearing a bit configures the pin to
detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are
cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x40C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IEV
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IEV
R/W
0x00
GPIO Interrupt Event
The IEV values are defined as follows:
Value Description
0
Falling edge or Low levels on corresponding pins trigger
interrupts.
1
Rising edge or High levels on corresponding pins trigger
interrupts.
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General-Purpose Input/Outputs (GPIOs)
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding
pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables
interrupt triggering on that pin. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x410
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IME
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IME
R/W
0x00
GPIO Interrupt Mask Enable
The IME values are defined as follows:
Value Description
0
1
Corresponding pin interrupt is masked.
Corresponding pin interrupt is not masked.
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Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the
status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the
requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask
(GPIOIM) register (see page 218). Bits read as zero indicate that corresponding input pins have not
initiated an interrupt. All bits are cleared by a reset.
GPIO Raw Interrupt Status (GPIORIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x414
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
RIS
RO
0x00
GPIO Interrupt Raw Status
Reflects the status of interrupt trigger condition detection on pins (raw,
prior to masking).
The RIS values are defined as follows:
Value Description
0
1
Corresponding pin interrupt requirements not met.
Corresponding pin interrupt has met requirements.
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Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x418
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
MIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
MIS
RO
0x00
GPIO Masked Interrupt Status
Masked value of interrupt due to corresponding pin.
The MIS values are defined as follows:
Value Description
0
1
Corresponding GPIO line interrupt not active.
Corresponding GPIO line asserting interrupt.
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Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.
GPIO Interrupt Clear (GPIOICR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x41C
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IC
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IC
W1C
0x00
GPIO Interrupt Clear
The IC values are defined as follows:
Value Description
0
1
Corresponding interrupt is unaffected.
Corresponding interrupt is cleared.
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General-Purpose Input/Outputs (GPIOs)
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore
no GPIO line is set to hardware control by default.
Important: All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the exception
of the five JTAG pins (PB7 and PC[3:0]). The JTAG pins default to their JTAG
functionality (GPIOAFSEL=1). A Power-On-Reset (POR) or asserting an external reset
(RST) puts both groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a Low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris®
microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their
GPIO functionality, the debugger may not have enough time to connect and halt the controller before
the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided
with a software routine that restores JTAG functionality based on an external or software trigger.
GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x420
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
AFSEL
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
31:8
Name
reserved
Type
RO
Reset
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S102 Microcontroller
Bit/Field
7:0
Name
Type
R/W
Reset
-
Description
AFSEL
GPIO Alternate Function Select
The AFSEL values are defined as follows:
Value Description
0
1
Software control of corresponding GPIO line (GPIO mode).
Hardware control of corresponding GPIO line (alternate
hardware function).
Note:
The default reset value for the GPIOAFSEL register
is 0x0000.0000 for all GPIO pins, with the exception
of the five JTAG pins (PB7 and PC[3:0]). These five
pins default to JTAG functionality. Because of this,
the default reset value of GPIOAFSEL for GPIO Port
B is 0x0000.0080 while the default reset value for
Port C is 0x0000.000F.
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General-Purpose Input/Outputs (GPIOs)
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO
signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 2-mA Drive Select (GPIODR2R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x500
Type R/W, reset 0x0000.00FF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DRV2
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DRV2
R/W
0xFF
Output Pad 2-mA Drive Enable
A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the
corresponding 2-mA enable bit. The change is effective on the second
clock cycle after the write.
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Stellaris® LM3S102 Microcontroller
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 4-mA Drive Select (GPIODR4R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x504
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DRV4
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DRV4
R/W
0x00
Output Pad 4-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the
corresponding 4-mA enable bit. The change is effective on the second
clock cycle after the write.
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General-Purpose Input/Outputs (GPIOs)
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R
register are automatically cleared by hardware.
GPIO 8-mA Drive Select (GPIODR8R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x508
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DRV8
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DRV8
R/W
0x00
Output Pad 8-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the
corresponding 8-mA enable bit. The change is effective on the second
clock cycle after the write.
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Stellaris® LM3S102 Microcontroller
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Enable (GPIODEN) register (see page 231).
Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R, and
GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open-drain
input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the
GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has no
effect until the GPIO is changed to an output.
When using the I2C module, in addition to configuring the pin to open drain, the GPIO Alternate
Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set to 1 (see
examples in “Initialization and Configuration” on page 209).
GPIO Open Drain Select (GPIOODR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x50C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
ODE
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
ODE
R/W
0x00
Output Pad Open Drain Enable
The ODE values are defined as follows:
Value Description
0
1
Open drain configuration is disabled.
Open drain configuration is enabled.
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General-Purpose Input/Outputs (GPIOs)
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up
resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 229).
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x510
Type R/W, reset 0x0000.00FF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PUE
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PUE
R/W
0xFF
Pad Weak Pull-Up Enable
Value Description
0
1
The corresponding pin's weak pull-up resistor is disabled.
The corresponding pin's weak pull-up resistor is enabled.
A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n]
enables. The change is effective on the second clock cycle after the
write.
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Stellaris® LM3S102 Microcontroller
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak
pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 228).
GPIO Pull-Down Select (GPIOPDR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x514
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PDE
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PDE
R/W
0x00
Pad Weak Pull-Down Enable
Value Description
0
1
The corresponding pin's weak pull-down resistor is disabled.
The corresponding pin's weak pull-down resistor is enabled.
A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n]
enables. The change is effective on the second clock cycle after the
write.
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General-Purpose Input/Outputs (GPIOs)
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 226).
GPIO Slew Rate Control Select (GPIOSLR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x518
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SRL
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
SRL
R/W
0x00
Slew Rate Limit Enable (8-mA drive only)
The SRL values are defined as follows:
Value Description
0
1
Slew rate control disabled.
Slew rate control enabled.
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Stellaris® LM3S102 Microcontroller
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
Note: Pins configured as digital inputs are Schmitt-triggered.
The GPIODEN register is the digital enable register. By default, all GPIO signals are configured as
digital inputs at reset. If a pin is being used as a GPIO or its Alternate Hardware Function, it should
be configured as a digital input. The only time that a pin should not be configured as a digital input
is when the GPIO pin is configured to be one of the analog input signals for the analog comparators.
GPIO Digital Enable (GPIODEN)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0x51C
Type R/W, reset 0x0000.00FF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DEN
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DEN
R/W
0xFF
Digital Enable
The DEN values are defined as follows:
Value Description
0
1
Digital functions disabled.
Digital functions enabled.
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General-Purpose Input/Outputs (GPIOs)
Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 4 (GPIOPeriphID4)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID4
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID4
RO
0x00
GPIO Peripheral ID Register[7:0]
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Stellaris® LM3S102 Microcontroller
Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 5 (GPIOPeriphID5)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID5
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID5
RO
0x00
GPIO Peripheral ID Register[15:8]
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General-Purpose Input/Outputs (GPIOs)
Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 6 (GPIOPeriphID6)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID6
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID6
RO
0x00
GPIO Peripheral ID Register[23:16]
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Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 7 (GPIOPeriphID7)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID7
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID7
RO
0x00
GPIO Peripheral ID Register[31:24]
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General-Purpose Input/Outputs (GPIOs)
Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 0 (GPIOPeriphID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0xFE0
Type RO, reset 0x0000.0061
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID0
RO
0x61
GPIO Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
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Register 24: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 1 (GPIOPeriphID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID1
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID1
RO
0x00
GPIO Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
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General-Purpose Input/Outputs (GPIOs)
Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 2 (GPIOPeriphID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID2
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID2
RO
0x18
GPIO Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
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Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 3 (GPIOPeriphID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID3
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID3
RO
0x01
GPIO Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
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General-Purpose Input/Outputs (GPIOs)
Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 0 (GPIOPCellID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID0
RO
0x0D
GPIO PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
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Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 1 (GPIOPCellID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID1
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID1
RO
0xF0
GPIO PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
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General-Purpose Input/Outputs (GPIOs)
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 2 (GPIOPCellID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID2
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
GPIO PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
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Stellaris® LM3S102 Microcontroller
Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 3 (GPIOPCellID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID3
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
GPIO PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
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General-Purpose Timers
8
General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris® General-Purpose Timer Module (GPTM) contains two GPTM blocks (Timer0 and
Timer1). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and TimerB)
that can be configured to operate independently as timers or event counters, or configured to operate
as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
The GPT Module is one timing resource available on the Stellaris microcontrollers. Other timer
resources include the System Timer (SysTick) (see 81).
The General-Purpose Timers provide the following features:
■ Two General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters.
Each GPTM can be configured to operate independently:
–
–
–
As a single 32-bit timer
As one 32-bit Real-Time Clock (RTC) to event capture
For Pulse Width Modulation (PWM)
■ 32-bit Timer modes
–
–
–
–
Programmable one-shot timer
Programmable periodic timer
Real-Time Clock when using an external 32.768-KHz clock as the input
User-enabled stalling when the controller asserts CPU Halt flag during debug
■ 16-bit Timer modes
–
–
–
–
General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)
Programmable one-shot timer
Programmable periodic timer
User-enabled stalling when the controller asserts CPU Halt flag during debug
■ 16-bit Input Capture modes
–
–
Input edge count capture
Input edge time capture
■ 16-bit PWM mode
–
Simple PWM mode with software-programmable output inversion of the PWM signal
8.1
Block Diagram
Note: In Figure 8-1 on page 245, the specific CCP pins available depend on the Stellaris device.
See Table 8-1 on page 245 for the available CCPs.
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Figure 8-1. GPTM Module Block Diagram
0x0000 (Down Counter Modes)
TimerA Control
GPTMTAPMR
GPTMTAPR
TA Comparator
GPTMAR En
Clock / Edge
Detect
GPTMTAMATCHR
GPTMTAILR
Interrupt / Config
32 KHz or
Even CCP Pin
GPTMTAMR
GPTMCFG
GPTMCTL
GPTMIMR
GPTMRIS
GPTMMIS
GPTMICR
TimerA
Interrupt
RTC Divider
TimerB
Interrupt
TimerB Control
GPTMTBR En
TB Comparator
GPTMTBPMR
GPTMTBPR
Clock / Edge
Detect
Odd CCP Pin
GPTMTBMATCHR
GPTMTBILR
GPTMTBMR
0x0000 (Down Counter Modes)
System
Clock
Table 8-1. Available CCP Pins
Timer
16-Bit Up/Down Counter
Even CCP Pin
Odd CCP Pin
Timer 0
TimerA
TimerB
TimerA
TimerB
CCP0
-
-
-
-
CCP1
Timer 1
-
-
8.2
Signal Description
Table 8-2 on page 245 and Table 8-3 on page 246list the external signals of the GP Timer module
and describe the function of each. The GP Timer signals are alternate functions for some GPIO
signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment"
lists the possible GPIO pin placements for these GP Timer signals. The AFSEL bit in the GPIO
Alternate Function Select (GPIOAFSEL) register (page 222) should be set to choose the GP Timer
function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 202.
Table 8-2. General-Purpose Timers Signals (28SOIC)
Pin Name
32KHz
CCP0
Pin Number
Pin Type
Buffer Typea Description
20
19
2
I
TTL
TTL
TTL
32-KHz input to the timer.
I/O
I/O
Capture/Compare/PWM 0.
Capture/Compare/PWM 1.
CCP1
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
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General-Purpose Timers
Table 8-3. General-Purpose Timers Signals (48QFP)
Pin Name
32KHz
CCP0
Pin Number
Pin Type
Buffer Typea Description
30
29
42
I
TTL
TTL
TTL
32-KHz input to the timer.
I/O
I/O
Capture/Compare/PWM 0.
Capture/Compare/PWM 1.
CCP1
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
8.3
Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit
load/initialization registers and their associated control functions. The exact functionality of each
GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 256),
the GPTM TimerA Mode (GPTMTAMR) register (see page 257), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 259). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
8.3.1
8.3.2
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 270) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 271). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 274) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 275).
32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 270
■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 271
■ GPTM TimerA (GPTMTAR) register [15:0], see page 278
■ GPTM TimerB (GPTMTBR) register [15:0], see page 279
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
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8.3.2.1
32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register
(see page 257), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.
When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 261), the
timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches
the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status
(GPTMRIS) register (see page 266), and holds it until it is cleared by writing the GPTM Interrupt
Clear (GPTMICR) register (see page 268). If the time-out interrupt is enabled in the GPTM Interrupt
Mask (GPTMIMR) register (see page 264), the GPTM also sets the TATOMIS bit in the GPTM Masked
Interrupt Status (GPTMMIS) register (see page 267).
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TASTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
8.3.2.2
32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is
loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA
Match (GPTMTAMATCHR) register (see page 272) by the controller.
The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal
is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter.
The 32KHz pin is dedicated to the 32-bit RTC function, and the input clock is 32.768 KHz.
When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its
preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until
either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs,
the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTMIMR, the
GPTM also sets the RTCMIS bit in GPTMMIS and generates a controller interrupt. The status flags
are cleared by writing the RTCCINT bit in GPTMICR.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
8.3.3
16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 256). This section describes each of the GPTM 16-bit modes of
operation. TimerA and TimerB have identical modes, so a single description is given using an n to
reference both.
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8.3.3.1
16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR)
register.
When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting.
In addition to reloading the count value, the timer generates interrupts and triggers when it reaches
the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is
cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTMIMR, the GPTM
also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 20-MHz clock with Tc=20 ns (clock period).
Table 8-4. 16-Bit Timer With Prescaler Configurations
Prescale
00000000
#Clock (T c)a
Max Time
3.2768
6.554
Units
mS
mS
mS
--
1
2
00000001
00000010
3
9.8302
--
------------
--
11111101
254
255
256
832.3073
835.584
838.8608
mS
mS
mS
11111110
11111111
a. Tc is the clock period.
8.3.3.2
16-Bit Input Edge Count Mode
Note: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note: The prescaler is not available in 16-Bit Input Edge Count mode.
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that
must be counted.
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When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked).
The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM
automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached,
all further events are ignored until TnEN is re-enabled by software.
Figure 8-2 on page 249 shows how input edge count mode works. In this case, the timer start value
is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so that
four edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMTnMATCHR register.
Figure 8-2. 16-Bit Input Edge Count Mode Example
Timer stops,
flags
asserted
Timer reload
on next cycle
Ignored
Ignored
Count
0x000A
0x0009
0x0008
0x0007
0x0006
Input Signal
8.3.3.3
16-Bit Input Edge Time Mode
Note: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note: The prescaler is not available in 16-Bit Input Edge Time mode.
In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value
loaded in the GPTMTnILR register (or 0xFFFF at reset). The timer is capable of capturing three
types of events: rising edge, falling edge, or both. The timer is placed into Edge Time mode by
setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is
determined by the TnEVENT fields of the GPTMCTL register.
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR
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register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and
the CnEMIS bit, if the interrupt is not masked).
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMTnILR register.
Figure 8-3 on page 250 shows how input edge timing mode works. In the diagram, it is assumed that
the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).
Figure 8-3. 16-Bit Input Edge Time Mode Example
Count
0xFFFF
GPTMTnR=X
GPTMTnR=Y
GPTMTnR=Z
Z
X
Y
Time
Input Signal
8.3.3.4
16-Bit PWM Mode
Note: The prescaler is not available in 16-Bit PWM mode.
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. In this mode, the PWM
frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM
mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL
register. No interrupts or status bits are asserted in PWM mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern Match
Register (GPTMTnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
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Figure 8-4 on page 251 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMTnIRL=0xC350 and the match value is
GPTMTnMATCHR=0x411A.
Figure 8-4. 16-Bit PWM Mode Example
GPTMTnR=GPTMnMR
GPTMTnR=GPTMnMR
Count
0xC350
0x411A
Time
TnEN set
TnPWML = 0
TnPWML = 1
Output
Signal
8.4
Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0
and TIMER1 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported timer
modes.
8.4.1
32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.
3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR).
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5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
In One-Shot mode, the timer stops counting after step 7 on page 252. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
8.4.2
32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To
enable the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1.
3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).
4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.
5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTAMATCHR register, the GPTM asserts the
RTCRIS bit in the GPTMRIS register and continues counting until Timer A is disabled or a hardware
reset. The interrupt is cleared by writing the RTCCINT bit in the GPTMICR register.
8.4.3
16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4.
3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register
(GPTMTnPR).
5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).
6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.
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8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
In One-Shot mode, the timer stops counting after step 8 on page 253. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
8.4.4
16-Bit Input Edge Count Mode
A timer is configured to Input Edge Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.
7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
In Input Edge Count Mode, the timer stops after the desired number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 253
through step 9 on page 253.
8.4.5
16-Bit Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
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8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timern (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
8.4.6
16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
8.5
Register Map
Table 8-5 on page 254 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:
■ Timer0: 0x4003.0000
■ Timer1: 0x4003.1000
Note that the Timer module clock must be enabled before the registers can be programmed (see
page 173). There must be a delay of 3 system clocks after the Timer module clock is enabled before
any Timer module registers are accessed.
Table 8-5. Timers Register Map
See
page
Offset
Name
Type
Reset
Description
0x000
0x004
0x008
GPTMCFG
GPTMTAMR
GPTMTBMR
R/W
R/W
R/W
0x0000.0000
0x0000.0000
0x0000.0000
GPTM Configuration
GPTM TimerA Mode
GPTM TimerB Mode
256
257
259
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Table 8-5. Timers Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0x00C
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
GPTMCTL
R/W
R/W
RO
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0xFFFF.FFFF
0x0000.FFFF
0xFFFF.FFFF
0x0000.FFFF
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0xFFFF.FFFF
0x0000.FFFF
GPTM Control
261
264
266
267
268
270
271
272
273
274
275
276
277
278
279
GPTMIMR
GPTM Interrupt Mask
GPTM Raw Interrupt Status
GPTM Masked Interrupt Status
GPTM Interrupt Clear
GPTM TimerA Interval Load
GPTM TimerB Interval Load
GPTM TimerA Match
GPTMRIS
GPTMMIS
RO
GPTMICR
W1C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
GPTMTAILR
GPTMTBILR
GPTMTAMATCHR
GPTMTBMATCHR
GPTMTAPR
GPTMTBPR
GPTMTAPMR
GPTMTBPMR
GPTMTAR
GPTM TimerB Match
GPTM TimerA Prescale
GPTM TimerB Prescale
GPTM TimerA Prescale Match
GPTM TimerB Prescale Match
GPTM TimerA
GPTMTBR
RO
GPTM TimerB
8.6
Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by address
offset.
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Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 16-bit mode.
GPTM Configuration (GPTMCFG)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
GPTMCFG
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:3
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0
GPTMCFG
R/W
0x0
GPTM Configuration
The GPTMCFG values are defined as follows:
Value Description
0x0 32-bit timer configuration.
0x1 32-bit real-time clock (RTC) counter configuration.
0x2 Reserved
0x3 Reserved
0x4-0x7 16-bit timer configuration, function is controlled by bits 1:0 of
GPTMTAMR and GPTMTBMR.
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Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
GPTM TimerA Mode (GPTMTAMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TAAMS TACMR
TAMR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:4
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TAAMS
R/W
0
GPTM TimerA Alternate Mode Select
The TAAMS values are defined as follows:
Value Description
0
1
Capture mode is enabled.
PWM mode is enabled.
Note:
To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
2
TACMR
R/W
0
GPTM TimerA Capture Mode
The TACMR values are defined as follows:
Value Description
0
1
Edge-Count mode
Edge-Time mode
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Bit/Field
1:0
Name
TAMR
Type
R/W
Reset
0x0
Description
GPTM TimerA Mode
The TAMR values are defined as follows:
Value Description
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer modes for
TimerA.
In 32-bit timer configuration, this register controls the mode and the
contents of GPTMTBMR are ignored.
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Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.
GPTM TimerB Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TBAMS TBCMR
TBMR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:4
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TBAMS
R/W
0
GPTM TimerB Alternate Mode Select
The TBAMS values are defined as follows:
Value Description
0
1
Capture mode is enabled.
PWM mode is enabled.
Note:
To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.
2
TBCMR
R/W
0
GPTM TimerB Capture Mode
The TBCMR values are defined as follows:
Value Description
0
1
Edge-Count mode
Edge-Time mode
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Bit/Field
1:0
Name
TBMR
Type
R/W
Reset
0x0
Description
GPTM TimerB Mode
The TBMR values are defined as follows:
Value Description
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer modes
for TimerB.
In 32-bit timer configuration, this register’s contents are ignored and
GPTMTAMR is used.
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Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
reserved
reserved
TBPWML
reserved
TBEVENT
TBSTALL TBEN
TAPWML
RTCEN
TAEVENT
TASTALL
TAEN
Type
Reset
RO
0
R/W
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:15
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
TBPWML
R/W
0
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
Value Description
0
1
Output is unaffected.
Output is inverted.
13:12
11:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
TBEVENT
R/W
0x0
GPTM TimerB Event Mode
The TBEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
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Bit/Field
9
Name
TBSTALL
Type
R/W
Reset
0
Description
GPTM Timer B Stall Enable
The TBSTALL values are defined as follows:
Value Description
0
Timer B continues counting while the processor is halted by the
debugger.
1
Timer B freezes counting while the processor is halted by the
debugger.
If the processor is executing normally, the TBSTALL bit is ignored.
8
TBEN
R/W
0
GPTM TimerB Enable
The TBEN values are defined as follows:
Value Description
0
1
TimerB is disabled.
TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
7
6
reserved
TAPWML
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
GPTM TimerA PWM Output Level
The TAPWML values are defined as follows:
Value Description
0
1
Output is unaffected.
Output is inverted.
5
4
reserved
RTCEN
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
GPTM RTC Enable
The RTCEN values are defined as follows:
Value Description
0
1
RTC counting is disabled.
RTC counting is enabled.
3:2
TAEVENT
R/W
0x0
GPTM TimerA Event Mode
The TAEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
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Bit/Field
1
Name
Type
R/W
Reset
0
Description
TASTALL
GPTM Timer A Stall Enable
The TASTALL values are defined as follows:
Value Description
0
Timer A continues counting while the processor is halted by the
debugger.
1
Timer A freezes counting while the processor is halted by the
debugger.
If the processor is executing normally, the TASTALL bit is ignored.
0
TAEN
R/W
0
GPTM TimerA Enable
The TAEN values are defined as follows:
Value Description
0
1
TimerA is disabled.
TimerA is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
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Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x018
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CBEIM
CBMIM TBTOIM
reserved
RTCIM
CAEIM
CAMIM TATOIM
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:11
Name
Type
Reset
0x00
Description
reserved
RO
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
CBEIM
R/W
0
0
0
0
GPTM CaptureB Event Interrupt Mask
The CBEIM values are defined as follows:
Value Description
0
1
Interrupt is disabled.
Interrupt is enabled.
9
CBMIM
TBTOIM
reserved
R/W
R/W
RO
GPTM CaptureB Match Interrupt Mask
The CBMIM values are defined as follows:
Value Description
0
1
Interrupt is disabled.
Interrupt is enabled.
8
GPTM TimerB Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
Value Description
0
1
Interrupt is disabled.
Interrupt is enabled.
7:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
3
Name
Type
R/W
Reset
0
Description
RTCIM
GPTM RTC Interrupt Mask
The RTCIM values are defined as follows:
Value Description
0
1
Interrupt is disabled.
Interrupt is enabled.
2
1
0
CAEIM
CAMIM
TATOIM
R/W
R/W
R/W
0
0
0
GPTM CaptureA Event Interrupt Mask
The CAEIM values are defined as follows:
Value Description
0
1
Interrupt is disabled.
Interrupt is enabled.
GPTM CaptureA Match Interrupt Mask
The CAMIM values are defined as follows:
Value Description
0
1
Interrupt is disabled.
Interrupt is enabled.
GPTM TimerA Time-Out Interrupt Mask
The TATOIM values are defined as follows:
Value Description
0
1
Interrupt is disabled.
Interrupt is enabled.
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Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CBERIS CBMRIS TBTORIS
reserved
RTCRIS CAERIS CAMRIS TATORIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:11
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
9
CBERIS
CBMRIS
TBTORIS
reserved
RO
RO
RO
RO
0
0
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
8
0
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
7:4
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
2
1
0
RTCRIS
CAERIS
CAMRIS
TATORIS
RO
RO
RO
RO
0
0
0
0
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
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Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CBEMIS CBMMIS TBTOMIS
reserved
RTCMIS CAEMIS CAMMIS TATOMIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:11
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
9
CBEMIS
CBMMIS
TBTOMIS
reserved
RO
RO
RO
RO
0
0
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
8
0
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
7:4
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
2
1
0
RTCMIS
CAEMIS
CAMMIS
TATOMIS
RO
RO
RO
RO
0
0
0
0
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
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Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x024
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TBTOCINT
TATOCINT
RTCCINT CAECINT CAMCINT
reserved
CBECINT CBMCINT
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
W1C
0
W1C
0
W1C
0
RO
0
RO
0
RO
0
RO
0
W1C
0
W1C
0
W1C
0
W1C
0
Bit/Field
31:11
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
CBECINT
W1C
W1C
W1C
RO
0
GPTM CaptureB Event Interrupt Clear
The CBECINT values are defined as follows:
Value Description
0
1
The interrupt is unaffected.
The interrupt is cleared.
9
CBMCINT
TBTOCINT
reserved
0
GPTM CaptureB Match Interrupt Clear
The CBMCINT values are defined as follows:
Value Description
0
1
The interrupt is unaffected.
The interrupt is cleared.
8
0
GPTM TimerB Time-Out Interrupt Clear
The TBTOCINT values are defined as follows:
Value Description
0
1
The interrupt is unaffected.
The interrupt is cleared.
7:4
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
3
Name
Type
W1C
Reset
0
Description
RTCCINT
GPTM RTC Interrupt Clear
The RTCCINT values are defined as follows:
Value Description
0
1
The interrupt is unaffected.
The interrupt is cleared.
2
1
0
CAECINT
CAMCINT
TATOCINT
W1C
W1C
W1C
0
0
0
GPTM CaptureA Event Interrupt Clear
The CAECINT values are defined as follows:
Value Description
0
1
The interrupt is unaffected.
The interrupt is cleared.
GPTM CaptureA Match Interrupt Clear
The CAMCINT values are defined as follows:
Value Description
0
1
The interrupt is unaffected.
The interrupt is cleared.
GPTM TimerA Time-Out Interrupt Clear
The TATOCINT values are defined as follows:
Value Description
0
1
The interrupt is unaffected.
The interrupt is cleared.
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Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028
This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
GPTM TimerA Interval Load (GPTMTAILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x028
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TAILRH
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TAILRL
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
31:16
Name
Type
R/W
Reset
Description
GPTM TimerA Interval Load Register High
TAILRH
TAILRL
0xFFFF
When configured for 32-bit mode via the GPTMCFG register, the GPTM
TimerB Interval Load (GPTMTBILR) register loads this value on a
write. A read returns the current value of GPTMTBILR.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBILR.
15:0
R/W
0xFFFF
GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the counter for
TimerA. A read returns the current value of GPTMTAILR.
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Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C
This register is used to load the starting count value into TimerB. When the GPTM is configured to
a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.
GPTM TimerB Interval Load (GPTMTBILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TBILRL
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
31:16
Name
Type
RO
Reset
Description
reserved
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TBILRL
R/W
0xFFFF
GPTM TimerB Interval Load Register
When the GPTM is not configured as a 32-bit timer, a write to this field
updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.
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General-Purpose Timers
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerA Match (GPTMTAMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x030
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TAMRH
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TAMRL
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
31:16
Name
Type
R/W
Reset
Description
GPTM TimerA Match Register High
TAMRH
TAMRL
0xFFFF
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the upper half of
GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBMATCHR.
15:0
R/W
0xFFFF
GPTM TimerA Match Register Low
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the lower half of
GPTMTAR, to determine match events.
When configured for PWM mode, this value along with GPTMTAILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTAILR
minus this value.
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Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 16-bit PWM and Input Edge Count modes.
GPTM TimerB Match (GPTMTBMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x034
Type R/W, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TBMRL
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
31:16
Name
Type
RO
Reset
Description
reserved
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TBMRL
R/W
0xFFFF
GPTM TimerB Match Register Low
When configured for PWM mode, this value along with GPTMTBILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTBILR
minus this value.
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Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerA Prescale (GPTMTAPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TAPSR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
TAPSR
R/W
0x00
GPTM TimerA Prescale
The register loads this value on a write. A read returns the current value
of the register.
Refer to Table 8-4 on page 248 for more details and an example.
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Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerB Prescale (GPTMTBPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x03C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TBPSR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
TBPSR
R/W
0x00
GPTM TimerB Prescale
The register loads this value on a write. A read returns the current value
of this register.
Refer to Table 8-4 on page 248 for more details and an example.
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Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040
This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerA Prescale Match (GPTMTAPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x040
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TAPSMR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
TAPSMR
R/W
0x00
GPTM TimerA Prescale Match
This value is used alongside GPTMTAMATCHR to detect timer match
events while using a prescaler.
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Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044
This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerB Prescale Match (GPTMTBPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x044
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TBPSMR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
TBPSMR
R/W
0x00
GPTM TimerB Prescale Match
This value is used alongside GPTMTBMATCHR to detect timer match
events while using a prescaler.
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Register 17: GPTM TimerA (GPTMTAR), offset 0x048
This register shows the current value of the TimerA counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the number of edges that have occurred.
GPTM TimerA (GPTMTAR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x048
Type RO, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TARH
TARL
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
31:16
Name
Type
RO
Reset
Description
GPTM TimerA Register High
TARH
0xFFFF
If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the
GPTMCFG is in a 16-bit mode, this is read as zero.
15:0
TARL
RO
0xFFFF
GPTM TimerA Register Low
A read returns the current value of the GPTM TimerA Count Register,
except in Input Edge-Count mode, when it returns the number of edges
that have occurred.
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Register 18: GPTM TimerB (GPTMTBR), offset 0x04C
This register shows the current value of the TimerB counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the number of edges that have occurred.
GPTM TimerB (GPTMTBR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x04C
Type RO, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TBRL
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
31:16
Name
Type
RO
Reset
Description
reserved
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TBRL
RO
0xFFFF
GPTM TimerB
A read returns the current value of the GPTM TimerB Count Register,
except in Input Edge-Count mode, when it returns the number of edges
that have occurred.
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Watchdog Timer
9
Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
The Stellaris® Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the controller asserts the CPU Halt flag during debug
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
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9.1
Block Diagram
Figure 9-1. WDT Module Block Diagram
WDTLOAD
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
Interrupt
WDTRIS
WDTMIS
32-Bit Down
Counter
0x00000000
WDTLOCK
WDTTEST
System Clock
Comparator
WDTVALUE
Identification Registers
WDTPCellID0 WDTPeriphID0 WDTPeriphID4
WDTPCellID1 WDTPeriphID1 WDTPeriphID5
WDTPCellID2 WDTPeriphID2 WDTPeriphID6
WDTPCellID3 WDTPeriphID3 WDTPeriphID7
9.2
Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the
Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written,
which prevents the timer configuration from being inadvertently altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
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Watchdog Timer
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
9.3
Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.
9.4
Register Map
Table 9-1 on page 282 lists the Watchdog registers. The offset listed is a hexadecimal increment to
the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.
Table 9-1. Watchdog Timer Register Map
See
page
Offset
Name
Type
Reset
Description
0x000
0x004
0x008
0x00C
0x010
0x014
0x418
0xC00
0xFD0
0xFD4
0xFD8
0xFDC
0xFE0
0xFE4
0xFE8
WDTLOAD
R/W
RO
R/W
WO
RO
RO
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
0xFFFF.FFFF
0xFFFF.FFFF
0x0000.0000
-
Watchdog Load
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
WDTVALUE
WDTCTL
Watchdog Value
Watchdog Control
WDTICR
Watchdog Interrupt Clear
WDTRIS
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0005
0x0000.0018
0x0000.0018
Watchdog Raw Interrupt Status
Watchdog Masked Interrupt Status
Watchdog Test
WDTMIS
WDTTEST
WDTLOCK
Watchdog Lock
WDTPeriphID4
WDTPeriphID5
WDTPeriphID6
WDTPeriphID7
WDTPeriphID0
WDTPeriphID1
WDTPeriphID2
Watchdog Peripheral Identification 4
Watchdog Peripheral Identification 5
Watchdog Peripheral Identification 6
Watchdog Peripheral Identification 7
Watchdog Peripheral Identification 0
Watchdog Peripheral Identification 1
Watchdog Peripheral Identification 2
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Table 9-1. Watchdog Timer Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0xFEC
0xFF0
0xFF4
0xFF8
0xFFC
WDTPeriphID3
WDTPCellID0
WDTPCellID1
WDTPCellID2
WDTPCellID3
RO
RO
RO
RO
RO
0x0000.0001
0x0000.000D
0x0000.00F0
0x0000.0005
0x0000.00B1
Watchdog Peripheral Identification 3
Watchdog PrimeCell Identification 0
Watchdog PrimeCell Identification 1
Watchdog PrimeCell Identification 2
Watchdog PrimeCell Identification 3
299
300
301
302
303
9.5
Register Descriptions
The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.
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Watchdog Timer
Register 1: Watchdog Load (WDTLOAD), offset 0x000
This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.
Watchdog Load (WDTLOAD)
Base 0x4000.0000
Offset 0x000
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WDTLoad
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WDTLoad
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
31:0
Name
WDTLoad
Type
R/W
Reset
Description
0xFFFF.FFFF Watchdog Load Value
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Stellaris® LM3S102 Microcontroller
Register 2: Watchdog Value (WDTVALUE), offset 0x004
This register contains the current count value of the timer.
Watchdog Value (WDTVALUE)
Base 0x4000.0000
Offset 0x004
Type RO, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WDTValue
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WDTValue
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
31:0
Name
WDTValue
Type
RO
Reset
Description
0xFFFF.FFFF Watchdog Value
Current value of the 32-bit down counter.
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Watchdog Timer
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
Watchdog Control (WDTCTL)
Base 0x4000.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RESEN
INTEN
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
Bit/Field
31:2
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
RESEN
R/W
0
Watchdog Reset Enable
The RESEN values are defined as follows:
Value Description
0
1
Disabled.
Enable the Watchdog module reset output.
0
INTEN
R/W
0
Watchdog Interrupt Enable
The INTEN values are defined as follows:
Value Description
0
Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
1
Interrupt event enabled. Once enabled, all writes are ignored.
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Stellaris® LM3S102 Microcontroller
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the Watchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is
indeterminate.
Watchdog Interrupt Clear (WDTICR)
Base 0x4000.0000
Offset 0x00C
Type WO, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WDTIntClr
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WDTIntClr
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
Bit/Field
31:0
Name
WDTIntClr
Type
WO
Reset
-
Description
Watchdog Interrupt Clear
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Watchdog Timer
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
Watchdog Raw Interrupt Status (WDTRIS)
Base 0x4000.0000
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WDTRIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
WDTRIS
RO
0
Watchdog Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of WDTINTR.
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Stellaris® LM3S102 Microcontroller
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
Watchdog Masked Interrupt Status (WDTMIS)
Base 0x4000.0000
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WDTMIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
WDTMIS
RO
0
Watchdog Masked Interrupt Status
Gives the masked interrupt state (after masking) of the WDTINTR
interrupt.
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Watchdog Timer
Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Watchdog Test (WDTTEST)
Base 0x4000.0000
Offset 0x418
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
STALL
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:9
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
STALL
R/W
RO
0
Watchdog Stall Enable
When set to 1, if the Stellaris microcontroller is stopped with a debugger,
the watchdog timer stops counting. Once the microcontroller is restarted,
the watchdog timer resumes counting.
7:0
reserved
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S102 Microcontroller
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00
Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value
written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns
0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)).
Watchdog Lock (WDTLOCK)
Base 0x4000.0000
Offset 0xC00
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WDTLock
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WDTLock
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:0
Name
WDTLock
Type
R/W
Reset
Description
Watchdog Lock
0x0000
A write of the value 0x1ACC.E551 unlocks the watchdog registers for
write access. A write of any other value reapplies the lock, preventing
any register updates.
A read of this register returns the following values:
Value
Description
0x0000.0001 Locked
0x0000.0000 Unlocked
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Watchdog Timer
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 4 (WDTPeriphID4)
Base 0x4000.0000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID4
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID4
RO
0x00
WDT Peripheral ID Register[7:0]
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Stellaris® LM3S102 Microcontroller
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset
0xFD4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 5 (WDTPeriphID5)
Base 0x4000.0000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID5
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID5
RO
0x00
WDT Peripheral ID Register[15:8]
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Watchdog Timer
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset
0xFD8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 6 (WDTPeriphID6)
Base 0x4000.0000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID6
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID6
RO
0x00
WDT Peripheral ID Register[23:16]
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Stellaris® LM3S102 Microcontroller
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset
0xFDC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 7 (WDTPeriphID7)
Base 0x4000.0000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID7
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID7
RO
0x00
WDT Peripheral ID Register[31:24]
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Watchdog Timer
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset
0xFE0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 0 (WDTPeriphID0)
Base 0x4000.0000
Offset 0xFE0
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID0
RO
0x05
Watchdog Peripheral ID Register[7:0]
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Stellaris® LM3S102 Microcontroller
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset
0xFE4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 1 (WDTPeriphID1)
Base 0x4000.0000
Offset 0xFE4
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID1
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID1
RO
0x18
Watchdog Peripheral ID Register[15:8]
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Watchdog Timer
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset
0xFE8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 2 (WDTPeriphID2)
Base 0x4000.0000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID2
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID2
RO
0x18
Watchdog Peripheral ID Register[23:16]
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Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset
0xFEC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 3 (WDTPeriphID3)
Base 0x4000.0000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID3
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID3
RO
0x01
Watchdog Peripheral ID Register[31:24]
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Watchdog Timer
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 0 (WDTPCellID0)
Base 0x4000.0000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID0
RO
0x0D
Watchdog PrimeCell ID Register[7:0]
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Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 1 (WDTPCellID1)
Base 0x4000.0000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID1
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID1
RO
0xF0
Watchdog PrimeCell ID Register[15:8]
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Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 2 (WDTPCellID2)
Base 0x4000.0000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID2
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
Watchdog PrimeCell ID Register[23:16]
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Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 3 (WDTPCellID3)
Base 0x4000.0000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID3
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
Watchdog PrimeCell ID Register[31:24]
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Universal Asynchronous Receivers/Transmitters (UARTs)
10
Universal Asynchronous Receivers/Transmitters
(UARTs)
The Stellaris® Universal Asynchronous Receiver/Transmitter (UART) has the following features:
■ Fully programmable 16C550-type UART
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
■ Programmable baud-rate generator allowing speeds up to 1.25 Mbps
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
–
–
–
5, 6, 7, or 8 data bits
Even, odd, stick, or no-parity bit generation/detection
1 or 2 stop bit generation
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10.1
Block Diagram
Figure 10-1. UART Module Block Diagram
System Clock
Interrupt
Interrupt Control
TxFIFO
16 x 8
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
.
.
.
Identification
Registers
UnTx
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
Transmitter
Baud Rate
Generator
UARTIBRD
UARTFBRD
UARTDR
UnRx
Receiver
Control/Status
RxFIFO
16 x 8
UARTRSR/ECR
UARTFR
.
.
.
UARTLCRH
UARTCTL
UARTILPR
10.2
Signal Description
Table 10-1 on page 305 and Table 10-2 on page 305 list the external signals of the UART module
and describe the function of each. The UART signals are alternate functions for some GPIO signals
and default to be GPIO signals at reset, with the exception of the U0Rx and U0Tx pins which default
to the UART function. The column in the table below titled "Pin Assignment" lists the possible GPIO
pin placements for these UART signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 222) should be set to choose the UART function. For more information
on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 202.
Table 10-1. UART Signals (28SOIC)
Pin Name
U0Rx
Pin Number
Pin Type
Buffer Typea Description
11
12
I
TTL
TTL
UART module 0 receive.
UART module 0 transmit.
U0Tx
O
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 10-2. UART Signals (48QFP)
Pin Name
Pin Number
Pin Type
Buffer Typea Description
TTL UART module 0 receive.
U0Rx
17
I
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Table 10-2. UART Signals (48QFP) (continued)
Pin Name
Pin Number
Pin Type
Buffer Typea Description
TTL UART module 0 transmit.
U0Tx
18
O
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
10.3
Functional Description
Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 322). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
10.3.1
Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 10-2 on page 306 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 10-2. UART Character Frame
UnTX
1
1-2
stop bits
LSB
MSB
5-8 data bits
0
n
Parity bit
if enabled
Start
10.3.2
Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 318) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 319). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.)
BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
where UARTSysClk is the system clock connected to the UART.
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
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UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error
detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 320), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■ UARTIBRD write, UARTFBRD write, and UARTLCRH write
■ UARTFBRD write, UARTIBRD write, and UARTLCRH write
■ UARTIBRD write and UARTLCRH write
■ UARTFBRD write and UARTLCRH write
10.3.3
Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 316) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 (described in “Transmit/Receive Logic” on page 306).
The start bit is valid and recognized if UnRx is still low on the eighth cycle of Baud16, otherwise it
is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle
of Baud16 (that is, one bit period later) according to the programmed length of the data characters.
The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the
UARTLCRH register.
Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When
a full word is received, the data is stored in the receive FIFO, with any error bits associated with
that word.
10.3.4
FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 312). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 320).
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Universal Asynchronous Receivers/Transmitters (UARTs)
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 316) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the
UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 324). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For
example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt
after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the
½ mark.
10.3.5
Interrupts
The UART can generate interrupts when the following conditions are observed:
■ Overrun Error
■ Break Error
■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 329).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 326) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 328).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 330).
The receive interrupt changes state when one of the following events occurs:
■ If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level, the RXRIS
bit is set. The receive interrupt is cleared by reading data from the receive FIFO until it becomes
less than the trigger level, or by clearing the interrupt by writing a 1 to the RXIC bit.
■ If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the
location, the RXRIS bit is set. The receive interrupt is cleared by performing a single read of the
receive FIFO, or by clearing the interrupt by writing a 1 to the RXIC bit.
The transmit interrupt changes state when one of the following events occurs:
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■ If the FIFOs are enabled and the transmit FIFO reaches the programmed trigger level, the TXRIS
bit is set. The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes
greater than the trigger level, or by clearing the interrupt by writing a 1 to the TXIC bit.
■ If the FIFOs are disabled (have a depth of one location) and there is no data present in the
transmitters single location, the TXRIS bit is set. It is cleared by performing a single write to the
transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit.
10.3.6
Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 322). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
10.4
Initialization and Configuration
To use the UART, the peripheral clock must be enabled by setting the UART0 bit in the RCGC1
register.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz and the desired UART configuration is:
■ 115200 baud rate
■ Data length of 8 bits
■ One stop bit
■ No parity
■ FIFOs disabled
■ No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the
equation described in “Baud-Rate Generation” on page 306, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 318) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 319) is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
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Universal Asynchronous Receivers/Transmitters (UARTs)
5. Enable the UART by setting the UARTEN bit in the UARTCTL register.
10.5
Register Map
Table 10-3 on page 310 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
Note that the UART module clock must be enabled before the registers can be programmed (see
page 173). There must be a delay of 3 system clocks after the UART module clock is enabled before
any UART module registers are accessed.
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 322)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 10-3. UART Register Map
See
page
Offset
Name
Type
Reset
Description
0x000
0x004
0x018
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0xFD0
0xFD4
0xFD8
0xFDC
0xFE0
0xFE4
0xFE8
0xFEC
0xFF0
UARTDR
R/W
R/W
RO
0x0000.0000
0x0000.0000
0x0000.0090
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0300
0x0000.0012
0x0000.0000
0x0000.000F
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0011
0x0000.0000
0x0000.0018
0x0000.0001
0x0000.000D
UART Data
312
314
316
318
319
320
322
324
326
328
329
330
332
333
334
335
336
337
338
339
340
UARTRSR/UARTECR
UARTFR
UART Receive Status/Error Clear
UART Flag
UARTIBRD
R/W
R/W
R/W
R/W
R/W
R/W
RO
UART Integer Baud-Rate Divisor
UART Fractional Baud-Rate Divisor
UART Line Control
UARTFBRD
UARTLCRH
UARTCTL
UART Control
UARTIFLS
UART Interrupt FIFO Level Select
UART Interrupt Mask
UARTIM
UARTRIS
UART Raw Interrupt Status
UART Masked Interrupt Status
UART Interrupt Clear
UARTMIS
RO
UARTICR
W1C
RO
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPCellID0
UART Peripheral Identification 4
UART Peripheral Identification 5
UART Peripheral Identification 6
UART Peripheral Identification 7
UART Peripheral Identification 0
UART Peripheral Identification 1
UART Peripheral Identification 2
UART Peripheral Identification 3
UART PrimeCell Identification 0
RO
RO
RO
RO
RO
RO
RO
RO
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Table 10-3. UART Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0xFF4
0xFF8
0xFFC
UARTPCellID1
UARTPCellID2
UARTPCellID3
RO
RO
RO
0x0000.00F0
0x0000.0005
0x0000.00B1
UART PrimeCell Identification 1
UART PrimeCell Identification 2
UART PrimeCell Identification 3
341
342
343
10.6
Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 1: UART Data (UARTDR), offset 0x000
Important: This register is read-sensitive. See the register description for details.
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OE
BE
PE
FE
DATA
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:12
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
OE
RO
0
UART Overrun Error
The OE values are defined as follows:
Value Description
0
1
There has been no data loss due to a FIFO overrun.
New data was received when the FIFO was full, resulting in
data loss.
10
BE
RO
0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the receive data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state) and the next valid start bit is received.
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Bit/Field
9
Name
PE
Type
RO
Reset
0
Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
8
FE
RO
0
0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
7:0
DATA
R/W
Data Transmitted or Received
When written, the data that is to be transmitted via the UART. When
read, the data that was received by the UART.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.
Reads
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OE
BE
PE
FE
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:4
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
OE
RO
0
UART Overrun Error
When this bit is set to 1, data is received and the FIFO is already full.
This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must now read the data in order to empty the FIFO.
2
BE
RO
0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the received data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
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Bit/Field
1
Name
PE
Type
RO
Reset
0
Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
0
FE
RO
0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
Writes
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DATA
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
Bit/Field
31:8
Name
Type
WO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DATA
WO
0
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
Offset 0x018
Type RO, reset 0x0000.0090
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TXFE
RXFF
TXFF
RXFE
BUSY
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
TXFE
RO
1
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding
register is empty.
If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO
is empty.
6
5
4
RXFF
TXFF
RXFE
RO
RO
RO
0
0
1
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is full.
If the FIFO is enabled, this bit is set when the receive FIFO is full.
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding register
is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is full.
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is empty.
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Bit/Field
3
Name
BUSY
Type
RO
Reset
0
Description
UART Busy
When this bit is 1, the UART is busy transmitting data. This bit remains
set until the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 306
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART0 base: 0x4000.C000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIVINT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:16
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DIVINT
R/W
0x0000
Integer Baud-Rate Divisor
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Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 306
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART0 base: 0x4000.C000
Offset 0x028
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DIVFRAC
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:6
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:0
DIVFRAC
R/W
0x000
Fractional Baud-Rate Divisor
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 6: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
Offset 0x02C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SPS
WLEN
FEN
STP2
EPS
PEN
BRK
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
SPS
R/W
R/W
0
0
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
6:5
WLEN
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
Value Description
0x3 8 bits
0x2 7 bits
0x1 6 bits
0x0 5 bits (default)
4
3
FEN
R/W
R/W
0
0
UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO
mode).
When cleared to 0, FIFOs are disabled (Character mode). The FIFOs
become 1-byte-deep holding registers.
STP2
UART Two Stop Bits Select
If this bit is set to 1, two stop bits are transmitted at the end of a frame.
The receive logic does not check for two stop bits being received.
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Bit/Field
2
Name
EPS
Type
R/W
Reset
0
Description
UART Even Parity Select
If this bit is set to 1, even parity generation and checking is performed
during transmission and reception, which checks for an even number
of 1s in data and parity bits.
When cleared to 0, then odd parity is performed, which checks for an
odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.
1
0
PEN
BRK
R/W
R/W
0
0
UART Parity Enable
If this bit is set to 1, parity checking and generation is enabled; otherwise,
parity is disabled and no parity bit is added to the data frame.
UART Send Break
If this bit is set to 1, a Low level is continually output on the UnTX output,
after completing transmission of the current character. For the proper
execution of the break command, the software must set this bit for at
least two frames (character periods). For normal use, this bit must be
cleared to 0.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 7: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are written.
If the UART is disabled during a transmit or receive operation, the current transaction is completed
prior to the UART stopping.
Note: The UARTCTL register should not be changed while the UART is enabled or else the results
are unpredictable. The following sequence is recommended for making changes to the
UARTCTL register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register (UARTLCRH).
4. Reprogram the control register.
5. Enable the UART.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
Offset 0x030
Type R/W, reset 0x0000.0300
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RXE
TXE
LBE
reserved
UARTEN
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
1
R/W
1
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:10
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9
8
RXE
R/W
R/W
1
1
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled. When
the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note:
To enable reception, the UARTEN bit must also be set.
TXE
UART Transmit Enable
If this bit is set to 1, the transmit section of the UART is enabled. When
the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note:
To enable transmission, the UARTEN bit must also be set.
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Bit/Field
7
Name
LBE
Type
R/W
Reset
0
Description
UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
6:1
0
reserved
UARTEN
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
UART Enable
If this bit is set to 1, the UART is enabled. When the UART is disabled
in the middle of transmission or reception, it completes the current
character before stopping.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
Offset 0x034
Type R/W, reset 0x0000.0012
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RXIFLSEL
TXIFLSEL
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
Bit/Field
31:6
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:3
RXIFLSEL
R/W
0x2
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
Value Description
0x0
0x1
0x2
0x3
0x4
RX FIFO ≥ ⅛ full
RX FIFO ≥ ¼ full
RX FIFO ≥ ½ full (default)
RX FIFO ≥ ¾ full
RX FIFO ≥ ⅞ full
0x5-0x7 Reserved
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Stellaris® LM3S102 Microcontroller
Bit/Field
2:0
Name
Type
R/W
Reset
0x2
Description
TXIFLSEL
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
Value
0x0
0x1
0x2
0x3
0x4
Description
TX FIFO ≤ ⅞ empty
TX FIFO ≤ ¾ empty
TX FIFO ≤ ½ empty (default)
TX FIFO ≤ ¼ empty
TX FIFO ≤ ⅛ empty
0x5-0x7 Reserved
July 24, 2012
325
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 9: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OEIM
BEIM
PEIM
FEIM
RTIM
TXIM
RXIM
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:11
Name
Type
Reset
0x00
Description
reserved
RO
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
9
OEIM
R/W
0
0
0
0
0
0
0
UART Overrun Error Interrupt Mask
On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller.
BEIM
PEIM
FEIM
RTIM
TXIM
RXIM
R/W
R/W
R/W
R/W
R/W
R/W
UART Break Error Interrupt Mask
On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller.
8
UART Parity Error Interrupt Mask
On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller.
7
UART Framing Error Interrupt Mask
On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller.
6
UART Receive Time-Out Interrupt Mask
On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller.
5
UART Transmit Interrupt Mask
On a read, the current mask for the TXIM interrupt is returned.
Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller.
4
UART Receive Interrupt Mask
On a read, the current mask for the RXIM interrupt is returned.
Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller.
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Stellaris® LM3S102 Microcontroller
Bit/Field
3:0
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
July 24, 2012
327
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
Offset 0x03C
Type RO, reset 0x0000.000F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OERIS
BERIS
PERIS
FERIS
RTRIS
TXRIS
RXRIS
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
Bit/Field
31:11
Name
Type
Reset
0x00
Description
reserved
RO
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
9
OERIS
BERIS
PERIS
FERIS
RTRIS
TXRIS
RXRIS
reserved
RO
RO
RO
RO
RO
RO
RO
RO
0
0
UART Overrun Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
UART Break Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
8
0
UART Parity Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
7
0
UART Framing Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
6
0
UART Receive Time-Out Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
5
0
UART Transmit Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
4
0
UART Receive Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
3:0
0xF
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S102 Microcontroller
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
Offset 0x040
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OEMIS
BEMIS
PEMIS
FEMIS
RTMIS
TXMIS
RXMIS
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:11
Name
Type
Reset
0x00
Description
reserved
RO
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
9
OEMIS
BEMIS
PEMIS
FEMIS
RTMIS
TXMIS
RXMIS
reserved
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
UART Overrun Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Break Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
8
UART Parity Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
7
UART Framing Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
6
UART Receive Time-Out Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
5
UART Transmit Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
4
UART Receive Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
3:0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 12: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
Offset 0x044
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OEIC
BEIC
PEIC
FEIC
RTIC
TXIC
RXIC
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:11
Name
Type
Reset
0x00
Description
reserved
RO
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OEIC
W1C
0
0
0
0
Overrun Error Interrupt Clear
The OEIC values are defined as follows:
Value Description
0
1
No effect on the interrupt.
Clears interrupt.
9
BEIC
PEIC
FEIC
W1C
W1C
W1C
Break Error Interrupt Clear
The BEIC values are defined as follows:
Value Description
0
1
No effect on the interrupt.
Clears interrupt.
8
Parity Error Interrupt Clear
The PEIC values are defined as follows:
Value Description
0
1
No effect on the interrupt.
Clears interrupt.
7
Framing Error Interrupt Clear
The FEIC values are defined as follows:
Value Description
0
1
No effect on the interrupt.
Clears interrupt.
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Stellaris® LM3S102 Microcontroller
Bit/Field
6
Name
RTIC
Type
W1C
Reset
0
Description
Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0
1
No effect on the interrupt.
Clears interrupt.
5
TXIC
W1C
W1C
RO
0
Transmit Interrupt Clear
The TXIC values are defined as follows:
Value Description
0
1
No effect on the interrupt.
Clears interrupt.
4
RXIC
0
Receive Interrupt Clear
The RXIC values are defined as follows:
Value Description
0
1
No effect on the interrupt.
Clears interrupt.
3:0
reserved
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
July 24, 2012
331
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART0 base: 0x4000.C000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID4
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID4
RO
0x0000
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
332
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Stellaris® LM3S102 Microcontroller
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID5
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID5
RO
0x0000
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
July 24, 2012
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
UART0 base: 0x4000.C000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID6
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID6
RO
0x0000
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
334
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Stellaris® LM3S102 Microcontroller
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
UART0 base: 0x4000.C000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID7
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID7
RO
0x0000
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
July 24, 2012
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Texas Instruments-Production Data
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
UART0 base: 0x4000.C000
Offset 0xFE0
Type RO, reset 0x0000.0011
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID0
RO
0x11
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
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Stellaris® LM3S102 Microcontroller
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
UART0 base: 0x4000.C000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID1
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID1
RO
0x00
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
July 24, 2012
337
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
UART0 base: 0x4000.C000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID2
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID2
RO
0x18
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
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Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
UART0 base: 0x4000.C000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID3
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID3
RO
0x01
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART0 base: 0x4000.C000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID0
RO
0x0D
UART PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
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Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 1 (UARTPCellID1)
UART0 base: 0x4000.C000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID1
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID1
RO
0xF0
UART PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 2 (UARTPCellID2)
UART0 base: 0x4000.C000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID2
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
UART PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
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Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 3 (UARTPCellID3)
UART0 base: 0x4000.C000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID3
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
UART PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
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Synchronous Serial Interface (SSI)
11
Synchronous Serial Interface (SSI)
The Stellaris® Synchronous Serial Interface (SSI) is a master or slave interface for synchronous
serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas
Instruments synchronous serial interfaces.
The Stellaris SSI module has the following features:
■ Master or slave operation
■ Programmable clock bit rate and prescale
■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
11.1
Block Diagram
Figure 11-1. SSI Module Block Diagram
Interrupt
Interrupt Control
SSIIM
TxFIFO
8 x16
SSIMIS
SSIRIS
SSIICR
Control/ Status
.
.
.
SSICR0
SSICR1
SSISR
SSITx
SSIRx
SSIClk
SSIFss
Transmit/
Receive
Logic
SSIDR
RxFIFO
8 x16
System Clock
.
.
.
Clock
Prescaler
Identification
Registers
SSICPSR
SSIPCellID0
SSIPCellID1
SSIPCellID2
0
SSIPeriphID4
SSIPeriphID 5
SSIPeriphID 6
SSIPeriphID
1
2
SSIPeriphID
SSIPeriphID
SSIPCellID3 SSIPeriphID 3 SSIPeriphID7
11.2
Signal Description
Table 11-1 on page 345 and Table 11-2 on page 345 list the external signals of the SSI module and
describe the function of each. The SSI signals are alternate functions for some GPIO signals and
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default to be GPIO signals at reset., with the exception of the SSI0Clk, SSI0Fss, SSI0Rx, and
SSI0Tx pins which default to the SSI function. The column in the table below titled "Pin Assignment"
lists the possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate
Function Select (GPIOAFSEL) register (page 222) should be set to choose the SSI function. For
more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 202.
Table 11-1. SSI Signals (28SOIC)
Pin Name
SSIClk
SSIFss
SSIRx
Pin Number
Pin Type
Buffer Typea Description
13
14
15
16
I/O
I/O
I
TTL
TTL
TTL
TTL
SSI clock.
SSI frame.
SSI receive.
SSI transmit.
SSITx
O
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 11-2. SSI Signals (48QFP)
Pin Name
SSIClk
SSIFss
SSIRx
Pin Number
Pin Type
Buffer Typea Description
19
20
21
22
I/O
I/O
I
TTL
TTL
TTL
TTL
SSI clock.
SSI frame.
SSI receive.
SSI transmit.
SSITx
O
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
11.3
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.
11.3.1
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 1.5 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 364). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 357).
The frequency of the output clock SSIClk is defined by:
SSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note: For master mode, the system clock must be at least two times faster than the SSIClk. For
slave mode, the system clock must be at least 12 times faster than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 452 to view SSI timing parameters.
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11.3.2
FIFO Operation
11.3.2.1 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 361), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit
FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit
FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was
enabled using the SSI bit in the RGCG1 register, then 0 is transmitted. Care should be taken to
ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt
or a µDMA request when the FIFO is empty.
11.3.2.2 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
11.3.3
Interrupts
The SSI can generate interrupts when the following conditions are observed:
■ Transmit FIFO service
■ Receive FIFO service
■ Receive FIFO time-out
■ Receive FIFO overrun
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
can only generate a single interrupt request to the controller at any given time. You can mask each
of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask
(SSIIM) register (see page 365). Setting the appropriate mask bit to 1 enables the interrupt.
Provision of the individual outputs, as well as a combined interrupt output, allows use of either a
global interrupt service routine, or modular device drivers to handle interrupts. The transmit and
receive dynamic dataflow interrupts have been separated from the status interrupts so that data
can be read or written in response to the FIFO trigger levels. The status of the individual interrupt
sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status
(SSIMIS) registers (see page 367 and page 368, respectively).
11.3.4
Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:
■ Texas Instruments synchronous serial
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■ Freescale SPI
■ MICROWIRE
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and
latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique, which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
11.3.4.1 Texas Instruments Synchronous Serial Frame Format
Figure 11-2 on page 347 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
Figure 11-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk
SSIFss
SSITx/SSIRx
MSB
LSB
4 to 16 bits
In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is
pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data
is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 11-3 on page 348 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
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Figure 11-3. TI Synchronous Serial Frame Format (Continuous Transfer)
SSIClk
SSIFss
SSITx/SSIRx
MSB
LSB
4 to 16 bits
11.3.4.2 Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition
before the first data capture edge. When the SPH phase control bit is Low, data is captured on the
first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition.
11.3.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 11-4 on page 348 and Figure 11-5 on page 349.
Figure 11-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx
SSITx
LSB
LSB
Q
MSB
4 to 16 bits
MSB
Note:
Q is undefined.
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Figure 11-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx
SSITx
LSB
LSB
MSB
MSB
LSB
LSB
MSB
4 to16 bits
MSB
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto
the SSIRx input line of the master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further half
SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
11.3.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
11-6 on page 350, which covers both single and continuous transfers.
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Figure 11-6. Freescale SPI Frame Format with SPO=0 and SPH=1
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
LSB
LSB
Q
4 to 16 bits
MSB
Note:
Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After
a further one half SSIClk period, both master and slave valid data is enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
11.3.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 11-7 on page 350 and Figure 11-8 on page 351.
Figure 11-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSIRx
SSITx
MSB
LSB
LSB
Q
4 to 16 bits
MSB
Note:
Q is undefined.
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Figure 11-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSITx/SSIRx
LSB
MSB
LSB
MSB
4 to 16 bits
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low, which causes slave data to be immediately
transferred onto the SSIRx line of the master. The master SSITx output pad is enabled.
One half period later, valid master data is transferred to the SSITx line. Now that both the master
and slave data have been set, the SSIClk master clock pin becomes Low after one further half
SSIClk period. This means that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
11.3.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
11-9 on page 352, which covers both single and continuous transfers.
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Figure 11-9. Freescale SPI Frame Format with SPO=1 and SPH=1
SSIClk
SSIFss
SSIRx
SSITx
MSB
MSB
Q
LSB
LSB
Q
4 to 16 bits
Note:
Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
11.3.4.7 MICROWIRE Frame Format
Figure 11-10 on page 352 shows the MICROWIRE frame format, again for a single frame. Figure
11-11 on page 353 shows the same format when back-to-back frames are transmitted.
Figure 11-10. MICROWIRE Frame Format (Single Frame)
SSIClk
SSIFss
SSITx
SSIRx
MSB
LSB
8-bit control
0
MSB
LSB
4 to 16 bits
output data
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MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex, using a master-slave message passing technique. Each serial transmission begins with
an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the
SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains
tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of
each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a
one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven
onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising
edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one
clock period after the last bit has been latched in the receive serial shifter, which causes the data
to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.
Figure 11-11. MICROWIRE Frame Format (Continuous Transfer)
SSIClk
SSIFss
SSITx
LSB
MSB
LSB
8-bit control
SSIRx
0
MSB
MSB
LSB
4 to 16 bits
output data
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
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Figure 11-12 on page 354 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 11-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
tSetup=(2*tSSIClk
)
tHold=tSSIClk
SSIClk
SSIFss
SSIRx
First RX data to be
sampled by SSI slave
11.4
Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
4. Write the SSICR0 register with the following configuration:
■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■ The data size (DSS)
5. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
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■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
11.5
Register Map
Table 11-3 on page 355 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
Note that the SSI module clock must be enabled before the registers can be programmed (see
page 173). There must be a delay of 3 system clocks after the SSI module clock is enabled before
any SSI module registers are accessed.
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 11-3. SSI Register Map
See
page
Offset
Name
Type
Reset
Description
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
SSICR0
SSICR1
SSIDR
R/W
R/W
R/W
RO
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0003
0x0000.0000
0x0000.0000
0x0000.0008
0x0000.0000
0x0000.0000
SSI Control 0
357
359
361
362
364
365
367
368
369
SSI Control 1
SSI Data
SSISR
SSI Status
SSICPSR
SSIIM
R/W
R/W
RO
SSI Clock Prescale
SSI Interrupt Mask
SSI Raw Interrupt Status
SSI Masked Interrupt Status
SSI Interrupt Clear
SSIRIS
SSIMIS
SSIICR
RO
W1C
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Table 11-3. SSI Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0xFD0
0xFD4
0xFD8
0xFDC
0xFE0
0xFE4
0xFE8
0xFEC
0xFF0
0xFF4
0xFF8
0xFFC
SSIPeriphID4
SSIPeriphID5
SSIPeriphID6
SSIPeriphID7
SSIPeriphID0
SSIPeriphID1
SSIPeriphID2
SSIPeriphID3
SSIPCellID0
SSIPCellID1
SSIPCellID2
SSIPCellID3
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0022
0x0000.0000
0x0000.0018
0x0000.0001
0x0000.000D
0x0000.00F0
0x0000.0005
0x0000.00B1
SSI Peripheral Identification 4
SSI Peripheral Identification 5
SSI Peripheral Identification 6
SSI Peripheral Identification 7
SSI Peripheral Identification 0
SSI Peripheral Identification 1
SSI Peripheral Identification 2
SSI Peripheral Identification 3
SSI PrimeCell Identification 0
SSI PrimeCell Identification 1
SSI PrimeCell Identification 2
SSI PrimeCell Identification 3
370
371
372
373
374
375
376
377
378
379
380
381
11.6
Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
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Register 1: SSI Control 0 (SSICR0), offset 0x000
SSICR0 is control register 0 and contains bit fields that control various functions within the SSI
module. Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCR
SPH
SPO
FRF
DSS
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:16
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8
SCR
R/W
0x0000
SSI Serial Clock Rate
The value SCR is used to generate the transmit and receive bit rate of
the SSI. The bit rate is:
BR=FSSIClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
7
SPH
R/W
0
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. It has the most impact on the first bit transmitted by
either allowing or not allowing a clock transition before the first data
capture edge.
When the SPH bit is 0, data is captured on the first clock edge transition.
If SPH is 1, data is captured on the second clock edge transition.
6
SPO
FRF
R/W
R/W
0
SSI Serial Clock Polarity
This bit is only applicable to the Freescale SPI Format.
When the SPO bit is 0, it produces a steady state Low value on the
SSIClk pin. If SPO is 1, a steady state High value is placed on the
SSIClk pin when data is not being transferred.
5:4
0x0
SSI Frame Format Select
The FRF values are defined as follows:
Value Frame Format
0x0 Freescale SPI Frame Format
0x1 Texas Instruments Synchronous Serial Frame Format
0x2 MICROWIRE Frame Format
0x3 Reserved
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Bit/Field
3:0
Name
DSS
Type
R/W
Reset
0x00
Description
SSI Data Size Select
The DSS values are defined as follows:
Value
Data Size
0x0-0x2 Reserved
0x3
0x4
0x5
0x6
0x7
0x8
4-bit data
5-bit data
6-bit data
7-bit data
8-bit data
9-bit data
0x9 10-bit data
0xA 11-bit data
0xB 12-bit data
0xC 13-bit data
0xD 14-bit data
0xE 15-bit data
0xF 16-bit data
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Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SOD
MS
SSE
LBM
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:4
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
SOD
R/W
0
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
The SOD values are defined as follows:
Value Description
0
1
SSI can drive SSITx output in Slave Output mode.
SSI must not drive the SSITx output in Slave mode.
2
MS
R/W
0
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
SSI is disabled (SSE=0).
The MS values are defined as follows:
Value Description
0
1
Device configured as a master.
Device configured as a slave.
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Bit/Field
1
Name
SSE
Type
R/W
Reset
0
Description
SSI Synchronous Serial Port Enable
Setting this bit enables SSI operation.
The SSE values are defined as follows:
Value Description
0
1
SSI operation disabled.
SSI operation enabled.
Note:
This bit must be set to 0 before any control registers
are reprogrammed.
0
LBM
R/W
0
SSI Loopback Mode
Setting this bit enables Loopback Test mode.
The LBM values are defined as follows:
Value Description
0
1
Normal serial port operation enabled.
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
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Register 3: SSI Data (SSIDR), offset 0x008
Important: This register is read-sensitive. See the register description for details.
SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO
(pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI
receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed
to by the current FIFO write pointer).
When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written
to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is
loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed
bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:16
Name
Type
RO
Reset
Description
reserved
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DATA
R/W
0x0000
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
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Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
Offset 0x00C
Type RO, reset 0x0000.0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
BSY
RFF
RNE
TNF
TFE
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
R0
1
Bit/Field
31:5
Name
Type
Reset
0x00
Description
reserved
RO
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
BSY
RO
0
SSI Busy Bit
The BSY values are defined as follows:
Value Description
0
1
SSI is idle.
SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
3
2
1
RFF
RNE
TNF
RO
RO
RO
0
0
1
SSI Receive FIFO Full
The RFF values are defined as follows:
Value Description
0
1
Receive FIFO is not full.
Receive FIFO is full.
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
Value Description
0
1
Receive FIFO is empty.
Receive FIFO is not empty.
SSI Transmit FIFO Not Full
The TNF values are defined as follows:
Value Description
0
1
Transmit FIFO is full.
Transmit FIFO is not full.
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Bit/Field
0
Name
TFE
Type
R0
Reset
1
Description
SSI Transmit FIFO Empty
The TFE values are defined as follows:
Value Description
0
1
Transmit FIFO is not empty.
Transmit FIFO is empty.
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Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CPSDVSR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CPSDVSR
R/W
0x00
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.
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Stellaris® LM3S102 Microcontroller
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TXIM
RXIM
RTIM
RORIM
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:4
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
2
1
TXIM
R/W
R/W
R/W
0
0
0
SSI Transmit FIFO Interrupt Mask
The TXIM values are defined as follows:
Value Description
0
1
TX FIFO half-empty or less condition interrupt is masked.
TX FIFO half-empty or less condition interrupt is not masked.
RXIM
SSI Receive FIFO Interrupt Mask
The RXIM values are defined as follows:
Value Description
0
1
RX FIFO half-full or more condition interrupt is masked.
RX FIFO half-full or more condition interrupt is not masked.
RTIM
SSI Receive Time-Out Interrupt Mask
The RTIM values are defined as follows:
Value Description
0
1
RX FIFO time-out interrupt is masked.
RX FIFO time-out interrupt is not masked.
July 24, 2012
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Synchronous Serial Interface (SSI)
Bit/Field
0
Name
Type
R/W
Reset
0
Description
RORIM
SSI Receive Overrun Interrupt Mask
The RORIM values are defined as follows:
Value Description
0
1
RX FIFO overrun interrupt is masked.
RX FIFO overrun interrupt is not masked.
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Stellaris® LM3S102 Microcontroller
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
Offset 0x018
Type RO, reset 0x0000.0008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TXRIS
RXRIS
RTRIS RORRIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
Bit/Field
31:4
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
2
1
0
TXRIS
RXRIS
RTRIS
RO
RO
RO
RO
1
0
0
0
SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half empty or less, when set.
SSI Receive FIFO Raw Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
SSI Receive Time-Out Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
RORRIS
SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
July 24, 2012
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Synchronous Serial Interface (SSI)
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TXMIS
RXMIS
RTMIS RORMIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:4
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
2
1
0
TXMIS
RXMIS
RTMIS
RO
RO
RO
RO
0
0
0
0
SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half empty or less, when set.
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
RORMIS
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
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Stellaris® LM3S102 Microcontroller
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
Offset 0x020
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RTIC
RORIC
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
W1C
0
W1C
0
Bit/Field
31:2
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
RTIC
W1C
0
SSI Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0
1
No effect on interrupt.
Clears interrupt.
0
RORIC
W1C
0
SSI Receive Overrun Interrupt Clear
The RORIC values are defined as follows:
Value Description
0
1
No effect on interrupt.
Clears interrupt.
July 24, 2012
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Synchronous Serial Interface (SSI)
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID4
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID4
RO
0x00
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
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Texas Instruments-Production Data
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Stellaris® LM3S102 Microcontroller
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 5 (SSIPeriphID5)
SSI0 base: 0x4000.8000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID5
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID5
RO
0x00
SSI Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
July 24, 2012
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Synchronous Serial Interface (SSI)
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 6 (SSIPeriphID6)
SSI0 base: 0x4000.8000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID6
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID6
RO
0x00
SSI Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
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Stellaris® LM3S102 Microcontroller
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 7 (SSIPeriphID7)
SSI0 base: 0x4000.8000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID7
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID7
RO
0x00
SSI Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
July 24, 2012
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Synchronous Serial Interface (SSI)
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 0 (SSIPeriphID0)
SSI0 base: 0x4000.8000
Offset 0xFE0
Type RO, reset 0x0000.0022
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
1
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID0
RO
0x22
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
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Stellaris® LM3S102 Microcontroller
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 1 (SSIPeriphID1)
SSI0 base: 0x4000.8000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID1
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID1
RO
0x00
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
July 24, 2012
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Synchronous Serial Interface (SSI)
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 2 (SSIPeriphID2)
SSI0 base: 0x4000.8000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID2
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID2
RO
0x18
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
376
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Stellaris® LM3S102 Microcontroller
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 3 (SSIPeriphID3)
SSI0 base: 0x4000.8000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PID3
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID3
RO
0x01
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
July 24, 2012
377
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Synchronous Serial Interface (SSI)
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID0
RO
0x0D
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
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Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 1 (SSIPCellID1)
SSI0 base: 0x4000.8000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID1
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID1
RO
0xF0
SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
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Synchronous Serial Interface (SSI)
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 2 (SSIPCellID2)
SSI0 base: 0x4000.8000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID2
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
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Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 3 (SSIPCellID3)
SSI0 base: 0x4000.8000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CID3
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
SSI PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
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Inter-Integrated Circuit (I2C) Interface
12
Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C
bus may also be used for system testing and diagnostic purposes in product development and
manufacture. The LM3S102 microcontroller includes one I2C module, providing the ability to interact
(both send and receive) with other I2C devices on the bus.
The Stellaris® I2C interface has the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
–
–
Supports both sending and receiving data as either a master or a slave
Supports simultaneous master and slave operation
■ Four I2C modes
–
–
–
–
Master transmit
Master receive
Slave transmit
Slave receive
■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
■ Master and slave interrupt generation
–
Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
–
Slave generates interrupts when data has been sent or requested by a master
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
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12.1
Block Diagram
Figure 12-1. I2C Block Diagram
I2CSCL
I2CSDA
I2C Control
I2C Master Core
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMMIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIM
I2CSCL
I2CSDA
Interrupt
I2C I/O Select
I2CSRIS
I2CSMIS
I2CSICR
I2CSCL
I2CSDA
I2C Slave Core
12.2
Signal Description
Table 12-1 on page 383 and Table 12-2 on page 383 list the external signals of the I2C interface and
describe the function of each. The I2C interface signals are alternate functions for some GPIO signals
and default to be GPIO signals at reset., with the exception of the I2C0SCL and I2CSDA pins which
default to the I2C function. The column in the table below titled "Pin Assignment" lists the possible
GPIO pin placements for the I2C signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 222) should be set to choose the I2C function. Note that the I2C pins
should be set to open drain using the GPIO Open Drain Select (GPIOODR) register. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 202.
Table 12-1. I2C Signals (28SOIC)
Pin Name
I2CSCL
I2CSDA
Pin Number
Pin Type
I/O
Buffer Typea Description
23
24
OD
OD
I2C clock.
I2C data.
I/O
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 12-2. I2C Signals (48QFP)
Pin Name
I2CSCL
I2CSDA
Pin Number
Pin Type
I/O
Buffer Typea Description
33
34
OD
OD
I2C clock.
I2C data.
I/O
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
12.3
Functional Description
I2C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I2C bus configuration is shown in Figure 12-2 on page 384.
See “Inter-Integrated Circuit (I2C) Interface” on page 453 for I2C timing diagrams.
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Figure 12-2. I2C Bus Configuration
R
R
PUP
PUP
SCL
SDA
2
I C Bus
I2CSCL I2CSDA
SCL
SDA
SCL
SDA
3rd Party Device
with I C Interface
3rd Party Device
with I C Interface
TM
2
2
Stellaris
12.3.1
I2C Bus Functional Overview
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 384) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
12.3.1.1 START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
12-3 on page 384.
Figure 12-3. START and STOP Conditions
SDA
SCL
SDA
SCL
START
STOP
condition
condition
12.3.1.2 Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 12-4 on page 385. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction
bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates
a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a
STOP condition. Various combinations of receive/send formats are then possible within a single
transfer.
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Figure 12-4. Complete Data Transfer with a 7-Bit Address
SDA
MSB
LSB
R/S
ACK
MSB
LSB
ACK
SCL
1
2
7
8
9
1
2
7
8
9
Slave address
Data
The first seven bits of the first byte make up the slave address (see Figure 12-5 on page 385). The
eighth bit determines the direction of the message. A zero in the R/S position of the first byte means
that the master will write (send) data to the selected slave, and a one in this position means that
the master will receive data from the slave.
Figure 12-5. R/S Bit in First Byte
MSB
LSB
R/S
Slave address
12.3.1.3 Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is Low (see Figure 12-6 on page 385).
Figure 12-6. Data Validity During Bit Transfer on the I2C Bus
SDA
SCL
Change
of data
allowed
Dataline
stable
12.3.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data
validity requirements described in “Data Validity” on page 385.
When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Since the master controls the number of bytes in the transfer, it signals the end
of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave
transmitter must then release SDA to allow the master to generate the STOP or a repeated START
condition.
12.3.1.5 Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
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arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of
the competing master devices to place a '1' (High) on SDA while another master transmits a '0'
(Low) will switch off its data output stage and retire until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
12.3.2
Available Speed Modes
The I2C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP.
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see
page 403).
The I2C clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
Table 12-3 on page 386 gives examples of timer period, system clock, and speed mode (Standard
or Fast).
Table 12-3. Examples of I2C Master Timer Period versus Speed Mode
System Clock
4 MHz
Timer Period
0x01
Standard Mode
100 Kbps
100 Kbps
89 Kbps
Timer Period
Fast Mode
-
-
6 MHz
0x02
-
-
12.5 MHz
16.7 MHz
20 MHz
0x06
0x01
0x02
0x02
312 Kbps
278 Kbps
333 Kbps
0x08
93 Kbps
0x09
100 Kbps
12.3.3
Interrupts
The I2C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master arbitration lost
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■ Master transaction error
■ Slave transaction received
■ Slave transaction requested
There is a separate interrupt signal for the I2C master and I2C slave modules. While both modules
can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
12.3.3.1 I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or
receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I2C
master interrupt, software must set the IM bit in the I2C Master Interrupt Mask (I2CMIMR) register.
When an interrupt condition is met, software must check the ERROR and ARBLST bits in the I2C
Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction
and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction
wasn't acknowledged by the slave. If an error is not detected and the master has not lost arbitration,
the application can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in
the I2C Master Interrupt Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Master Raw Interrupt Status (I2CMRIS) register.
12.3.3.2 I2C Slave Interrupts
The slave module can generate an interrupt when data has been received or requested. This interrupt
is enabled by writing a 1 to the DATAIM bit in the I2C Slave Interrupt Mask (I2CSIMR) register.
Software determines whether the module should write (transmit) or read (receive) data from the I2C
Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a 1 to the DATAIC bit
in the I2C Slave Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Slave Raw Interrupt Status (I2CSRIS) register.
12.3.4
12.3.5
Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This
is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In
loopback mode, the SDA and SCL signals from the master and slave modules are tied together.
Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and
slave mode.
12.3.5.1 I2C Master Command Sequences
The figures that follow show the command sequences available for the I2C master.
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Figure 12-7. Master Single SEND
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Write data to
I2CMDR
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write ---0-111 to
I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
NO
Error Service
ERROR bit=0?
YES
Idle
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Figure 12-8. Master Single RECEIVE
Idle
Sequence may be
omitted in a Single
Master system
Write Slave
Address to
I2CMSA
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write ---00111 to
I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
NO
Error Service
ERROR bit=0?
YES
Read data from
I2CMDR
Idle
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Figure 12-9. Master Burst SEND
Idle
Write Slave
Sequence
Read I2CMCS
Address to
may be
I2CMSA
omitted in a
Single Master
system
Write data to
NO
I2CMDR
BUSY bit=0?
YES
Read I2CMCS
NO
ERROR bit=0?
NO
BUSBSY bit=0?
YES
NO
Write data to
I2CMDR
ARBLST bit=1?
YES
Write ---0-011 to
I2CMCS
YES
Write ---0-100 to
I2CMCS
NO
Write ---0-001 to
I2CMCS
Index=n?
Error Service
YES
Write ---0-101 to
I2CMCS
Idle
Read I2CMCS
NO
BUSY bit=0?
YES
NO
Error Service
ERROR bit=0?
YES
Idle
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Figure 12-10. Master Burst RECEIVE
Idle
Sequence
may be
Write Slave
Address to
I2CMSA
omitted in a
Single Master
system
Read I2CMCS
BUSY bit=0?
Read I2CMCS
NO
YES
NO
BUSBSY bit=0?
NO
ERROR bit=0?
YES
NO
ARBLST bit=1?
Write ---01011 to
I2CMCS
Read data from
I2CMDR
YES
Write ---0-100 to
I2CMCS
NO
Write ---01001 to
I2CMCS
Index=m-1?
Error Service
Idle
YES
Write ---00101 to
I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
NO
ERROR bit=0?
YES
Read data from
I2CMDR
Error Service
Idle
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Figure 12-11. Master Burst RECEIVE after Burst SEND
Idle
Master operates in
Master Transmit mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---01011 to
I2CMCS
Repeated START
condition is generated
with changing data
direction
Master operates in
Master Receive mode
Idle
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Figure 12-12. Master Burst SEND after Burst RECEIVE
Idle
Master operates in
Master Receive mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---0-011 to
I2CMCS
Repeated START
condition is generated
with changing data
direction
Master operates in
Master Transmit mode
Idle
12.3.5.2 I2C Slave Command Sequences
Figure 12-13 on page 394 presents the command sequence available for the I2C slave.
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Figure 12-13. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1 to
I2CSCSR
Read I2CSCSR
NO
NO
TREQ bit=1?
RREQ bit=1?
FBR is
also valid
YES
YES
Write data to
I2CSDR
Read data from
I2CSDR
12.4
Initialization and Configuration
The following example shows how to configure the I2C module to send a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation.
4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020.
5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
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TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;
TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
6. Specify the slave address of the master and that the next operation will be a Send by writing
the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired
data.
8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x0000.0007 (STOP, START, RUN).
9. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
12.5
Register Map
Table 12-4 on page 395 lists the I2C registers. All addresses given are relative to the I2C base
addresses for the master and slave:
■ I2C 0: 0x4002.0000
Note that the I2C module clock must be enabled before the registers can be programmed (see
page 173). There must be a delay of 3 system clocks after the I2C module clock is enabled before
any I2C module registers are accessed.
The hw_i2c.h file in the StellarisWare® Driver Library uses a base address of 0x800 for the I2C slave
registers. Be aware when using registers with offsets between 0x800 and 0x818 that StellarisWare
uses an offset between 0x000 and 0x018 with the slave base address.
Table 12-4. Inter-Integrated Circuit (I2C) Interface Register Map
See
page
Offset
Name
Type
Reset
Description
I2C Master
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMMIS
I2CMICR
I2CMCR
R/W
R/W
R/W
R/W
R/W
RO
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0001
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
I2C Master Slave Address
I2C Master Control/Status
I2C Master Data
397
398
402
403
404
405
406
407
408
I2C Master Timer Period
I2C Master Interrupt Mask
I2C Master Raw Interrupt Status
I2C Master Masked Interrupt Status
I2C Master Interrupt Clear
I2C Master Configuration
RO
WO
R/W
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Inter-Integrated Circuit (I2C) Interface
Table 12-4. Inter-Integrated Circuit (I2C) Interface Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
I2C Slave
0x800
0x804
0x808
0x80C
0x810
0x814
0x818
I2CSOAR
I2CSCSR
I2CSDR
R/W
RO
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
I2C Slave Own Address
I2C Slave Control/Status
I2C Slave Data
410
411
413
414
415
416
417
R/W
R/W
RO
I2CSIMR
I2CSRIS
I2CSMIS
I2CSICR
I2C Slave Interrupt Mask
I2C Slave Raw Interrupt Status
I2C Slave Masked Interrupt Status
I2C Slave Interrupt Clear
RO
WO
12.6
Register Descriptions (I2C Master)
The remainder of this section lists and describes the I2C master registers, in numerical order by
address offset. See also “Register Descriptions (I2C Slave)” on page 409.
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Stellaris® LM3S102 Microcontroller
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Send (Low).
I2C Master Slave Address (I2CMSA)
I2C 0 base: 0x4002.0000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SA
R/S
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:1
0
SA
R/W
R/W
0
0
I2C Slave Address
This field specifies bits A6 through A0 of the slave address.
R/S
Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or Send
(Low).
Value Description
0
1
Send.
Receive.
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Inter-Integrated Circuit (I2C) Interface
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004
This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I2C bus
controller.
The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes
the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed
(or aborted due an error), the interrupt pin becomes active and the data may be read from the
I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set
normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after
each byte. This bit must be reset when the I2C bus controller requires no further data to be sent
from the slave transmitter.
Reads
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
BUSBSY
IDLE
ARBLST DATACK ADRACK ERROR
BUSY
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:7
Name
Type
Reset
0x00
Description
reserved
RO
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
BUSBSY
RO
0
Bus Busy
This bit specifies the state of the I2C bus. If set, the bus is busy;
otherwise, the bus is idle. The bit changes based on the START and
STOP conditions.
5
4
IDLE
RO
RO
0
0
I2C Idle
This bit specifies the I2C controller state. If set, the controller is idle;
otherwise the controller is not idle.
ARBLST
Arbitration Lost
This bit specifies the result of bus arbitration. If set, the controller lost
arbitration; otherwise, the controller won arbitration.
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Stellaris® LM3S102 Microcontroller
Bit/Field
3
Name
Type
RO
Reset
0
Description
DATACK
Acknowledge Data
This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data was
acknowledged.
2
1
ADRACK
ERROR
RO
RO
0
0
Acknowledge Address
This bit specifies the result of the last address operation. If set, the
transmitted address was not acknowledged; otherwise, the address was
acknowledged.
Error
This bit specifies the result of the last bus operation. If set, an error
occurred on the last operation; otherwise, no error was detected. The
error can be from the slave address not being acknowledged or the
transmit data not being acknowledged.
0
BUSY
RO
0
I2C Busy
This bit specifies the state of the controller. If set, the controller is busy;
otherwise, the controller is idle. When the BUSY bit is set, the other status
bits are not valid.
Writes
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
ACK
STOP
START
RUN
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
Bit/Field
31:4
Name
Type
WO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
2
1
ACK
WO
WO
WO
0
0
0
Data Acknowledge Enable
When set, causes received data byte to be acknowledged automatically
by the master. See field decoding in Table 12-5 on page 400.
STOP
Generate STOP
When set, causes the generation of the STOP condition. See field
decoding in Table 12-5 on page 400.
START
Generate START
When set, causes the generation of a START or repeated START
condition. See field decoding in Table 12-5 on page 400.
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Bit/Field
0
Name
RUN
Type
WO
Reset
0
Description
I2C Master Enable
When set, allows the master to send or receive data. See field decoding
in Table 12-5 on page 400.
Table 12-5. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3)
I2CMSA[0]
I2CMCS[3:0]
STOP START
Current
State
Description
R/S
ACK
RUN
0
Xa
0
1
1
START condition followed by SEND (master goes to the
Master Transmit state).
0
1
1
1
1
X
0
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
START condition followed by a SEND and STOP
condition (master remains in Idle state).
START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
Idle
START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
START condition followed by RECEIVE (master goes
to the Master Receive state).
Illegal.
All other combinations not listed are non-operations. NOP.
X
X
0
0
1
SEND operation (master remains in Master Transmit
state).
X
X
X
X
1
1
0
0
0
1
STOP condition (master goes to Idle state).
SEND followed by STOP condition (master goes to Idle
state).
0
0
1
X
X
0
0
1
0
1
1
1
1
1
1
Repeated START condition followed by a SEND (master
remains in Master Transmit state).
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
Master
Transmit
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
Repeated START condition followed by a SEND and
STOP condition (master goes to Idle state).
Repeated START condition followed by RECEIVE
(master goes to Master Receive state).
Illegal.
All other combinations not listed are non-operations. NOP.
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Stellaris® LM3S102 Microcontroller
Table 12-5. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) (continued)
I2CMSA[0]
I2CMCS[3:0]
STOP START
Current
State
Description
R/S
ACK
RUN
X
0
0
0
1
RECEIVE operation with negative ACK (master remains
in Master Receive state).
X
X
X
0
1
1
0
0
0
1
STOP condition (master goes to Idle state).b
RECEIVE followed by STOP condition (master goes to
Idle state).
X
1
0
0
1
RECEIVE operation (master remains in Master Receive
state).
X
1
1
0
1
0
0
1
1
1
Illegal.
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
Master
Receive
1
1
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
Repeated START condition followed by RECEIVE
(master remains in Master Receive state).
X
X
Repeated START condition followed by SEND (master
goes to Master Transmit state).
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
All other combinations not listed are non-operations. NOP.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
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Inter-Integrated Circuit (I2C) Interface
Register 3: I2C Master Data (I2CMDR), offset 0x008
Important: This register is read-sensitive. See the register description for details.
This register contains the data to be transmitted when in the Master Transmit state, and the data
received when in the Master Receive state.
I2C Master Data (I2CMDR)
I2C 0 base: 0x4002.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DATA
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DATA
R/W
0x00
Data Transferred
Data transferred during transaction.
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Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C
This register specifies the period of the SCL clock.
Caution – Take care not to set bit 7 when accessing this register as unpredictable behavior can occur.
I2C Master Timer Period (I2CMTPR)
I2C 0 base: 0x4002.0000
Offset 0x00C
Type R/W, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TPR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
Bit/Field
31:7
Name
Type
Reset
0x00
Description
reserved
RO
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:0
TPR
R/W
0x1
SCL Clock Period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 127).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
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Inter-Integrated Circuit (I2C) Interface
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C 0 base: 0x4002.0000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IM
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
IM
R/W
0
Interrupt Mask
This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.
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Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C 0 base: 0x4002.0000
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RIS
RO
0
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I2C
master block. If set, an interrupt is pending; otherwise, an interrupt is
not pending.
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Inter-Integrated Circuit (I2C) Interface
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C 0 base: 0x4002.0000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
MIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
MIS
RO
0
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I2C master
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
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Stellaris® LM3S102 Microcontroller
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C
This register clears the raw interrupt.
I2C Master Interrupt Clear (I2CMICR)
I2C 0 base: 0x4002.0000
Offset 0x01C
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IC
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
IC
WO
0
Interrupt Clear
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise, a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.
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Inter-Integrated Circuit (I2C) Interface
Register 9: I2C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C 0 base: 0x4002.0000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SFE
MFE
reserved
LPBK
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:6
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
4
SFE
R/W
R/W
0
0
I2C Slave Function Enable
This bit specifies whether the interface may operate in Slave mode. If
set, Slave mode is enabled; otherwise, Slave mode is disabled.
MFE
I2C Master Function Enable
This bit specifies whether the interface may operate in Master mode. If
set, Master mode is enabled; otherwise, Master mode is disabled and
the interface clock is disabled.
3:1
0
reserved
LPBK
RO
0x00
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
I2C Loopback
This bit specifies whether the interface is operating normally or in
Loopback mode. If set, the device is put in a test mode loopback
configuration; otherwise, the device operates normally.
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12.7
Register Descriptions (I2C Slave)
The remainder of this section lists and describes the I2C slave registers, in numerical order by
address offset. See also “Register Descriptions (I2C Master)” on page 396.
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Inter-Integrated Circuit (I2C) Interface
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800
This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus.
I2C Slave Own Address (I2CSOAR)
I2C 0 base: 0x4002.0000
Offset 0x800
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OAR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:7
Name
Type
Reset
0x00
Description
reserved
RO
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:0
OAR
R/W
0x00
I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
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Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First
Byte Received (FBR) bit is set only after the Stellaris device detects its own slave address and
receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates that
the Stellaris I2C device has received a data byte from an I2C master. Read one data byte from the
I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit
indicates that the Stellaris I2C device is addressed as a Slave Transmitter. Write one data byte into
the I2C Slave Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris I2C slave operation.
Reads
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
Offset 0x804
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FBR
TREQ
RREQ
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:3
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
1
FBR
RO
RO
0
0
First Byte Received
Indicates that the first byte following the slave’s own address is received.
This bit is only valid when the RREQ bit is set, and is automatically cleared
when data has been read from the I2CSDR register.
Note:
This bit is not used for slave transmit operations.
TREQ
RREQ
Transmit Request
This bit specifies the state of the I2C slave with regards to outstanding
transmit requests. If set, the I2C unit has been addressed as a slave
transmitter and uses clock stretching to delay the master until data has
been written to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
0
RO
0
Receive Request
This bit specifies the status of the I2C slave with regards to outstanding
receive requests. If set, the I2C unit has outstanding receive data from
the I2C master and uses clock stretching to delay the master until the
data has been read from the I2CSDR register. Otherwise, no receive
data is outstanding.
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Inter-Integrated Circuit (I2C) Interface
Writes
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
Offset 0x804
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DA
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DA
WO
0
Device Active
Value Description
0
1
Disables the I2C slave operation.
Enables the I2C slave operation.
Once this bit has been set, it should not be set again unless it has been
cleared by writing a 0 or by a reset, otherwise transfer failures may
occur.
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Register 12: I2C Slave Data (I2CSDR), offset 0x808
Important: This register is read-sensitive. See the register description for details.
This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
I2C 0 base: 0x4002.0000
Offset 0x808
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DATA
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:8
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DATA
R/W
0x0
Data for Transfer
This field contains the data for transfer during a slave receive or transmit
operation.
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Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C 0 base: 0x4002.0000
Offset 0x80C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DATAIM
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DATAIM
R/W
0
Data Interrupt Mask
This bit controls whether the raw interrupt for data received and data
requested is promoted to a controller interrupt. If set, the interrupt is not
masked and the interrupt is promoted; otherwise, the interrupt is masked.
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Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C 0 base: 0x4002.0000
Offset 0x810
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DATARIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DATARIS
RO
0
Data Raw Interrupt Status
This bit specifies the raw interrupt state for data received and data
requested (prior to masking) of the I2C slave block. If set, an interrupt
is pending; otherwise, an interrupt is not pending.
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Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C 0 base: 0x4002.0000
Offset 0x814
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DATAMIS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DATAMIS
RO
0
Data Masked Interrupt Status
This bit specifies the interrupt state for data received and data requested
(after masking) of the I2C slave block. If set, an interrupt was signaled;
otherwise, an interrupt has not been generated since the bit was last
cleared.
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Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818
This register clears the raw interrupt. A read of this register returns no meaningful data.
I2C Slave Interrupt Clear (I2CSICR)
I2C 0 base: 0x4002.0000
Offset 0x818
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DATAIC
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DATAIC
WO
0
Data Interrupt Clear
This bit controls the clearing of the raw interrupt for data received and
data requested. When set, it clears the DATARIS interrupt bit; otherwise,
it has no effect on the DATARIS bit value.
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Analog Comparator
13
Analog Comparator
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
Note: Not all comparators have the option to drive an output pin. See the Comparator Operating
Mode tables in “Functional Description” on page 419 for more information.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts to cause it to start
capturing a sample sequence.
The Stellaris® Analog Comparators module has the following features:
■ One integrated analog comparator
■ Configurable for output to drive an output pin or generate an interrupt
■ Compare external pin input to external pin input or to internal programmable voltage reference
■ Compare a test voltage against any one of these voltages
–
–
–
An individual external reference voltage
A shared single external reference voltage
A shared internal reference voltage
13.1
Block Diagram
Figure 13-1. Analog Comparator Module Block Diagram
C0-
-ve input
+ve input
Comparator 0
output
C0+
C0o
+ve input (alternate)
ACCTL0
ACSTAT0
interrupt
reference input
Interrupt Control
Voltage
Ref
ACRIS
ACMIS
ACINTEN
internal
bus
ACREFCTL
interrupt
13.2
Signal Description
Table 13-1 on page 419 and Table 13-2 on page 419 list the external signals of the Analog Comparators
and describe the function of each. The Analog Comparator output signal is an alternate functions
for a GPIO signal and default to be a GPIO signal at reset. The column in the table below titled "Pin
Assignment" lists the possible GPIO pin placements for the Analog Comparator signals. The AFSEL
bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 222) should be set to choose
the Analog Comparator function. The positive and negative input signal are configured by clearing
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the DEN bit in the GPIO Digital Enable (GPIODEN) register. For more information on configuring
GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 202.
Table 13-1. Analog Comparators Signals (28SOIC)
Pin Name
C0+
Pin Number
Pin Type
Buffer Typea Description
2
4
3
I
I
Analog
Analog
TTL
Analog comparator 0 positive input.
C0-
Analog comparator 0 negative input.
Analog comparator 0 output.
C0o
O
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 13-2. Analog Comparators Signals (48QFP)
Pin Name
C0+
Pin Number
Pin Type
Buffer Typea Description
42
44
43
I
I
Analog
Analog
TTL
Analog comparator 0 positive input.
Analog comparator 0 negative input.
Analog comparator 0 output.
C0-
C0o
O
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
13.3
Functional Description
Important: It is recommended that the Digital-Input enable (the GPIODEN bit in the GPIO module)
for the analog input pin be disabled to prevent excessive current draw from the I/O
pads.
The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.
VIN- < VIN+, VOUT = 1
VIN- > VIN+, VOUT = 0
As shown in Figure 13-2 on page 419, the input source for VIN- is an external input. In addition to
an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference.
Figure 13-2. Structure of Comparator Unit
-ve input
0
1
2
output
+ve input
CINV
IntGen
(alternate)
+ve input
reference input
ACCTL
ACSTAT
A comparator is configured through two status/control registers (ACCTL and ACSTAT ). The internal
reference is configured through one control register (ACREFCTL). Interrupt status and control is
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Analog Comparator
configured through three registers (ACMIS, ACRIS, and ACINTEN). The operating modes of the
comparators are shown in the Comparator Operating Mode tables.
Typically, the comparator output is used internally to generate controller interrupts. It may also be
used to drive an external pin.
Important: The ASRCP bits in the ACCTLn register must be set before using the analog
comparators. The proper pad configuration for the comparator input and output pins
are described in the Comparator Operating Mode tables.
Table 13-3. Comparator 0 Operating Modes
ACCTL0
ASRCP
00
Comparator 0
VIN-
C0-
C0-
C0-
C0-
VIN+
Output
Interrupt
C0+
C0+
C0o
C0o
C0o
C0o
yes
yes
yes
yes
01
10
Vref
11
reserved
13.3.1
Internal Reference Programming
The structure of the internal reference is shown in Figure 13-3 on page 420. This is controlled by a
single configuration register (ACREFCTL). Table 13-4 on page 420 shows the programming options
to develop specific internal reference values, to compare an external voltage against a particular
voltage generated internally.
Figure 13-3. Comparator Internal Reference Structure
8R
AVDD
8R
R
R
R
•••
EN
15
14
1
0
•••
Decoder
internal
reference
VREF
RNG
Table 13-4. Internal Reference Voltage and ACREFCTL Field Values
ACREFCTL Register
Output Reference Voltage Based on VREF Field Value
EN Bit Value
RNG Bit Value
EN=0
RNG=X
0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and
VREF=0 for the least noisy ground reference.
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Table 13-4. Internal Reference Voltage and ACREFCTL Field Values (continued)
ACREFCTL Register
Output Reference Voltage Based on VREF Field Value
EN Bit Value
RNG Bit Value
RNG=0
Total resistance in ladder is 31 R.
The range of internal reference in this mode is 0.85-2.448 V.
Total resistance in ladder is 23 R.
EN=1
RNG=1
The range of internal reference for this mode is 0-2.152 V.
13.4
Initialization and Configuration
The following example shows how to configure an analog comparator to read back its output value
from an internal register.
1. Enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the RCGC1 register
in the System Control module.
2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input.
3. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the
value 0x0000.030C.
4. Configure comparator 0 to use the internal voltage reference and to not invert the output by
writing the ACCTL0 register with the value of 0x0000.040C.
5. Delay for some time.
6. Read the comparator output value by reading the ACSTAT0 register’s OVAL value.
Change the level of the signal input on C0- to see the OVAL value change.
13.5
Register Map
Table 13-5 on page 422 lists the comparator registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Analog Comparator base address of 0x4003.C000.
Note that the analog comparator module clock must be enabled before the registers can be
programmed (see page 173). There must be a delay of 3 system clocks after the ADC module clock
is enabled before any ADC module registers are accessed.
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Analog Comparator
Table 13-5. Analog Comparators Register Map
See
page
Offset
Name
Type
Reset
Description
0x000
0x004
0x008
0x010
0x020
0x024
ACMIS
R/W1C
RO
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Analog Comparator Masked Interrupt Status
Analog Comparator Raw Interrupt Status
Analog Comparator Interrupt Enable
Analog Comparator Reference Voltage Control
Analog Comparator Status 0
423
424
425
426
427
428
ACRIS
ACINTEN
ACREFCTL
ACSTAT0
ACCTL0
R/W
R/W
RO
R/W
Analog Comparator Control 0
13.6
Register Descriptions
The remainder of this section lists and describes the Analog Comparator registers, in numerical
order by address offset.
422
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Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000
This register provides a summary of the interrupt status (masked) of the comparator.
Analog Comparator Masked Interrupt Status (ACMIS)
Base 0x4003.C000
Offset 0x000
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IN0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
IN0
R/W1C
0
Comparator 0 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
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Analog Comparator
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004
This register provides a summary of the interrupt status (raw) of the comparator.
Analog Comparator Raw Interrupt Status (ACRIS)
Base 0x4003.C000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IN0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
IN0
RO
0
Comparator 0 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
0.
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Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008
This register provides the interrupt enable for the comparator.
Analog Comparator Interrupt Enable (ACINTEN)
Base 0x4003.C000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IN0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Bit/Field
31:1
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
IN0
R/W
0
Comparator 0 Interrupt Enable
When set, enables the controller interrupt from the comparator 0 output.
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Analog Comparator
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset
0x010
This register specifies whether the resistor ladder is powered on as well as the range and tap.
Analog Comparator Reference Voltage Control (ACREFCTL)
Base 0x4003.C000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
EN
RNG
reserved
VREF
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
31:10
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9
EN
R/W
0
Resistor Ladder Enable
The EN bit specifies whether the resistor ladder is powered on. If 0, the
resistor ladder is unpowered. If 1, the resistor ladder is connected to
the analog VDD
.
This bit is reset to 0 so that the internal reference consumes the least
amount of power if not used and programmed.
8
RNG
R/W
0
Resistor Ladder Range
The RNG bit specifies the range of the resistor ladder. If 0, the resistor
ladder has a total resistance of 31 R. If 1, the resistor ladder has a total
resistance of 23 R.
7:4
3:0
reserved
VREF
RO
0x00
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
Resistor Ladder Voltage Ref
The VREF bit field specifies the resistor ladder tap that is passed through
an analog multiplexer. The voltage corresponding to the tap position is
the internal reference voltage available for comparison. See Table
13-4 on page 420 for some output reference voltage examples.
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Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020
This register specifies the current output value of the comparator.
Analog Comparator Status 0 (ACSTAT0)
Base 0x4003.C000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
reserved
OVAL
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
31:2
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
0
OVAL
RO
RO
0
0
Comparator Output Value
The OVAL bit specifies the current output value of the comparator.
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Analog Comparator
Register 6: Analog Comparator Control 0 (ACCTL0), offset 0x024
This register configures the comparator’s input and output.
Analog Comparator Control 0 (ACCTL0)
Base 0x4003.C000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
reserved
ASRCP
reserved
ISLVAL
ISEN
CINV
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
Bit/Field
31:11
Name
Type
RO
Reset
0x00
Description
reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:9
ASRCP
R/W
0x00
Analog Source Positive
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
Value Function
0x0 Pin value
0x1 Pin value of C0+
0x2 Internal voltage reference
0x3 Reserved
8:5
4
reserved
ISLVAL
RO
0
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
Interrupt Sense Level Value
The ISLVAL bit specifies the sense value of the input that generates
an interrupt if in Level Sense mode. If 0, an interrupt is generated if the
comparator output is Low. Otherwise, an interrupt is generated if the
comparator output is High.
3:2
ISEN
R/W
0x0
Interrupt Sense
The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:
Value Function
0x0 Level sense, see ISLVAL
0x1 Falling edge
0x2 Rising edge
0x3 Either edge
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Stellaris® LM3S102 Microcontroller
Bit/Field
1
Name
CINV
Type
R/W
Reset
0
Description
Comparator Output Invert
The CINV bit conditionally inverts the output of the comparator. If 0, the
output of the comparator is unchanged. If 1, the output of the comparator
is inverted prior to being processed by hardware.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Pin Diagram
14
Pin Diagram
The LM3S102 microcontroller pin diagrams are shown below.
Note: The 28-pin SOIC package is OBSOLETE. TI has discontinued production of this device.
Figure 14-1. 28-Pin SOIC Package Pin Diagram
430
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Stellaris® LM3S102 Microcontroller
Figure 14-2. 48-Pin QFP Package Pin Diagram
July 24, 2012
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Signal Tables
15
Signal Tables
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register. All digital inputs are Schmitt triggered.
■ Signals by Pin Number
■ Signals by Signal Name
■ Signals by Function, Except for GPIO
■ GPIO Pins and Alternate Functions
■ Connections for Unused Signals
Important: The 28-pin SOIC package is OBSOLETE. TI has discontinued production of this device.
15.1
28-Pin SOIC Package Pin Tables
15.1.1
Signals by Pin Number
Table 15-1. Signals by Pin Number
Pin Number
Pin Name
PB7
Pin Type
Buffer Typea Description
I/O
I
TTL
TTL
GPIO port B bit 7.
1
TRST
PB6
JTAG TRST.
I/O
I
TTL
GPIO port B bit 6.
2
C0+
Analog
TTL
Analog comparator 0 positive input.
Capture/Compare/PWM 1.
GPIO port B bit 5.
CCP1
PB5
I/O
I/O
O
I/O
I
TTL
3
4
C0o
TTL
Analog comparator 0 output.
GPIO port B bit 4.
PB4
TTL
C0-
Analog
TTL
Analog comparator 0 negative input.
System reset input.
5
6
RST
I
LDO
-
Power
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater.
7
8
9
VDD
GND
-
-
Power
Power
Analog
Analog
Positive supply for I/O and some logic.
Ground reference for logic and I/O pins.
OSC0
OSC1
I
Main oscillator crystal input or an external clock reference input.
O
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
10
11
PA0
U0Rx
PA1
I/O
I
TTL
TTL
TTL
TTL
TTL
TTL
GPIO port A bit 0.
UART module 0 receive.
GPIO port A bit 1.
UART module 0 transmit.
GPIO port A bit 2.
SSI clock.
I/O
O
12
13
U0Tx
PA2
I/O
I/O
SSIClk
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Stellaris® LM3S102 Microcontroller
Table 15-1. Signals by Pin Number (continued)
Pin Number
Pin Name
PA3
Pin Type
Buffer Typea Description
I/O
I/O
I/O
I
TTL
TTL
TTL
TTL
TTL
TTL
Power
Power
TTL
TTL
TTL
TTL
Power
Power
TTL
OD
GPIO port A bit 3.
14
SSIFss
PA4
SSI frame.
GPIO port A bit 4.
SSI receive.
15
16
SSIRx
PA5
I/O
O
GPIO port A bit 5.
SSI transmit.
SSITx
VDD
17
18
-
Positive supply for I/O and some logic.
Ground reference for logic and I/O pins.
GPIO port B bit 0.
GND
-
PB0
I/O
I/O
I/O
I
19
20
CCP0
PB1
Capture/Compare/PWM 0.
GPIO port B bit 1.
32KHz
GND
32-KHz input to the timer.
Ground reference for logic and I/O pins.
Positive supply for I/O and some logic.
GPIO port B bit 2.
21
22
-
VDD
-
PB2
I/O
I/O
I/O
I/O
I/O
O
23
24
I2CSCL
PB3
I2C clock.
TTL
OD
GPIO port B bit 3.
I2CSDA
PC3
I2C data.
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
GPIO port C bit 3.
25
26
27
SWO
JTAG TDO and SWO.
JTAG TDO and SWO.
GPIO port C bit 2.
TDO
O
PC2
I/O
I
TDI
JTAG TDI.
PC1
I/O
I/O
I/O
I/O
I
GPIO port C bit 1.
SWDIO
TMS
JTAG TMS and SWDIO.
JTAG TMS and SWDIO.
GPIO port C bit 0.
PC0
28
SWCLK
TCK
JTAG/SWD CLK.
I
JTAG/SWD CLK.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.1.2
Signals by Signal Name
Table 15-2. Signals by Signal Name
Pin Name
32KHz
C0+
Pin Number
Pin Type
Buffer Typea Description
20
2
I
I
TTL
Analog
Analog
TTL
32-KHz input to the timer.
Analog comparator 0 positive input.
Analog comparator 0 negative input.
Analog comparator 0 output.
Capture/Compare/PWM 0.
C0-
4
I
C0o
3
O
I/O
I/O
CCP0
CCP1
19
2
TTL
TTL
Capture/Compare/PWM 1.
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Signal Tables
Table 15-2. Signals by Signal Name (continued)
Pin Name
Pin Number
Pin Type
Buffer Typea Description
GND
8
-
Power
Ground reference for logic and I/O pins.
18
21
I2CSCL
I2CSDA
LDO
23
24
6
I/O
I/O
-
OD
OD
I2C clock.
I2C data.
Power
Low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 µF or
greater.
OSC0
OSC1
9
I
Analog
Analog
Main oscillator crystal input or an external clock reference
input.
10
O
Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
PA0
PA1
11
12
13
14
15
16
19
20
23
24
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
GPIO port A bit 0.
GPIO port A bit 1.
GPIO port A bit 2.
GPIO port A bit 3.
GPIO port A bit 4.
GPIO port A bit 5.
GPIO port B bit 0.
GPIO port B bit 1.
GPIO port B bit 2.
GPIO port B bit 3.
GPIO port B bit 4.
GPIO port B bit 5.
GPIO port B bit 6.
GPIO port B bit 7.
GPIO port C bit 0.
GPIO port C bit 1.
GPIO port C bit 2.
GPIO port C bit 3.
System reset input.
SSI clock.
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
3
PB6
2
PB7
1
PC0
28
27
26
25
5
PC1
PC2
PC3
RST
SSIClk
SSIFss
SSIRx
SSITx
SWCLK
SWDIO
SWO
13
14
15
16
28
27
25
28
26
25
27
1
I/O
I/O
I
SSI frame.
SSI receive.
O
SSI transmit.
I
JTAG/SWD CLK.
JTAG TMS and SWDIO.
JTAG TDO and SWO.
JTAG/SWD CLK.
JTAG TDI.
I/O
O
TCK
I
TDI
I
TDO
O
JTAG TDO and SWO.
JTAG TMS and SWDIO.
JTAG TRST.
TMS
I/O
I
TRST
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Stellaris® LM3S102 Microcontroller
Table 15-2. Signals by Signal Name (continued)
Pin Name
U0Rx
Pin Number
Pin Type
Buffer Typea Description
11
12
I
O
-
TTL
TTL
UART module 0 receive.
UART module 0 transmit.
Positive supply for I/O and some logic.
U0Tx
VDD
7
Power
17
22
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.1.3
Signals by Function, Except for GPIO
Table 15-3. Signals by Function, Except for GPIO
Function
Pin Name
C0+
Pin Number
Pin Type
Buffer Typea
Description
Analog comparator 0 positive input.
Analog comparator 0 negative input.
Analog comparator 0 output.
32-KHz input to the timer.
Capture/Compare/PWM 0.
Capture/Compare/PWM 1.
I2C clock.
2
I
I
Analog
Analog
TTL
Analog Comparators C0-
4
C0o
3
O
I
32KHz
20
19
2
TTL
General-Purpose
Timers
CCP0
CCP1
I2CSCL
I2CSDA
SWCLK
SWDIO
SWO
I/O
I/O
I/O
I/O
I
TTL
TTL
23
24
28
27
25
28
26
25
27
1
OD
I2C
OD
I2C data.
TTL
JTAG/SWD CLK.
I/O
O
I
TTL
JTAG TMS and SWDIO.
JTAG TDO and SWO.
JTAG/SWD CLK.
TTL
TCK
TTL
JTAG/SWD/SWO
TDI
I
TTL
JTAG TDI.
TDO
O
I/O
I
TTL
JTAG TDO and SWO.
JTAG TMS and SWDIO.
JTAG TRST.
TMS
TTL
TRST
GND
TTL
8
-
Power
Ground reference for logic and I/O pins.
18
21
LDO
VDD
6
-
-
Power
Power
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater.
Power
7
Positive supply for I/O and some logic.
17
22
SSIClk
SSIFss
SSIRx
SSITx
OSC0
13
14
15
16
9
I/O
I/O
I
TTL
TTL
SSI clock.
SSI frame.
SSI receive.
SSI transmit.
SSI
TTL
O
I
TTL
Analog
Main oscillator crystal input or an external clock
reference input.
System Control &
Clocks
OSC1
RST
10
5
O
I
Analog
TTL
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
System reset input.
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Signal Tables
Table 15-3. Signals by Function, Except for GPIO (continued)
Function
Pin Name
U0Rx
U0Tx
Pin Number
Pin Type
Buffer Typea
Description
UART module 0 receive.
UART module 0 transmit.
11
12
I
TTL
UART
O
TTL
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.1.4
GPIO Pins and Alternate Functions
Table 15-4. GPIO Pins and Alternate Functions
IO
Pin Number
Multiplexed Function
Multiplexed Function
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
11
12
13
14
15
16
19
20
23
24
4
U0Rx
U0Tx
SSIClk
SSIFss
SSIRx
SSITx
CCP0
32KHz
I2CSCL
I2CSDA
C0-
3
C0o
2
C0+
CCP1
1
TRST
TCK
28
27
26
25
SWCLK
SWDIO
TMS
TDI
TDO
SWO
15.2
48-Pin Package Pin Table
15.2.1
Signals by Pin Number
Table 15-5. Signals by Pin Number
Pin Number
Pin Name
NC
Pin Type
Buffer Typea Description
1
2
3
4
5
-
-
-
-
I
-
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
System reset input.
NC
-
NC
-
-
NC
RST
TTL
Power
LDO
-
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater.
6
7
8
VDD
GND
-
-
Power
Power
Positive supply for I/O and some logic.
Ground reference for logic and I/O pins.
436
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Table 15-5. Signals by Pin Number (continued)
Pin Number
Pin Name
OSC0
Pin Type
Buffer Typea Description
9
I
Analog
Analog
Main oscillator crystal input or an external clock reference input.
OSC1
O
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
10
11
12
13
14
15
16
NC
NC
-
-
-
-
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
GPIO port A bit 0.
NC
-
-
NC
-
-
NC
-
-
NC
-
-
PA0
I/O
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Power
Power
-
17
18
19
20
21
22
U0Rx
PA1
UART module 0 receive.
I/O
O
I/O
I/O
I/O
I/O
I/O
I
GPIO port A bit 1.
U0Tx
PA2
UART module 0 transmit.
GPIO port A bit 2.
SSIClk
PA3
SSI clock.
GPIO port A bit 3.
SSIFss
PA4
SSI frame.
GPIO port A bit 4.
SSIRx
PA5
SSI receive.
I/O
O
-
GPIO port A bit 5.
SSITx
VDD
SSI transmit.
23
24
25
26
27
28
Positive supply for I/O and some logic.
Ground reference for logic and I/O pins.
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
GPIO port B bit 0.
GND
-
NC
-
NC
-
-
NC
-
-
NC
-
-
PB0
I/O
I/O
I/O
I
TTL
TTL
TTL
TTL
Power
Power
TTL
OD
TTL
OD
-
29
30
CCP0
PB1
Capture/Compare/PWM 0.
GPIO port B bit 1.
32KHz
GND
32-KHz input to the timer.
31
32
-
Ground reference for logic and I/O pins.
Positive supply for I/O and some logic.
GPIO port B bit 2.
VDD
-
PB2
I/O
I/O
I/O
I/O
-
33
34
I2CSCL
PB3
I2C clock.
GPIO port B bit 3.
I2CSDA
NC
I2C data.
35
36
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
GPIO port C bit 3.
NC
-
-
PC3
I/O
O
O
TTL
TTL
TTL
37
SWO
JTAG TDO and SWO.
TDO
JTAG TDO and SWO.
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Signal Tables
Table 15-5. Signals by Pin Number (continued)
Pin Number
Pin Name
PC2
Pin Type
Buffer Typea Description
I/O
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Analog
TTL
TTL
TTL
TTL
Analog
-
GPIO port C bit 2.
38
TDI
JTAG TDI.
PC1
I/O
I/O
I/O
I/O
I
GPIO port C bit 1.
39
SWDIO
TMS
JTAG TMS and SWDIO.
JTAG TMS and SWDIO.
PC0
GPIO port C bit 0.
40
41
42
SWCLK
TCK
JTAG/SWD CLK.
I
JTAG/SWD CLK.
PB7
I/O
I
GPIO port B bit 7.
TRST
PB6
JTAG TRST.
I/O
I
GPIO port B bit 6.
C0+
Analog comparator 0 positive input.
Capture/Compare/PWM 1.
GPIO port B bit 5.
CCP1
PB5
I/O
I/O
O
I/O
I
43
44
C0o
Analog comparator 0 output.
GPIO port B bit 4.
PB4
C0-
Analog comparator 0 negative input.
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
45
46
47
48
NC
-
NC
-
-
NC
-
-
NC
-
-
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.2.2
Signals by Signal Name
Table 15-6. Signals by Signal Name
Pin Name
32KHz
C0+
Pin Number
Pin Type
Buffer Typea Description
30
42
44
43
29
42
I
I
TTL
Analog
Analog
TTL
32-KHz input to the timer.
Analog comparator 0 positive input.
Analog comparator 0 negative input.
Analog comparator 0 output.
C0-
I
C0o
O
I/O
I/O
-
CCP0
CCP1
GND
TTL
Capture/Compare/PWM 0.
TTL
Capture/Compare/PWM 1.
8
Power
Ground reference for logic and I/O pins.
24
31
I2CSCL
I2CSDA
LDO
33
34
6
I/O
I/O
-
OD
OD
I2C clock.
I2C data.
Power
Low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 µF or
greater.
438
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Table 15-6. Signals by Signal Name (continued)
Pin Name
Pin Number
Pin Type
Buffer Typea Description
NC
1
-
-
No connect. Leave the pin electrically unconnected/isolated.
2
3
4
11
12
13
14
15
16
25
26
27
28
35
36
45
46
47
48
OSC0
OSC1
9
I
Analog
Analog
Main oscillator crystal input or an external clock reference
input.
10
O
Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
PA0
PA1
17
18
19
20
21
22
29
30
33
34
44
43
42
41
40
39
38
37
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
GPIO port A bit 0.
GPIO port A bit 1.
GPIO port A bit 2.
GPIO port A bit 3.
GPIO port A bit 4.
GPIO port A bit 5.
GPIO port B bit 0.
GPIO port B bit 1.
GPIO port B bit 2.
GPIO port B bit 3.
GPIO port B bit 4.
GPIO port B bit 5.
GPIO port B bit 6.
GPIO port B bit 7.
GPIO port C bit 0.
GPIO port C bit 1.
GPIO port C bit 2.
GPIO port C bit 3.
System reset input.
SSI clock.
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
RST
SSIClk
SSIFss
SSIRx
SSITx
SWCLK
19
20
21
22
40
I/O
I/O
I
SSI frame.
SSI receive.
O
SSI transmit.
I
JTAG/SWD CLK.
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Signal Tables
Table 15-6. Signals by Signal Name (continued)
Pin Name
SWDIO
SWO
Pin Number
Pin Type
Buffer Typea Description
39
37
40
38
37
39
41
17
18
I/O
O
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Power
JTAG TMS and SWDIO.
JTAG TDO and SWO.
JTAG/SWD CLK.
TCK
TDI
I
JTAG TDI.
TDO
O
I/O
I
JTAG TDO and SWO.
JTAG TMS and SWDIO.
JTAG TRST.
TMS
TRST
U0Rx
U0Tx
VDD
I
UART module 0 receive.
UART module 0 transmit.
Positive supply for I/O and some logic.
O
-
7
23
32
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.2.3
Signals by Function, Except for GPIO
Table 15-7. Signals by Function, Except for GPIO
Function
Pin Name
C0+
Pin Number
Pin Type
Buffer Typea
Description
Analog comparator 0 positive input.
Analog comparator 0 negative input.
Analog comparator 0 output.
32-KHz input to the timer.
Capture/Compare/PWM 0.
Capture/Compare/PWM 1.
I2C clock.
42
44
43
30
29
42
33
34
40
39
37
40
38
37
39
41
I
I
Analog
Analog
TTL
Analog Comparators C0-
C0o
O
I
32KHz
TTL
General-Purpose
Timers
CCP0
CCP1
I2CSCL
I2CSDA
SWCLK
SWDIO
SWO
I/O
I/O
I/O
I/O
I
TTL
TTL
OD
I2C
OD
I2C data.
TTL
JTAG/SWD CLK.
I/O
O
I
TTL
JTAG TMS and SWDIO.
JTAG TDO and SWO.
JTAG/SWD CLK.
TTL
TCK
TTL
JTAG/SWD/SWO
TDI
I
TTL
JTAG TDI.
TDO
O
I/O
I
TTL
JTAG TDO and SWO.
JTAG TMS and SWDIO.
JTAG TRST.
TMS
TTL
TRST
GND
TTL
8
-
Power
Ground reference for logic and I/O pins.
24
31
LDO
VDD
6
-
-
Power
Power
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater.
Power
7
Positive supply for I/O and some logic.
23
32
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Table 15-7. Signals by Function, Except for GPIO (continued)
Function
Pin Name
SSIClk
Pin Number
Pin Type
Buffer Typea
Description
19
20
21
22
9
I/O
I/O
I
TTL
SSI clock.
SSIFss
SSIRx
SSITx
OSC0
TTL
SSI frame.
SSI receive.
SSI transmit.
SSI
TTL
O
I
TTL
Analog
Main oscillator crystal input or an external clock
reference input.
System Control &
Clocks
OSC1
10
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST
5
I
I
TTL
TTL
TTL
System reset input.
U0Rx
U0Tx
17
18
UART module 0 receive.
UART module 0 transmit.
UART
O
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.2.4
GPIO Pins and Alternate Functions
Table 15-8. GPIO Pins and Alternate Functions
IO
Pin Number
Multiplexed Function
Multiplexed Function
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
17
18
19
20
21
22
29
30
33
34
44
43
42
41
40
39
38
37
U0Rx
U0Tx
SSIClk
SSIFss
SSIRx
SSITx
CCP0
32KHz
I2CSCL
I2CSDA
C0-
C0o
C0+
CCP1
TRST
TCK
SWCLK
SWDIO
TMS
TDI
TDO
SWO
15.3
Connections for Unused Signals
Table 15-9 on page 442 show how to handle signals for functions that are not used in a particular
system implementation. Two options are shown in the table: an acceptable practice and a preferred
practice for reduced power consumption and improved EMC characteristics.
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Signal Tables
Table 15-9. Connections for Unused Signals
Function
Signal Name
All unused GPIOs
OSC0
Pin Number
Acceptable Practice
Preferred Practice
GPIO
-
9
NC
NC
NC
GND
GND
NC
OSC1
10
5
System Control
RST
Pull up as shown in Figure
5-1 on page 137
Connect through a capacitor to
GND as close to pin as possible
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16
Operating Characteristics
Table 16-1. Temperature Characteristics
Characteristic
Symbol
TA
Value
Unit
Industrial operating temperature range
Extended operating temperature range
Unpowered storage temperature range
-40 to +85
-40 to +105
-65 to +150
°C
°C
°C
TA
TS
Table 16-2. Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance (junction to ambient)a
ΘJA
74 (28-pin SOIC)
50 (48-pin QFP)
°C/W
Junction temperatureb
TJ
TA + (P • ΘJA
)
°C
°C
Maximum junction temperature
TJMAX
115
c
a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator.
b. Power dissipation is a function of temperature.
c. TJMAX calculation is based on power consumption values and conditions as specified in “Power Specifications”.
Table 16-3. ESD Absolute Maximum Ratingsa
Parameter Name
VESDHBM
Min
Nom
Max
2.0
Unit
kV
kV
V
-
-
-
-
-
-
VESDCDM
1.0
VESDMM
100
a. All Stellaris parts are ESD tested following the JEDEC standard.
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Electrical Characteristics
17
Electrical Characteristics
17.1
DC Characteristics
17.1.1
Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device.
Note: The device is not guaranteed to operate properly at the maximum ratings.
Table 17-1. Maximum Ratings
Characteristica
Symbol
Value
0.0 to +3.6
-0.3 to 5.5
-0.3 to VDD + 0.3
100
Unit
V
Supply voltage range (VDD
)
VDD
Input voltage
V
VIN
Input voltage for a GPIO configured as an analog input
Maximum current for pins, excluding pins operating as GPIOs
Maximum current for GPIO pins
V
I
I
mA
mA
mV
100
Maximum input voltage on a non-power pin when the
microcontroller is unpowered
VNON
300
a. Voltages are measured with respect to GND.
Important: This device contains circuitry to protect the inputs against damage due to high-static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (for example, either GND or VDD).
17.1.2
Recommended DC Operating Conditions
Table 17-2. Recommended DC Operating Conditions
Parameter Parameter Name
Min
3.0
2.0
-0.3
2.4
-
Nom
Max
3.6
5.0
1.3
-
Unit
V
VDD
VIH
Supply voltage
3.3
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
High-level source current, VOH=2.4 V
2-mA Drive
-
-
-
-
V
VIL
V
VOH
VOL
V
0.4
V
2.0
4.0
8.0
-
-
-
-
-
-
mA
mA
mA
IOH
4-mA Drive
8-mA Drive
Low-level sink current, VOL=0.4 V
2-mA Drive
2.0
4.0
8.0
-
-
-
-
-
-
mA
mA
mA
IOL
4-mA Drive
8-mA Drive
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17.1.3
On-Chip Low Drop-Out (LDO) Regulator Characteristics
Table 17-3. LDO Regulator Characteristics
Parameter
Parameter Name
Min
Nom
Max
Unit
Programmable internal (logic) power supply
output value
2.25
-
2.75
V
VLDOOUT
Output voltage accuracy
Power-on time
-
2%
-
%
µs
tPON
tON
-
-
-
100
200
100
-
Time on
-
-
µs
tOFF
Time off
-
µs
VSTEP
CLDO
Step programming incremental voltage
-
50
-
mV
µF
External filter capacitor size for internal power
supply
1.0
3.0
17.1.4
GPIO Module Characteristics
Table 17-4. GPIO Module DC Characteristics
Parameter
RGPIOPU
RGPIOPD
ILKG
Parameter Name
Min
50
55
-
Nom
Max
110
180
2
Unit
kΩ
GPIO internal pull-up resistor
GPIO internal pull-down resistor
GPIO input leakage currenta
-
-
-
kΩ
µA
a. The leakage current is measured with GND or VDD applied to the corresponding pin(s). The leakage of digital port pins is
measured individually. The port pin is configured as an input and the pullup/pulldown resistor is disabled.
17.1.5
Power Specifications
The power measurements specified in the tables that follow are run on the core processor using
SRAM with the following specifications (except as noted):
■ VDD = 3.3 V
■ Temperature = 25°C
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Electrical Characteristics
Table 17-5. Detailed Power Specifications
Parameter Parameter Name
Run mode 1 (Flash loop) LDO = 2.50 V
Code = while(1){} executed out of Flash
Conditions
Nom
Max
Unit
45
50
mA
Peripherals = All clock-gated ON
System Clock = 20 MHz (with PLL)
Run mode 2 (Flash loop) LDO = 2.50 V
25
40
20
30
45
25
mA
mA
mA
Code = while(1){} executed out of Flash
Peripherals = All clock-gated OFF
System Clock = 20 MHz (with PLL)
IDD_RUN
Run mode 1 (SRAM
loop)
LDO = 2.50 V
Code = while(1){} executed in SRAM
Peripherals = All clock-gated ON
System Clock = 20 MHz (with PLL)
Run mode 2 (SRAM
loop)
LDO = 2.50 V
Code = while(1){} executed in SRAM
Peripherals = All clock-gated OFF
System Clock = 20 MHz (with PLL)
IDD_SLEEP
Sleep mode
LDO = 2.50 V
17
20
mA
μA
Peripherals = All clock-gated OFF
System Clock = 20 MHz (with PLL)
IDD_DEEPSLEEP Deep-Sleep mode
LDO = 2.25 V
800
1000
Peripherals = All OFF
System Clock = MOSC/16
17.1.6
Flash Memory Characteristics
Table 17-6. Flash Memory Characteristics
Parameter
Parameter Name
Min
Nom
Max
Unit
PECYC
Number of guaranteed program/erase cycles
before failurea
10,000
100,000
-
cycles
TRET
Data retention at average operating temperature
of 85˚C (industrial) or 105˚C (extended)
10
-
-
years
TPROG
TERASE
TME
Word program time
Page erase time
Mass erase time
20
20
-
-
-
-
-
-
µs
ms
ms
250
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.
17.2
AC Characteristics
17.2.1
Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements. Timing
measurements are for 4-mA drive strength.
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Figure 17-1. Load Conditions
pin
CL = 50 pF
GND
17.2.2
Clocks
Table 17-7. Phase Locked Loop (PLL) Characteristics
Parameter
fref_crystal
fref_ext
fpll
Parameter Name
Crystal referencea
External clock referencea
PLL frequencyb
Min
Nom
Max
8.192
8.192
-
Unit
MHz
MHz
MHz
ms
3.579545
-
3.579545
-
200
-
-
-
TREADY
PLL lock time
0.5
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration
(RCC) register.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.
Table 17-8. Clock Characteristics
Parameter
Parameter Name
Min
7
Nom
Max
22
Unit
MHz
MHz
ns
fIOSC
Internal oscillator frequency
Main oscillator frequency
Main oscillator period
12
-
fMOSC
1
8
tMOSC_per
fref_crystal_bypass
125
1
-
1000
8
Crystal reference using the main oscillator
(PLL in BYPASS mode)
-
MHz
fref_ext_bypass
fsystem_clock
External clock reference (PLL in BYPASS
mode)
0
0
-
-
20
20
MHz
MHz
System clock
17.2.3
JTAG and Boundary Scan
Table 17-9. JTAG Characteristics
Parameter
No.
Parameter
Parameter Name
Min
Nom
Max
Unit
J1
J2
J3
J4
J5
J6
J7
J8
J9
fTCK
tTCK
TCK operational clock frequency
TCK operational clock period
TCK clock Low time
0
100
-
-
10
-
MHz
ns
-
tTCK_LOW
tTCK_HIGH
tTCK_R
tTCK/2
-
ns
TCK clock High time
-
tTCK/2
-
ns
TCK rise time
0
-
-
-
-
-
10
10
-
ns
tTCK_F
TCK fall time
0
ns
tTMS_SU
tTMS_HLD
tTDI_SU
TMS setup time to TCK rise
TMS hold time from TCK rise
TDI setup time to TCK rise
20
20
25
ns
-
ns
-
ns
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Electrical Characteristics
Table 17-9. JTAG Characteristics (continued)
Parameter
No.
Parameter
Parameter Name
Min
Nom
Max
Unit
J10
tTDI_HLD
TDI hold time from TCK rise
2-mA drive
25
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23
15
14
18
21
14
13
18
9
35
26
25
29
35
25
24
28
11
9
4-mA drive
J11
TCK fall to Data
Valid from High-Z
-
-
-
t TDO_ZDV
8-mA drive
8-mA drive with slew rate control
2-mA drive
TCK fall to Data
Valid from Data
Valid
4-mA drive
J12
t TDO_DV
8-mA drive
8-mA drive with slew rate control
2-mA drive
4-mA drive
7
J13
TCK fall to High-Z
from Data Valid
t TDO_DVZ
8-mA drive
6
8
8-mA drive with slew rate control
TRST assertion time
TRST setup time to TCK rise
7
9
J14
J15
tTRST
100
10
-
-
tTRST_SU
-
-
Figure 17-2. JTAG Test Clock Input Timing
J2
J3
J4
TCK
J6
J5
Figure 17-3. JTAG Test Access Port (TAP) Timing
TCK
J7
TMS Input Valid
J9 J10
TDI Input Valid
J8
J7
TMS Input Valid
J9 J10
TDI Input Valid
J8
TMS
TDI
J11
J12
J13
TDO Output Valid
TDO Output Valid
TDO
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Figure 17-4. JTAG TRST Timing
TCK
J14
J15
TRST
17.2.4
Reset
Table 17-10. Reset Characteristics
Parameter
No.
Parameter
Parameter Name
Min
Nom
Max
Unit
R1
R2
R3
R4
R5
R6
R7
VTH
VBTH
Reset threshold
-
2.85
-
2.0
2.9
10
500
-
-
2.95
-
V
V
Brown-Out threshold
TPOR
Power-On Reset timeout
Brown-Out timeout
ms
µs
ms
µs
µs
TBOR
-
-
TIRPOR
TIRBOR
TIRHWR
Internal reset timeout after POR
Internal reset timeout after BORa
15
2.5
2.9
30
20
29
-
Internal reset timeout after hardware reset
-
(RST pin)
R8
TIRSWR
Internal reset timeout after
software-initiated system reset a
2.5
-
20
µs
R9
R10
TIRWDR
TIRLDOR
TVDDRISE
Internal reset timeout after watchdog reseta
Internal reset timeout after LDO reseta
Supply voltage (VDD) rise time (0 V-3.3 V)
2.5
2.5
-
-
-
-
20
20
µs
µs
R11
100
ms
a. 20 * t MOSC_per
Figure 17-5. External Reset Timing (RST)
RST
R7
/Reset
(Internal)
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Electrical Characteristics
Figure 17-6. Power-On Reset Timing
R1
VDD
R3
/POR
(Internal)
R5
/Reset
(Internal)
Figure 17-7. Brown-Out Reset Timing
R2
VDD
R4
/BOR
(Internal)
R6
/Reset
(Internal)
Figure 17-8. Software Reset Timing
SW Reset
R8
/Reset
(Internal)
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Figure 17-9. Watchdog Reset Timing
WDOG
Reset
(Internal)
R9
/Reset
(Internal)
Figure 17-10. LDO Reset Timing
LDO Reset
(Internal)
R10
/Reset
(Internal)
17.2.5
Sleep Modes
Table 17-11. Sleep Modes AC Characteristicsa
Parameter No
Parameter
Parameter Name
Min
Nom
Max
Unit
D1
tWAKE_S
Time to wake from interrupt in sleep or
deep-sleep mode, not using the PLL
-
-
7
system clocks
D2
tWAKE_PLL_S
Time to wake from interrupt in sleep or
deep-sleep mode when using the PLL
-
-
TREADY
ms
a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode.
17.2.6
General-Purpose I/O (GPIO)
Note: All GPIOs are 5 V-tolerant.
Table 17-12. GPIO Characteristics
Parameter Parameter Name Condition
Min
Nom
17
9
Max
26
13
9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
2-mA drive
4-mA drive
GPIO Rise Time
tGPIOR
(from 20% to 80%
of VDD
-
8-mA drive
6
)
8-mA drive with slew rate control
2-mA drive
10
17
8
12
25
12
10
13
GPIO Fall Time
4-mA drive
tGPIOF
(from 80% to 20%
-
8-mA drive
6
of VDD
)
8-mA drive with slew rate control
11
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Electrical Characteristics
17.2.7
Synchronous Serial Interface (SSI)
Table 17-13. SSI Characteristics
Parameter
No.
Parameter Parameter Name
Min
Nom
Max
Unit
S1
S2
S3
S4
S5
S6
S7
S8
S9
tclk_per
tclk_high
tclk_low
tclkrf
SSIClk cycle time
2
-
-
65024
system clocks
t clk_per
SSIClk high time
0.5
-
-
SSIClk low time
SSIClk rise/fall timea
-
0.5
t clk_per
-
6
-
10
1
-
ns
tDMd
Data from master valid delay time
Data from master setup time
Data from master hold time
Data from slave setup time
Data from slave hold time
0
1
2
1
2
system clocks
system clocks
system clocks
system clocks
system clocks
tDMs
-
tDMh
-
-
tDSs
-
-
tDSh
-
-
a. Note that the delays shown are using 8-mA drive strength.
Figure 17-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
S1
S2
S4
SSIClk
SSIFss
S3
SSITx
SSIRx
MSB
LSB
4 to 16 bits
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Figure 17-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
S2
S1
SSIClk
SSIFss
SSITx
SSIRx
S3
MSB
LSB
8-bit control
0
MSB
LSB
4 to 16 bits output data
Figure 17-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1
S1
S4
S2
SSIClk
(SPO=0)
S3
SSIClk
(SPO=1)
S6
S7
S9
SSITx
(master)
MSB
LSB
S5
S8
SSIRx
(slave)
MSB
LSB
SSIFss
17.2.8
Inter-Integrated Circuit (I2C) Interface
Table 17-14. I2C Characteristics
Parameter
No.
Parameter Parameter Name
Min
Nom
Max
Unit
I1a
I2a
I3b
tSCH
tLP
Start condition hold time
36
36
-
-
-
-
-
-
system clocks
system clocks
ns
Clock Low period
tSRT
I2CSCL/I2CSDA rise time (VIL =0.5 V
to V IH =2.4 V)
(see note
b)
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Electrical Characteristics
Table 17-14. I2C Characteristics (continued)
Parameter
No.
Parameter Parameter Name
Min
Nom
Max
Unit
I4a
I5c
tDH
Data hold time
2
-
-
-
system clocks
ns
tSFT
I2CSCL/I2CSDA fall time (VIH =2.4 V
9
10
to V IL =0.5 V)
I6a
I7a
I8a
tHT
tDS
Clock High time
Data setup time
24
18
36
-
-
-
-
-
-
system clocks
system clocks
system clocks
tSCSR
Start condition setup time (for repeated
start condition only)
I9a
tSCS
Stop condition setup time
24
-
-
system clocks
a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
Figure 17-14. I2C Timing
I2
I6
I5
I2CSCL
I1
I4
I7
I8
I3
I9
I2CSDA
17.2.9
Analog Comparator
Table 17-15. Analog Comparator Characteristics
Parameter
VOS
Parameter Name
Min
Nom
Max
Unit
mV
V
Input offset voltage
-
0
50
-
±10
±25
VCM
Input common mode voltage range
Common mode rejection ratio
Response time
-
-
-
-
VDD-1.5
CMRR
TRT
-
dB
µs
1
TMC
Comparator mode change to Output Valid
-
10
µs
Table 17-16. Analog Comparator Voltage Reference Characteristics
Parameter
RHR
Parameter Name
Min
Nom
Max
-
Unit
Resolution high range
Resolution low range
-
-
-
-
VDD/31
LSB
LSB
LSB
LSB
RLR
VDD/23
-
AHR
Absolute accuracy high range
Absolute accuracy low range
-
-
±1/2
±1/4
ALR
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A
Serial Flash Loader
A.1
Serial Flash Loader
The Stellaris® serial flash loader is a preprogrammed flash-resident utility used to download code
to the flash memory of a device without the use of a debug interface. The serial flash loader uses
a simple packet interface to provide synchronous communication with the device. The flash loader
runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used.
The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both
the data format and communication protocol are identical for both serial interfaces.
A.2
Interfaces
Once communication with the flash loader is established via one of the serial interfaces, that interface
is used until the flash loader is reset or new code takes over. For example, once you start
communicating using the SSI port, communications with the flash loader via the UART are disabled
until the device is reset.
A.2.1
UART
The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial
format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is
automatically detected by the flash loader and can be any valid baud rate supported by the host
and the device. The auto detection sequence requires that the baud rate should be no more than
1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the
same as the hardware limitation for the maximum baud rate for any UART on a Stellaris device
which is calculated as follows:
Max Baud Rate = System Clock Frequency / 16
In order to determine the baud rate, the serial flash loader needs to determine the relationship
between its own crystal frequency and the baud rate. This is enough information for the flash loader
to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows
the host to use any valid baud rate that it wants to communicate with the device.
The method used to perform this automatic synchronization relies on the host sending the flash
loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can
use to calculate the ratios needed to program the UART to match the host’s baud rate. After the
host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader
returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received
after at least twice the time required to transfer the two bytes, the host can resend another pattern
of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has
received a synchronization pattern correctly. For example, the time to wait for data back from the
flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate
of 115200, this time is 2*(20/115200) or 0.35 ms.
A.2.2
SSI
The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications,
with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame
Formats” on page 346 in the SSI chapter for more information on formats for this transfer protocol.
Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI
clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running
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Serial Flash Loader
the flash loader. Since the host device is the master, the SSI on the flash loader device does not
need to determine the clock as it is provided directly by the host.
A.3
Packet Handling
All communications, with the exception of the UART auto-baud, are done via defined packets that
are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same
format for receiving and sending packets, including the method used to acknowledge successful or
unsuccessful reception of a packet.
A.3.1
Packet Format
All packets sent and received from the device use the following byte-packed format.
struct
{
unsigned char ucSize;
unsigned char ucCheckSum;
unsigned char Data[];
};
ucSize
The first byte received holds the total size of the transfer including
the size and checksum bytes.
ucChecksum
Data
This holds a simple checksum of the bytes in the data buffer only.
The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3].
This is the raw data intended for the device, which is formatted in
some form of command interface. There should be ucSize–2
bytes of data provided in this buffer to or from the device.
A.3.2
Sending Packets
The actual bytes of the packet can be sent individually or all at once; the only limitation is that
commands that cause flash memory access should limit the download sizes to prevent losing bytes
during flash programming. This limitation is discussed further in the section that describes the serial
flash loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA
(0x24)” on page 458).
Once the packet has been formatted correctly by the host, it should be sent out over the UART or
SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned
from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from
the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This
does not indicate that the actual contents of the command issued in the data portion of the packet
were valid, just that the packet was received correctly.
A.3.3
Receiving Packets
The flash loader sends a packet of data in the same format that it receives a packet. The flash loader
may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte
is the size of the packet followed by a checksum byte, and finally followed by the data itself. There
is no break in the data after the first non-zero byte is sent from the flash loader. Once the device
communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to
indicate that the transmission was successful. The appropriate response after sending a NAK to
the flash loader is to resend the command that failed and request the data again. If needed, the
host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the
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flash loader only accepts the first non-zero data as a valid response. This zero padding is needed
by the SSI interface in order to receive data to or from the flash loader.
A.4
Commands
The next section defines the list of commands that can be sent to the flash loader. The first byte of
the data should always be one of the defined commands, followed by data or parameters as
determined by the command that is sent.
A.4.1
COMMAND_PING (0X20)
This command simply accepts the command and sets the global status to success. The format of
the packet is as follows:
Byte[0] = 0x03;
Byte[1] = checksum(Byte[2]);
Byte[2] = COMMAND_PING;
The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one
byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status,
the receipt of an ACK can be interpreted as a successful ping to the flash loader.
A.4.2
COMMAND_GET_STATUS (0x23)
This command returns the status of the last command that was issued. Typically, this command
should be sent after every command to ensure that the previous command was successful or to
properly respond to a failure. The command requires one byte in the data of the packet and should
be followed by reading a packet with one byte of data that contains a status code. The last step is
to ACK or NAK the received data so the flash loader knows that the data has been read.
Byte[0] = 0x03
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_GET_STATUS
A.4.3
COMMAND_DOWNLOAD (0x21)
This command is sent to the flash loader to indicate where to store data and how many bytes will
be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit
values that are both transferred MSB first. The first 32-bit value is the address to start programming
data into, while the second is the 32-bit size of the data that will be sent. This command also triggers
an erase of the full area to be programmed so this command takes longer than other commands.
This results in a longer time to receive the ACK/NAK back from the board. This command should
be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size
are valid for the device running the flash loader.
The format of the packet to send this command is a follows:
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_DOWNLOAD
Byte[3] = Program Address [31:24]
Byte[4] = Program Address [23:16]
Byte[5] = Program Address [15:8]
Byte[6] = Program Address [7:0]
Byte[7] = Program Size [31:24]
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Serial Flash Loader
Byte[8] = Program Size [23:16]
Byte[9] = Program Size [15:8]
Byte[10] = Program Size [7:0]
A.4.4
COMMAND_SEND_DATA (0x24)
This command should only follow a COMMAND_DOWNLOAD command or another
COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands
automatically increment address and continue programming from the previous location. The caller
should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program
successfully and not overflow input buffers of the serial interfaces. The command terminates
programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been
received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to
ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK
to this command, the flash loader does not increment the current address to allow retransmission
of the previous data.
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_SEND_DATA
Byte[3] = Data[0]
Byte[4] = Data[1]
Byte[5] = Data[2]
Byte[6] = Data[3]
Byte[7] = Data[4]
Byte[8] = Data[5]
Byte[9] = Data[6]
Byte[10] = Data[7]
A.4.5
COMMAND_RUN (0x22)
This command is used to tell the flash loader to execute from the address passed as the parameter
in this command. This command consists of a single 32-bit value that is interpreted as the address
to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK
signal back to the host device before actually executing the code at the given address. This allows
the host to know that the command was received successfully and the code is now running.
Byte[0] = 7
Byte[1] = checksum(Bytes[2:6])
Byte[2] = COMMAND_RUN
Byte[3] = Execute Address[31:24]
Byte[4] = Execute Address[23:16]
Byte[5] = Execute Address[15:8]
Byte[6] = Execute Address[7:0]
A.4.6
COMMAND_RESET (0x25)
This command is used to tell the flash loader device to reset. This is useful when downloading a
new image that overwrote the flash loader and wants to start from a full reset. Unlike the
COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set
up for the new code. It can also be used to reset the flash loader if a critical error occurs and the
host device wants to restart communication with the flash loader.
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Byte[0] = 3
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_RESET
The flash loader responds with an ACK signal back to the host device before actually executing the
software reset to the device running the flash loader. This allows the host to know that the command
was received successfully and the part will be reset.
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Register Quick Reference
B
Register Quick Reference
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
The Cortex-M3 Processor
R0, type R/W, , reset - (see page 47)
DATA
DATA
R1, type R/W, , reset - (see page 47)
R2, type R/W, , reset - (see page 47)
R3, type R/W, , reset - (see page 47)
R4, type R/W, , reset - (see page 47)
R5, type R/W, , reset - (see page 47)
R6, type R/W, , reset - (see page 47)
R7, type R/W, , reset - (see page 47)
R8, type R/W, , reset - (see page 47)
R9, type R/W, , reset - (see page 47)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
R10, type R/W, , reset - (see page 47)
R11, type R/W, , reset - (see page 47)
R12, type R/W, , reset - (see page 47)
SP, type R/W, , reset - (see page 48)
DATA
DATA
DATA
DATA
DATA
DATA
SP
SP
LR, type R/W, , reset 0xFFFF.FFFF (see page 49)
PC, type R/W, , reset - (see page 50)
LINK
LINK
PC
PC
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31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
PSR, type R/W, , reset 0x0100.0000 (see page 51)
N
Z
C
V
Q
ICI / IT
THUMB
ICI / IT
ISRNUM
PRIMASK, type R/W, , reset 0x0000.0000 (see page 55)
FAULTMASK, type R/W, , reset 0x0000.0000 (see page 56)
BASEPRI, type R/W, , reset 0x0000.0000 (see page 57)
CONTROL, type R/W, , reset 0x0000.0000 (see page 58)
PRIMASK
FAULTMASK
BASEPRI
ASP
TMPL
Cortex-M3 Peripherals
System Timer (SysTick) Registers
Base 0xE000.E000
STCTRL, type R/W, offset 0x010, reset 0x0000.0000
STRELOAD, type R/W, offset 0x014, reset 0x0000.0000
STCURRENT, type R/WC, offset 0x018, reset 0x0000.0000
COUNT
CLK_SRC INTEN
ENABLE
RELOAD
RELOAD
CURRENT
CURRENT
Cortex-M3 Peripherals
Nested Vectored Interrupt Controller (NVIC) Registers
Base 0xE000.E000
EN0, type R/W, offset 0x100, reset 0x0000.0000
DIS0, type R/W, offset 0x180, reset 0x0000.0000
PEND0, type R/W, offset 0x200, reset 0x0000.0000
UNPEND0, type R/W, offset 0x280, reset 0x0000.0000
ACTIVE0, type RO, offset 0x300, reset 0x0000.0000
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
PRI0, type R/W, offset 0x400, reset 0x0000.0000
INTD
INTC
INTA
INTB
PRI1, type R/W, offset 0x404, reset 0x0000.0000
INTD
INTB
INTC
INTA
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Register Quick Reference
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
PRI2, type R/W, offset 0x408, reset 0x0000.0000
INTD
INTC
INTA
INTB
PRI3, type R/W, offset 0x40C, reset 0x0000.0000
INTD
INTC
INTA
INTB
PRI4, type R/W, offset 0x410, reset 0x0000.0000
INTD
INTC
INTA
INTB
PRI5, type R/W, offset 0x414, reset 0x0000.0000
INTD
INTC
INTA
INTB
PRI6, type R/W, offset 0x418, reset 0x0000.0000
INTD
INTC
INTA
INTB
PRI7, type R/W, offset 0x41C, reset 0x0000.0000
INTD
INTC
INTA
INTB
SWTRIG, type WO, offset 0xF00, reset 0x0000.0000
INTID
Cortex-M3 Peripherals
System Control Block (SCB) Registers
Base 0xE000.E000
CPUID, type RO, offset 0xD00, reset 0x410F.C231
IMP
VAR
CON
REV
PARTNO
INTCTRL, type R/W, offset 0xD04, reset 0x0000.0000
UNPENDSV PENDSTSET PENDSTCLR
RETBASE
NMISET
PENDSV
ISRPRE ISRPEND
OFFSET
VECPEND
VECPEND
VECACT
VTABLE, type R/W, offset 0xD08, reset 0x0000.0000
BASE
OFFSET
APINT, type R/W, offset 0xD0C, reset 0xFA05.0000
VECTKEY
VECTCLRACT
VECTRESET
ENDIANESS
SYSRESREQ
PRIGROUP
SYSCTRL, type R/W, offset 0xD10, reset 0x0000.0000
SEVONPEND
DIV0
SLEEPDEEP SLEEPEXIT
MAINPEND
CFGCTRL, type R/W, offset 0xD14, reset 0x0000.0000
SYSPRI1, type R/W, offset 0xD18, reset 0x0000.0000
STKALIGN BFHFNMIGN
UNALIGNED
BASETHR
USAGE
BUS
SYSPRI2, type R/W, offset 0xD1C, reset 0x0000.0000
SVC
SYSPRI3, type R/W, offset 0xD20, reset 0x0000.0000
TICK
PENDSV
DEBUG
462
July 24, 2012
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Stellaris® LM3S102 Microcontroller
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
SYSHNDCTRL, type R/W, offset 0xD24, reset 0x0000.0000
USAGE
BUS
MEM
SVC
BUSP
MEMP USAGEP
TICK
PNDSV
MON
SVCA
USGA
NOCP
BUSA
MEMA
FAULTSTAT, type R/W1C, offset 0xD28, reset 0x0000.0000
DIV0
UNALIGN
IBUS
INVPC INVSTAT UNDEF
IERR
BFARV
HFAULTSTAT, type R/W1C, offset 0xD2C, reset 0x0000.0000
DBG FORCED
BSTKE BUSTKE IMPRE PRECISE
MMARV
VECT
MMADDR, type R/W, offset 0xD34, reset -
FAULTADDR, type R/W, offset 0xD38, reset -
ADDR
ADDR
ADDR
ADDR
System Control
Base 0x400F.E000
DID0, type RO, offset 0x000, reset - (see page 147)
VER
MAJOR
MINOR
PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD (see page 149)
BORTIM
BORIOR BORWT
LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000 (see page 150)
RIS, type RO, offset 0x050, reset 0x0000.0000 (see page 151)
IMC, type R/W, offset 0x054, reset 0x0000.0000 (see page 152)
MISC, type R/W1C, offset 0x058, reset 0x0000.0000 (see page 153)
RESC, type R/W, offset 0x05C, reset - (see page 154)
VADJ
PLLLRIS
PLLLIM
CLRIS
CLIM
IOFRIS MOFRIS LDORIS BORRIS PLLFRIS
IOFIM
MOFIM
LDOIM
BORIM
PLLFIM
PLLLMIS CLMIS
IOFMIS MOFMIS LDOMIS BORMIS
LDO
SW
WDT
BOR
POR
EXT
RCC, type R/W, offset 0x060, reset 0x0780.3AC0 (see page 155)
USESYSDIV
ACG
SYSDIV
PWRDN
OEN
BYPASS PLLVER
XTAL
OSCSRC
IOSCVER MOSCVER IOSCDIS MOSCDIS
PLLCFG, type RO, offset 0x064, reset - (see page 158)
OD
F
R
DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000 (see page 159)
CLKVCLR, type R/W, offset 0x150, reset 0x0000.0000 (see page 160)
LDOARST, type R/W, offset 0x160, reset 0x0000.0000 (see page 161)
IOSC
VERCLR
LDOARST
July 24, 2012
463
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Register Quick Reference
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
DID1, type RO, offset 0x004, reset - (see page 162)
VER
FAM
PARTNO
PKG
TEMP
ROHS
QUAL
DC0, type RO, offset 0x008, reset 0x0007.0003 (see page 164)
DC1, type RO, offset 0x010, reset 0x0000.901F (see page 165)
SRAMSZ
FLASHSZ
MINSYSDIV
PLL
WDT
SWO
SWD
JTAG
DC2, type RO, offset 0x014, reset 0x0103.1011 (see page 166)
COMP0
TIMER1 TIMER0
UART0
I2C0
DC3, type RO, offset 0x018, reset 0x8300.01C0 (see page 168)
32KHZ
SSI0
CCP1
CCP0
C0O
C0PLUS C0MINUS
DC4, type RO, offset 0x01C, reset 0x0000.0007 (see page 169)
GPIOC
GPIOB
GPIOA
RCGC0, type R/W, offset 0x100, reset 0x00000040 (see page 170)
SCGC0, type R/W, offset 0x110, reset 0x00000040 (see page 171)
DCGC0, type R/W, offset 0x120, reset 0x00000040 (see page 172)
RCGC1, type R/W, offset 0x104, reset 0x00000000 (see page 173)
WDT
WDT
WDT
COMP0
COMP0
COMP0
TIMER1 TIMER0
UART0
I2C0
SSI0
SSI0
SSI0
SCGC1, type R/W, offset 0x114, reset 0x00000000 (see page 175)
TIMER1 TIMER0
UART0
I2C0
DCGC1, type R/W, offset 0x124, reset 0x00000000 (see page 177)
TIMER1 TIMER0
UART0
I2C0
RCGC2, type R/W, offset 0x108, reset 0x00000000 (see page 179)
GPIOC
GPIOC
GPIOC
GPIOB
GPIOB
GPIOB
GPIOA
GPIOA
GPIOA
SCGC2, type R/W, offset 0x118, reset 0x00000000 (see page 180)
DCGC2, type R/W, offset 0x128, reset 0x00000000 (see page 181)
SRCR0, type R/W, offset 0x040, reset 0x00000000 (see page 182)
WDT
SRCR1, type R/W, offset 0x044, reset 0x00000000 (see page 183)
COMP0
TIMER1 TIMER0
UART0
I2C0
SSI0
464
July 24, 2012
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Stellaris® LM3S102 Microcontroller
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
SRCR2, type R/W, offset 0x048, reset 0x00000000 (see page 184)
GPIOC
GPIOB
GPIOA
Internal Memory
Flash Memory Control Registers (Flash Control Offset)
Base 0x400F.D000
FMA, type R/W, offset 0x000, reset 0x0000.0000
FMD, type R/W, offset 0x004, reset 0x0000.0000
FMC, type R/W, offset 0x008, reset 0x0000.0000
FCRIS, type RO, offset 0x00C, reset 0x0000.0000
FCIM, type R/W, offset 0x010, reset 0x0000.0000
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000
OFFSET
DATA
DATA
WRKEY
COMT MERASE ERASE
WRITE
ARIS
PRIS
PMASK
PMISC
AMASK
AMISC
Internal Memory
Flash Memory Protection Registers (System Control Offset)
Base 0x400F.E000
USECRL, type R/W, offset 0x140, reset 0x13
USEC
FMPRE, type R/W, offset 0x130, reset 0x8000.000F
DBG
READ_ENABLE
READ_ENABLE
FMPPE, type R/W, offset 0x134, reset 0x0000.000F
PROG_ENABLE
PROG_ENABLE
General-Purpose Input/Outputs (GPIOs)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIODATA, type R/W, offset 0x000, reset 0x0000.0000 (see page 213)
GPIODIR, type R/W, offset 0x400, reset 0x0000.0000 (see page 214)
GPIOIS, type R/W, offset 0x404, reset 0x0000.0000 (see page 215)
GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000 (see page 216)
DATA
DIR
IS
IBE
July 24, 2012
465
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Register Quick Reference
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000 (see page 217)
GPIOIM, type R/W, offset 0x410, reset 0x0000.0000 (see page 218)
GPIORIS, type RO, offset 0x414, reset 0x0000.0000 (see page 219)
GPIOMIS, type RO, offset 0x418, reset 0x0000.0000 (see page 220)
GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000 (see page 221)
GPIOAFSEL, type R/W, offset 0x420, reset - (see page 222)
IEV
IME
RIS
MIS
IC
AFSEL
DRV2
DRV4
DRV8
ODE
PUE
PDE
SRL
GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF (see page 224)
GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000 (see page 225)
GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000 (see page 226)
GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000 (see page 227)
GPIOPUR, type R/W, offset 0x510, reset 0x0000.00FF (see page 228)
GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000 (see page 229)
GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000 (see page 230)
GPIODEN, type R/W, offset 0x51C, reset 0x0000.00FF (see page 231)
GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 232)
GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 233)
GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 234)
DEN
PID4
PID5
PID6
466
July 24, 2012
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Stellaris® LM3S102 Microcontroller
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 235)
GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061 (see page 236)
GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 237)
GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 238)
GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 239)
GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 240)
GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 241)
GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 242)
GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 243)
PID7
PID0
PID1
PID2
PID3
CID0
CID1
CID2
CID3
General-Purpose Timers
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000 (see page 256)
GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000 (see page 257)
GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000 (see page 259)
GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000 (see page 261)
GPTMCFG
TAAMS
TBAMS
TACMR
TBCMR
TAMR
TBMR
TBPWML
TBEVENT
TBSTALL
TBEN
TAPWML
RTCEN
TAEVENT
TASTALL
CAMIM
TAEN
GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000 (see page 264)
CBEIM
CBMIM
TBTOIM
RTCIM
CAEIM
TATOIM
GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 266)
CBERIS CBMRIS TBTORIS
GPTMMIS, type RO, offset 0x020, reset 0x0000.0000 (see page 267)
RTCRIS CAERIS CAMRIS TATORIS
RTCMIS CAEMIS CAMMIS TATOMIS
CBEMIS CBMMIS TBTOMIS
July 24, 2012
467
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Register Quick Reference
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
GPTMICR, type W1C, offset 0x024, reset 0x0000.0000 (see page 268)
TBTOCINT
TATOCINT
RTCCINT CAECINT CAMCINT
CBECINT CBMCINT
GPTMTAILR, type R/W, offset 0x028, reset 0xFFFF.FFFF (see page 270)
GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF (see page 271)
GPTMTAMATCHR, type R/W, offset 0x030, reset 0xFFFF.FFFF (see page 272)
GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF (see page 273)
GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000 (see page 274)
GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000 (see page 275)
GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000 (see page 276)
GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000 (see page 277)
GPTMTAR, type RO, offset 0x048, reset 0xFFFF.FFFF (see page 278)
GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF (see page 279)
TAILRH
TAILRL
TBILRL
TAMRH
TAMRL
TBMRL
TAPSR
TBPSR
TAPSMR
TBPSMR
TARH
TARL
TBRL
Watchdog Timer
Base 0x4000.0000
WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF (see page 284)
WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF (see page 285)
WDTCTL, type R/W, offset 0x008, reset 0x0000.0000 (see page 286)
WDTICR, type WO, offset 0x00C, reset - (see page 287)
WDTLoad
WDTLoad
WDTValue
WDTValue
RESEN
INTEN
WDTIntClr
WDTIntClr
WDTRIS, type RO, offset 0x010, reset 0x0000.0000 (see page 288)
WDTMIS, type RO, offset 0x014, reset 0x0000.0000 (see page 289)
WDTRIS
WDTMIS
468
July 24, 2012
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Stellaris® LM3S102 Microcontroller
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
WDTTEST, type R/W, offset 0x418, reset 0x0000.0000 (see page 290)
STALL
WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000 (see page 291)
WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 292)
WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 293)
WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 294)
WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 295)
WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005 (see page 296)
WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018 (see page 297)
WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 298)
WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 299)
WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 300)
WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 301)
WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 302)
WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 303)
WDTLock
WDTLock
PID4
PID5
PID6
PID7
PID0
PID1
PID2
PID3
CID0
CID1
CID2
CID3
Universal Asynchronous Receivers/Transmitters (UARTs)
UART0 base: 0x4000.C000
UARTDR, type R/W, offset 0x000, reset 0x0000.0000 (see page 312)
OE
BE
PE
FE
DATA
UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000 (Reads) (see page 314)
OE
BE
PE
FE
UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000 (Writes) (see page 314)
DATA
July 24, 2012
469
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Register Quick Reference
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
UARTFR, type RO, offset 0x018, reset 0x0000.0090 (see page 316)
TXFE
RXFF
TXFF
RXFE
BUSY
UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000 (see page 318)
UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000 (see page 319)
UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000 (see page 320)
UARTCTL, type R/W, offset 0x030, reset 0x0000.0300 (see page 322)
DIVINT
DIVFRAC
SPS
LBE
WLEN
FEN
STP2
EPS
PEN
BRK
RXE
TXE
UARTEN
UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012 (see page 324)
UARTIM, type R/W, offset 0x038, reset 0x0000.0000 (see page 326)
RXIFLSEL
RXIM
TXIFLSEL
OEIM
BEIM
PEIM
PERIS
PEMIS
PEIC
FEIM
FERIS
FEMIS
FEIC
RTIM
RTRIS
RTMIS
RTIC
TXIM
TXRIS
TXMIS
TXIC
UARTRIS, type RO, offset 0x03C, reset 0x0000.000F (see page 328)
OERIS
BERIS
RXRIS
RXMIS
RXIC
UARTMIS, type RO, offset 0x040, reset 0x0000.0000 (see page 329)
OEMIS
BEMIS
UARTICR, type W1C, offset 0x044, reset 0x0000.0000 (see page 330)
OEIC
BEIC
UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 332)
PID4
UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 333)
UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 334)
UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 335)
UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011 (see page 336)
UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 337)
UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 338)
PID5
PID6
PID7
PID0
PID1
PID2
470
July 24, 2012
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Stellaris® LM3S102 Microcontroller
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 339)
UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 340)
UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 341)
UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 342)
UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 343)
PID3
CID0
CID1
CID2
CID3
Synchronous Serial Interface (SSI)
SSI0 base: 0x4000.8000
SSICR0, type R/W, offset 0x000, reset 0x0000.0000 (see page 357)
SCR
SPH
SPO
FRF
DSS
SSICR1, type R/W, offset 0x004, reset 0x0000.0000 (see page 359)
SOD
MS
SSE
LBM
SSIDR, type R/W, offset 0x008, reset 0x0000.0000 (see page 361)
SSISR, type RO, offset 0x00C, reset 0x0000.0003 (see page 362)
SSICPSR, type R/W, offset 0x010, reset 0x0000.0000 (see page 364)
SSIIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 365)
SSIRIS, type RO, offset 0x018, reset 0x0000.0008 (see page 367)
SSIMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 368)
SSIICR, type W1C, offset 0x020, reset 0x0000.0000 (see page 369)
SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 370)
SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 371)
SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 372)
DATA
BSY
RFF
RNE
TNF
TFE
CPSDVSR
TXIM
RXIM
RXRIS
RXMIS
RTIM
RTRIS
RTMIS
RTIC
RORIM
RORRIS
RORMIS
RORIC
TXRIS
TXMIS
PID4
PID5
PID6
July 24, 2012
471
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Register Quick Reference
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 373)
SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022 (see page 374)
SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 375)
SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 376)
SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 377)
SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 378)
SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 379)
SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 380)
SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 381)
PID7
PID0
PID1
PID2
PID3
CID0
CID1
CID2
CID3
Inter-Integrated Circuit (I2C) Interface
I2C Master
I2C 0 base: 0x4002.0000
I2CMSA, type R/W, offset 0x000, reset 0x0000.0000
I2CMCS, type RO, offset 0x004, reset 0x0000.0000 (Reads)
I2CMCS, type WO, offset 0x004, reset 0x0000.0000 (Writes)
I2CMDR, type R/W, offset 0x008, reset 0x0000.0000
I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001
I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000
I2CMRIS, type RO, offset 0x014, reset 0x0000.0000
SA
R/S
BUSY
RUN
BUSBSY
IDLE
ARBLST DATACK ADRACK ERROR
ACK
STOP
START
DATA
TPR
IM
RIS
472
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Stellaris® LM3S102 Microcontroller
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
I2CMMIS, type RO, offset 0x018, reset 0x0000.0000
I2CMICR, type WO, offset 0x01C, reset 0x0000.0000
I2CMCR, type R/W, offset 0x020, reset 0x0000.0000
MIS
IC
SFE
MFE
LPBK
Inter-Integrated Circuit (I2C) Interface
I2C Slave
I2C 0 base: 0x4002.0000
I2CSOAR, type R/W, offset 0x800, reset 0x0000.0000
OAR
I2CSCSR, type RO, offset 0x804, reset 0x0000.0000 (Reads)
I2CSCSR, type WO, offset 0x804, reset 0x0000.0000 (Writes)
I2CSDR, type R/W, offset 0x808, reset 0x0000.0000
I2CSIMR, type R/W, offset 0x80C, reset 0x0000.0000
I2CSRIS, type RO, offset 0x810, reset 0x0000.0000
I2CSMIS, type RO, offset 0x814, reset 0x0000.0000
I2CSICR, type WO, offset 0x818, reset 0x0000.0000
FBR
TREQ
RREQ
DA
DATA
DATAIM
DATARIS
DATAMIS
DATAIC
Analog Comparator
Base 0x4003.C000
ACMIS, type R/W1C, offset 0x000, reset 0x0000.0000 (see page 423)
ACRIS, type RO, offset 0x004, reset 0x0000.0000 (see page 424)
ACINTEN, type R/W, offset 0x008, reset 0x0000.0000 (see page 425)
IN0
IN0
IN0
ACREFCTL, type R/W, offset 0x010, reset 0x0000.0000 (see page 426)
EN
RNG
VREF
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Register Quick Reference
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
ACSTAT0, type RO, offset 0x020, reset 0x0000.0000 (see page 427)
OVAL
CINV
ACCTL0, type R/W, offset 0x024, reset 0x0000.0000 (see page 428)
ASRCP
ISLVAL
ISEN
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Stellaris® LM3S102 Microcontroller
C
Ordering and Contact Information
C.1
Ordering Information
L M 3 S n n n n – g p p s s – r r m
Part Number
nnn = Sandstorm-class parts
nnnn = All other Stellaris® parts
Shipping Medium
T = Tape-and-reel
Omitted = Default shipping (tray or tube)
Temperature
E = –40°C to +105°C
Revision
I = –40°C to +85°C
Speed
Package
20 = 20 MHz
25 = 25 MHz
50 = 50 MHz
80 = 80 MHz
BZ = 108-ball BGA
QC = 100-pin LQFP
QN = 48-pin LQFP
QR = 64-pin LQFP
Table C-1. Part Ordering Information
Orderable Part Number
LM3S102-IQN20-C2
LM3S102-IQN20-C2T
Description
Stellaris® LM3S102 Microcontroller Industrial Temperature 48-pin LQFP
Stellaris LM3S102 Microcontroller Industrial Temperature 48-pin LQFP
Tape-and-reel
LM3S102-EQN20-C2
LM3S102-EQN20-C2T
Stellaris LM3S102 Microcontroller Extended Temperature 48-pin LQFP
Stellaris LM3S102 Microcontroller Extended Temperature 48-pin LQFP
Tape-and-reel
LM3S102-IRN20-C2a
LM3S102-IRN20-C2Ta
Stellaris LM3S102 Microcontroller Industrial Temperature 28-pin SOIC
Stellaris LM3S102 Microcontroller Industrial Temperature 28-pin SOIC
Tape-and-reel
LM3S102-ERN20-C2a
LM3S102-ERN20-C2Ta
Stellaris LM3S102 Microcontroller Extended Temperature 28-pin SOIC
Stellaris LM3S102 Microcontroller Extended Temperature 28-pin SOIC
Tape-and-reel
a. OBSOLETE: TI has discontinued production of this device.
C.2
Part Markings
The Stellaris microcontrollers are marked with an identifying number. This code contains the following
information:
■ The first line indicates the part number, for example, LM3S9B90.
■ In the second line, the first eight characters indicate the temperature, package, speed, revision,
and product status. For example in the figure below, IQC80C0X indicates an Industrial temperature
(I), 100-pin LQFP package (QC), 80-MHz (80), revision C0 (C0) device. The letter immediately
following the revision indicates product status. An X indicates experimental and requires a waiver;
an S indicates the part is fully qualified and released to production.
■ The remaining characters contain internal tracking numbers.
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Ordering and Contact Information
C.3
Kits
The Stellaris Family provides the hardware and software tools that engineers need to begin
development quickly.
■ Reference Design Kits accelerate product development by providing ready-to-run hardware and
comprehensive documentation including hardware design files
■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris microcontrollers
before purchase
■ Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box
See the website at www.ti.com/stellaris for the latest tools available, or ask your distributor.
C.4
Support Information
For support on Stellaris products, contact the TI Worldwide Product Information Center nearest you:
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm.
476
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Stellaris® LM3S102 Microcontroller
D
Package Information
D.1
28-Pin SOIC Package
D.1.1
Package Dimensions
Figure D-1. Stellaris LM3S102 28-Pin SOIC Package1
Note: The following notes apply to the package drawing.
1. Dimension "D" does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions,
and gate burrs shall not exceed .006" (0.15 mm) per side.
2. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusion
shall not exceed .010" (0.25 mm) per side.
3. "L" is the length of terminal for soldering to a substrate.
4. "N" is the number of terminal positions.
5. Terminal numbers are shown for reference only.
6. The lead width "B", as measured .014" (0.36 mm) or greater above the seating plane, shall not
exceed a maximum value of .024" (0.61 mm).
7. Reference drawing JEDEC MS013, Variation AE.
1OBSOLETE: TI has discontinued production of this device.
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Package Information
Dimension in Inch
Dimension in mm
MIN
Symbol
MIN
MAX
.014
.012
.020
.013
.713
.299
MAX
2.65
0.30
0.51
.032
18.10
7.60
A
A1
B
C
D
E
e
.093
.004
.013
.009
.696
.291
0.050 BSC
.394
.010
.016
.021
0°
2.35
0.10
0.33
0.23
17.70
7.40
1.27 BSC
10.00
0.25
H
h
.419
.029
.050
.031
8°
10.65
0.75
1.27
.0787
8°
L
0.40
S
α
0.533
0°
478
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Stellaris® LM3S102 Microcontroller
D.2
48-Pin LQFP Package
D.2.1
Package Dimensions
Figure D-2. Stellaris LM3S102 48-Pin LQFP Package
Note: The following notes apply to the package drawing.
1. All dimensions are in mm.
2. Dimensions shown are nominal with tolerances indicated.
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Package Information
3. Foot length "L" is measured at gage plane 0.25 mm above seating plane.
4. L/F: Eftec 64T Cu or equivalent, 0.127 mm (0.005") thick.
Package Type
Symbol
48LD LQFP
Note
MIN
MAX
1.60
0.15
1.40
A
A1
A2
D
-
0.05
-
9.00
7.00
9.00
7.00
0.60
0.50
0.22
0° - 7°
0.08
0.08
D1
E
E1
L
e
b
theta
ddd
ccc
JEDEC Reference Drawing
Variation Designator
MS-026
BBC
480
July 24, 2012
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NRND: Not recommended for new designs.
Stellaris® LM3S102 Microcontroller
D.2.2
Tray Dimensions
Figure D-3. 48-Pin LQFP Tray Dimensions
July 24, 2012
481
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Package Information
482
July 24, 2012
Texas Instruments-Production Data
NRND: Not recommended for new designs.
Stellaris® LM3S102 Microcontroller
D.2.3
Tape and Reel Dimensions
Figure D-4. 48-Pin LQFP Tape and Reel Dimensions
July 24, 2012
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Texas Instruments-Production Data
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