LM4312 [TI]
LM4312 Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with Optional Dithering and Look Up Table;
| 型号： | LM4312 |
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TEXAS INSTRUMENTS |
| 描述： | LM4312 Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with Optional Dithering and Look Up Table |
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LM4312
www.ti.com
SNLS265A –MAY 2008–REVISED MAY 2013
LM4312 Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with
Optional Dithering and Look Up Table
Check for Samples: LM4312
1
FEATURES
DESCRIPTION
The LM4312 is a MPL-2 Serializer (SER) that accepts
a 24- or 18-RGB interface and serializes this wide
bus to 3 differential signals. The optional Dithering
feature can reduce 24-bit RGB to 18-bit RGB. The
optional Look Up Table (Three X 256 X 8 bit RAM) is
provided for independent color correction. 18-bit
Bufferless displays from QVGA (320 x 240) up to
>VGA (640 x 480) pixels are supported.
2
•
RGB Display Interface to >640 x 480 (VGA)
Resolution
•
•
•
24 or 18-bit RGB Transport
24–to–18-bit RGB Dithering Option
Look Up Table Option for Independent Color
Correction Option
•
•
Robust MPL-2 Differential SLVS Interface
The interconnect is reduced from 28 LVCMOS
signals (RGB888+V+H+DE+PCLK) to only 3 active
differential signals (DD0P/M, DCP/M, DD1P/M) with
the LM4312 Serializer and companion LM4310
Deserializer easing flex interconnect design, size
constraints and cost.
SPI Interface for Configuration / Control and
LUT Options
•
•
•
Low Power Consumption & SLEEP State
Auto Power Down on STOP PCLK
Automatically Generates Frame Sequence Bits
for Resync upon Data or Clock Error
The LM4312 SER resides by the application, graphics
or baseband processor and translates the wide
parallel video bus from LVCMOS levels to serial
MPL-2 levels for transmission over a flex cable and
PCB traces to the DES located in the display module.
•
Odd Parity Generation
SYSTEM BENEFITS
•
•
•
•
•
Dithered Data Reduction
Independent RGB Color Correction
24-bit Color Input
When in Power_Down, the SER is put to sleep and
draws less than 10μA. The SER can be powered
down by stopping the PCLK or by asserting its PD*
input pin.
Small Robust Interface
Low Power & Low EMI
The LM4312 implements the physical layer of the
MPL-2 Interface and features robust common-mode
noise rejection.
Typical Application Diagram - Bridge Chips - 24-bit to 18-bit RGB
LM4312 Serializer
LM4310 Deserializer
Apps
Processor
---
Graphics
Processor
---
D
i
t
R[7:0]
G[7:0]
B[7:0]
VS
HS
DE
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
DD0
P
2
h
S
2
P
S
e
r
DC
RGB Display
VGA
Baseband
Processor
PCLK
PCLK
DD1
18-Bit Color Depth
PE
PLL
SPI_CSX
SPI_SCL
SPI_DI
PCLK
S
P
I
PD*
Three
256 x 8
LUTs
RDS
Config.
Mode24
SPI_DO
PD*
Configuration
[Supply, all Configuration pins, and bypass caps. and grounding not shown]
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2008–2013, Texas Instruments Incorporated
LM4312
SNLS265A –MAY 2008–REVISED MAY 2013
www.ti.com
Pin Descriptions
No.
Pin Name
Description
RGB Serializer
I/O, Type(1)
of Pins
MPL-2 SERIAL BUS PINS
DD0P, DD0M,
DD1P, DD1M
4
2
O, MPL-2
O, MPL-2
MPL-2 Differential Data Line Driver True (Plus) and Compliment (Minus) Outputs
Channel 0 and 1
DCP, DCM
MPL-2 Differential Clock Line Driver True (Plus) and Compliment (Minus) Outputs
SPI INTERFACE and CONFIGURATION PINS
SPI_CSX
SPI_SCL
SPI_DI
SPI_DO
PD*
1
1
1
1
1
I,
SPI_Chip Select Input
SPI port is enabled when: SPI_CSX is Low, PD* is High.
LVCMOS
I,
SPI_Clock Input
SPI Data Input
SPI Data Output
LVCMOS
I,
LVCMOS
O,
LVCMOS
I,
Power Down Mode Input
LVCMOS
PD* = Low, SER is in SLEEP Mode,
SPI Registers are RESET, LUT Data is retained.
PD* = High and PCLK = Stopped, SER is in SLEEP Mode,
SPI Register settings are retained and LUT data is retained.
PD* = High, Device is enabled.
RES1
TM
1
1
I,
Tie High
LVCMOS
I
Tie Low
LVCMOS
H = Test Mode (Reserved)
VIDEO INTERFACE PINS
PCLK
1
I,
Pixel Clock Input
LVCMOS
Video Signals are latched on the RISING edge.
R[7:0]
G[7:0]
B[7:0]
24
I,
RGB Data Bus Inputs – Bit 7 is the MSB.
24-bit Mode - use RGB[7:0]
18-bit Mode - use RGB[7:2], tie off RGB[1:0] to GND, do not float.
LVCMOS
VS
1
I,
Vertical Sync. Input
LVCMOS
This signal is used as a frame start for the Dither block and is required when
Dither option is selected.
The VS signal is serialized unmodified.
HS
DE
1
1
I,
Horizontal Sync. Input
Data Enable Input
LVCMOS
I,
LVCMOS
POWER/GROUND PINS
VDD
7
1
Power Supply Power Supply Pins. All VDD pins must be connect to power supply.
1.6V to 2.0V
VSS
Ground
Ground Pin
DAP pad must be connected to Ground.
(1) Note: I = Input, O = Output, IO = Input/Output. Do not float unused input pins.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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SNLS265A –MAY 2008–REVISED MAY 2013
(1)(2)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD
)
−0.3V to +2.2V
−0.3V to (VDD +0.3V)
−0.3V to VDD
+150°C
LVCMOS Input/Output Voltage
MPL-2 Output Voltage
Junction Temperature
Storage Temperature
ESD Ratings:
−65°C to +150°C
≥±2 kV
HBM, 1.5 kΩ, 100 pF
EIAJ, 0Ω, 200 pF
≥±200V
Maximum Package Power Dissipation
Capacity at 25°C
X2QFN Package
2.25 W
Derate X2QFN Package above 25°C
22.57 mW/°C
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply
that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
RECOMMENDED OPERATING CONDITIONS
Min
1.6
5
Typ
Max
2.0
30
Units
V
Supply Voltage
VDD to VSS
1.8
Pixel Clock Frequency (6X)
Pixel Clock Frequency (8X)
DC Frequency
MHz
MHz
MHz
°C
5
30
30
−40
240
85
Ambient Temperature
25
ELECTRICAL CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Symbol
MPL-2
VOD
Parameter
Conditions
Min
Typ
Max
Units
(3)
Differential Output Voltage
100 Ω Load
See
VOD setting
VOD setting
VOD = 150
95
150
200
0
211
270
10
mV
|mV|
mV
140
(3)
ΔVOD
Delta Differential Output
Voltage
Match of
See
Differential
Output Voltage
magnitude
between logic
states.
VOD = 200
0
10
(3)
VOS
Differential Driver Offset
Voltage
100 Ω Load
See
VOD = 150
VOD = 200
VOD = 150
112
150
150
200
0
188
250
5
(3)
ΔVOS
Differential Driver Offset
Voltage Match
Match of Driver See
Offset Voltage
magnitude
|mV|
VOD = 200
0
5
between logic
states.
ROUT
Driver Output Impedance
50
Ω
LVCMOS (1.6V to 2.0V Operation)
VIH
VIL
Input Voltage High Level
Input Voltage Low Level
Input Hysteresis
0.7 VDD
GND
VDD
V
V
0.3 VDD
VHY
IIN
100
0
mV
µA
V
Input Current
−1
0.8 VDD
VSS
+1
VDD
VOH
VOL
Output Voltage High Level
Output Voltage Low Level
SPI_DO
IOH = −1 mA
IOL = 1 mA
0.2 VDD
V
(1) Typical values are given for VDD =1.8V and TA = 25°C.
(2) Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground
unless otherwise specified.
(3) Specification is ensured by design or characterization
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Units
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
SUPPLY CURRENT
IDD
Total Supply Current -
RGB24 Mode.
DC = 240 MHz, Checker
VOD = 150
VOD = 200
VOD = 150
VOD = 200
VOD = 150
VOD = 200
VOD = 150
VOD = 200
20
22
15
17
17
19
13
15
1
(4)
Board, LUT Enable, Dither
mA
mA
mA
mA
(5)
33
Disable.
DC = 160 MHz, Checker
Board, LUT Enable, Dither
Disable
Total Supply Current -
RGB18 Mode.
DC = 180 MHz, Checker
Board, LUT Enable, Dither
Disable.
DC = 120 MHz, Checker
Board, LUT Enable, Dither
Disable.
IDDZ
Supply Current—Disable
Power Down Modes
PD* = L
10
10
µA
µA
Ta = 25°C
Stop Clock: PD* = H and
PCLK = L or H
1
mW
PD
Power Dissipation
VOD = 200 mV, VDD = 1.8 V
27
(4) For IDD tests - input signal conditions are: (swing, edge, freq, DE = H, VS = L, HS = L, RGB Checkerboard Pattern: AAAAAA-555555)
(5) Total Supply Current Conditions: SER CL= 15 pF, TYP VDD = 1.8V.
SWITCHING CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
PARALLEL BUS TIMING
tSET
Set Up Time
Hold Time
SER Inputs: RGB, VS, HS, DE to PCLK
Figure 1
5
5
ns
ns
tHOLD
SER Inputs: PCLK to RGB, VS, HS, DE
Figure 1
MPL-2 SERIAL BUS TIMING
(2) (3)
tDVBC
tDVAC
tT
Serial Data Valid before Clock SER Data Pulse Width Figure 2,
Edge
0.3
0.3
0.7
0.7
UI
Serial Data Valid after Clock
Edge
UI
ps
(4)
Transition Time
See
300
POWER UP TIMING
tPLL
PLL Lock Time
PCLK
cycles
1024
(5)
tPZXclk
Enable Time - Clock Start
PCLK to DCOUT Figure 4, Figure 8
See
MPL-2 POWER OFF TIMING
(6)
tPAZ
Disable Time to Power Down
Disable Time - Clock Stop
See
15
ms
(7)
tPXZclk
PCLK to DCOUT Figure 3
PCLK
cycles
2
SPI INTERFACE
tACC SPI Data Active (SPI_DO)
tOHR SPI Data Tri-State (SPI_DO)
See Figure 15
0
0
50
50
ns
ns
(3)
See Figure 15
(1) Typical values are given for VDD =1.8V and TA = 25°C.
(2) 1 UI is the serial data DD pulse width = 1 / 12xPCLK (18-bit mode), 1 UI is the serial data DD pulse width = 1 / 16xPCLK (24-bit mode)
(3) Specification is ensured by design or characterization
(4) MPL-2 serial link transition time is measured from 20% to 80 %.
(5) Enable Time is a complete MPL-2 start up t1+t2+t3. See also Figure 8.
(6) Specified functionally by the IDDZ parameter. See also Figure 9.
(7) This is the minimum time that the PCLK needs to be held off for in order for the device to be reset. Once PCLK is reapplied, a PLL Lock
is required and start up sequence before video data is serialized.
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RECOMMENDED INPUT TIMING REQUIREMENTS (PCLK AND SPI)
Over recommended operating supply and temperature ranges unless otherwise specified.
(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
PIXEL CLOCK (PCLK)
fPCLK
Pixel Clock Frequency
18-bit RGB Mode (6X)
5
5
30
30
70
MHz
MHz
%
24-bit RGB Mode (8X)
PCLKDC
tT
Pixel Clock Duty Cycle
Input Transition Time
Clock Stop Gap
30
2
50
>2
(2)(3)
See
ns
tSTOPpclk
PCLK
cycles
(4) (3)
See
4
2
SPI INTERFACE
fSCLw
fSCLr
ts0
SPI_SCL Frequency
WRITE
READ
10
MHz
MHz
ns
6.67
SPI_CSX Set Time
SI Set Time
60
30
30
35
60
35
60
ts1
See Figure 14
ns
th1
SI Hold Time
ns
tw1h
SPI_SCL Pulse Width High
WRITE
READ
WRITE
READ
ns
ns
See Figure 14 ,
Figure 15
tw1l
SPI_SCL Pulse Width Low
ns
ns
tr
SPI_SCL Rise Time
SPI_SCL Fall Time
SI Hold Time
5
5
ns
tf
ns
t0H
th0
tw2
See Figure 14
30
65
ns
SPI_CSX Hold Time
SPI_CSX OFF Time
ns
100
ns
(1) Typical values are given for VDD =1.8V and TA = 25°C.
(2) Maximum transition time is a function of clock rate and should be less than 30% of the clock period to preserve signal quality.
(3) Specification is ensured by design or characterization
(4) This is the minimum time that the PCLK needs to be held off for in order for the device to be reset. Once PCLK is reapplied, a PLL Lock
is required and start up sequence before video data is serialized.
TIMING DIAGRAMS
VS
HS
PCLK
tSET
tHOLD
Data,
DE
Figure 1. Input Timing for RGB Interface
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DC
DD0,
DD1
tDVBC tDVAC
tDVBC
tDVAC
Figure 2. Serial Data Valid
PCLKin
Active DC
DC
OUT
DC OFF
t
PXZclk
Figure 3. Stop Pixel Clock (PCLK) Power Down
PCLKin
DC
OUT
active DC
DC OFF
t
PZXclk
Figure 4. Stop Pixel Clock (PCLK) Power Up
CSX
(host)
SCL
(host)
t
0HR
SDA
(host)
A0
t
SDA
ACC
SDA
(device)
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. SPI Interface
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FUNCTIONAL DESCRIPTION
The LM4312 is a Mobile Pixel Link two Serializer that serializes a 24-bit RGB plus three control signals (VS, HS,
and DE) to two MPL-2 DD lines plus the serial clock DC line. 18-bit RGB, 24-bit RGB, or optionally 24-bit RGB
data is dithered to 18 bits and then serialized and level translated to MPL-2 by the SER. An optional Look Up
Table consisting of three 256 X 8-bit RAMs may also be used and is controlled via a 3 or 4-wire SPI interface.
The LM4312 is compatible with the LM4310 Deserializer and also Display Drivers with integrated MPL-2
Deserializers.
Three link configurations are provided by the LM4312 SER. 24-bit RGB can be serialized onto the 2 DD + DC
configuration using a 8X DC clock. 24-bit RGB can be dithered to 18-bit RGB and serialized onto the 2 DD + DC
configuration using a 6X DC clock. Or 18-bit RGB can be serialized onto the 2 DD + DC configuration using a 6X
DC clock. See Table 1. The device's default configuration is for 18 bits input, Dither OFF, and 6X mode.
LM4312
DD0P
DD0
R[7:0]
DD0M
L
A
T
C
H
D
I
T
H
E
R
G[7:0]
DCP
DCM
P
2
S
DC
/
B[7:0]
DD1P
DD1M
F
I
F
O
VS, HS, DE
DD1
PCLK
LUT
Enable
SPI_CSX
SPI_SCL
SPI_DI
S
PLL
P
I
Three X 256 X 8
Look Up Table
I
/
F
PCLK
SPI_DO
PD*
TM
CONFIGURATION
Figure 6. General LM4312 Block Diagram
Table 1. 2DD+DC MPL-2 Link Options
Input
Serial
Output
Notes
24-bit RGB
24-bit RGB
18-bit RGB
2 DD + DC, Figure 10
2 DD + DC, Figure 11
2 DD + DC, Figure 11
24-bit RGB
18-bit RGB
18-bit RGB
Dither OFF, DC = 8X PCLK
Dither ON, DC = 6X PCLK
Dither OFF, DC = 6X PCLK
BUS OVERVIEW
The LM4312 is a multi-lane MPL-2 Serializer that supports an 18-bit or 24-bit RGB source interface. The MPL-2
physical layer is purpose-built for robustness, low power and low EMI data transmission while requiring the
fewest number of signal lines. No external line components are required, as termination is provided internal to
the MPL-2 receiver. The differential interface conforms to the JEDEC SLVS (Scalable Low Voltage Signalling)
Interface standard. A maximum raw throughput of >900 Mbps (2-lane raw) is possible with this chipset. The
MPL-2 interface is designed for use with 80Ω to 100Ω differential lines. Lines may be microstrip or stripline
construction.
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SERIAL BUS TIMING
Data valid is relative to both edges of a RGB transaction as shown in Figure 7. Data valid is specified as: Data
Valid before Clock, Data Valid after Clock, and Skew between data lines should be less than 500ps.
DC
DD0
DD1
Figure 7. Dual Link Timing
SERIAL BUS PHASES
There are three bus phases on the RGB MPL-2 serial bus. These are determined by the state of the DC and DD
lines. The MPL-2 bus phases are shown in Table 2.
Table 2. Link Phases
Name
DC State
DDn State
Phase Description
Pre-Phase
A, or LU
O
Post-Phase
OFF (O)
GND
GND
Link is Off
Start Up
LU
A or O
O
LINK-UP (LU)
ACTIVE (A)
L
L
A
X
Streaming Data
LU
SERIAL BUS START UP TIMING
In the Serial Bus OFF phase, SER differential outputs are all driven to Ground.
When the SER is enabled, the differential outputs are driven to valid static High state until the SER PLL is
locked. Then the DC becomes active and data is streamed to the DES.
Link-Up is shown in Figure 8. The DC and DDn signals are shown both as single-ended and differential
waveforms.
Link
Off
Bus
Phase
Link-Up
active
PD*
(SER)
PD*
(DES)
LVCMOS
PCLK
(SER)
SE
SLVS
SLVS
t
Start
DIFF
SLVS
t
1
t
t
3
2
Figure 8. MPL-2 - LM4312 Link Up Timing
OFF PHASE
In the Serial Bus OFF phase, SER differential outputs are all driven to Ground. Figure 9 shows the transition of
the MPL-2 bus into the OFF phase.
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Bus
Phase
Active
Off
PD*
DIFF
SE
0V
300 mV
100 mV
0V (GND)
Figure 9. MPL-2 - LM4312 Link Off Timing
RGB VIDEO INTERFACE
The LM4312 is transparent to data format and control signal polarity timing. Each PCLK, RGB inputs, HS, VS
and DE are sampled on the rising edge of the PCLK. A PCLK by PCLK representation of these signals is
duplicated on the opposite device after being transferred across the MPL-2 interface.
The LM4312 can accommodate a wide range of display formats. QVGA to >VGA can be supported within the
5MHz to 30 MHz PCLK input range.
Three operating modes of the link are possible (see Table 1).
The 24-bit RGB (R[7:0], G[7:0], B[7:0]) color information is serialized, followed by the control bits VS (VSYNC),
HS (HSYNC), DE (Data Enable) and PE (Odd Parity) and Frame Sequence (F[1:0]) bits. The DC clock is 8X the
PCLK, and 32 serial bits are sent per PCLK. The two additional Reserved (Low) bits are sent to complete the
payload.
DC
Res
L
Res
L
DD0 R0
R1
R3
R4
R6
R5
R7
G0
G2
G1
G3
G4
G6
G5
G7
B0
B2
B1
B3
B4
B6
B5
B7
R0
R2
DE
F0
PE
F1
R2
DD1
VS
HS
Figure 10. 24-bit RGB, 2 DD + DC Lane Serial Payload (8X)
When Dither option is enabled, the 24-bit RGB (R[7:0], G[7:0], B[7:0]) color information is Dithered to 18 bits,
then serialized, followed by the control bits VS (VSYNC), HS (HSYNC), DE (Data Enable) and PE (Odd Parity)
and Frame Sequence (F[1:0]) bits. The DC clock is 6X the PCLK, and 24 serial bits are sent per PCLK
With Dithering disabled, 18-bit RGB (R[7:2], G[7:2], B[7:2]) color information is serialized, followed by the control
bits VS (VSYNC), HS (HSYNC), DE (Data Enable) and PE (Odd Parity) and Frame Sequence (F[1:0]) bits.
Unused inputs (RGB[1:0]) must be tied off, do not float. The DC clock is 6X the PCLK, and 24 serial bits are sent
per PCLK.
At a PCLK of 20.8 MHz, a 125 MHz DC clock is generated. The data lanes use both clock edges, thus 250 Mbps
(raw) are sent per DD lane for a 500Mbps maximum throughput for the 2DD+DC configuration.
DC
DD0
DD1
R0
R2
R1
R3
R4
G0
R5
G1
G2
G4
G3
G5
B0
B2
B1
B3
B4
VS
B5
HS
DE
F0
PE
F1
R0
R2
Figure 11. 24-bit dithered to 18-bit RGB / 18-bit RGB, 2 DD + DC Lane Serial Payload (6X)
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SERIAL PAYLOAD PARITY BIT
Odd Parity is calculated on the RGB bits, control (VS, HS, and DE) bits and F0, F1 bits and then sent from the
SER to the DES via the serial PE bit. See DES Data sheets to determine how the parity bit is handled by the
DES device.
FRAME SEQUENCE — SYNC DETECT AND RECOVERY
If a data error or clock slip error occurs over the MPL-2 link, the RGB MPL-2 Deserializer can detect this
condition and quickly recover from it. The method chosen is a data transparent method, and has very little
overhead because it does not use a data expansion coding method. For the 18-bit RGB color transaction, it uses
two bits that are already required in the 6 DC cycle transaction. Total overhead for each pixel is 3/24 or 12.5%,
where the 3 bits are PE, F0 and F1.
The LM4312 MPL-2 RGB Serializer simply increments the two bit field F[1:0] on every pixel (MPL-2 frame)
transmitted. Therefore every four MPL-2 frames, the pattern will repeat. It is very unlikely that this pattern would
be found within the payload data, and if it were found, the probability that it would repeat for many frames
becomes infinitely small. This code is used by the MPL-2 Deserializer to detect any frame alignment problems
and quickly recover.
The RGB MPL-2 Deserializer, upon a normal power up sequence, uses the FS bits to obtain bit alignment. Once
this is obtained, correct pixel data is recovered and driven to the display. If synchronization is lost for any reason,
the DES searches for the incrementing pattern. Once found, it resynchronizes the output pixel data and timing
signals. See MPL-2 DES Datasheet for details on how the specific DES handles the Frame Sequence.
OPTIONAL DITHERING FEATURE
The LM4312 provides an optional Dithering mode. When selected, 24-bit RGB input data is internally dithered to
18-bits using a high-quality stochastic dithering process. This process has a "blue noise" characteristic that
minimizes the visibility of the dither patterns. The resulting data stream of 18-bit data is then serialized and
transmitted via MPL-2.
The Dither circuitry requires the VS control signal for proper operation. This signal is used to generate an
internal signal that marks the start of the (video) frame. The serializer samples and sends the VS information
unmodified.
Dithering parameters are controlled by two registers. When the dithering is bypassed, only RGB[7:2] is serialized
and transmitted for 18-bit input RGB [5:0] (MSB aligned). Input RGB[1:0] should not be connected and the
unused inputs should be tied low; do not float. Dithering option is off by default.
OPTIONAL LOOK UP TABLE
The look up table is comprised of three 256 Byte SRAMs. It may be used for independent color correction. When
the LM4312 is in the 24-bit RGB mode, the full 8-bits per color are used for addressing the 256 Bytes for each
color. When the LM4312 is used in an 18-bit RGB mode and the LUT is desired, all 8-bits per color are still used
for the LUT look-up. The 6 active bits from each color are used for addressing 64 locations in the LUT. The two
LSBs of the 8-bit bus can be tied to 00, and every fourth location of the SRAM where the two LSBs equal 00,
(addresses 0x00, 0x04, 0x08, 0x0c, etc.) will be used." Or, the two LSBs of the 8-bits can be tied to 01 and every
fourth location of the SRAM where the low two bits equal 01(addresses 0x01, 0x05, 0x09, 0x0d, etc.) will be
used and so on. Selecting the two LSBs with GPIOs (0x0, 0x1, 0x2, and 0x3) allows for four different color
correction tables to be accessed. The LUT is disabled by default and also after a device PD* cycle. The PD*
cycle can be entered via the PD* input pin directly, or by stopping the PCLK. When stop PCLK is used to disable
the device, LUT data is retained. Before using the LUT, the SRAM must be loaded with its contents. If power is
cycled to the device, the LUT must be loaded again.
To enable the LUT:
1. Select/Unlock the LM4312 SPI Interface - Write 0xFF to REG 0x16
2. Write the LUT contents to the SRAM using Writes or Page Writes
3. Enable the LUT - Write a 0x01 to REG 0x00
4. De-Select/Lock the LM4312 SPI interface - Write 0x00 to REG 0x16
When waking up the LM4312 from the power down mode (PD*=L), the LUT needs to be enabled if it is desired,
and the contents to the SRAM are still held and valid.
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1. Select/Unlock the LM4312 SPI Interface - Write 0xFF to REG 0x16
2. Enable the LUT - Write a 0x01 to REG 0x00
3. Optional -select desired Level Select - if not using default value
4. De-Select/Lock the LM4312 SPI interface - Write 0x00 to REG 0x16
If power is cycled to the device, the LUT SRAMs must be loaded again.
SPI INTERFACE
The Serial Peripheral Interface (SPI) allows control over various aspects of the LM4312, the Look Up Table
operation, and access to the three 256 x 8-RAM blocks. Three SPI transactions are supported, which are: 16-bit
WRITE, PAGE WRITE, and a 16-bit READ. The SPI interface is disabled when the device is in the sleep mode
via the PD* pin (PD* = L). The SPI interface may be used when PD* = H or when the device is in SLEEP via the
PCLK stop feature. A device (SER) reset function is also available via the Configuration 3 register bit 1.
Due to the Select/Unlock – De-Select/Lock feature of the device the SPI interface may be shared with the display
driver. Several connection configurations are possible. A couple examples are shown in Figure 12 and Figure 13.
SPI_DI and SPI_DO may be tied together to form a bi-directional SDA line. If READs are not required, leave the
SPI_DO pin as a NC.
16-bit WRITE
The 16-bit WRITE is shown in Figure 14. The SPI_DI payload consists of a "0" (Write Command), seven address
bits and eight data bits. The SPI_CSX signal is driven Low, and 16-bits of DI (data input) are sent to the device.
Data is latched on the rising edge of the SPI_SCL. After each 16-bit WRITE, SPI_CSX must return HIGH.
Table 3. 16-bit WRITE – SPI
Bit
DI
B15
0
B14
A6
B13
A5
B12
A4
B11
A3
B10
A2
B9
A1
B8
A0
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
16-bit READ
The 16-bit READ is shown in Figure 15. The SPI_DI payload consists of a "1" (Read Command), seven address
bits. The SPI_DO consists of eight data bits which are driven from the device. The SPI_CSX signal is driven
Low, and the host drives the first 8 bits of the DI ("1" and seven address bits), the device then drives the
respective 8 bits of the data on the DO signal.
Table 4. 16-bit READ – SPI
Bit
DI
B15
1
B14
A6
Z
B13
A5
Z
B12
A4
Z
B11
A3
Z
B10
A2
Z
B9
A1
Z
B8
A0
Z
B7
Z
B6
Z
B5
Z
B4
Z
B3
Z
B2
Z
B1
Z
B0
Z
DO
Z
D7
D6
D5
D4
D3
D2
D1
D0
PAGE WRITE
The PAGE WRITE is shown in Figure 16. The SPI_DI payload consists of a "0" (Write Command), seven
address bits of the start address and then the consecutive data bytes. 256 bytes maximum can be sent. The
SPI_CSX signal is driven Low, and the host drives the SDA signal with a "0" (Write Command), the seven start
address bits and the variable length data bytes. The Page Write is denoted by the SPI_CSX signal staying low
while the data bytes are streamed. Data is latched on the rising edge of the SPI_SCL.
There are four SPI Interface signals: SPI_CSX - SPI Chip Select, SPI_SCL - SPI Clock, DI - SPI Data In and DO
- SPI Data Out. SPI_CSX, SPI_SCL and SPI_DI are inputs on the LM4312. SPI_DO is the Data Output line for
the READ_DATA portion of a READ operation. READs are optional and are not required.
Table 5. PAGE WRITE
Bit
DI
B15
0
B14
A6
B13
A5
B12
A4
B11
A3
B10
A2
B9
A1
B8
A0
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
(start address)
D6 D5
(Data Byte 0)
D7 D6
DI
D7
D4
D3
D2
D1
D0
D5
D4
D3
D2
D1
D0
(Data Byte 1)
(Data Byte n, 256 max.)
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LM4312
CSX
SCL
SDA
CSX
SCL
SDI
C
O
N
N
DISPLAY
DRIVER
FPD95xxx
HOST
SDO
Figure 12. LM4312 WRITE & READ to 3-signal SPI HOST
LM4312
CSX
SCL
SDO
CSX
SCL
SDI
C
O
N
N
DISPLAY
DRIVER
FPD95xxx
HOST
SDO
SDI
Figure 13. LM4312 WRITE & READ to 4-signal SPI HOST
Table 6. LM4312 SPI Registers
Name
Address
Type(1)
Description
Default
Command
0x00
R/W
Bit 0 = LUT Enable
0x00
0’b = LUT Disabled, 1’b = LUT Enabled
Bit 4 = Special Register Access
0’b = SRA Locked, 1’b = SRA Unlocked
For access to Registers 0x08, 0x09, 0x0B, the Special Register Access bit
must be unlocked. Must write all 8 bits.
(2)
Reserved,
0x01
0x02
na
Reserved
LUT Red RAM
Address
R/W
Red Address - This register contains the address for the next access to the
Red LUT RAM. After every read or write access to the Red Data Register,
this register auto-increments.
0x00
LUT Red RAM Data
0x03
0x04
R/W
R/W
Red Data
0xXX
0x00
LUT Green RAM
Address
Green Address - This register contains the address for the next access to the
Green LUT RAM. After every read or write access to the Green Data
Register, this register auto-increments.
LUT Green RAM Data
0x05
0x06
R/W
R/W
Green Data
0xXX
0x00
LUT Blue RAM
Address
Blue Address - This register contains the address for the next access to the
Blue LUT RAM. After every read or write access to the Blue Data Register,
this register auto-increments.
LUT Blue RAM Data
0x07
R/W
Blue Data
0xXX
(1) If a WRITE is done to a reserved bits, data should be all 0’s. If a READ is done to a reserved location, either 1’s or 0’s may be returned.
Mask reserved data bits.
(2) DO NOT write to Reserved Registers.
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Table 6. LM4312 SPI Registers (continued)
Address
Type(1)
Description
Default
Dither Configuration1
0x08
R/W
Bit 0 - Dither Bypass
1’b = Bypass Dither, 0’b = Dither ON
Bit 1 - DE INV
0x65
(3)
1’b = Active Low DE, 0’b = Active High DE
Does not alter DE signal, dither block input only.
Bit 2 - VS INV
1’b = Active Low VS signal, 0’b = Active High VS signal.
Does not alter VS signal, dither block input only.
Bit 4 - Tempen0
1’b = Transposed Dither Pattern,
0’b = Even and odd frames use same dither pattern
Bit 5 - Tempen1
1’b = Temporal Dithering is Enabled, 0’b = Disabled
Bit 6 - Dith3 - Dither Amplitude
1’b = set to 3 bits, 0’b = set to 4 bits
Dither Configuration2
0x09
R/W
Dither Parameter
Reserved, Default value recommended.
0x67
0x00
(3)
Reserved
0x0A
0x0B
na
Reserved
Configuration 3,
R/W
Bit 0 - Mode 24
1'b = 24-bit RGB Mode, 0'b= 18-bit RGB Mode
Bit 1 - SER_PD
(3)
1'b = RESET the SER, 0'b = normal mode
Bit[5:4] - Driver Level Select
00’b = VOD = 200mV
01’b = VOD = 150mV
(4)
Reserved,
0x0C-
0x15
na
R/W
na
Reserved
Device Select
(Unlock/Lock)
0x16
0xFF’h enables LM4312 SPI
All other values disables LM4312 SPI (0x00 to 0xFE)
0x00
(4)
Reserved,
0x17-
0x7F
Reserved
(3) This register must be unlocked first through bit 4 of register 0. This register is currently a write only register, read is not supported.
(4) DO NOT write to Reserved Registers.
SPI RESET BIT
Configuration 3 register, bit 1 is a device RESET function. When this bit is set to a 1, the device is placed into
reset. When this bit is a 0, the device is in normal mode and is controlled by the PCLK and PD* signal pins.
SPI Timing
CSX
(host)
t
s0
t
t
t
t
f
w1H
w1L
r
th0
tw2
SCL
(host)
t
h1
t
s1
SDA
(host)
0
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 14. 16-bit SPI WRITE
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CSX
(host)
t
h0
t
w2
SCL
(host)
SDA
(host)
1
A6
A5
A4
A3
A2
A1
A0
t
0HR
t
ACC
SDA
(device)
D7 D6
D5
D4
D3
D2
D1
D0
Figure 15. 16-bit SPI READ
CSX
(host)
SCL
(host)
SDA
(host)
0
A6
A5
A0
D7
D1
D0
D7
D0
D7
D1
D0
Data Byte n
(256 maximum)
Data Byte 0
Data Byte 1
Figure 16. SPI Page Write
Figure 14, Figure 15, and Figure 16 show a 3–wire SPI Interface with the (LM4312) SPI_DI and (LM4312)
SPI_DO pins tied together to form a bi-directional SPI data signal SDA. In the 16–bit READ, the SPI HOST
drives the first 8 bits of the operation, and the SPI target (LM4312) drives the last 8 bits as shown in Figure 15.
RGB888
DD0
DDO
DDC
DD1
VS
HS
DC
F
P
D
9
LM4312
DD1
DE
PCLK
PD*
5
H
O
S
T
X
X
X
CSX
CSX
SCL
DI
SCL
SDO
SDI
DO
RSTN
RST_N
8 Signals
FLEX
33
Signals
PCB
GLASS
Figure 17. Typical Application Connection Diagram
In Figure 17, 33 host signals are reduced to only 7 or 8 signals. The reduced width interface to the display
includes: 3 differential signals (DD0, DC, DD1), a Display Driver Reset signal (RSTN) and 3 or 4 wire SPI
interface.
LM4312 Operation
POWER SUPPLY & BYPASS RECOMMENDATION
The VDD power supply pins are intended to be connected together to the same plane.
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Bypass capacitors should be placed near the power supply pins of the device. Use high frequency ceramic
(surface mount recommended) 0.1 µF capacitors. A 2.2 to 4.7 µF Tantalum capacitor is recommended near the
SER for PLL bypass. Connect bypass capacitors with wide traces and use dual or larger via to reduce resistance
and inductance of the feeds. Utilizing a thin spacing between power and ground planes will provide good high
frequency bypass above the frequency range where most typical surface mount capacitors are less effective. To
gain the maximum benefit from this, low inductance feed points are important. Also, adjacent signal layers can be
filled to create additional capacitance. Minimize loops in the ground returns also for improved signal fidelity and
lowest emissions.
UNUSED INPUT PINS
Unused inputs must be tied to the proper input level — do not float.
PHASE-LOCKED LOOP
A PLL is enabled to generate the serial link clock. The Phase-locked loop system generates the serial data clock
at 6 or 8 of the input clock depending upon 18 or 24-bit RGB transport mode (set by SPI Register).
SLEEP MODE & STOP CLOCK
The LM4312 (SER) can eneter SLEEP (Low Power state) by two methods. The PD* pin is one method, the other
is by stopping the PCLK input (to a static level).
The PD* Input pin may be controlled by the Host. When PD* = High, the SER is enabled. When the PD* = Low,
the SER is in SLEEP Mode. Note that SPI Registers are reset to defult values, and LUT data is retained.
When using the auto power down mode, the PD* input needs to be held High. When the PCLK is held static, the
SER will detect this condition and power down. When the PCLK is restarted, the SER powers up. See Figure 3,
Figure 4, and Figure 8. The stopping of the pixel clock should be done cleanly. The minimum clock stop gap
should be at least 4 PCLK cycles wide. Floating of the PCLK input pin is not recommended. Consult the MPL-2
DES datasheet to determine requirements that the DES requires. When the SER is in SLEEP by the STOP
CLOCK feature, SPI Register and LUT contents are retained.
If power is removed from the device, SPI Register and LUT contents are reset upon power up.
Table 7. LM4312 Memory Status (LUT and SPI Registers)
Mode
LUT
SPI Registers
Power Cycle
VDDs = 0V
LUT contents are reset
Registers RESET to Defaults
Sleep State
PD* = L
LUT contents retained
LUT contents retained
Registers RESET to Defaults
Register contents retained
Sleep State
PD* = H and PCLK = static (H or L)
Application Information
SYSTEM BANDWIDTH CALCULATIONS
For a HVGA (320 X 480) application with the following assumptions: 60 Hz refresh rate, 10% blanking, RGB666,
the following calculations can be made:
Calculate PCLK - 320 X 480 X 1.1 X 60 = 10.14 MHz PCLK
Calculate DC rate - since the application is 2 DD + DC and RGB666, PCLK X 6 is the DC rate or 60.83 MHz.
Also check that this DC rate does not exceed the DC maximum rate for the chipset.
Calculate DD rate - MPL-2 uses both edges of the DC to send serialized data, thus data rate is 2X the DC rate,
or 121.7 Mbps per DD lane in our example.
Calculate the application throughput - using 2 DD lanes, throughput is 2 X of the DD rate or 243.3 Mbps of raw
band width.
For a VGA (640 X 480) application with the following assumptions: 60 Hz refresh rate, 35% blanking, RGB888,
the following calculations can be made:
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Calculate PCLK - 640 X 480 X 1.35 X 60 = 24.88 MHz PCLK
Calculate DC rate - since the application is 2 DD + DC and RGB888, PCLK X 8 is the DC rate or ~ 200 MHz.
Calculate DD rate - MPL-2 uses both edges of the DC to send serialized data, thus data rate is 2X the DC rate,
or 400 Mbps per DD lane in our example.
Calculate the application throughput - using 2 DD lanes, throughput is 2X of the DD rate or 800 Mbps of raw
band width.
SYSTEM CONSIDERATIONS
Typical VGA RGB888 Operation
A Smart Display application is shown in Figure 18. The Serializer (SER) resides by the host (BBP) and connects
to a Memory Interface. BBP Bus signals are connected as shown (PCLK, Data, DE, PD*, VS, HS, and SPI
signals). The device can be configured for 18-bit or 24-bit RGB interfaces. RGB signals are samples on the rising
edge of the PCLK, and the serial data lines use both edge of the serial clock. The SER requires a pixel clock
reference which is typically 25 MHz in a VGA application. This signal is used to generate the serial DC clock.
The PCLK input is multiplied by the selected PLL multiplier to determine the serial clock rate. In the 25 MHz
PCLK and 8X application, the DC rate will be 200 MHz. Due to the serial transmission scheme using both clock
edges, the raw bandwidth is 400 Mbps per lane and device throughput is 800 Mbps. Dither and LUT options are
OFF by default and can be turned ON by device SPI programming. The SER has a SLEEP mode to save power
when the display is not active. The Sleep state is entered when the PD* signal is driven Low. It is also entered if
the PD* signal is High and the PCLK input is stopped. When PCLK stop is used to place SER into Sleep mode,
the SPI registers and the LUT content are retained. In the Sleep state, supply current into the SER is >1µA
typical. Several configuration pins are also required to be set. For a SER, tie TM = L and RES1 = H. The DES
recovers the serial signals and generates the parallel bus for the Display.
LM4312 (ser)
1.8V
1.8V
LM4310 (des)
7
7
31
VDD
VDD
VDD
23
24
23
24
25
26
27
28
29
30
13
14
15
16
17
20
21
22
3
5
6
8
9
10
11
12
31
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
VDD
25
26
27
28
29
30
13
14
15
16
17
20
21
22
3
5
6
C5
C1
C2
18
19
18
19
VDD
VDD
VDD
VDD
RGB
C6
C3
LVCMOS
Parallel
Interface
to Display
RGB Bus
LVCMOS
Parallel
40
44
46
40
44
46
Interface
VDD
VDD
VDD
VDD
VDD
VDD
C4
C8
C7
8
9
10
11
12
45
43
42
38
39
41
DD0P
DD0M
DD0P
DD0M
Serial
MPL-2
Interface
Serial
MPL-2
Interface
DCP
DCM
DCP
41
38
39
48
42
45
43
DE
PD*
VS
GPIO
GPIO
GPIO
GPIO
DCM
DD1P
DD1M
48
32
1
36
1
DE
PE
VS
HS
DD1P
DD1M
2
HS
2
4
33
36
35
PCLK
PCLK
4
RDS
PD*
Mode24
GPIO
GPIO
GPIO
PCLK
32
33
34
SPI_DO
SPI_DI
SPI_SCL
GPIO
GPIO
GPIO
GPIO
34
47
RES0
RES0
37
TM
35
DAP
37
SPI_CSX
DAP
VSS
TM
VSS
1.8V
47
RES1
Notes:
Notes :
1. RDS (Receiver Drive Strength Control) , Tie = Low recommended
2. Mode24 , Tie = L for 18-bit mode or tie = H for 24-bit mode operation
3. Bypass Capacitor Values :
C5,C7 = 4.7 mF
C6,C8 = 0.1 mF
1. PD* = system GPIO ( control by BBP)
2. Bypass Capacitor Values :
C1,C2 = 4.7 mF
C3,C4 = 0.1 mF
Figure 18. Typical VGA RGB888 Connection Diagram
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The DES VDD is set to be compatible with the Display(s) employed. Depending on application, the Mode24 and
RDS may be tie to high, low or connected to BBP (GPIO) pins. The PD* should be tied to PD* pin on SER
device. The other signals DE, VS, and HS signals are outputs only. The connection between the DES device and
the display(s) should be done such that long stubs are avoided. The DES has user adjustable edge rate controls
for the parallel bus outputs. This can be used to optimize the edge rate vs. the required VDD magnitude. This
allows for using softer edges on the wide parallel data bus signals. The DES also provides a PE pin to flag any
parity errors detected. This signal maybe routed back to the host for monitoring, or bought out to a test point. The
DES supports 18-bit for 24-bit mode. These modes are obtained by setting the MODE24 pin to a logic Low for
18-bit mode or to logic High for 24-bit mode. The Sleep state of the display may be entered by driving the PD*
signal to a logic Low. This pin should be connected SED PD* pin. Several configuration pins are also required to
be set. For a DES, tie TM = L and RES0 = L.
FLEX CIRCUIT RECOMMENDATIONS
The MPL-2 lines should generally run together to minimize any trace length differences (skew). For impedance
control and also noise isolation (crosstalk), guard ground traces are recommended in between the signals.
Commonly a Ground-Signal-Signal-Ground (GSSGSSG) layout is used. Locate fast edge rate and large swing
signals further away to also minimize any coupling (unwanted crosstalk). In a stacked flex interconnect, crosstalk
also needs to be taken into account in the above and below layers (vertical direction). To minimize any coupling
locate MPL-2 traces next to a ground layer. Power rails also tend to generate less noise than LVCMOS so they
are also good candidates for use as isolation and separation.
The interconnect from the SER to the DES may act like a transmission line. Thus impedance control and ground
returns are an important part of system design. Impedance should be in the 80 to 100 Ohms for the differential
pair.
GROUNDING
The LM4312 offered in the 48 X2QFN package uses the center DAP Pad for the Ground connection. This pad
MUST be connected to Ground for proper device operation.
PCB RECOMMENDATIONS
General guidelines for the PCB design:
•
•
•
•
•
•
•
Floor plan - locate MPL-2 SER near the connector to limit chance of cross talk to high speed serial signals.
Route serial traces together, minimize the number of layer changes to reduce loading.
Use ground lines as guards to minimize any noise coupling (specifies distance).
Avoid parallel runs with fast edge, large LVCMOS swings.
Also use a GSSG pinout in connectors (Board to Board or ZIF).
DES device - follow similar guidelines.
Bypass the device with MLC surface mount devices and thinly separated power and ground planes with low
inductance feeds.
•
•
High current returns should have a separate path with a width proportional to the amount of current carried to
minimize any resulting IR effects.
See AN-1187 (SNOA401) X2QFN Package Application Note for SMT Assembly Recommendations
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Connection Diagram 48 X2QFN Package
G0
G1
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
DE
RES1
VDD
DD0P
VDD
DD0M
DCP
DCM
VDD
DD1M
DD1P
TM
G2
G3
LM4312
X2QFN PACKAGE
G4
VDD
VDD
G5
DAP = GND
TOP VIEW
G6
Not to Scale
G7
R0
R1
Figure 19. TOP VIEW
(not to scale)
18
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM4312
LM4312
www.ti.com
SNLS265A –MAY 2008–REVISED MAY 2013
REVISION HISTORY
Changes from Original (May 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 18
Copyright © 2008–2013, Texas Instruments Incorporated
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Product Folder Links: LM4312
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2014
PACKAGING INFORMATION
Orderable Device
LM4312SN/NOPB
LM4312SNX/NOPB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
X2QFN
X2QFN
NJS
48
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
4312SN
4312SN
ACTIVE
NJS
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM4312SN/NOPB
LM4312SNX/NOPB
X2QFN
X2QFN
NJS
NJS
48
48
250
178.0
330.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM4312SN/NOPB
LM4312SNX/NOPB
X2QFN
X2QFN
NJS
NJS
48
48
250
210.0
367.0
185.0
367.0
35.0
38.0
2500
Pack Materials-Page 2
MECHANICAL DATA
NJS0048A
SNF48A (Rev A)
www.ti.com
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