LM4546AVHX [TI]
SPECIALTY CONSUMER CIRCUIT, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48;
| 型号： | LM4546AVHX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 商用集成电路 |
| 文件： | 总28页 (文件大小：1343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OBSOLETE
July 15, 2009
LM4546A
AC '97 Rev 2 Multi-Channel Audio Codec with Sample Rate
Conversion and National 3D Sound
General Description
Key Specifications
The LM4546A is an audio codec for PC systems which is fully
PC98 compliant and performs the analog intensive functions
of the AC '97 Rev 2 architecture. Using 18-bit Sigma-Delta
ADCs and DACs, the LM4546A provides 90 dB of Dynamic
Range.
Analog Mixer Dynamic Range
97 dB (typ)
89 dB (typ)
90 dB (typ)
■
DAC Dynamic Range
ADC Dynamic Range
■
■
Features
The LM4546A was designed specifically to provide a high
quality audio path and provide all analog functionality in a PC
audio system. It features full duplex stereo ADCs and DACs
and analog mixers with access to 2 stereo and 2 mono inputs.
Each mixer input has separate gain, attenuation and mute
control and the mixers drive 1 mono and 1 stereo output, each
with attenuation and mute control. The LM4546A supports
National's 3D Sound stereo enhancement and a comprehen-
sive sample rate conversion capability. The sample rate for
the ADCs and DACs can be programmed separately with a
resolution of 1 Hz to convert any rate in the range 4 kHz –
48 kHz. Sample timing from the ADCs and sample request
timing for the DACs are completely deterministic to ease task
scheduling and application software development. These fea-
tures together with an extended temperature range also make
the LM4546A suitable for non-PC codec applications.
AC '97 Rev 2 comiant
■
High quality Sale Re Conversion from 4 kHz to 48
kHz in 1 Hz ine
■
Multiple coc su
■
■
■
■
■
NationalD Sound so enhancement circuitry
Advand er management support
Digtal 3.3V ansupply options
Eended Temperature: −40°C ≤ TA ≤ 85°C
Apatins
DesktoC audio systems on PCI cards, AMR cards, or
with motherboard chips sets featuring AC Link
■
Porle PC systems as on MDC cards, or with a chipset
celerator featuring AC Link
The LM4546A features the ability to connect several
together using the Extended AC Link configuratio
dedicated serial data signal to the Controller pe
LM4546A systems support up to 8 simultaneous cha
streaming data on Input Frames (Codec to Ctroller)
Output Frames (Controller to Codec) carry 2 reams to mul-
tiple codecs. The LM4546A may also be usewith
the National LM4550 to support up to 6 simultaneous an-
nels of streaming data on Output Fra
General and Multi-channel audio frequency systems
■
The AC '97 architecture separateand digital
functions of the PC audio system for system
design flexibility and increased perfor
© 2009 National Semiconductor Corporation
200308
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Block Diagram
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Soldering Information
LQFP Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
215°C
220°C
θ
JA (typ) – VBH48A
74°C/W
Supply Voltage
Storage Temperature
Input Voltage
6.0V
−65°C to +150°C
−0.3V to VDD +0.3V
2000V
Operating Ratings
Temperature Range
ESD Susceptibility (Note 2)
pin 3
ESD Susceptibility (Note 3)
pin 3
750V
200V
100V
150°C
TMIN ≤ TA ≤ TMAX (Note 4)
Analog Supply Range
Digital Supply Range
−40°C ≤ TA ≤ 85°C
4.2V ≤ AVDD ≤ 5.5V
3.0V ≤ DVDD ≤ 5.5V
Junction Temperature
Electrical Characteristics (Notes 1, 5) The following specifications apply for AVDD = 5V, DVDD = 5V, Sampling
Frequency (Fs) = 48 kHz, single codec configuration, unless otherwise noted. Limits aply for TA= 25°C. The reference for 0 dB
is 1 Vrms unless otherwise specified.
Units
(Limits)
LM4546A
Symbol
Parameter
Conditions
Typical
Limit
(Note 6)
(Note 7)
AVDD
Analog Supply Range
4.2
5.5
3.0
5.5
V (min)
V (max)
V (min)
V (max)
mA
DVDD
DIDD
Digital Supply Range
Digital Quiescent Power Supply
Current
DVDD = 5 V
43
20
DVDD = 3.
mA
Analog Quiescent Power Supply
Current
AIDD
53
mA
IDSD
Digital Shutdown Current
Analog Shutdown Current
Reference Voltage
500
30
µA
µA
V
IASD
VREF
PSRR
2.23
40
Power Supply Rejection Ratio
dB
Analog Loopthrough Mode (Note 8)
D Input to Line Output, -60 dB Input THD
+N, A-Weighted
Dynamic Range (Note
97
90
dB (min)
% (max)
THD
Total Harmonic Distortion
VO = -3 dB, f = 1 kHz, RL = 10 kΩ
0.01
0.02
Analog Input Section
LINE_IN, AUX, CD, VIDEO, PC_BEEP,
PHONE
VIN
Line Input Vol
1
Vrms
VIN
Mic Input with 20
Mic Input with 0 dB Gain
Crosstalk
0.1
1
Vrms
Vrms
dB
VIN
Xtalk
ZIN
CD Left to Right
All Analog Inputs
-95
40
Input Impedance (Note 9)
Input Capacitance
10
kΩ (min)
pF
CIN
15
Interchannel Gain Mismatch
CD Left to Right
0 dB to 22.5 dB
0.01
dB
Record Gain Amplifier - ADC
AS
Step Size
1.5
86
dB
dB
AM
Mute Attenuation (Note 9)
Mixer Section
AS
Step Size
+12 dB to -34.5 dB
1.5
86
dB
dB
AM
Mute Attenuation
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Units
(Limits)
LM4546A
Symbol
Parameter
Conditions
Typical
Limit
(Note 6)
(Note 7)
Analog to Digital Converters
Resolution
18
90
20
Bits
dB (min)
kHz
Dynamic Range (Note 9)
Frequency Response
Digital to Analog Converters
-60 dB Input THD+N, A-Weighted
-1 dB Bandwidth
86
Resolution
18
89
Bits
dB (min)
%
Dynamic Range (Note 9)
Total Harmonic Distortion
Frequency Response
Group Delay (Note 9)
Out of Band Energy (Note 10)
Stop Band Rejection
Discrete Tones
-60 dB Input THD+N, A-Weighted
85
2
THD
VIN = -3 dB, f = 1 kHz, RL = 10 kΩ
0.01
20 - 21 k
Hz
ms (max)
dB
-40
70
dB
DT
Analog Output Section
-96
dB
AS
Step Size
0 dB to -46.5 dB
1.5
86
dB
dB
Ω
AM
Mute Attenuation
Output Impedance (Note 9)
ZOUT
All Analog Outp
TBD
Digital I/O (Note 9)
0.40 x
DVDD
VIH
VIL
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
V (min)
V (max)
V (min)
V (max)
0.30 x
DVDD
0.50 x
DVDD
VOH
VOL
0.20 x
DVDD
IL
Input Leakage Current
Tri state Leakage Current
Output drive current
AC nk inputs
±10
±10
µA
µA
IL
h impedance AC Link outputs
AC Link outputs
IDR
5
mA
Digital Timing Specifications (Note 9)
FBC
BIT_CLK frequen
BIT_CLK perio
12.288
81.4
MHz
ns
TBCP
TCH
BIT_CLK high
Variation of BIT_CLK duty cycle from 50%
±20
% (max)
kHz
FSYNC
TSP
SYNC frequency
48
SYNC period
20.8
1.3
µs
TSH
SYNC high pulse width
SYNC low pulse width
Setup Time for codec data input
µs
TSL
19.5
µs
TDSETUP
SDATA_OUT to falling edge of BIT_CLK
15
5
ns (min)
Hold time of SDATA_OUT from falling edge
of BIT_CLK
TDHOLD
TSSETUP
TSHOLD
Hold Time for codec data input
Setup Time for codec SYNC input
Hold Time for codec SYNC input
ns (min)
ns (min)
ns (min)
SYNC to rising edge of BIT_CLK
TBD
TBD
Hold time of SYNC from rising edge of
BIT_CLK
Output Delay of SDATA_IN from rising
edge of BIT_CLK
TCO
Output Valid Delay
Rise Time
TBD
15
6
ns (max)
ns (max)
BIT_CLK, SYNC, SDATA_IN or
SDATA_OUT
TRISE
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Units
(Limits)
LM4546A
Symbol
Parameter
Conditions
Typical
Limit
(Note 6)
(Note 7)
BIT_CLK, SYNC, SDATA_IN or
SDATA_OUT
TFALL
Fall Time
RESET# active low pulse width
6
ns (max)
TRST_LOW
TRST2CLK
TSH
For Cold Reset
1.0
µs (min)
ns (min)
µs (min)
ns (min)
RESET# inactive to BIT_CLK start up For Cold Reset
TBD
1.3
162.8
TBD
SYNC active high pulse width
For Warm Reset
For Warm Reset
TSYNC2CLK
SYNC inactive to BIT_CLK start up
TBD
162.8
Delay from end of Slot 2 to BIT_CLK,
SDATA_IN low
TS2_PDOWN
AC Link Power Down Delay
Power On Reset
1
1
µs (max)
µs (min)
Time from minimum valid supply levels to
end of Reset
TSUPPLY2RST
TSU2RST
TRST2HZ
Setup to trailing edge of RESET#
Rising edge of RESET# to Hi-Z
For ATE Test Mode
For ATE Test Mode
15
25
ns (min)
ns (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occuperating Ratndicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC electrical specifications under particular test conditions
which guarantee specific performance limits. This assumes that the device is within the Operg RSpecifications are not guaranteed for parameters
where no limit is given, however, the typical value is a good indication of device performance.
Note 2: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 3: Machine Model, 220 pF – 240 pF discharged through all pins.
Note 4: The maximum power dissipation must be derated at elevated temperatures and ed by AX, θJA, and the ambient temperature TA. The maximum
allowable power dissipation is PDMAX = (TJMAX– TA)/θJA or the number given in Absolute Mangs, whichever is lower. For the LM4546A, TJMAX = 150°
C. The typical junction-to-ambient thermal resistance is 74°C/W for package number VBH48A.
Note 5: All voltages are measured with respect to the ground pin, unless otse specified.
Note 6: Typicals are measured at 25°C and represent the parametric norm.
Note 7: Limits are guaranteed to National's AOQL (Average Outgoing QLevel)
Note 8: Loopthrough mode describes a path from an analog input tlog mixers to an analog output.
Note 9: These specifications are guaranteed by design and charae not production tested.
Note 10: Out of band energy is measured from 28.8 kHz to 100 kHrms DAC output.
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Timing Diagrams
Clocks
Data Delay, Setup and Hold
20030810
20030811
Digital Rise and Fall
Legend
20030830
20030812
Por On R
20030829
Cold Reset
20030813
Warm Reset
20030814
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Typical Application
20030803
FIGURE 1. LM4546A Typical Application Circuit, Single Codec, 1 Vrms inputs
APPLICATION HINTS
•
The LM4546A must be initialized by using RESET# to perform a Power-On-Reset as shown in the Power On Reset Timing
Diagram
•
•
VREF must be pulled high to AVDD with a 10 kΩ resistor to ensure correct operation
Don't leave unused analog inputs floating. Tie all unused inputs together and connect to Analog Ground through a capacitor
(e.g. 0.1 µF)
•
•
•
Do not leave CD_GND floating when using the CD stereo input. CD_GND is the AC signal reference for the CD channels and
should be connected to the CD source ground (Analog Ground may also be acceptable) through a 1 µF capacitor
If using a non-standard AC Link controller take care to keep the SYNC and SDATA_IN signals low during Cold Reset to avoid
entering the ATE or Vendor test modes by mistake
The PC_Beep input should be explicitly muted if not used since it defaults to 0 dB gain on reset, unlike the mute default of the
other analog inputs
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Connection Diagram
20030802
Toew
Order Number 54VH
See NS Pacge NumBH48A
Pin Descriptions
G I/O
ꢀ
Name
Pin
I / O
Functional Dcripti
Mono
ThVrms nominal) mono input is mixed equally into both channels of the Stereo Mix
signder the control of the PC_Beep Volume control register, 0Ah. The PC_BEEP level
can be adjusted from 0 dB to -45 dB in 3 dB steps. The Stereo Mix signal feeds both the
ut anLine Level Out analog outputs and is also selectable at the Record Select Mux.
PC_BEEP
12
I
put
level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo Mix
at MIX2 under the control of the Phone Volume register, 0Ch. The PHONE level can be
muted or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. The Stereo Mix signal feeds both the
Line Out and Line Level Out analog stereo outputs and is also selectable at the Record Select Mux.
PHONE
CD_L
13
18
I
I
Left Stereo Channel Input
This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Input Mux for
conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D
signal at MIX1 under the control of the CD Volume register, 12h. The CD_L level can be muted
(along with CD_R) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix 3D is mixed
into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Line Level Out.
AC Ground Reference
This input is the reference for the signals on both CD_L and CD_R. CD_GND is NOT a DC ground
and should be AC-coupled to the stereo source ground common to both CD_L and CD_R. The
three inputs CD_GND, CD_L and CD_R act together as a quasi-differential stereo input with
CD_GND providing AC common-mode feedback to reject ground noise. This can improve the input
SNR for a stereo source with a good common ground but precision resistors may be needed in
any external attenuators to achieve the necessary balance between the two channels.
CD_GND
19
I
9
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ꢀ
Name
Pin
I / O
Functional Description
Right Stereo Channel Input
This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Input Mux for
conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix
3D signal at MIX1 under the control of the CD Volume register, 12h. The CD_R level can be muted
(along with CD_L) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined
into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Line Level Out.
CD_R
20
I
Mono microphone input
Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS
bit (bit D8) in the General Purpose register, 20h. The boost amplifier gain (0 dB or 20 dB) is set by
the 20dB bit (D6) in the Mic Volume register, 0Eh. Nominal input levels at the two gain settings are
1 Vrms and 0.1 Vrms respectively. The amplifier output is selectable (Record Select register, 1Ah)
by either the right or left channels of the Record Select Mux for conversion on either or both
channels of the stereo ADCs. The amplifier output can also be accessed at the stereo mixer MIX1
(muting and mixing adjustments via Mic Volume reger, 0Eh) where it is mixed equally into both
left and right channels of Stereo Mix 3D for accesthe ereo outputs Line Out and Line Level
Out. Access to the Mono analog output is seleced bux ctrolled by the MIX bit (D9) in
General Purpose register, 20h.
MIC1
21
I
Mono microphone input
Either MIC1 or MIC2 can be muxed to a programe boost amplifier with selection by the MS
bit (bit D8) in the General Purpose reger, 20h. The boost amplifier gain (0 dB or 20 dB) is set by
the 20dB bit (D6) in the Mic Volume iste0Eh. Nominal input levels at the two gain settings are
1 Vrms and 0.1 Vrms respectively. Tlifier tput is selectable (Record Select register, 1Ah)
by either the right or left channels of the Select Mux for conversion on either or both
channels of the stereo ADCsThe amplifier otput can also be accessed at the stereo mixer MIX1
(muting and mixing adjustmea Mic lume register, 0Eh) where it is mixed equally into both
left and right channels of Stereo Mor access to the stereo outputs Line Out and Line Level
Out. Access to the Moutpt is selected by a mux controlled by the MIX bit (D9) in
General Purpose re
MIC2
22
I
Left Stereo Channe
This line level put (1 minal) is selectable at the left channel of the stereo Record Select
Mux for consion by the left channel ADC. It can also be mixed into the left channel of the Stereo
Mix 3D signder the control of the Line In Volume register, 10h. The LINE_IN_L level
can be muted (along wLINE_IN_R) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo
Mix 3ombined to the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out
anut.
LINE_IN_L
23
I
Righnnel Input
This line nput (1 Vrms nominal) is selectable at the right channel of the stereo Input Mux for
sion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix
l at MIX1 under the control of the Line In Volume register, 10h. The LINE_IN_R level can
d (along with LINE_IN_L) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix
combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and
Line Level Out.
LINE_IN_R
24
35
Left Stereo Channel Output
This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal from
MIX2 via the Master Volume register, 02h. The LINE_OUT_L amplitude can be muted (along with
LINE_OUT_R) or adjusted from 0 dB to -46.5 dB in 1.5 dB steps.
LINE_OUT_L
O
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ꢀ
Name
Pin
I / O
Functional Description
Right Stereo Channel Output
This line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal from
MIX2 via the Master Volume register, 02h. The LINE_OUT_R amplitude can be muted (along with
LINE_OUT_L) or adjusted from 0 dB to -46.5 dB in 1.5 dB steps.
LINE_OUT_R
36
O
Mono Output
This mono line level output (1 Vrms nominal) is fed from either a microphone input (MIC1 or MIC2,
after boost amplifier) or from the mono sum of the left and right Stereo Mix 3D channels from MIX1.
The optional National 3D Sound enhancement can be disabled (default) by the 3D bit (bit D13) in
the General Purpose register, 20h. Choice of input is by the MIX bit (D9) in the same register.
MIX=0 selects a microphone input. Output level can be muted or adjusted from 0 dB to -46.5 dB
in 1.5 dB steps via the Mono Volume register, 06h.
MONO_OUT
37
O
DIGITAL I/O AND CLOCKING
Functional Driptn
Name
Pin
I / O
24.576 MHz crystal or oscillator input
To complete the oscillator circuit use a fundantal modtal operating in parallel resonance
and connect a 1MΩ resistor across pins 2 aChoose the load capacitors (Figure 2, C1, C2) to
suit the load capacitance required by the crstal (1 = C2 = 33 pF for a 20 pF crystal Assumes
that each 'Input + trace' capacitance = pF).
XTL_IN
2
I
This pin may also be used as the inpfor aexternal oscillator (24.576 MHz nominal) at standard
logic levels (VIH, VIL).
This pin is only used when the codec is in mode. It may be left open (NC) for any Secondary
mode.
24.576 MHz crystal output
Used with XTAL_IN to configure a oscillator.
When the codec is usexteral oscillator this pin should be left open (NC).
When the codec is cSecondary mode this pin is not used and may be left open (NC).
XTL_OUT
3
5
O
I
Input to codec
This is the inpor AC put Frames from an AC '97 Digital Audio Controller to the LM4546A
codec. Thesrames can contain both control data and DAC PCM audio data. This input is sampled
by the LM4talling edge of BIT_CLK.
SDATA_OUT
AC Link clock
An OT when iPrimary Codec mode. This pin provides a 12.288 MHz clock for the AC Link.
Thed (internally divided by two) from the 24.576 MHz signal at the crystal input
(XTL
This pin iNPUT when the codec is configured in any of the Secondary Codec modes and
ormally use the AC Link clock generated by a Primary Codec.
BIT_CLK
6
8
I/O
O
om codec
he output for AC Link Input Frames from the LM4546A codec to an AC '97 Digital Audio
oller. These frames can contain both codec status data and PCM audio data from the ADCs.
The LM4546A clocks data from this output on the rising edge of BIT_CLK.
SDATA_IN
AC Link frame marker and Warm Reset
This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of BIT_CLK. In
normal operation SYNC is a 48 kHz positive pulse with a duty cycle of 6.25% (16/256). SYNC is
sampled on the rising edge of BIT_CLK and the codec takes the first positive sample of SYNC as
defining the start of a new AC Link frame. If a subsequent SYNC pulse occurs within 255 BIT_CLK
periods of the frame start it will be ignored.
SYNC
10
I
SYNC is also used as an active high input to perform an (asynchronous) Warm Reset. Warm Reset
is used to clear a power down state on the codec AC Link interface.
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Name
Pin
I / O
Functional Description
Cold Reset
This active low signal causes a hardware reset which returns the control registers and all internal
circuits to their default conditions. RESET# MUST be used to initialize the LM4546A after Power
On when the supplies have stabilized. Cold Reset also clears the codec from both ATE and Vendor
test modes. In addition, while active, it switches the PC_BEEP mono input directly to both channels
of the LINE_OUT stereo output.
RESET#
11
I
Codec Identity
ID1# and ID0# determine the Codec Identity for multiple codec use. The Codec Identity configures
the codec in either Primary or one of three Secondary Codec modes. These Identity pins have the
same polarity as the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-only Extended Audio
ID register, 28h. If the ID0# pin (pin 45) is connected to ground then the ID0 bit (D14, reg 28h) will
be set to “1”. Similarly, connection to DVDD will set the ID0 bit to “0”. If left open (NC), ID0# is pulled
high by an internal pull-up resistor.
ID0#
ID1#
45
46
I
I
Codec Identity
ID1# and ID0# determine the codec address for mule codec use. The Codec Identity configures
the codec in either Primary or one of three SecondCoc modes. These Identity pins have the
same polarity as the Codec Identity bits ID1, ID(bits , Din the read-only Extended Audio
ID register, 28h. If the ID1# pin (pin 46) is cocted to grthen the ID1 bit (D15, reg 28h) will
be set to “1”. Similarly, connection to DVDl he ID1 bit to “0”. If left open (NC), ID1# is pulled
high by an internal pull-up resistor.
POWER SUPPLIES AND FENCES
Name
AVDD
Pin
25
26
1
I / O
FunnDescription
I
I
I
I
I
I
Analog supply
Analog ground
Digital supply
Digital supply
Digital ground
Digital ground
AVSS
DVDD1
DVDD2
DVSS1
DVSS2
9
4
7
Nominal 2.2 internal reference
Not intendeource current. Use short traces to bypass (3.3 µF, 0.1 µF) this pin to
maximize codec perfoance. This pin must be tied to AVDD with a 10 kΩ pull-up resistor.
VREF
27
28
O
O
NomV reference output
C5 mA of current and can be used to bias a microphone.
VREF_OUT
SOUND AND NO-CONNECTS (NC)
Functional Description
Name
Pin
I /
ins are used to complete the National 3D Sound stereo enhancement circuit. Connect a
µF capacitor between pins 3DP and 3DN. National 3D Sound can be turned on and off via
the 3D bit (D13) in the General Purpose register, 20h. National 3D Sound uses a fixed-depth type
stereo enhancement circuit hence the 3D Control register, 22h is read-only and is not
programmable. If National 3D Sound is not needed, these pins should be left open (NC).
3DP, 3DN
33,34
O
14–17
29–32
38–44
47, 48
These pins are not used and should be left open (NC).
For second source applications these pins may be connected to a noise-free supply or ground
(e.g. AVDD or AVSS), either directly or through a capacitor.
NC
NC
Typical Performance Characteristics
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ADC Frequency
Response
DAC Frequency
Response
20030819
20030820
ADC Noise Floor
DAC Noise Floor
20030815
20030816
Line Out Noise Floor
(Analog Loopthrough)
20030818
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O u t p u t V o l u m e I n p u t V o l u m e
A D C S o u r c e s
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200308 Version 5 Revision 1 Print Date/Time: 2009/07/15 15:26:52
Functional Description
GENERAL
eral Purpose register, 20h, and is a fixed depth implementa-
tion. The 3D Control register, 22h, is therefore not pro-
grammable (read-only). The 3D Sound circuitry defaults to
disabled after reset.
The LM4546A codec can mix, process and convert among
analog (stereo and mono) and digital (AC Link format) inputs
and outputs. There are two stereo and four mono analog in-
puts and one stereo and one mono analog outputs. A single
codec supports data streaming on two input and two output
channels of the AC Link digital interface simultaneously.
ANALOG MIXING: MIX2
MIX2 combines the output of MIX1 (Stereo Mix 3D) with the
two mono analog inputs, PHONE and PC_BEEP, these each
level-adjusted by the input control registers Phone Volume
(0Ch) and PC_Beep Volume (0Ah) respectively. If selected
by the POP bit (D15, reg 20h), the DAC output is also summed
into MIX2.
ADC INPUTS AND OUTPUTS
Both stereo analog inputs and three of the mono analog inputs
can be selected for conversion by the 18-bit stereo ADC. Dig-
ital output from the left and right channel ADCs is always
located in AC Link Input Frame slots 3 and 4 respectively.
Input level to either ADC channel can be muted or adjusted
from the Record Gain register, 1Ch. Adjustments are in 1.5
dB steps over a gain range of 0 dB to +22.5 dB and both
channels mute together (D15). Input selection for the ADC is
through the Record Select Mux controlled from the Record
Select register, 1Ah, together with microphone selection con-
trolled by the MS bit (D8) in the General Purpose register, 20h.
The stereo input, CD_IN, uses a quasi-differential 3-pin inter-
face where both stereo channel inputs are referenced to the
third pin, CD_GND. CD_GND should be AC coupled to the
source ground and provides common-mode feedback to can-
cel ground noise. It is not a DC ground. The other stereo input,
LINE_IN, is a 2-pin interface, single-ended for each stereo
channel with analog ground (AVSS) as the signals' reference.
Either of the two mono microphone inputs can be muxed to a
programmable boost amplifier before selection for either
channel of the ADC. The Microphone Mux is controlled by the
Microphone Selection (MS) bit (D8) in the General Pur
register 20h and the 20 dB programmable boost is e
by the 20dB bit (D6) in register 0Eh. The other sel
mono input, coupled directly to the Record Select M
PHONE.
STEREO MIX
The output of MIX2 is the signal, Stereo Mix. Stereo Mix is
used to drive the e output (LINE_OUT) and can also be
selected as the ut to e ADC by the Record Select Mux.
In addition, the cnnelof Stereo Mix are summed to
form a mono ignal o ) also selectable by the Record
Select Mus an input ther channel of the ADC.
STEREOUT
The utput volumm LINE_OUT can be muted or adjusted
by dB to 45 dB in nominal 3 dB steps under the control of
Mar Volume register, 02h. As with the input volume
reg, adjments to the levels of the two stereo channels
can be independently but both left and right channels
share a mte bit (D15).
ONOUTPUT
Tono output (MONO_OUT) is driven by one of two sig-
nals selected by the MIX bit (D9) in the General Purpose
register, 20h. The signal selected by default (MIX = 0) is the
mono summation of the two channels of Stereo Mix 3D, the
stereo output of the mixer MIX1. Setting the control bit MIX =
1, selects a microphone input, MIC1 or MIC2. The choice of
microphone is controlled by the Microphone Select (MS) bit
(D8) also in the General Purpose register, 20h.
ANALOG MIXING: MIX1
Three analog inputs are available for mixing athe sto
mixer, MIX1 – both stereo and one monmely the ro-
phone input selected by MS (D8, reg itinput to the
codec can be directed to either MIfter con-
version by the 18-bit stereo DAC and leent by the
PCM Out Volume control register (18h). Eput to MIX1
may be muted or level adjuste appropriate Mixer
Input Volume Register: Mic ), Line_In Volume
(10h), CD Volume (12h) anolume (18h). The
mono microphone input is my into left and right
stereo channels but stereo mixing thogonal, i.e. left chan-
nels are only mixed with other left channels and right with
right. The left and right amplitudes of any stereo input may be
adjusted independently however mute for a stereo input acts
on both left and right channels.
ANALOG LOOPTHROUGH AND DIGITAL LOOPBACK
Analog Loopthrough refers to an all-analog signal path from
an analog input through the mixers to an analog output. Digital
Loopback refers to a mixed-mode analog and digital signal
path from an analog input through the ADC, looped-back (LP-
BK bit – D7, 20h) through the DAC and mixers to an analog
output.
RESETS
COLD RESET is performed when RESET# (pin 11) is pulled
low for > 1 µs. It is a complete reset. All registers and internal
circuits are reset to their default state. It is the only reset which
clears the ATE and Vendor Test Modes.
WARM RESET is performed when SYNC (pin 10) is held high
for > 1 µs and the codec AC Link digital interface is in pow-
erdown (PR4 = 1, Powerdown Control / Status register, 26h).
It is used to clear PR4 and power up the AC Link digital in-
terface but otherwise does not change the contents of any
registers nor reset any internal circuitry.
DAC MIXING AND 3D PROCESSING
Control of routing the DAC output to MIX1 or MIX2 is by the
POP bit (D15) in the General Purpose register, 20h. If MIX1
is selected (default, POP=0) then the DAC output is available
for processing by the National 3D Sound circuitry. If MIX2 is
selected, the DAC output will bypass the 3D processing. This
allows analog inputs to be enhanced by the analog 3D Sound
circuitry prior to mixing with digital audio. The digital audio
may then use alternative digital 3D enhancements. National
3D Sound circuitry is enabled by the 3D bit (D13) in the Gen-
REGISTER RESET is performed when any value is written to
the RESET register, 00h. It resets all registers to their default
state and will modify circuit configurations accordingly but
does not reset any other internal circuits.
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AC Link Serial Interface Protocol
20030804
FIGURE 3. AC Link Bidirectional Audio Fram
20030806
RE 4. AC Link Output Frame
AC LINK OUTPUT FRAME
SDATA_OUT, CONTROLLO LM4546A INPUT
The AC Link Output Frame cl and PCM data to
the LM4546A control registers stereo DAC. Output
Frames are carried on the SDATA_OUT signal which is an
output from the AC '97 Digital Controller and an input to the
LM4546A codec. As shown in Figure 3, Output Frames are
constructed from thirteen time slots: one Tag Slot followed by
twelve Data Slots. Each Frame consists of 256 bits with each
of the twelve Data Slots containing 20 bits. Input and Output
Frames are aligned to the same SYNC transition. Note that
since the LM4546A is a two channel codec, it only accepts
data in 4 of the twelve Data Slots – 2 for control, one each for
PCM data to the left and right channel DACs. Data Slot 3 & 4
are used to stream data to the stereo DAC for all modes se-
lected by the Identity pins ID1#, ID0#.
and sampled by the LM4546A on the following falling edge.
The AC '97 Controller should always clock data to
SDATA_OUT on a rising edge of BIT_CLK and the LM4546A
always samples SDATA_OUT on the next falling edge. SYNC
is sampled with the rising edge of BIT_CLK.
The LM4546A checks each Frame to ensure 256 bits are re-
ceived. If a new Frame is detected (a low-to-high transition on
SYNC) before 256 bits are received from the old Frame then
the new Frame is ignored i.e. the data on SDATA_OUT is
discarded until a valid new Frame is detected.
The LM4546A expects to receive data MSB first, in an MSB
justified format.
SDATA_OUT: Slot 0 – Tag Phase
A new Output Frame is signaled with a low-to-high transition
of SYNC. SYNC should be clocked from the controller on a
rising edge of BIT_CLK and, as shown in Figure 4 and Figure
5, the first tag bit in the Frame (“Valid Frame”) should be
clocked from the controller by the next rising edge of BIT_CLK
The first bit of Slot 0 is designated the "Valid Frame" bit. If this
bit is 1, it indicates that the current Output Frame contains at
least one slot of valid data and the LM4546A will check further
tag bits for valid data in the expected Data Slots. With the
codec in Primary mode, a controller will indicate valid data in
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a slot by setting the associated tag bit equal to 1. Since it is a
two channel codec the LM4546A can only receive data from
four slots in a given frame and so only checks the valid-data
bits for 4 slots. In Primary mode these tag bits are for: slot 1
(Command Address), slot 2 (Command Data), slot 3 (PCM
data for left DAC) and slot 4 (PCM data for right DAC).
Bit
Description
Comment
Controller should stuff these
slots with “0”s
10:2
Not Used
The codec ID is used in a multi-
codec system to identify the
target Secondary codec for the
Control Register address and/or
data sent in the Output Frame
Codec ID
(ID1, ID0)
The last two bits in the Tag contain the Codec ID used to se-
lect the target codec to receive the frame in multiple codec
systems. When the frame is being sent to a codec in one of
the Secondary modes the controller does not use bits 14 and
13 to indicate valid Command Address and Data in slots 1
and 2. Instead, this role is performed by the Codec ID bits –
operation of the Extended AC Link assumes that the controller
would not access a secondary codec unless it was providing
valid Command Address and/or Data. When in one of the
secondary modes the LM4546A only checks the tag bits for
the Codec ID and for valid data in the two audio data slots 3
& 4.
1,0
SDATA_OUT: Slot 1 – Read/Write, Control Address
Slot 1 is used by a controller to indicate both the address of
a target register in the LM4546A and whether the access op-
eration is a register read or register write. The MSB of slot 1
(bit 19) is set to 1 to indicate that the current access operation
is 'read'. Bits 18 through 12 are used to specify the 7-bit reg-
ister address of the read or write operation. The least signifi-
cant twelve bits areserved and should be stuffed with zeros
by the AC '97 colle
When sending an Output Frame to a Secondary mode codec,
a controller should set tag bits 14 and 13 to zero.
SL, OTPUT FRAME
Bits
scription
Comment
1 = Read
0 = Write
19
Reaite
Register
Adress
Identifies the Status/Command
register for read/write
:12
11:
eserved
Controller should set to "0"
SDATA_OUT: Slot 2 – Control Data
lot used to transmit 16-bit control data to the LM4546A
the access operation is 'write'. The least significant four
bits should be stuffed with zeros by the AC '97 controller. If
the access operation is a register read, the entire slot, bits 19
through 0 should be stuffed with zeros.
2003805
SLOT 2, OUTPUT FRAME
FIGURE 5. Start of AC Link Output ame
Bits
19:4
3:0
Description
Comment
Control Register Controller should stuff with zeros
SLOT 0, OUTPUT FRAME
Write Data
Reserved
if operation is “read”
Set to "0"
Bit
Description
Cnt
1 = Valit one
slot.
15
Valid Frame
SDATA_OUT: Slots 3 & 4 – PCM Playback Left/Right
Channels
Control register 1 = ontrodress in
address mary codec only)
Control register 1 rol Data in Slot 2
14
13
Slots 3 and 4 are 20-bit fields used to transmit PCM data to
the left and right channels of the stereo DAC for all codec
Primary and Secondary modes. Any unused bits should be
stuffed with zeros. The LM4546A DACs have 18-bit resolution
and will therefore use the 18 MSBs of the 20-bit PCM data
(MSB justified).
data
codec only)
1 = Valid PCM Data in Slot 3
(Primary & all Secondary
modes)
Left DAC data in
Slot 3
12
11
SLOTS 3 & 4, OUTPUT FRAME
1 = Valid PCM Data in Slot 4
(Primary & all Secondary
modes)
Right DAC data
in Slot 4
Bits
Description
Comment
Slots used to stream data to
DACs for all Primary or
Secondary modes.
PCM DAC Data
(Left /Right
19:0
Channels)
Set unused bits to "0"
SDATA_OUT: Slots 5 to 12 – Reserved
These slots are not used by the LM4546A and should all be
stuffed with zeros by the AC '97 Controller.
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20030808
FIGURE 6. AC Link Input Frame
AC LINK INPUT FRAME:
SDATA_IN, CONTROLLER INPUT FROM LM4546A OUTPUT
The AC Link Input Frame contains status and PCM data from
the LM4546A control registers and stereo ADC. Input Frames
are carried on the SDATA_IN signal which is an input to the
AC '97 Digital Audio Controller and an output from the
LM4546A codec. As shown in Figure 3, Input Frames are
constructed from thirteen time slots: one Tag Slot followed by
twelve Data Slots. The Tag Slot, Slot 0, contains 16 bits of
which 5 are used by the LM4546A. One is used to ind
that the AC Link interface is fully operational and the
to indicate the validity of the data in the four of the
following Data Slots that are used by the LM4546A.
Frame consists of 256 bits with each of the tweldata s
containing 20 bits.
A new Input Frame is signaled with a low-to-hitiof
SYNC. SYNC should be clocked from the controller on a rg
edge of BIT_CLK and, as shown in Figund Figurthe
first tag bit in the Frame (“Codec Read from the
LM4546A by the next rising edge of M4546A
always clocks data to SDATA_IN on a risBIT_CLK
and the controller is expected tmple SA_IN on the
next falling edge. The LM454SYNC on the rising
edge of BIT_CLK.
20030807
FIGURE 7. Start of AC Link Input Frame
SDATA_IN: Slot 0 – Codec/Slot Status Bits
The first bit (bit 15, “Codec Ready”) of slot 0 in the AC Link
Input Frame indicates when the codec's AC Link digital inter-
face and its status/control registers are fully operational. The
digital controller is then able to read the LSBs from the Pow-
erdown Control/Stat register (26h) to determine the status of
the four main analog subsections. It is important to check the
status of these subsections after Initialization, Cold Reset or
the use of the powerdown modes in order to minimize the risk
of distorting analog signals passed before the subsections are
ready.
Input and Output Frames are same SYNC tran-
sition.
The LM4546A checks each Frame to ensure 256 bits are re-
ceived. If a new Frame is detected (a low-to-high transition on
SYNC) before 256 bits are received from an old Frame then
the new Frame is ignored i.e. no valid data is sent on
SDATA_IN until a valid new Frame is detected.
The 4 bits 14, 13, 12 and 11 indicate that the data in slots 1,
2, 3 and 4, respectively, are valid.
The LM4546A transmits data MSB first, in a MSB justified
format. All reserved bits and slots are stuffed with "0"s by the
LM4546A.
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SLOT 0, INPUT FRAME
Bits
Description
Comment
Bit
Description
Comment
0 = Controller should send
valid data in Slot 3 of the
next Output Frame.
Slot 3 Request
bit
(For left DAC
PCM data)
Codec Ready
Bit
1 = AC Link Interface Ready
15
11
1 = Controller should not send
Slot 3 data.
1 = Valid Status Address or
Slot Request
14 Slot 1 data valid
0 = Controller should send
valid data in Slot 4 of the
next Output Frame.
13 Slot 2 data valid 1 = Valid Status Data
Slot 4 Request
bit
(For right DAC
PCM data)
1 = Valid PCM Data
12 Slot 3 data valid
10
(Left ADC)
1 = Controller should not send
Slot 4 data.
1 = Valid PCM Data
11 Slot 4 data valid
(Right ADC)
Unused Slot
Request bits
9:2
1,0
Stuffed with "0"s by LM4546A
Stuffed with "0"s by LM4546A
SDATA_IN: Slot 1 – Status Address / Slot Request Bits
This slot echoes (in bits 18 – 12) the 7-bit address of the codec
control/status register received from the controller as part of
a read-request in the previous frame. If no read-request was
received, the codec stuffs these bits with zeros.
Reserved
SDATA_IN: Slot – Status Data
This slot return-biatus data read from a codec control/
status register. Thec sds the data in the frame follow-
ing a read-uest by ttroller (bit 15, slot 1 of the Output
Frame). read-request was made in the previous frame
the codwilff this slot with zeros.
Bits 11, 10 are Slot Request bits that support the Variable
Rate Audio (VRA) capabilities of the LM4546A. For all codec
Primary and Secondary modes, the left and right channels of
the DAC take PCM data from slots 3 and 4 in the Output
Frame respectively. The codec will therefore use bits 11 and
10 to request DAC data from these two slots. If bits 11 and 10
are set to 0, the controller should respond with valid PCM data
in slots 3 and 4 of the next Output Frame. If bits 11 and 10
are set to 1, the controller should not send data.
SOT 2, INPUT FRAME
ts
19:4
Description
tatus Data
Reserved
Comment
Data read from a codec control/
status register.
Stuffed with “0”s if no read-
request in previous frame.
The codec has full control of the slot request bits. By default,
data is requested in every frame, corresponding to a sample
rate equal to the frame rate (SYNC frequency) – 48 kHz when
XTAL_IN = 24.576 MHz. To send samples at a rate below t
frame rate, a controller should set VRA = 1 (bit 0 in t
tended Audio Control/Status register, 2Ah) and progr
desired rate into the PCM DAC Rate register, 2Ch. Bo
channels operate at the same sample rate. Values for
mon sample rates are given in the Register Dription sec-
tion (Sample Rate Control Registers, 2Ch, 32but ate
between 4 kHz and 48 kHz (to a resolution o) is p-
ported. Slot Requests from the LM4546A are issued m-
pletely deterministically. For example if ple rate 8000
Hz is programmed into 2Ch then thill always
issue a slot request in every sixth framy of 9600
Hz will result in a request every fifth framfrequency
of 8800 Hz will cause slot reqbe spd alternately
five and six frames apart. Thm makes it easy to
plan task scheduling on a ler and simplifies
application software develop
Stuffed with "0"s by LM4546A
SDATA_IN: Slot 3 – PCM Record Left Channel
This slot contains sampled data from the left channel of the
stereo ADC. The signal to be digitized is selected using the
Record Select register (1Ah) and subsequently routed
through the Record Select Mux and the Record Gain amplifier
to the ADC.
This is a 20-bit slot and the digitized 18-bit PCM data is trans-
mitted in an MSB justified format. The remaining 2 LSBs are
stuffed with zeros.
SLOT 3, INPUT FRAME
Bits
19:2
1:0
Description
Comment
PCM Record 18-bit PCM sample from left ADC
Left Channel
data
The LM4546A will ignore data in t Frame slots that do
not follow an Input Frame with a Slot Request. For example,
if the LM4546A is expecting data at a 8000 Hz rate yet the AC
'97 Digital Audio Controller continues to send data at 48000
Hz, then only those one-in-six audio samples that follow a Slot
Request will be used by the DAC. The rest will be discarded.
Reserved
Stuffed with "0"s by LM4546A
SDATA_IN: Slot 4 – PCM Record Right Channel
This slot contains sampled data from the right channel of the
stereo ADC. The signal to be digitized is selected using the
Record Select register (1Ah) and subsequently routed
through the Record Select Mux and the Record Gain amplifier
to the ADC.
Bits 9 – 2 are request bits for slots not used by the LM4546A
and are stuffed with zeros. Bits 1 and 0 are reserved and are
also stuffed with zeros.
This is a 20-bit slot and the digitized 18-bit PCM data is trans-
mitted in an MSB justified format. The remaining 2 LSBs are
stuffed with zeros.
SLOT 1, INPUT FRAME
Bits
Description
Comment
19
Reserved
Stuffed with "0" by LM4546A
Status Register Echo of the requested Status
18:12
Index
Register address
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SLOT 4, INPUT FRAME
Description Comment
PCM Record 18-bit PCM audio sample from
SDATA_IN: Slots 5 to 12 – Reserved
Slots 5 – 12 of the AC Link Input Frame are not used for data
by the LM4546A and are always stuffed with zeros.
Bits
19:2 Right Channel right ADC
data
1:0
Reserved
Stuffed with "0"s by LM4546A
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Register Descriptions
Default settings are indicated by *.
Mute
Gx4:Gx0
0 0000
Function
+12dB gain
0
RESET REGISTER (00h)
0
0 1000
0dB gain
Writing any value to this register causes a Register Reset
which changes all registers back to their default values. If a
read is performed on this register, the LM4546A will return a
value of 0D40h. This value can be interpreted in accordance
with the AC '97 specification to indicate that National 3D
Sound is implemented and 18-bit data is supported for both
the ADCs and DACs.
0
1
1 1111
34.5dB attenuation
*mute
X XXXX
Default:
8008h (mono registers)
8808h (stereo registers)
RECORD SELECT REGISTER (1Ah)
MASTER VOLUME REGISTER (02h)
This register independently controls the sources for the right
and left channels of the stereo ADC. The default value of
0000h corresponds to selecting the (mono) Mic input for both
channels.
This output register allows the output level from either channel
of the stereo LINE_OUT to be muted or attenuated over the
range 0 dB – 46.5 dB in nominal 1.5 dB steps. There are 5
bits of volume control for each channel and both stereo chan-
nels can be individually attenuated. The mute bit (D15) acts
simultaneously on both stereo channels of LINE_OUT.
SL2:SL0
Source for Left Channel ADC
*Mic input
0
1
2
3
4
5
input (L)
Mute
Mx4:Mx0
0 0000
Function
0dB attenuation
VIDEO input (L)
AUX input (L)
0
0
1 1111
46.5dB attenuation
*mute
LINE_IN input (L)
Stereo Mix (L)
Mono Mix
1
X XXXX
Default: 8000h
MONO VOLUME REGISTER (06h)
PHONE input
This output register allows the level from MONO_OUT to be
muted or attenuated over the range 0 dB – 46.5 dB in nominal
1.5 dB steps. There are 5 bits of volume control and one mute
bit (D15).
SR2:SR0
Source for Right Channel ADC
*Mic input
1
2
3
4
5
6
7
CD input (R)
Mute
MM4:MM0
0 0000
Function
0dB attenuation
VIDEO input (R)
AUX input (R)
0
0
1 1111
46.5dB attenuation
*mute
LINE_IN input (R)
Stereo Mix (R)
Mono Mix
1
X XXXX
Default: 8000h
PHONE input
PC BEEP VOLUME REGISTER (0Ah)
This input register adjusts the level ooPC_BEEP
input to the stereo mixer MIX2 where ually into
both channels of the Stereo Mix signal. Pn be both
muted and attenuated over a range of 0 dB tin nominal
3 dB steps. Note that the defaor the PC_Beep Vol-
ume register is 0 dB attenuan mute.
Default: 0000h
RECORD GAIN REGISTER (1Ch)
This register controls the input levels for both channels of the
stereo ADC. The inputs come from the Record Select Mux
and are selected via the Record Select Control register, 1Ah.
The gain of each channel can be individually programmed
from 0dB to +22.5dB in 1.5dB steps. Both channels can also
be muted by setting the MSB to 1.
Mute
PV3:PV0
0000
unction
*0dttenuation
45dB attenuation
mute
0
0
1111
Record Gain Register (1Ch)
1
XXXX
Mute
Gx3:Gx0
1111
Function
22.5dB gain
Default: 0000h
0
MIXER INPUT VOLUME REGISTERS (Index 0Ch - 18h)
0
0000
0dB gain
*mute
These input registers adjust the volume levels into the stereo
mixers MIX1 and MIX2. Each channel may be adjusted over
a range of +12dB gain to 34.5dB attenuation in 1.5dB steps.
For stereo ports, volumes of the left and right channels can
be independently adjusted. Muting a given port is accom-
plished by setting the MSB to 1. Setting the MSB to 1 for
stereo ports mutes both the left and right channel. The Mic
Volume register (0Eh) controls an additional 20dB boost for
the selected microphone input by setting the 20dB bit (D6).
1
XXXX
Default: 8000h
GENERAL PURPOSE REGISTER (20h)
This register controls many miscellaneous functions imple-
mented on the LM4546A. The miscellaneous control bits
include POP which allows the DAC output to bypass the Na-
tional 3D Sound circuitry, 3D which enables or disables the
National 3D Sound circuitry, MIX which selects the
MONO_OUT source, MS which controls the Microphone Se-
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lection mux and LPBK which connects the output of the stereo
ADC to the input of the stereo DAC. LPBK provides a mixed-
mode analog and digital loopback path between analog inputs
and analog outputs.
BIT#
BIT
Function: Status
1 = ADC section ready to
transmit data
0
ADC
1 = DAC section ready to accept
data
1
DAC
BIT
Function
*0 = 3D allowed
PCM Out Path:
National 3D Sound:
Mono output select:
Mic select:
2
3
ANL
REF
1 = Analog mixers ready
POP
1 = 3D bypassed
*0 = off
1 = VREF is up to nominal level
3D
MIX
MS
BIT#
8
BIT
PR0
PR1
PR2
Function: Powerdown
1 = on
1 = Powerdown ADCs and
Record Select Mux
*0 = Mix
1 = Mic
9
1 = Powerdown DACs
*0 = MIC1
1 = MIC2
1 = Powerdown Analog Mixer
(VREF still on)
10
ADC/DAC Loopback: *0 = No Loopback
1 = Loopback
LPBK
1 = Powerdown Analog Mixer
(VREF off)
11
12
3
PR
Default: 0000h
1 Powerdown AC Link digital
interface (BIT_CLK off)
3D CONTROL REGISTER (22h)
This read-only (0101h) register indicates, in accordance with
the AC '97 Rev 2.1 Specification, the fixed depth and center
characteristics of the National 3D Sound stereo enhance-
ment.
13
14
15
PR5
6
PR7
1 = Disable Internal Clock
Not Used
Not Used
POWERDOWN CONTROL / STATUS REGISTER (26h)
a000h
This read/write register is used both to monitor subsystem
readiness and also to program the LM4546A powerdown
states. The 4 LSBs indicate status and 6 of the 8 MSBs control
powerdown.
EXTENAUDIO ID REGISTER (28h)
This read-only register identifies which AC '97 Extended Au-
io feures are supported. The LM4546A features VRA
ble Rate Audio) and ID1, ID0 (Multiple Codec support).
VRis indicated by a "1" in bit 0. The two MSBs, ID1 and ID0,
show the current Codec Identity as defined by the Identity pins
ID1#, ID0# (pins 46 and 45). Note that the external logic con-
nections to ID1#, ID0# (pins 46 and 45) are inverse in polarity
to the value of the Codec Identity (ID1, ID0) held in bits D15,
D14. Codec mode selections are shown in the table below.
The 4 LSBs of this register indicate the status of the 4 aud
subsections of the codec: Reference voltage, Analog
and amplifiers, DAC section, ADC section. When the
Ready" indicator bit in the AC Link Input Frame (SDA
slot 0, bit 15) is a "1", it indicates that the AC Link and A
registers are in a fully operational state and thcontrol and
status information can be transferred. It does indihat
the codec is ready to send or receive audio Pta o
pass signals through the analog I/O and mixers. To deterne
that readiness, the Controller must cht the 4 Ls of
this register are set to “1” indicating thate audio
subsections are ready.
Pin 46
(ID1#)
Pin 45 D15,28h D14,28h Codec Identity
(ID0#)
(ID1)
(ID0)
Mode
NC/DVDD NC/DVDD
Primary
0
0
1
1
0
1
0
1
NC/DVDD
GND
GND
NC/DVDD
GND
Secondary 1
Secondary 2
Secondary 3
The powerdown bits PR0 – PR5 control inubsections
of the codec. They are implecompnce with AC
'97 Rev 2 to support the stanower management
states D0 – D3 as defined d PCI Bus Power
Management specification.
GND
EXTENDED AUDIO STATUS/CONTROL REGISTER (2Ah)
This read/write register provides status and control of the
variable sample rate capabilities in the LM4546A. Setting the
LSB of this register to "1" enables Variable Rate Audio (VRA)
mode and allows DAC and ADC sample rates to be pro-
grammed via registers 2Ch and 32h respectively.
PR0 controls the powerdown state ADC and associated
sampling rate conversion circuitry. PR1 controls powerdown
for the DAC and the DAC sampling rate conversion circuitry.
PR2 powers down the mixer circuits (MIX1, MIX2, National
3D Sound, Mono Out, Line Out). PR3 powers down VREF in
addition to all the same mixer circuits as PR2. PR4 powers
down the AC Link digital interface – see Figure 8 for signal
powerdown timing. PR5 disables internal clocks. PR6 and
PR7 are not used.
BIT
Function
*0 = VRA off (Frame-rate sampling)
1 = VRA on
VRA
Default: 0000h
SAMPLE RATE CONTROL REGISTERS (2Ch, 32h)
These read/write registers are used to set the sample rate for
the left and right channels of the DAC (PCM DAC Rate, 2Ch)
and the ADC (PCM ADC Rate, 32h). When Variable Rate
Audio is enabled via bit 0 of the Extended Audio Control/Sta-
tus register (2Ah), the sample rates can be programmed, in 1
www.national.com
22
200308 Version 5 Revision 1 Print Date/Time: 2009/07/15 15:26:52
Hz increments, to be any value from 4 kHz to 48 kHz. The
value required is the hexadecimal representation of the de-
sired sample rate, e.g. 800010 = 1F40h. Below is a list of the
most common sample rates and the corresponding register
(hex) values.
designation. The first 24 bits (4Eh, 53h, 43h) represent the
three ASCII characters “NSC” which is National's Vendor ID
for Microsoft's Plug and Play. The last 8 bits are the two binary
coded decimal characters, 4, 6 and identify the codec to be
an LM4546A.
Common Sample Rates
RESERVED REGISTERS
SR15:SR0
1F40h
Sample Rate (Hz)
8000
Do not write to reserved registers. In particular, do not write
to registers 24h, 5Ah, 74h and 7Ah. All registers not listed in
the LM4546A Register Map are reserved. Reserved Regis-
ters will return 0000h if read.
2B11h
11025
3E80h
16000
5622h
22050
AC44h
*BB80h
44100
*48000
VENDOR ID REGISTERS (7Ch – 7Eh)
These two read-only (4E53h, 4350h) registers contain
National's Vendor ID and National's LM45xx codec version
register (26hmusollto confirm readiness. In partic-
ular the stap time of REF circuitry depends on the value
of the deing capacitors on pin 27 (3.3 µF, 0.1 µF in par-
allel is comded) and this dependency is behind the
requement for bR2 and PR3 functionality in AC '97 Rev
2.
Low Power Modes
The LM4546A provides 6 bits to control the powerdown state
of internal analog and digital subsections and clocks. These
6 bits (PR0 – PR5) are located in the 8 MSBs of the Power-
down Control/Status register, 26h. The status of the four main
analog subsections is given by the 4 LSBs in the same reg-
ister, 26h.
n AC Link Digital Interface is powered down the
codutpusignals SDATA_IN and BIT_CLK (Primary
mode) ared to zero and no control data can be passed
between cntroller and codec(s). This powerdown state can
be cleed in two ways: Cold Reset (RESET# = 0) or Warm
sSYNC = 1, no BIT_CLK). Cold Reset sets all registers
bto their default values (including clearing PR4) whereas
Warm Reset only clears the PR4 bit and restarts the AC Link
Digital Interface leaving all register contents otherwise unaf-
fected. For Warm Reset (see Timing Diagrams), the SYNC
input is used asynchronously. The LM4546A codec allows the
AC Link digital interface powerdown state to be cleared im-
mediately so that its duration can be essentially as short as
TSH, the Warm Reset pulse width. However for conformance
with AC '97 Rev 2, Warm Reset should not be applied within
4 frame times of powerdown i.e. the AC Link powerdown state
should be allowed to last at least 82.8 µs.
The powerdown bits are implemented in compliance with AC
'97 Rev 2 to support the standard device power management
states D0 – D3 as defined in the ACPI and PCI Bus Power
Management specification.
PR0 controls the powerdown state of the ADC and associ
sampling rate conversion circuitry. PR1 controls powe
for the DAC and the DAC sampling rate conversion c
PR2 powers down the mixer circuits (MIX1, MIX2, N
3D Sound, Mono Out, Line Out). PR3 powers dwn VREF
addition to all the same mixer circuits as PRPR4 powers
down the AC Link Digital Interface – see Fig8 al
powerdown timing. PR5 disables internal clocut les
the crystal oscillator and BIT_CLK runnineeded for ini-
mum Primary mode powerdown disin multi-codec
systems). PR6 and PR7 are not use
After a subsection has undergone a pcycle, the
appropriate status bit(s) in the werdowntrol/Status
20030809
FIGURE 8. AC Link Powerdown Timing
23
200308 Version 5 Revision 1 Print Date/Time: 2009/07/15 15:26:52
www.national.com
Output Frames for Command/Status register access. For a
timing source, a Primary codec divides down by 2 the fre-
quency of the signal on XTAL_IN and also generates this as
the BIT_CLK output for the use of the controller and any Sec-
ondary codecs. Secondary codecs use BIT_CLK as an input
and as their timing source and do not use XTAL_IN or
XTAL_OUT. The use of Tag Bits is described below.
Improving System Performance
The audio codec is capable of dynamic range performance in
excess of 90 db., but the user must pay careful attention to
several factors to achieve this. A primary consideration is
keeping analog and digital grounds separate, and connecting
them together in only one place. Some designers show the
connection as a zero ohm resistor, which allows naming the
nets separately. Although it is possible to use a two layer
board, it is recommended that a minimum of four layers be
used, with the two inside layers being analog ground and dig-
ital ground. If EMI is a system consideration, then as many as
eight layers have been successfully used. The 12 and 25
MHz. clocks can have significant harmonic content depend-
ing on the rise and fall times. With the exception of the digital
VDD pins, (covered later) bypass capacitors should be very
close to the package. The analog VDD pins should be sup-
plied from a separate regulator to reduce noise. By operating
the digital portion on 3.3V instead of 5V, an additional 0.5-0.7
db improvement can be obtained.
SECONDARY CODEC REGISTER ACCESS
For Secondary Codec access, the controller must set the tag
bits for Command Address and Data in the Output Frame as
invalid (i.e. equal to 0). The Command Address and Data tag
bits are in slot 0, bits 14 and 13 and Output Frames are those
in the SDATA_OUT signal from controller to codec. The con-
troller must also place the non-zero value (01, 10, or 11)
corresponding to the Identity (ID1, ID0) of the target Sec-
ondary Codec into the Codec ID field (slot 0, bits 1 and 0) in
that same Output Fme. The value set in the Codec ID field
determines whicf the three possible Secondary Codecs is
accessed. UnliPrary Codec, a Secondary Codec will
disregard the Cod Aress and Data tag bits when
there is a mch betwe2-bit Codec ID value (slot 0, bits
1 and 0) he Codec Identity (ID1, ID0). Instead it uses the
Codec/Idematch to indicate that the Command Ad-
dresin slot 1 aa “write”) the Command Data in slot 2
aralid.
Depending on power supply layout, routing, and capacitor
ESR, a device instability can occur, resulting in increased
noise on the outputs. This can be eliminated by adding an
inductor in the digital supply line between the supply bypass
capacitors and the DVDD pins, which increases the high fre-
quency impedance of the supply as seen by the part. This
“current starving” technique slows down internal rise and fall
times, which will improve the signal to noise ratio, especially
at low temperatures. In addition, the EMI radiated from the
board is also reduced.
n rding from a Secondary Codec, the controller must
secort Codec ID bits (i.e. the target Codec Identity
in slot 1 and 0) along with the read-request bit (slot 1,
bit 19) antarget register address (slot 1, bits 18 – 12). To
write ta Secondary Codec, a controller must send the cor-
ct dec ID bits when slot 1 contains a valid target register
ass and “write” indicator bit and slot 2 contains valid tar-
get register data. A write operation is only valid if the register
address and data are both valid and sent within the same
frame. When accessing the Primary Codec, the Codec ID bits
are cleared and the tag bits 14 and 13 resume their role indi-
cating the validity of Command Address and Data in slots 1
and 2.
Multiple Codecs
EXTENDED AC LINK
Up to four codecs can be supported on the extended A
These multiple codec implementations should run off a
mon BIT_CLK generated by the Primary CodeAll cod
share the AC '97 Digital Controller output sals, SYNC,
SDATA_OUT, and RESET#. Each codec, hoes
its own SDATA_IN signal back to the controller, wh the rlt
that the controller requires one dedicateut pin per dec
(Figure 9).
The use of the tag bits in Input Frames (carried by the
SDATA_IN signal) is the same for Primary and Secondary
Codecs.
The Codec Identity is determined by the inverting input pins
ID1#, ID0# (pins 46 and 45) and can be read as the value of
the ID1, ID0 bits (D15, D14) in the Extended Audio ID register,
28h of the target codec.
By definition there can be one Primap to three
Secondary Codecs on an extended Ae Primary
Codec has a Codec Identity = (ID0) = Iwhile Sec-
ondary Codecs take identiti01, 10 or 11. The
Codec Identity is used as a nction. This allows
the Command and Status reof the codecs to be
individually addressed althouess mechanism for
Secondary Codecs differs slightly from that for a Primary.
Slots in the AC Link Output Frame are always mapped to carry
data to the left DAC channel in slot 3 and data to the right DAC
channel in slot 4. Similarly, slots in AC Link Input Frames are
always mapped such that PCM data from the left ADC chan-
nel is carried by slot 3 and PCM data from the right ADC
channel by slot 4. Output Frames are those carried by the
SDATA_OUT signal from the controller to the codec while In-
put Frames are those carried by the SDATA_IN signal from
the codec to the controller.
The Identity control pins, ID1#, ID0# (pins 46 and 45) are in-
ternally pulled up to DVDD. The Codec may therefore be
configured as 'Primary' either by leaving ID1#, ID0# open
(NC) or by strapping them externally to DVDD (Digital Supply).
The difference between Primary and Secondary codec
modes is in their timing source and in the Tag Bit handling in
SLOT 0: TAG bits in Output Frames (controller to codec)
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Valid Slot 1 Slot 2 Slot 3 Slot 4
Frame Valid Valid Valid Valid
X
X
X
X
X
X
X
X
X
ID1
ID0
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24
200308 Version 5 Revision 1 Print Date/Time: 2009/07/15 15:26:52
Extended Audio ID register (28h): Support for Multiple Codecs
Reg
Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
D0 Default
Extended
Audio ID
28h
ID1 ID0
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA X001h
20030823
FIGURE 9. Multiple Codecs using Extended AC Link
face for controller testing. ATE test mode timing parameters
are given in the Electrical Characteristics table. The Vendor
test mode is entered if SYNC is sampled high by the zero-to-
one transition of RESET#. Neither of these entry conditions
can occur in normal AC Link operation but care must be taken
to avoid mistaken activation of the test modes when using non
standard controllers.
Test Modes
AC '97 Rev 2 defines two test modes: ATE test mode and
Vendor test mode. Cold Reset is the only way to exit either of
them. The ATE test mode is activated if SDATA_OUT is sam-
pled high by the trailing edge (zero-to-one transition) of RE-
SET#. In ATE test mode the codec AC Link outputs
SDATA_IN and BIT_CLK are then configured to a high
impedance state to allow tester control of the AC Link inter-
25
200308 Version 5 Revision 1 Print Date/Time: 2009/07/15 15:26:52
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead , LQFP, 7 1.4mm, JEDEC (M)
Order Numbe4546H
NS Package NumH48A
www.national.com
26
200308 Version 5 Revision 1 Print Date/Time: 2009/07/15 15:26:52
Notes
27
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200308 Version 5 Revision 1 Print Date/Time: 2009/07/15 15:26:52
Notes
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200308 Version 5 Revision 1 Print Date/Time: 2009/07/15 15:26:52
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