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LM46001-Q1

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

LM46001-Q1 3.5V 至 60V 1A 同步降压转换器

1 特性

3 说明

1

•

符合汽车应用标准

具有符合 AEC-Q100 标准的下列特性：

LM46001-Q1 稳压器是一款易于使用的同步降压直流/

直流转换器，能够驱动高达 1A 的负载电流，输入电压

范围为 3.5V 至 60V。LM46001-Q1 以极小的解决方案

尺寸提供优异的效率、输出精度和压降电压。该器件的

扩展系列产品采用引脚对引脚兼容封装方式，可提供

0.5A 和 2A 负载电流选项。采用峰值电流模式控制来

实现简单控制环路补偿和逐周期电流限制。可选功能

包括可编程开关频率、同步、电源正常标志、精确使

能、内部软启动、可扩展软启动和跟踪，可为各种应

用提供灵活且易于使用的平台低功耗是一个关键问题。

轻负载时的断续传导和自动降低频率可改善轻负载效

率。此系列只需要很少的外部组件，而且引脚排列可实

现简单且优化的 PCB 布局。保护功能包括热关断、

–

器件温度 1 级：–40°C 至 +125°C 的工作结温

范围

•

24µA 稳压静态电流

可在轻负载条件下实现高效率（DCM 和 PFM）

测试结果符合 EN55022/CISPR 22 EMI 标准

集成同步整流

可调频率范围：200kHz 至 2.2MHz（默认值为

500kHz）

•

与外部时钟频率同步

内部补偿

与几乎任一陶瓷、聚合物、钽和铝质电容搭配使用

时均可保持稳定

V_CC欠压锁定、逐周期电流限制和输出短路保护。

•

电源正常指示

LM46001-Q1 器件采用 16 引脚 HTSSOP (PWP) 封装

(6.6mm × 5.1mm × 1.2mm)，引线间距为 0.65mm。

该器件与 LM4360x 和 LM4600x 系列引脚对引脚兼

容。LM46001A-Q1 版本针对 PFM 运行模式进行了优

化，推荐用于新设计。

软启动至预偏置负载

内部软启动：4.1ms

可由外部电容器延长的软启动时间

输出电压跟踪功能

精确使能实现系统欠压闭锁 (UVLO)

具有断续模式的输出短路保护

过热关断保护

使用 LM46001-Q1 并借助 WEBENCH^®电源设计

器创建定制设计

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

LM46001-Q1、

LM46001A-Q1

HTSSOP (16)

6.60mm × 5.10mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

2 应用

空白

•

AM 以下波段 12V 和 24V 汽车应用

电信系统

商用车辆电源

通用宽 V_IN稳压

高效负载点稳压

简化原理图

辐射发射图

V_OUT= 3.3V，V_IN= 24V，F_S= 500kHz，I_OUT= 1A

L

V_OUT

V_IN

VIN

SW

C_OUT

C_IN

LM46001-Q1

C_BOOT

dBuV

80

Vertical Polarization

CBOOT

BIAS

70

Horizontal Polarization

ENABLE

PGOOD

60

50

C_BIAS

C_FF

EN 55022 Class B Limit

40

R_FBT

SS/TRK

RT

30

20

FB

10

VCC

SYNC

AGND

R_FBB

Evaluation Board Emissions

C_VCC

30

100

Frequency (MHz)

1000

PGND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVSAA3

LM46001-Q1

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

www.ti.com.cn

7.3 Feature Description................................................. 15

7.4 Device Functional Modes........................................ 24

Applications and Implementation ...................... 25

8.1 Application Information............................................ 25

8.2 Typical Applications ................................................ 25

Power Supply Recommendations...................... 42

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements................................................ 6

6.7 Switching Characteristics.......................................... 7

6.8 Typical Characteristics.............................................. 8

Detailed Description ............................................ 14

7.1 Overview ................................................................. 14

7.2 Functional Block Diagram ....................................... 14

8

9

10 Layout................................................................... 42

10.1 Layout Guidelines ................................................. 42

10.2 Layout Example .................................................... 45

11 器件和文档支持 ..................................................... 46

11.1 器件支持................................................................ 46

11.2 接收文档更新通知 ................................................. 46

11.3 社区资源................................................................ 46

11.4 商标....................................................................... 46

11.5 静电放电警告......................................................... 46

11.6 Glossary................................................................ 46

12 机械、封装和可订购信息....................................... 46

7

4 修订历史记录

Changes from Revision A (August 2015) to Revision B

Page

•

已添加第 1 页上的 LM46001A-Q1 信息；添加了 Webench 链接.......................................................................................... 1

Added R_PGOODLM46001A-Q1 ................................................................................................................................................ 6

Changes from Original (July 2015) to Revision A

Page

•

已更改从“预览”更改为“生产数据” ........................................................................................................................................... 1

2

LM46001-Q1

www.ti.com.cn

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

5 Pin Configuration and Functions

PWP Package

16-Pin HTSSOP With Thermal Pad

Top View

SW

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

PGND

VIN

CBOOT

VCC

VIN

PAD

EN

BIAS

SS/TRK

AGND

FB

SYNC

RT

PGOOD

Pin Functions

DESCRIPTION

(1)

NAME

NUMBER

I/O

Switching output of the regulator. Internally connected to both power MOSFETs. Connect to

power inductor.

SW

1, 2

3

P

Boot-strap capacitor connection for high-side driver. Connect a high quality 470-nF capacitor from

CBOOT to SW.

CBOOT

VCC

P

Internal bias supply output for bypassing. Connect bypass capacitor from this pin to AGND. Do

not connect external load to this pin. Never short this pin to ground during operation.

4

Optional internal LDO supply input. To improve efficiency, TI recommends tying to V_OUTwhen 3.3

V ≤ V_OUT≤ 28 V, or tie to an external 3.3 V or 5 V rail if available. When used, place a bypass

capacitor (1 to 10 µF) from this pin to ground. Tie to ground if not used (V_OUT< 3.3 V). Do not

float.

BIAS

5

P

Clock input to synchronize switching action to an external clock. Use proper high speed

termination to prevent ringing. Connect to ground if not used. Do not float.

SYNC

RT

6

7

A

G

A

Connect a resistor R_Tfrom this pin to AGND to program switching frequency. Leave floating for

500 kHz default switching frequency.

Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to logic rail or other

DC voltage no higher than 12 V.

PGOOD

FB

8

Feedback sense input pin. Connect to the midpoint of feedback divider to set V_OUT. Do not short

this pin to ground during operation.

9

Analog ground pin. Ground reference for internal references and logic. Connect to system

ground.

AGND

SS/TRK

EN

10

11

12

Soft-start control pin. Leave floating for internal soft-start. Connect to a capacitor to extend soft

start time. Connect to external voltage ramp for tracking.

Enable input to the LM46001-Q1: High = ON and LOW = OFF. Connect to VIN, or to VIN through

resistor divider, or to an external voltage or logic source. Do not float.

Supply input pins to internal LDO and high side power FET. Connect to power supply and bypass

capacitors C_IN. Path from VIN pin to high frequency bypass C_INand PGND must be as short as

possible.

VIN

13, 14

P

Power ground pins, connected internally to the low side power FET. Connect to system ground,

PAD, AGND, ground pins of C_INand C_OUT. Path to C_INmust be as short as possible.

PGND

PAD

15, 16

—

G

Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path of

the die. Must be used for heat sinking to ground plane on PCB.

(1) P = Power, G = Ground, A = Analog

3

LM46001-Q1

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

VIN to PGND

MIN

–0.3

–3.5

–0.3

–65

MAX

65

UNIT

EN to PGND

V_IN+ 0.3

3.6

FB, RT, SS/TRK to AGND

Input voltages

PGOOD to AGND

SYNC to AGND

15

V

5.5

BIAS to AGND

30

AGND to PGND

0.3

SW to PGND

V_IN+ 0.3

65

SW to PGND less than 10-ns transients

CBOOT to SW

Output voltages

V

5.5

VCC to AGND

3.6

Storage temperature range, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

VIN to PGND

MIN

MAX

UNIT

3.5

–0.3

3.3

60

V_IN

1.1

12

EN

FB

Input voltages

PGOOD

V

BIAS input not used

BIAS input used

AGND to PGND

0.3

28

–0.1

0.1

Output voltage adjustable

range

V_OUT

1

28

V

Output current

Temperature

I_OUT

0

1

A

Operating junction temperature range, T_J

–40

125

°C

(1) Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For

ensured specifications, see Electrical Characteristics.

4

LM46001-Q1

www.ti.com.cn

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

6.4 Thermal Information

LM46001-Q1

THERMAL METRIC⁽¹⁾⁽²⁾

PWP (HTSSOP)

UNIT

16 PINS

39.9⁽³⁾

26.9

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

21.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.8

ψ_JB

21.5

R_θJC(bot)

2.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The package thermal impedance is calculated in accordance with JESD 51-7 standard with a 4-layer board and 1 W power dissipation.

(3)

R_θJAis highly related to PCB layout and heat sinking. Please refer to Figure 101 for measured R_θJAvs PCB area from a 2-layer board

and a 4-layer board.

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V, V_OUT= 3.3 V, F_S= 500 kHz.

PARAMETER

SUPPLY VOLTAGE (VIN PINS)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN-MIN-ST

I_SHDN

Minimum input voltage for startup

Shutdown quiescent current

3.8

5

V

V_EN= 0 V

2.3

7

µA

V_EN= 3.3 V

V_FB= 1.5 V

V_BIAS= 3.4 V external

Operating quiescent current (non-

switching) from V_IN

I_Q-NONSW

13

µA

V_EN= 3.3 V

V_FB= 1.5 V

V_BIAS= 3.4 V external

Operating quiescent current (non-

switching) from external V_BIAS

I_BIAS-NONSW

85

24

140

V_EN= 3.3 V

I_OUT= 0 A

I_Q-SW

Operating quiescent current (switching) R_T= open

V_BIAS= V_OUT= 3.3 V

µA

R_FBT= 1 Meg

ENABLE (EN PIN)

Voltage level to enable the internal LDO

output V_CC

V_EN-VCC-H

V_ENABLEhigh level

V_ENABLElow level

V_ENABLEhigh level

1.2

2

V

Voltage level to disable the internal LDO

output V_CC

V_EN-VCC-L

0.4

Precision enable level for switching and

regulator output: V_OUT

V_EN-VOUT-H

2.1

2.42

Hysteresis voltage between V_OUT

precision enable and disable thresholds

V_EN-VOUT-HYS

I_LKG-EN

V_ENABLEhysteresis

V_EN= 3.3 V

–305

0.8

mV

µA

Enable input leakage current

1.75

INTERNAL LDO (VCC PIN AND BIAS PIN)

V_CC

Internal LDO output voltage V_CC

V_IN≥ 3.8 V

3.3

V

V_CCrising threshold

3.14

Undervoltage lockout (UVLO) thresholds

for V_CC

V_CC-UVLO

Hysteresis voltage between rising and

falling thresholds

–567

2.96

–71

mV

V

V_BIASrising threshold

3.2

Internal LDO input change over

threshold to BIAS

V_BIAS-ON

Hysteresis voltage between rising and

falling thresholds

mV

5

LM46001-Q1

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

www.ti.com.cn

Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V, V_OUT= 3.3 V, F_S= 500 kHz.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOLTAGE REFERENCE (FB PIN)

T_J= 25ºC

1.009 1.016 1.023

0.999 1.016 1.039

V_FB

Feedback voltage

V

T_J= –40ºC to 125ºC

FB = 1.016 V

I_LKG-FB

Input leakage current at FB pin

0.2

65

nA

THERMAL SHUTDOWN

Shutdown threshold

Recovery threshold

160

150

(1)

T_SD

Thermal shutdown

ºC

CURRENT LIMIT AND HICCUP

I_HS-LIMIT

I_LS-LIMIT

SOFT START (SS/TRK PIN)

Peak inductor current limit

2.07

0.94

2.45

1.1

2.71

1.25

A

Valley inductor current limit

I_SSC

Soft-start charge current

Soft-start discharge resistance

1.17

2.2

16

2.85

µA

R_SSD

UVLO, TSD, OCP, or EN = 0 V

kΩ

POWER GOOD (PGOOD PIN)

Power-good flag overvoltage tripping

threshold

V_PGOOD-HIGH

% of FB voltage

110% 113%

Power-good flag undervoltage tripping

threshold

V_PGOOD-LOW

V_PGOOD-HYS

83%

90%

6%

Power-good flag recovery hysteresis

% of FB voltage

LM46001-Q1: V_EN= 3.3 V

LM46001-Q1: V_EN= 0 V

LM46001A-Q1: V_EN= 3.3 V

LM46001A-Q1: V_EN= 0 V

40

60

125

150

350

PGOOD pin pulldown resistance when

power bad

R_PGOOD

Ω

69

150

MOSFETS⁽²⁾

I_OUT= 0.5 A

V_BIAS= V_OUT= 3.3 V

R_DS-ON-HS

High-side MOSFET ON-resistance

Low-side MOSFET ON-resistance

419

231

mΩ

I_OUT= 0.5 A

V_BIAS= V_OUT= 3.3 V

R_DS-ON-LS

(1) Ensured by design.

(2) Measured at package pins.

6.6 Timing Requirements

Typical values represent the most likely parametric norm at T_J= 25°C.

MIN

NOM

MAX

UNIT

CURRENT LIMIT AND HICCUP

N_OC

T_OC

Hiccup wait cycles when LS current limit tripped

Hiccup retry delay time

32

Cycles

ms

5.5

SOFT START (SS/TRK PIN)

T_SS

Internal soft-start time when SS pin open circuit

4.1

ms

POWER GOOD (PGOOD PIN)

T_PGOOD-RISEPower-good flag rising transition deglitch delay

T_PGOOD-FALLPower-good flag falling transition deglitch delay

220

µs

6

LM46001-Q1

www.ti.com.cn

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

6.7 Switching Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V, V_OUT= 3.3 V, F_S= 500 kHz.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SW (SW PIN)

Minimum high side MOSFET ON-

time

(1)

t_ON-MIN

125

200

165

250

ns

Minimum high side MOSFET OFF-

time

(1)

t_OFF-MIN

OSCILLATOR (SW PINS AND SYNC PIN)

F_OSC-

DEFAULT

Oscillator default frequency

RT pin open circuit

445

500

570

kHz

Minimum adjustable frequency

200

2200

10%

kHz

F_ADJ

Maximum adjustable frequency

Frequency adjust accuracy

With 1% resistors at RT pin

V_SYNC-HIGHSync clock high level threshold

V_SYNC-LOWSync clock low level threshold

D_SYNC-MAXSync clock maximum duty cycle

D_SYNC-MINSync clock minimum duty cycle

2

V

0.4

90%

10%

Minimum sync clock ON- and OFF-

T_SYNC-MIN

time

80

ns

(1) Ensured by design.

7

LM46001-Q1

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

www.ti.com.cn

6.8 Typical Characteristics

Unless otherwise specified, V_IN= 24 V, V_OUT= 3.3 V, F_S= 500 kHz, L = 18 µH, C_OUT= 100 µF, C_FF= 33 pF. See Application

Performance Curves for bill of materials (BOM) for other V_OUTand F_Scombinations.

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

VIN = 36V

VIN = 42V

VIN = 8V

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

VIN = 36V

0.001

0.010

0.100

1.000

0.001

0.010

0.100

1.000

Load Current (A)

C002

C003

V_OUT= 3.3 V

F_S= 500 kHz

Figure 1. Efficiency

V_OUT= 5 V

F_S= 500 kHz

Figure 2. Efficiency

100

90

80

70

60

50

40

30

20

10

100

90

80

70

60

50

40

30

20

10

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

VIN = 8V

VIN = 24V

VIN = 42V

VIN = 12V

VIN = 28V

VIN = 48V

VIN = 18V

VIN = 36V

VIN = 60V

0

0.001

0.010

0.100

1.000

0.001

0.010

0.100

1.000

Load Current (A)

C004

C005

V_OUT= 5 V

F_S= 200 kHz

Figure 3. Efficiency

V_OUT= 5 V

F_S= 1 MHz

Figure 4. Efficiency

100

90

80

70

60

50

40

30

20

10

120

100

80

60

VIN = 24V

VIN = 28V

VIN = 36V

VIN = 42V

VIN = 48V

VIN = 60V

VIN = 36V

VIN = 42V

VIN = 48V

VIN = 60V

40

20

0

0.001

0.010

0.100

1.000

0.001

0.010

0.100

1.000

Load Current (A)

C007

C008

V_OUT= 12 V

F_S= 500 kHz

V_OUT= 24 V

F_S= 500 kHz

Figure 5. Efficiency

Figure 6. Efficiency

8

LM46001-Q1

www.ti.com.cn

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

Typical Characteristics (continued)

Unless otherwise specified, V_IN= 24 V, V_OUT= 3.3 V, F_S= 500 kHz, L = 18 µH, C_OUT= 100 µF, C_FF= 33 pF. See Application

Performance Curves for bill of materials (BOM) for other V_OUTand F_Scombinations.

3.40

3.38

3.36

3.34

3.32

3.30

3.28

3.26

3.24

3.22

3.20

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

VIN = 8V

VIN = 18V

VIN = 28V

VIN = 12V

VIN = 24V

VIN = 36V

VIN = 12V

VIN = 24V

VIN = 36V

VIN = 18V

VIN = 28V

VIN = 42V

0.001

0.010

0.100

1.000

0.001

0.010

0.100

1.000

Load Current (A)

C012

C013

V_OUT= 3.3 V

F_S= 500 kHz

Figure 7. V_OUTRegulation

V_OUT= 5 V

F_S= 500 kHz

Figure 8. V_OUTRegulation

5.15

5.10

5.05

5.00

4.95

4.90

4.85

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

VIN = 8V

VIN = 12V

VIN = 28V

VIN = 48V

VIN = 18V

VIN = 36V

VIN = 60V

VIN = 24V

VIN = 42V

4.80

0.001

0.010

0.100

1.000

0.001

0.010

0.100

1.000

Load Current (A)

C014

C015

V_OUT= 5 V

F_S= 200 kHz

V_OUT= 5 V

F_S= 1 MHz

Figure 10. V_OUTRegulation

Figure 9. V_OUTRegulation

12.5

12.4

12.3

12.2

12.1

12.0

11.9

11.8

11.7

11.6

25.0

24.8

24.6

24.4

24.2

24.0

23.8

23.6

23.4

23.2

VIN = 36V

VIN = 24V

VIN = 36V

VIN = 48V

VIN = 28V

VIN = 42V

VIN = 48V

VIN = 60V

VIN = 42V

VIN = 60V

11.5

23.0

0.001

0.010

0.100

1.000

0.001

0.010

0.100

1.000

Load Current (A)

C017

C018

V_OUT= 12 V

F_S= 500 kHz

Figure 11. V_OUTRegulation

V_OUT= 24 V

F_S= 500 kHz

Figure 12. V_OUTRegulation

9

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ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

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Typical Characteristics (continued)

Unless otherwise specified, V_IN= 24 V, V_OUT= 3.3 V, F_S= 500 kHz, L = 18 µH, C_OUT= 100 µF, C_FF= 33 pF. See Application

Performance Curves for bill of materials (BOM) for other V_OUTand F_Scombinations.

3.50

3.40

3.30

3.20

3.10

3.00

2.90

2.80

2.70

2.60

2.50

5.2

5.0

4.8

4.6

4.4

4.2

4.0

Load = 0.25A

Load = 0.5A

Load = 0.75A

Load = 1A

Load = 0.25A

Load = 0.5A

Load = 0.75A

Load = 1A

3.5

4.0

4.5

5.0

5.5

6.0

6.5

VIN (V)

C022

C023

V_OUT= 3.3 V

F_S= 500 kHz

V_OUT= 5 V

F_S= 500 kHz

Figure 13. Dropout Curve

Figure 14. Dropout Curve

5.2

5.0

4.8

4.6

4.4

4.2

5.2

5.0

4.8

4.6

4.4

4.2

Load = 0.25A

Load = 0.5A

Load = 0.75A

Load = 1A

Load = 0.25A

Load = 0.5A

Load = 0.75A

Load = 1A

4.0

5.0

4.0

5.0

5.5

6.0

6.5

5.5

6.0

6.5

VIN (V)

C024

C025

V_OUT= 5 V

F_S= 200 kHz

V_OUT= 5 V

F_S= 1 MHz

Figure 15. Dropout Curve

Figure 16. Dropout Curve

12.4

12.2

12.0

11.8

11.6

11.4

11.2

24.5

24.0

23.5

23.0

22.5

Load = 0.25A

Load = 0.5A

Load = 0.75A

Load = 1A

Load = 0.25A

Load = 0.5A

Load = 0.75A

Load = 1A

11.0

12.0

22.0

24.0

12.5

13.0

13.5

14.0

24.5

25.0

25.5

26.0

26.5

27.0

VIN (V)

C027

C028

V_OUT= 12 V

F_S= 500 kHz

V_OUT= 24 V

F_S= 500 kHz

Figure 17. Dropout Curve

Figure 18. Dropout Curve

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ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

Typical Characteristics (continued)

Unless otherwise specified, V_IN= 24 V, V_OUT= 3.3 V, F_S= 500 kHz, L = 18 µH, C_OUT= 100 µF, C_FF= 33 pF. See Application

Performance Curves for bill of materials (BOM) for other V_OUTand F_Scombinations.

1000000

100000

Load = 0.01 A

Load = 0.1 A

Load = 0.5 A

Load = 1 A

Load = 0.01 A

Load = 0.1 A

Load = 0.5 A

Load = 1 A

10000

3.4

3.6

3.8

4.0

4.2

4.4

4.6

4.8

5.0

5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0

VIN (V)

C001

V_OUT= 3.3 V

F_S= 500 kHz

V_OUT= 5 V

F_S= 1 MHz

Figure 19. Switching Frequency vs V_INin Dropout Operation

Figure 20. Switching Frequency vs V_INin Dropout Operation

dBuV

80

dBuV

80

Vertical Polarization

70

Horizontal Polarization

60

50

60

50

EN 55022 Class B Limit

40

EN 55022 Class B Limit

40

30

20

30

20

10

Evaluation Board Emissions

30

100

Frequency (MHz)

1000

30

100

Frequency (MHz)

1000

V_OUT= 3.3 V

F_S= 500 kHz

I_OUT= 1 A

V_OUT= 5 V

F_S= 500 kHz

I_OUT= 1 A

Measured on the LM46001QPWPEVM with default BOM. No input

filter used.

Measured on the LM46001QPWPEVM with L = 27 µH, C_OUT= 66

µF, C_FF= 33 pF. No input filter used.

Figure 21. Radiated EMI Curve

Figure 22. Radiated EMI Curve

dBuV

100

dBuV

100

90

80

70

90

80

70

Quasi Peak Limit

Average Limit

Quasi Peak Limit

Average Limit

60

50

40

30

20

10

60

50

40

30

20

10

Measured Peak Emissions

10

30

10

30

0.15

1

0.15

1

Frequency (MHz)

V_OUT= 3.3 V

F_S= 500 kHz

I_OUT= 1 A

V_OUT= 5 V

F_S= 500 kHz

I_OUT= 1 A

Measured on the LM46001QPWPEVM with default BOM. EVM

input filter: L_in= 1 µH C_d= 47 µF C_IN4= 68 µF

Measured on the LM46001QPWPEVM with L = 27 µH, C_OUT= 66

µF, C_FF= 33 pF. EVM input filter L_in= 1 µH C_d= 47 µF C_IN4= 68

µF

Figure 23. Conducted EMI Curve

Figure 24. Conducted EMI Curve

11

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ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

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Typical Characteristics (continued)

Unless otherwise specified, V_IN= 24 V, V_OUT= 3.3 V, F_S= 500 kHz, L = 18 µH, C_OUT= 100 µF, C_FF= 33 pF. See Application

Performance Curves for bill of materials (BOM) for other V_OUTand F_Scombinations.

800

700

600

500

400

300

200

100

0

4

3.5

3

2.5

2

1.5

1

HS

LS

VIN = 12V

VIN = 24V

0.5

0

-50

0

50

100

150

-50

0

50

100

150

Temperature (°C)

C001

Figure 25. High-Side and Low-side On Resistance vs

Junction Temperature

Figure 26. Shutdown Current vs Junction Temperature

2.5

1.4

1.2

1

2

1.5

1

EN-VOUT Rising TH

EN-VOUT Falling TH

EN-VCC Rising TH

EN-VCC Falling TH

0.8

0.6

0.4

0.5

0

0.2

VEN = 3.3V

0

-50

0

50

100

150

-50

0

50

100

150

Temperature (°C)

C001

Figure 27. Enable Threshold vs Junction Temperature

Figure 28. Enable Leakage Current vs

Junction Temperature

120%

1.030

1.025

1.020

1.015

1.010

1.005

1.000

0.995

0.990

115%

110%

105%

100%

95%

90%

OVP Trip Level

85%

VIN = 12V

VIN = 24V

OVP Recover Level

UVP Recover Level

UVP Trip Level

80%

75%

-50

0

50

Temperature (°C)

100

150

-50

0

50

100

150

Temperature (°C)

C001

Figure 29. PGOOD Threshold vs Junction Temperature

Figure 30. Feedback Voltage vs Junction Temperature

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ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

Typical Characteristics (continued)

Unless otherwise specified, V_IN= 24 V, V_OUT= 3.3 V, F_S= 500 kHz, L = 18 µH, C_OUT= 100 µF, C_FF= 33 pF. See Application

Performance Curves for bill of materials (BOM) for other V_OUTand F_Scombinations.

3.0

2.5

2.0

1.5

1.0

0.5

0.0

70

60

50

40

30

20

10

0

IL Peak Limit

IL Valley Limit

-50

0

50

100

150

0

10

20

30

40

50

60

Temperature (°C)

V_OUT= 3.3 V

VIN (V)

C001

V_IN= 24 V

F_S= 500 kHz

V_OUT= 3.3 V

F_S= 500 kHz

I_OUT= 0 A

Figure 31. Peak and Valley Current Limits vs Junction

Temperature

Figure 32. Operating I_Qvs V_INwith BIAS Connected to V_OUT

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ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

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7 Detailed Description

7.1 Overview

The LM46001-Q1 regulator is an easy-to-use synchronous step-down DC-DC converter that operates from 3.5 V

to 60 V supply voltage. It is capable of delivering up to 1 A DC load current with exceptional efficiency and

thermal performance in a very small solution size. An extended family is available in 0.5-A and 2-A load options

in pin-to-pin compatible packages.

The LM46001-Q1 employs fixed frequency peak current mode control with discontinuous conduction mode

(DCM) and pulse frequency modulation (PFM) mode at light load to achieve high efficiency across the load

range. The device is internally compensated, which reduces design time, and requires fewer external

components. The switching frequency is programmable from 200 kHz to 2.2 MHz by an external resistor, R_T. It

defaults at 500 kHz without R_T. The LM46001-Q1 is also capable of synchronization to an external clock within

the 200-kHz to 2.2-MHz frequency range. The wide switching frequency range allows the device to be optimized

to fit small board space at higher frequency, or high efficient power conversion at lower frequency.

Optional features are included for more comprehensive system requirements, including power-good (PGOOD)

flag, precision enable, synchronization to external clock, extendable soft-start time, and output voltage tracking.

These features provide a flexible and easy-to-use platform for a wide range of applications. Protection features

include overtemperature shutdown, V_CCundervoltage lockout (UVLO), cycle-by-cycle current limit, and short-

circuit protection with hiccup mode.

The family requires few external components and the pin arrangement was designed for simple, optimum PCB

layout. The LM46001-Q1 device is available in the 16-pin HTSSOP (PWP) leaded package (6.6 mm × 5.1 mm×

1.2 mm) with 0.65-mm lead pitch.

7.2 Functional Block Diagram

ENABLE

VCC

BIAS

LDO

VCC

Enable

VIN

Internal

SS

I_SSC

Precision

Enable

CBOOT

SS/TRK

HS I Sense

+

EA

+

REF

œ

R_C

C_C

+ œ

TSD

UVLO

SW

PWM CONTROL LOGIC

PFM

PGood

Detector

PGOOD

OV/UV

Detector

Slope

Comp

FB

HICCUP

Cross Detector

Freq

Foldback

Zero

Oscillator

LS I Sense

AGND

FB

PGood

SYNC

RT

PGND

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7.3 Feature Description

7.3.1 Fixed Frequency Peak Current Mode Controlled Step-Down Regulator

The following operating description of the LM46001-Q1 refers to the Functional Block Diagram and to the

waveforms in Figure 33. The LM46001-Q1 is a step-down Buck regulator with both high-side (HS) switch and

low-side (LS) switch (synchronous rectifier) integrated. The LM46001-Q1 supplies a regulated output voltage by

turning on the HS and LS NMOS switches with controlled ON-time. During the HS switch ON-time, the SW pin

voltage V_SWswings up to approximately V_IN, and the inductor current I_Lincreases with a linear slope (V_IN– V_OUT

)

/ L. When the HS switch is turned off by the control logic, the LS switch is turned on after a anti-shoot-through

dead time. Inductor current discharges through the LS switch with a slope of -V_OUT/ L. The control parameter of

buck converters are defined as duty cycle D = t_ON/ T_SW, where t_ONis the HS switch ON-time and T_SWis the

switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In

an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely

proportional to the input voltage: D = V_OUT/ V_IN.

V

SW

D = t

ON

/ T

SW

V

IN

t

OFF

ON

0

D1

t

-V

T

SW

i_L

I

LPK

OUT

ûi

L

0

t

Figure 33. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The LM46001-Q1 synchronous buck converter employs peak current mode control topology. A voltage feedback

loop is used to get accurate DC voltage regulation by adjusting the peak current command based on voltage

offset. The peak inductor current is sensed from the HS switch and compared to the peak current to control the

ON-time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external

components, makes it easy to design, and provides stable operation with almost any combination of output

capacitors. The regulator operates with fixed switching frequency in continuous conduction mode (CCM) and

discontinuous conduction mode (DCM). At very light load, the LM46001-Q1operates in PFM to maintain high

efficiency and the switching frequency decreases with reduced load current.

7.3.2 Light Load Operation

DCM operation is employed in the LM46001-Q1 when the inductor current valley reaches zero. The LM46001-Q1

is in DCM when load current is less than half of the peak-to-peak inductor current ripple in CCM. In DCM, the LS

switch is turned off when the inductor current reaches zero. Switching loss is reduced by turning off the LS FET

at zero current and the conduction loss is lowered by not allowing negative current conduction. Power conversion

efficiency is higher in DCM than CCM under the same conditions.

In DCM, the HS switch ON-time reduces with lower load current. When either the minimum HS switch ON-time

(T_ON-MIN) or the minimum peak inductor current (I_PEAK-MIN) is reached, the switching frequency will decrease to

maintain regulation. At this point, the LM46001-Q1 operates in PFM. In PFM, switching frequency is decreased

by the control loop when load current reduces to maintain output voltage regulation. Switching loss is further

reduced in PFM operation due to less frequent switching actions. Figure 34 shows an example of switching

frequency decreases with decreased load current.

15

LM46001-Q1

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Feature Description (continued)

1000000

100000

VIN = 8 V

VIN = 12 V

VIN = 18 V

VIN = 24 V

VIN = 36 V

10000

0.001

0.01

0.1

1

Load (A)

C001

Figure 34. Switching Frequency Decreases with Lower Load Current in PFM Operation

V_OUT= 5 V, F_S= 1 MHz

In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. The

lower the frequency in PFM, the more DC offset is needed at V_OUT. See the Typical Characteristics for typical DC

offset at very light load. If the DC offset on V_OUTis not acceptable for a given application, a static load at output is

recommended to reduce or eliminate the offset. Lowering values of the feedback divider R_FBTand R_FBBcan also

serve as a static load. In conditions with low V_INand/or high frequency, the LM46001-Q1 may not enter PFM

mode if the output voltage cannot be charged up to provide the trigger to activate the PFM detector. Once the

LM46001-Q1 is operating in PFM mode at higher V_IN, it remains in PFM operation when V_INis reduced.

7.3.3 Adjustable Output Voltage

The voltage regulation loop in the LM46001-Q1 regulates output voltage by maintaining the voltage on FB pin

(V_FB) to be the same as the internal REF voltage (V_REF). A resistor divider pair is needed to program the ratio

from output voltage V_OUTto V_FB. The resistor divider is connected from the V_OUTof the LM46001-Q1 to ground

with the mid-point connecting to the FB pin.

VOUT

R_FBT

FB

R_FBB

Figure 35. Output Voltage Setting

The voltage reference system produces a precise voltage reference over temperature. The internal REF voltage

is 1.016 V typically. To program the output voltage of the LM46001-Q1 to be a certain value V_OUT, R_FBBcan be

calculated with a selected R_FBTby

V_FB

R_FBB

=

R_FBT

V_OUT- V_FB

(1)

The choice of the R_FBTdepends on the application. R_FBTin the range from 10 kΩ to 100 kΩ is recommended for

most applications. A lower R_FBTvalue can be used if static loading is desired to reduce V_OUToffset in PFM

operation. Lower R_FBTreduces efficiency at very light load. Less static current goes through a larger R_FBTand

might be more desirable when light load efficiency is critical. But R_FBTlarger than 1 MΩ is not recommended

because it makes the feedback path more susceptible to noise. Larger R_FBTvalue requires more carefully

designed feedback path on the PCB. The tolerance and temperature variation of the resistor dividers affect the

output voltage regulation. It is recommended to use divider resistors with 1% tolerance or better and temperature

coefficient of 100 ppm or lower.

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ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

Feature Description (continued)

If the resistor divider is not connected properly, output voltage cannot be regulated since the feedback loop is

broken. If the FB pin is shorted to ground, the output voltage is driven close to V_IN, since the regulator sees

under voltage on the FB pin and increases the output voltage. The load connected to the output could be

damaged under such a condition. Do not short FB pin to ground when the LM46001-Q1 is enabled. It is

important to route the feedback trace away from the noisy area of the PCB. For more layout recommendations,

please refer to the Layout section.

7.3.4 Enable (ENABLE)

Voltage on the ENABLE pin (V_EN) controls the ON or OFF functionality of the LM46001-Q1. Applying a voltage

less than 0.4 V to the ENABLE input shuts down the operation of the LM46001-Q1. In shutdown mode the

quiescent current drops to typically 2.3 µA at V_IN= 24 V.

The internal LDO output voltage V_CCis turned on when V_ENis higher than 1.2 V. The switching action and output

regulation are enabled when V_ENis greater than 2.1 V (typical). The LM46001-Q1 supplies regulated output

voltage when enabled and output current up to 1 A.

The ENABLE pin is an input and cannot be left open circuited. The simplest way to enable the operation of the

LM46001-Q1 is to connect the ENABLE pin to the VIN pins directly. This allows self-start-up when V_INis within

the operation range.

Many applications will benefit from the employment of an enable divider R_ENTand R_ENBin Figure 36 to establish

a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power

as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such

as a battery discharge voltage level. An external logic signal can also be used to drive EN input for system

sequencing and protection.

VIN

R_ENT

ENABLE

R_ENB

Figure 36. System UVLO By Enable Dividers

7.3.5 VCC, UVLO and BIAS

The LM46001-Q1 integrates an internal LDO to generate V_CCfor control circuitry and MOSFET drivers. The

nominal voltage for V_CCis 3.3 V. The VCC pin is the output of the LDO and must be properly bypassed. A high

quality ceramic capacitor with 2.2 µF to 10 µF capacitance and 6.3 V or higher rated voltage should be placed as

close as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin should not be

loaded, left floating, connected to any other external supply, or shorted to ground during operation. Shorting VCC

to ground during operation may cause damage to the LM46001-Q1.

Under voltage lockout (UVLO) prevents the LM46001-Q1 from operating until the V_CCvoltage exceeds 3.14 V

(typical). The V_CCUVLO threshold has 567 mV of hysteresis (typically) to prevent undesired shuting down due to

temperary V_INdroops.

The internal LDO has two inputs: primary from VIN and secondary from BIAS input. The BIAS input powers the

LDO when V_BIASis higher than the change-over threshold. Power loss of an LDO is calculated by I_LDO* (V_IN-LDO

-

V_OUT-LDO). The higher the difference between the input and output voltages of the LDO, the more power loss

occur to supply the same output current. The BIAS input is designed to reduce the difference of the input and

output voltages of the LDO to reduce power loss and improve the LM46001-Q1 efficiency, especially at light load.

It is recommended to tie the BIAS pin to V_OUTwhen V_OUT≥ 3.3 V. The BIAS pin should be grounded in

applications with V_OUTless than 3.3 V. BIAS input can also come from an external voltage source, if available, to

reduce power loss. When used, TI recommends a 1-µF to 10-µF high-quality ceramic capacitor to bypass the

BIAS pin to ground.

17

LM46001-Q1

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www.ti.com.cn

Feature Description (continued)

7.3.6 Soft Start and Voltage Tracking (SS/TRK)

The LM46001-Q1 has a flexible and easy to use start up rate control pin: SS/TRK. The soft start feature is there

to prevent inrush current impacting the LM46001-Q1 and its supply when power is first applied. Soft start is

achieved by slowly ramping up the target regulation voltage when the device is first enabled or powered up.

The simplest way to use the device is to leave the SS/TRK pin open circuit. The LM46001-Q1 employs the

internal soft-start control ramp and start up to the regulated output voltage in 4.1 ms typically.

In applications with a large amount of output capacitors, or higher V_OUT, or other special requirements, the soft-

start time can be extended by connecting an external capacitor C_SSfrom SS/TRK pin to AGND. Extended soft-

start time further reduces the supply current needed to charge up output capacitors and supply any output

loading. An internal current source (I_SSC= 2.2 µA) charges C_SSand generates a ramp from 0 V to V_FBto control

the ramp-up rate of the output voltage. V_FBvalue is typically 1 V, and therefore it is not mentioned in Equation 2.

For a desired soft start time t_SS, the capacitance for C_SScan be found by:

C_SS= I_SSCì t_SS

(2)

The soft start capacitor C_SSis discharged by an internal FET when V_OUTis shutdown by hiccup protection due to

excessive load, temperature shutdown due to overheating or ENABLE = logic low. A large C_SScap will take a

long time to discharge when ENABLE is toggled low. If ENABLE is toggled high again before the C_SSis

completely discharged, then the next resulting soft-start ramp will follow the internal soft-start ramp. Only when

the soft-start voltage reaches the left-over voltage on C_SS, will the output follow the ramp programmed by C_SS

.

This behavior will look as if there are two slopes at startup. If this is not acceptable by a certain application, a R-

C low-pass filter can be added to ENABLE to slow down the shutting down of VCC, which allows more time to

discharge C_SS

.

The LM46001-Q1 is capable of start up into prebiased output conditions. When the inductor current reaches

zero, the LS switch will be turned off to avoid negative current conduction. This operation mode is also called

diode emulation mode. It is built-in by the DCM operation at light loads. With a prebiased output voltage, the

LM46001-Q1 will wait until the soft-start ramp allows regulation above the prebiased voltage. It will then follow

the soft-start ramp to the regulation level.

When an external voltage ramp is applied to the SS/TRK pin, the LM46001-Q1 FB voltage follows the external

ramp if the ramp magnitude is lower than the internal soft-start ramp. A resistor divider pair can be used on the

external control ramp to the SS/TRK pin to program the tracking rate of the output voltage. The final external

ramp voltage applied at the SS/TRK pin must be above 1.2 V to avoid abnormal operation.

EXT RAMP

R_TRT

SS/TRK

R_TRB

Figure 37. Soft-Start Tracking External Ramp

V_OUTtracked to an external voltage ramp has the option of ramping up slower or faster than the internal voltage

ramp. V_FBalways follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin.

Figure 38 shows the case when V_OUTramps slower than the internal ramp, while Figure 39 shows when V_OUT

ramps faster than the internal ramp. Faster start up time may result in inductor current tripping current protection

during start-up. Use with special care.

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ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

Feature Description (continued)

Enable

Internal SS Ramp

Ext Tracking Signal to SS pin

V_OUT

Figure 38. Tracking With Longer Start-up Time Than The Internal Ramp

Enable

Internal SS Ramp

Ext Tracking Signal to SS pin

V_OUT

Figure 39. Tracking With Shorter Start-up Time Than the Internal Ramp

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Feature Description (continued)

7.3.7 Switching Frequency (RT) and Synchronization (SYNC)

The switching frequency of the LM46001-Q1 can be programmed by the resistor R_Tfrom the RT pin to ground.

The frequency is inversely proportional to the R_Tresistance. The RT pin can be left floating, and the LM46001-

Q1 will operate at 500-kHz default switching frequency. The RT pin is not designed to be connected to ground or

any other voltage.

For a desired frequency, typical R_Tresistance can be found by Equation 3.

R_T(kΩ) = 40200 / Freq (kHz) – 0.6

(3)

Figure 40 shows R_Tresistance vs switching frequency F_Scurve.

250

200

150

100

50

0

500

1000

1500

2000

2500

Switching Frequency (kHz)

C008

Figure 40. R_TResistance vs Switching Frequency

Table 1 provides typical R_Tvalues for a given F_S.

Table 1. Typical Frequency Setting R_TResistance

F_S(kHz)

R_T(kΩ)

200

350

115

500

80.6

53.6

39.2

26.1

19.6

17.8

750

1000

1500

2000

2200

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Feature Description (continued)

The LM46001-Q1 switching action can also be synchronized to an external clock from 200 kHz to 2.2 MHz.

Connect an external clock to the SYNC pin, with proper high speed termination, to avoid ringing. The SYNC pin

should be grounded if not used.

SYNC

EXT CLOCK

R_TERM

Figure 41. Frequency Synchronization

The recommendations for the external clock include high level no lower than 2 V, low level no higher than 0.4 V,

duty cycle between 10% and 90% and both positive and negative pulse width no shorter than 80 ns. When the

external clock fails at logic high or low, the LM46001-Q1 switches at the frequency programmed by the R_T

resistor after a time-out period. It is recommended to connect a resistor R_Tto the RT pin such that the internal

oscillator frequency is the same as the target clock frequency when the LM46001-Q1 is synchronized to an

external clock. This allows the regulator to continue operating at approximately the same switching frequency if

the external clock fails.

The choice of switching frequency is usually a compromise between conversion efficiency and the size of the

application circuit. Lower switching frequency implies reduced switching losses (including gate charge losses,

switch transition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency

allows use of smaller LC output filters and hence a more compact design. Lower inductance also helps transient

response (higher large signal slew rate of inductor current), and reduces the DCR loss. The optimal switching

frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis.

It is related to the input voltage, output voltage, most frequent load current level(s), external component choices,

and circuit size requirement. The choice of switching frequency may also be limited if an operating condition

triggers t_ON-MINor t_OFF-MIN

.

7.3.8 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions

Minimum ON-time, t_ON-MIN, is the smallest duration of time that the HS switch can be on. T_ON-MINis typically 125

ns in the LM46001-Q1. Minimum OFF-time, t_OFF-MIN, is the smallest duration that the HS switch can be off. T_OFF-

_MINis typically 200 ns in the LM46001-Q1.

In CCM operation, t_ON-MINand t_OFF-MINlimits the voltage conversion range given a selected switching frequency.

The minimum duty cycle allowed is

D_MIN= t_ON-MIN× F_S

(4)

And the maximum duty cycle allowed is

D_MAX= 1 – t_OFF-MIN× F_S

(5)

Given fixed t_ON-MINand t_OFF-MIN, the higher the switching frequency the narrower the range of the allowed duty

cycle. In the LM46001-Q1, a frequency foldback scheme is employed to extend the maximum duty cycle when

t_OFF-MINis reached. The switching frequency decreases once longer duty cycle is needed under low VIN

conditions. The switching frequency can be decreased to approximately 1/10 of the programmed frequency by R_T

or the synchronization clock. Such wide range of frequency foldback allows the LM46001-Q1 output voltage to

stay in regulation with a much lower supply voltage V_IN. This leads to a lower effective Dropout voltage. See

Typical Characteristics for more details.

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution

size and efficiency. The maximum operating supply voltage can be found by

V_IN-MAX= V_OUT/ (F_S× t_ON-MIN

)

(6)

At lower supply voltage, the switching frequency decreases once t_OFF-MINis tripped. The minimum V_INwithout

frequency foldback can be approximated by:

V_IN-MIN= V_OUT/ (1 – F_S× t_OFF-MIN

)

(7)

Taking considerations of power losses in the system with heavy load operation, V_IN-MINis higher than the result

calculated in Equation 7 . With frequency foldback, V_IN-MINis lowered by decreased F_S. Figure 42 gives an

example of how F_Sdecreases with decreasing supply voltage V_INat dropout operation.

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Feature Description (continued)

1000000

100000

10000

Load = 0.01 A

Load = 0.1 A

Load = 0.5 A

Load = 1 A

5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0

VIN (V)

C001

Figure 42. Switching Frequency Decreases in Dropout Operation

V_OUT= 5 V, F_S= 1 MHz

7.3.9 Internal Compensation and C_FF

The LM46001-Q1 is internally compensated with R_C= 400 kΩ and C_C= 50 pF as shown in Functional Block

Diagram. The internal compensation is designed so that the loop response is stable over the entire operating

frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can

be low with all ceramic capacitors at the output. TI recommends an external feed-forward capacitor C_FFbe

placed in parallel with the top resistor divider R_FBTfor optimum transient performance as shown in Figure 43.

VOUT

R_FBT

C_FF

FB

R_FBB

Figure 43. Feed-Forward Capacitor for Loop Compensation

The feed-forward capacitor C_FFin parallel with R_FBTplaces an additional zero before the crossover frequency of

the control loop to boost phase margin. The zero frequency can be found by:

f_Z-CFF= 1 / ( 2π × R_FBT× C_FF

)

(8)

An additional pole is also introduced with C_FFat the frequency of

f_P-CFF= 1 / ( 2π × C_FF× ( R_FBT// R_FBB))

(9)

Select the C_FFso that the bandwidth of the control loop without the C_FFis centered between f_Z-CFFand f_P-CFF. The

zero f_Z-CFFadds phase boost at the crossover frequency and improves transient response. The pole f_P-CFFhelps

maintaining proper gain margin at frequency higher than the crossover frequency.

Designs with different combinations of output capacitors need different C_FF. Different types of capacitors have

different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most C_FF.

Electrolytic capacitors have much larger ESR and the ESR zero frequency

f_Z-ESR= 1 / ( 2π × ESR × C_OUT

)

(10)

and would be low enough to boost the phase up around the crossover frequency. Designs using mostly

electrolytic capacitors at the output may not need any C_FF.

The C_FFcreates a time constant with R_FBTthat couples in the attenuated output voltage ripple to the FB node. If

the C_FFvalue is too large, it can couple too much ripple to the FB and affect V_OUTregulation. It could also couple

too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, calculate C_FFbased on

output capacitors used in the system. At cold temperatures, the value of C_FFmight change based on the

tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To

avoid this, more capacitance can be added to the output or the value of C_FFcan be reduced. See the Detailed

Design Procedure for the calculation of C_FF.

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Feature Description (continued)

7.3.10 Bootstrap Voltage (BOOT)

The driver of the HS switch requires a bias voltage higher than V_INwhen the HS switch is ON. The capacitor

connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to (V_SW

+

V_CC). The boot diode is integrated on the LM46001-Q1 die to minimize the bill of material (BOM). A synchronous

switch is also integrated in parallel with the boot diode to reduce voltage drop on CBOOT. A high quality ceramic

0.47-µF, 6.3-V or higher capacitor is recommended for C_BOOT

.

7.3.11 Power Good (PGOOD)

The LM46001-Q1 has a built in power-good flag at the PGOOD pin to indicate whether the output voltage is

within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault

protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate DC voltage.

Voltage detected by the PGOOD pin should never exceed 12 V. A resistor divider pair can be used to divide the

voltage down from a higher potential. A typical range of pullup resistor value is 10 kΩ to 100 kΩ.

When the FB voltage is within the power-good band, +4% above and –4% below the internal reference V_REF

typically, the PGOOD switch is turned off and the PGOOD voltage will be pulled up to the voltage level defined

by the pull up resistor or divider. When the FB voltage is outside of the tolerance band, +10 % above or –10 %

below V_REFtypically, the PGOOD switch is turned on and the PGOOD pin voltage will be pulled low to indicate

power bad. Both rising and falling edges of the power-good flag have a built-in 220 µs (typical) deglitch delay.

7.3.12 Overcurrent and Short Circuit Protection

The LM46001-Q1 is protected from overcurrent conditions by cycle-by-cycle current limiting on both peak and

valley of the inductor current. Hiccup mode is activated to prevent over heating if a fault condition persists.

High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The

HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is

compared to the output of the error amplifier (EA) minus slope compensation every switching cycle. See

Functional Block Diagram for more details. The peak current of the HS switch is limited by the maximum EA

output voltage minus the slope compensation at every switching cycle. The slope compensation magnitude at the

peak current is proportional to the duty cycle.

When the LS switch is turned on, the current going through it is also sensed and monitored. The LS switch is not

turned OFF at the end of a switching cycle if its current is above the LS current limit I_LS-LIMIT. The LS switch is

kept ON so that inductor current keeps ramping down, until the inductor current ramps below I_LS-LIMIT. Then the

LS switch is turned OFF, and the HS switch is turned on after a dead time. If the current of the LS switch is

higher than the LS current limit for 32 consecutive cycles and the power-good flag is low, hiccup current

protection mode is activated. In hiccup mode, the regulator is shut down and kept off for 5.5 ms typically before

the LM46001-Q1 tries to start again. If overcurrent or short-circuit fault condition still exist, hiccup will repeat until

the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions,

preventing over heating and potential damage to the device.

Hiccup is only activated when the power-good flag is low. Under non-severe overcurrent conditions when V_OUT

has not fallen outside of the PGOOD tolerance band, the LM46001-Q1 reduces the switching frequency and

keeps the inductor current valley clamped at the LS current limit level. This operation mode allows slight over

current operation during load transients without tripping hiccup. If the power-good flag becomes low, hiccup

operation starts after LS current limit is tripped 32 consecutive cycles.

7.3.13 Thermal Shutdown

Thermal shutdown is a built-in self protection to limit junction temperature and prevent damages due to over

heating. Thermal shutdown turns off the device when the junction temperature exceeds 160°C typically to

prevent further power dissipation and temperature rise. The junction temperature reduces after thermal

shutdown. The LM46001-Q1 attempts to restart when the junction temperature drops to 150°C.

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7.4 Device Functional Modes

7.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control for the LM46001-Q1. When V_ENis below 0.4 V, the device is

in shutdown mode. Both the internal LDO and the switching regulator are off. In shutdown mode the quiescent

current drops to 2.3 µA typically with V_IN= 24 V. The LM46001-Q1 also employs UVLO protection. If the V_CC

voltage is below the UVLO level, the output of the regulator is turned off.

7.4.2 Standby Mode

The internal LDO has a lower enable threshold than the regulator. When ENABLE voltage is above 1.2 V and

below the precision enable falling threshold (1.8 V typically), the internal LDO regulates the V_CCvoltage at 3.3 V.

The precision enable circuitry is turned on once V_CCis above the UVLO threshold. The switching action and

voltage regulation are not enabled unless V_ENrises above the precision enable threshold (2.1 V typically).

7.4.3 Active Mode

The LM46001-Q1 is in active mode when V_ENis above the precision enable threshold and V_CCis above its UVLO

level. The simplest way to enable the LM46001-Q1 is to connect the EN pin to V_IN. This allows self start-up when

the input voltage is in the operation range: 3.5 V to 60 V. See Enable (ENABLE) and VCC, UVLO and BIAS for

details on setting these operating levels.

In Active Mode, depending on the load current, the LM46001-Q1 is in one of four modes:

1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the

peak-to-peak inductor current ripple;

2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of

the peak-to-peak inductor current ripple in CCM operation;

3. Pulse frequency modulation (PFM) when switching frequency is decreased at very light load;

4. Foldback mode when switching frequency is decreased to maintain output regulation at lower supply voltage

V_IN.

7.4.4 CCM Mode

Continuous conduction mode (CCM) operation is employed in the LM46001-Q1 when the load current is higher

than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed unless the

minimum HS switch ON-time (t_{ON_MIN}), the minimum HS switch OFF-time (t_{OFF_MIN}) or LS current limit is

exceeded. The output voltage ripple is at a minimum in this mode and the maximum output current of 1 A can be

supplied by the LM46001-Q1 device.

7.4.5 Light Load Operation

When the load current is lower than half of the peak-to-peak inductor current in CCM, the LM46001-Q1 operates

in discontinuous conduction mode (DCM), also known as diode emulation mode (DEM). In DCM operation, the

LS FET is turned off when the inductor current drops to 0 A to improve efficiency. Both switching losses and

conduction losses are reduced in DCM, comparing to forced PWM operation at light load.

At even lighter current loads, pulse frequency mode (PFM) is activated to maintain high efficiency operation.

When the HS switch ON-time reduces to t_{ON_MIN}or peak inductor current reduces to its minimum I_PEAK-MIN, the

switching frequency reduces to maintain proper regulation. Efficiency is greatly improved by reducing switching

and gate drive losses.

7.4.6 Self-Bias Mode

For highest efficiency of operation, TI recommends that the BIAS pin be connected directly to V_OUTwhen V_OUT

≥

3.3 V. In this self-bias mode of operation, the difference between the input and output voltages of the internal

LDO are reduced, and therefore the total efficiency is improved. These efficiency gains are more evident during

light load operation. During this mode of operation, the LM46001-Q1 operates with a minimum quiescent current

of 24 µA (typical). See VCC, UVLO and BIAS for more details.

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8 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM46001-Q1 is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a

lower DC voltage with a maximum output current of 1 A. The following design procedure can be used to select

components for the LM46001-Q1. Alternately, the WEBENCH® software may be used to generate complete

designs. When generating a design, the WEBENCH® software utilizes iterative design procedure and accesses

comprehensive databases of components. See www.ti.com and Detailed Design Procedure for more details.

This section presents a simplified discussion of the design process.

8.2 Typical Applications

The LM46001-Q1 only requires a few external components to convert from a wide range of supply voltage to

output voltage. Figure 44 shows a basic schematic when BIAS is connected to V_OUT. This is recommended for

V_OUT≥ 3.3 V. For V_OUT< 3.3 V, BIAS must be connected to ground, as shown in Figure 45.

L

V_OUT

V_IN

VIN

SW

VIN

SW

C_OUT

C_IN

LM46001-Q1

C_IN

LM46001-Q1

C_BOOT

CBOOT

BIAS

CBOOT

BIAS

ENABLE

PGOOD

ENABLE

PGOOD

C_BIAS

C_FF

R_FBT

SS/TRK

RT

SS/TRK

RT

FB

VCC

SYNC

AGND

SYNC

AGND

R_FBB

C_VCC

PGND

Figure 44. LM46001-Q1 Basic Schematic for

_OUT≥ 3.3 V, tie BIAS to V_OUT

Figure 45. LM46001-Q1 Basic Schematic for

V_OUT< 3.3 V, tie BIAS to Ground

V

The LM46001-Q1 also integrates a full list of optional features to aid system design requirements, such as

precision enable, V_CCUVLO, programmable soft-start, output voltage tracking, programmable switching

frequency, clock synchronization and power-good indication. Each application can select the features for a more

comprehensive design. A schematic with all features utilized is shown in Figure 46.

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Typical Applications (continued)

L

V_IN

V_OUT

VIN

SW

C_OUT

C_FF

C_IN

LM46001-Q1

C_BOOT

R_ENT

R_FBT

CBOOT

FB

ENABLE

R_ENB

VCC

R_FBB

SS/TRK

RT

C_VCC

C_SS

BIAS

R_T

C_BIAS

SYNC

AGND

PGOOD

PGND

R_SYNC

Tie BIAS to PGND

when V_OUT< 3.3 V

Figure 46. LM46001-Q1 Schematic with All Features

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Typical Applications (continued)

The external components have to fulfill the needs of the application, but also the stability criteria of the device's

control loop. The LM46001-Q1 is optimized to work within a range of external components. The LC output filter's

inductance and capacitance have to be considered in conjunction, creating a double pole, responsible for the

corner frequency of the converter. Table 2 can be used to simplify the output filter component selection.

Table 2. L, C_OUTand C_FFTypical Values

(2)

(3)(4)

F_S(kHz)

V_OUT= 1 V

L (µH)⁽¹⁾

C_OUT(µF)

C_FF(pF)

R_T(kΩ)

R_FBB(kΩ)

200

500

18

6.8

3.3

1.5

500

330

180

100

none

200

80.6 or open

39.2

100

1000

2200

17.8

V_OUT= 3.3 V

200

47

18

10

4.7

220

100

47

44

33

18

12

200

80.6 or open

39.2

442

500

1000

2200

27

17.8

V_OUT= 5 V

200

56

27

15

6.8

150

66

33

22

18

200

80.6 or open

39.2

249

500

1000

33

2200

22

17.8

V_OUT= 12 V

200

(5)

100

47

33

22

15

see note

47

200

80.6 or open

39.2

93.1

500

1000

22

33

V_OUT= 24 V

200

(5)

180

82

22

15

10

see note

200

80.6 or open

39.2

44.2

500

1000

47

(1) Inductor values are calculated based on typical V_IN= 24 V. For V_OUT= 24 V, V_IN= 48 V.

(2) All the C_OUTvalues are after derating. Add more when using ceramics

(3) R_FBT= 0 Ω for V_OUT= 1 V. R_FBT= 1 MΩ for all other V_OUTsettings.

(4) For designs with R_FBTother than 1 MΩ, adjust C_FFsuch that (C_FF× R_FBT) is unchanged and adjust R_FBBsuch that (R_FBT/ R_FBB) is

unchanged.

(5) High ESR C_OUTgives enough phase boost and C_FFmight not be needed.

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Typical Applications (continued)

8.2.1 Design Requirements

A detailed design procedure is described based on a design example. For this design example, use the

parameters listed in Table 3 as the input parameters.

Table 3. Design Example Parameters

DESIGN PARAMETER

Input voltage V_IN

VALUE

24 V typical, range from 3.8 V to 60 V

Output voltage V_OUT

Input ripple voltage

Output ripple voltage

Output current rating

Operating frequency

Soft-start time

3.3 V

400 mV

30 mV

1 A

500 kHz

10 ms

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM46001-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Setpoint

The output voltage of the LM46001-Q1 device is externally adjustable using a resistor divider network. The

divider network is comprised of top feedback resistor R_FBTand bottom feedback resistor R_FBB. Equation 11 is

used to determine the output voltage of the converter:

V_FB

R_FBB

=

R_FBT

V_OUT- V_FB

(11)

Choose the value of the R_FBTto be 1 MΩ to minimize quiescent current to improve light load efficiency in this

application. With the desired output voltage set to be 3.3 V and the V_FB= 1.016 V, the R_FBBvalue can then be

calculated using Equation 11. The formula yields a value of 444.83 kΩ. Choose the closest available value of 442

kΩ for the R_FBB. See Adjustable Output Voltage for more details.

8.2.2.3 Switching Frequency

The default switching frequency of the LM46001-Q1 device is set at 500 kHz when RT pin is open circuit. The

switching frequency is selected to be 500 kHz in this application for one less passive components. If other

frequency is desired, use Equation 12 to calculate the required value for R_T.

R_T(kΩ) = 40200 / Freq (kHz) – 0.6

(12)

For 500 kHz, the calculated R_Tis 79.8 kΩ, and standard value 80.6 kΩ can also be used to set the switching

frequency at 500 kHz.

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8.2.2.4 Input Capacitors

The LM46001-Q1 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor,

depending on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7

µF to 10 µF. A high-quality ceramic type X5R or X7R with sufficient voltage rating is recommended. The voltage

rating must be greater than the maximum input voltage. To compensate the derating of ceramic capacitor, TI

recommends a voltage rating of twice the maximum input voltage. Additionally, some bulk capacitance may be

required, especially if the LM46001-Q1 circuit is not located within approximately 5 cm from the input voltage

source. The bulk input capacitor is used to provide damping to the voltage spiking due to the lead inductance of

the cable or trace. The value for this capacitor is not critical but must be rated to handle the maximum input

voltage including ripple.

For this design, a 10 µF, X7R dielectric capacitor rated for 100 V is used for the input decoupling capacitor. The

equivalent series resistance (ESR) is approximately 3 mΩ, and the current-rating is 3 A. Include a capacitor with

a value of 0.1 µF for high-frequency filtering and place it as close as possible to the device pins.

NOTE

DC Bias effect: High capacitance ceramic capacitors have a DC bias effect, which will

have a strong influence on the final effective capacitance. Therefore the right capacitor

value has to be chosen carefully. Package size and voltage rating in combination with

dielectric material are responsible for differences between the rated capacitor value and

the effective capacitance.

8.2.2.5 Inductor Selection

The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is

based on the desired peak-to-peak ripple current, Δi_L, that flows in the inductor along with the DC load current.

As with switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductance

gives lower ripple current and hence lower output voltage ripple with the same output capacitors. Lower

inductance could result in smaller, less expensive component. An inductance that gives a ripple current of 20% to

40% of the 1 A at the typical supply voltage is a good starting point. Δi_L= (1/5 to 2/5) × I_OUT. The peak-to-peak

inductor current ripple can be found by Equation 13 and the range of inductance can be found by Equation 14

with the typical input voltage used as V_IN.

(V_IN- V_OUT)ìD

Di_L=

L ìF_S

(13)

(V_IN- V_OUT)ìD

0.4ìF_SìI_L-MAX

(V_IN- V_OUT)ìD

0.2ìF_SìI_L-MAX

Ç L Ç

(14)

D is the duty cycle of the converter, which in a buck converter it can be approximated as D = V_OUT/ V_IN,

assuming no loss power conversion. By calculating in terms of amperes, volts, and megahertz, the inductance

value will come out in micro Henries. The inductor ripple current ratio is defined by:

Di_L

I_OUT

r =

(15)

The second criterion is the inductor saturation current rating. The inductor must be rated to handle the maximum

load current plus the ripple current:

I_L-PEAK= I_LOAD-MAX+ Δ i_L

(16)

The LM46001-Q1 has both valley current limit and peak current limit. During an instantaneous short, the peak

inductor current can be high due to a momentary increase in duty cycle. The inductor current rating should be

higher than the HS current limit. It is advised to select an inductor with a larger core saturation margin and

preferably a softer roll off of the inductance value over load current.

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In general, choosing lower inductance is prefereable in switching power supplies, because it usually corresponds

to faster transient response, smaller DCR, and reduced size for more compact designs. But an inductance that is

too low can generate too large of an inductor current ripple such that overcurrent protection at the full load could

be falsely triggered. It also generates more conduction loss, since the RMS current is slightly higher relative that

with lower current ripple at the same DC current. Larger inductor current ripple also implies larger output voltage

ripple with the same output capacitors. With peak current mode control, it is not recommended to have too small

of an inductor current ripple. Enough inductor current ripple improves signal-to-noise ratio on the current

comparator and makes the control loop more immune to noise.

Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core

losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and

preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when

the peak design current is exceeded. The ‘hard’ saturation results in an abrupt increase in inductor ripple current

and consequent output voltage ripple. Do not allow the core to saturate!

For the design example, a standard 18-μH inductor from Würth, Coiltronics, or Vishay can be used for the 3.3-V

output with plenty of current rating margin.

8.2.2.6 Output Capacitor Selection

The device is designed to be used with a wide variety of LC filters. It is generally desired to use as little output

capacitance as possible to keep cost and size down. The output capacitor (s), C_OUT, must be chosen with care

since it directly affects the steady-state output voltage ripple, loop stability and the voltage over/undershoot

during load current transients.

The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going

through the equivalent series resistance (ESR) of the output capacitors:

ΔV_OUT-ESR= Δi_L× ESR

(17)

The other is caused by the inductor current ripple charging and discharging the output capacitors:

ΔV_OUT-C= Δi_L/ ( 8 × F_S× C_OUT

)

(18)

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the

sum of the two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage

regulation in the presence of large current steps and fast slew rates. When a fast large load transient happens,

output capacitors provide the required charge before the inductor current can slew to the appropriate level. The

initial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to droop until

the control loop response increases or decreases the inductor current to supply the load. To maintain a small

over-shoot or under-shoot during a transient, small ESR and large capacitance are desired. But these also come

with higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output

voltage deviation.

For a given input and output requirement, Equation 19 gives an approximation for an absolute minimum output

capacitor required:

2

»

…

ÿ

Ÿ

≈

’

1

r

Å

C_OUT

>

ì

ì(1+ D ) + D ì(1+ r)

∆

÷

(

)

÷

(F_Sìr ì DV_OUT/ I_OUT

)

12

Ÿ

⁄

«

◊

(19)

Along with this for the same requirement, calculate the maximum ESR per Equation 20

Å

D

1

ESR <

ì( + 0.5)

F_SìC_OUT

r

where

•

r = ripple ratio of the inductor ripple current (ΔI_L/ I_OUT

ΔV_OUT= target output voltage undershoot

D’ = 1 – duty cycle

)

F_S= switching frequency

I_OUT= load current

(20)

30

LM46001-Q1

www.ti.com.cn

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

A general guideline for C_OUTrange is that C_OUTmust be larger than the minimum required output capacitance

calculated by Equation 19, and smaller than 10 times the minimum required output capacitance or 1 mF. In

applications with V_OUTless than 3.3 V, it is critical that low ESR output capacitors are selected. This limits

potential output voltage overshoots as the input voltage falls below the device normal operating range. To

optimize the transient behavior a feed-forward capacitor could be added in parallel with the upper feedback

resistor. For this design example, two 47-µF,10-V, X7R ceramic capacitors are used in parallel.

8.2.2.7 Feed-Forward Capacitor

The LM46001-Q1 is internally compensated and the internal R-C values are 400 kΩ and 50 pF respectively.

Depending on the V_OUTand frequency F_S, if the output capacitor C_OUTis dominated by low ESR (ceramic types)

capacitors, it could result in low phase margin. To improve the phase boost an external feedforward capacitor

C_FFcan be added in parallel with R_FBT. C_FFis chosen such that phase margin is boosted at the crossover

frequency that occurs with C_FFremoved. A simple estimation for the crossover frequency without C_FF(f_x) is

shown in Equation 21, assuming C_OUThas very small ESR.

2.73

f_x=

V_OUTìC_OUT

(21)

Equation 22 for C_FFwas tested:

1

C_FF

=

ì

2pf_x

R_FBTì(R_FBT/ /R_FBB

)

(22)

Equation 22 indicates that the crossover frequency is geometrically centered on the zero and pole frequencies

caused by the C_FFcapacitor.

For designs with higher ESR, C_FFis not neeed when C_OUThas very high ESR and C_FFcalculated from

Equation 22 must be reduced with medium ESR. Table 2 can be used as a quick starting point.

For the application in this design example, a 33-pF COG capacitor is selected.

8.2.2.8 Bootstrap Capacitors

Every LM46001-Q1 design requires a bootstrap capacitor, C_BOOT. The recommended bootstrap capacitor is 0.47

μF and rated at 6.3 V or higher. The bootstrap capacitor is located between the SW pin and the CBOOT pin. The

bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature

stability.

8.2.2.9 VCC Capacitor

The VCC pin is the output of an internal LDO for LM46001-Q1. The input for this LDO comes from either VIN or

BIAS (see Functional Block Diagram for LM46001-Q1). To insure stability of the part, place a minimum of 2.2-µF,

10-V capacitor from this pin to ground.

8.2.2.10 BIAS Capacitors

For an output voltage of 3.3 V and greater, the BIAS pin can be connected to the output in order to increase light

load efficiency. This pin is an input for the VCC LDO. When BIAS is not connected, the input for the VCC LDO is

internally connected into VIN. Because this is an LDO, the voltage differences between the input and output

affects the efficiency of the LDO. If necessary, a capacitor with a value of 1 μF can be added close to the BIAS

pin as an input capacitor for the LDO.

31

LM46001-Q1

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

www.ti.com.cn

8.2.2.11 Soft-Start Capacitors

The user can leave the SS/TRK pin floating and the LM46001-Q1 implements a soft-start time of 4.1 ms typically.

In order to use an external soft-start capacitor, the capacitor must be sized such that the soft-start time is longer

than 4.1 ms. Use Equation 23 to calculate the soft-start capacitor value:

C_SS= I_SSCì t_SS

where

•

C_SS= soft-start capacitor value (µF)

I_SS= soft-start charging current (µA)

t_SS= desired soft-start time (s)

(23)

For the desired soft-start time of 10 ms and soft-start charging current of 2.2 µA, Equation 23 yields a soft-start

capacitor value of 0.022 µF.

8.2.2.12 Undervoltage Lockout Set-Point

The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R_ENTand R_ENB. R_ENT

is connected between VIN and the EN pin of the LM46001-Q1 device. R_ENBis connected between the EN pin

and the GND pin. The UVLO has two thresholds, one for power up when the input voltage is rising and one for

power down or brownouts when the input voltage is falling. Equation 24 can be used to determine the rising VIN

(UVLO) level:

V_{IN-UVLO-RISING}= V_ENH× (R_ENB+ R_ENT) / R_ENB

(24)

The EN rising threshold for LM46001-Q1 is set to be 2.1 V. Choose the value of R_ENBto be 1 MΩ to minimize

input current going into the converter. If the desired VIN (UVLO) level is at 5 V, then the value of R_ENTcan be

calculated using Equation 25:

R_ENT= (V_{IN-UVLO-RISING}/ V_ENH– 1) × R_ENB

(25)

Equation 25 yields a value of 1.37 MΩ. The resulting falling UVLO threshold can be calculated as follows:

V_{IN-UVLO-FALLING}= 1.8 × (R_ENB+ R_ENT) / R_ENB

(26)

8.2.2.13 PGOOD

A typical pullup resistor value is 10 kΩ to 100 kΩ from the PGOOD pin to a voltage no higher than 12 V. If it is

desired to pull up the PGOOD pin to a voltage higher than 12 V, a resistor can be added from the PGOOD pin to

ground to divide the voltage seen by the PGOOD pin to a value no higher than 12 V.

32

LM46001-Q1

www.ti.com.cn

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

8.2.3 Application Performance Curves

See Table 2 for bill of materials for each V_OUTand F_Scombination. Unless otherwise stated, application performance curves

were taken at T_A= 25°C.

100

90

V_OUT= 3.3 V F_S= 500 kHz

80

70

L=18 µH

V_OUT

60

50

40

30

20

10

0

SW

LM46001-Q1

RT

C_OUT

C_BOOT

CBOOT

BIAS

0.47 µF

100 µF

VIN = 8V

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

VIN = 36V

C_BIAS

1 µF

R_FBT

1 MΩ

C_FF

VCC

C_VCC

33 pF

FB

2.2 µF

R_FBB

432

kΩ

0.001

0.010

0.100

1.000

Load Current (A)

C002

V_OUT= 3.3 V

F_S= 500 kHz

V_IN= 24 V

V_OUT= 3.3 V

F_S= 500 kHz

Figure 47. BOM for V_OUT= 3.3 V F_S= 500 kHz

Figure 48. Efficiency

3.40

3.38

3.36

3.34

3.32

3.30

3.28

3.26

3.24

3.22

3.20

3.50

3.40

3.30

3.20

3.10

3.00

2.90

2.80

2.70

2.60

2.50

Load = 0.25A

Load = 0.5A

Load = 0.75A

Load = 1A

VIN = 8V

VIN = 18V

VIN = 28V

VIN = 12V

VIN = 24V

VIN = 36V

0.001

0.010

0.100

1.000

3.5

4.0

4.5

5.0

Load Current (A)

VIN (V)

C012

C022

V_OUT= 3.3 V

F_S= 500 kHz

V_OUT= 3.3 V

F_S= 500 kHz

Figure 49. Output Voltage Regulation

Figure 50. Dropout Curve

1.2

1

V_{DROP_ON_0.75Ω_LOAD}

(750 mV/DIV)

0.8

0.6

0.4

V_OUT(200 mV/DIV)

I_L(1 A/DIV)

R,JA = 10 °C/W

R,JA = 20 °C/W

R,JA = 30 °C/W

0.2

0

Time (200 µs/DIV)

50

60

70

80

90

100

110

120

Temperature (°C)

C001

V_OUT= 3.3 V

F_S= 500 kHz

V_IN= 24 V

V_OUT= 3.3 V

F_S= 500 kHz

V_IN= 24 V

Figure 51. Load Transient Between 0.1 A and 1 A

Figure 52. Derating Curve

33

LM46001-Q1

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

www.ti.com.cn

See Table 2 for bill of materials for each V_OUTand F_Scombination. Unless otherwise stated, application performance curves

were taken at T_A= 25°C.

100

90

V_OUT= 5 V F_S= 500 kHz

80

70

L=27 µH

V_OUT

60

50

40

30

20

10

0

SW

LM46001-Q1

RT

C_OUT

66 µF

C_BOOT

0.47 µF

CBOOT

BIAS

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

VIN = 36V

VIN = 42V

C_BIAS

1 µF

R_FBT

1 MΩ

C_FF

VCC

C_VCC

2.2 µF

33 pF

FB

R_FBB

249

kΩ

0.001

0.010

0.100

1.000

Load Current (A)

C003

V_OUT= 5 V

F_S= 500 kHz

V_IN= 24 V

V_OUT= 5 V

F_S= 500 kHz

Figure 53. BOM for V_OUT= 5 V, F_S= 500 kHz

Figure 54. Efficiency

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

5.2

5.0

4.8

4.6

4.4

4.2

4.0

Load = 0.25A

Load = 0.5A

Load = 0.75A

Load = 1A

VIN = 12V

VIN = 24V

VIN = 36V

VIN = 18V

VIN = 28V

VIN = 42V

0.001

0.010

0.100

1.000

5.0

5.5

6.0

6.5

Load Current (A)

VIN (V)

C013

C023

V_OUT= 5 V

F_S= 500 kHz

V_OUT= 5 V

F_S= 500 kHz

Figure 55. Output Voltage Regulation

Figure 56. Dropout Curve

1.2

V_{DROP_ON_0.75Ω_LOAD}

1

0.8

0.6

0.4

0.2

0

(750 mV/DIV)

V_OUT(200 mV/DIV)

I_L(1 A/DIV)

R,JA = 10 °C/W

R,JA = 20 °C/W

R,JA = 30 °C/W

Time (200 µs/DIV)

50

60

70

80

90

100

110

120

Temperature (°C)

C001

V_OUT= 5 V

F_S= 500 kHz

V_IN= 24 V

V_OUT= 5 V

F_S= 500 kHz

V_IN= 24 V

Figure 57. Load Transient Between 0.1 A and 1 A

Figure 58. Derating Curve

34

LM46001-Q1

www.ti.com.cn

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

See Table 2 for bill of materials for each V_OUTand F_Scombination. Unless otherwise stated, application performance curves

were taken at T_A= 25°C.

100

90

V_OUT= 5 V F_S= 200 kHz

80

70

L=56 µH

V_OUT

60

SW

LM46001-Q1

RT

C_OUT

R_T

200

kΩ

C_BOOT

50

40

30

20

10

0

CBOOT

BIAS

0.47 µF

150 µF

C_BIAS

1 µF

R_FBT

1 MΩ

C_FF

VCC

C_VCC

68 pF

VIN = 8V

VIN = 24V

VIN = 42V

VIN = 12V

VIN = 28V

VIN = 48V

VIN = 18V

VIN = 36V

VIN = 60V

FB

2.2 µF

R_FBB

249

kΩ

0.001

0.010

0.100

1.000

Load Current (A)

C004

V_OUT= 5 V

F_S= 200 kHz

V_IN= 24 V

V_OUT= 5 V

F_S= 200 kHz

Figure 59. BOM for V_OUT= 5 V, F_S= 200 kHz

Figure 60. Efficiency

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

5.2

5.0

4.8

4.6

4.4

4.2

4.0

Load = 0.25A

Load = 0.5A

Load = 0.75A

Load = 1A

VIN = 8V

VIN = 24V

VIN = 42V

VIN = 12V

VIN = 28V

VIN = 48V

VIN = 18V

VIN = 36V

VIN = 60V

0.001

0.010

0.100

1.000

5.0

5.5

6.0

6.5

Load Current (A)

VIN (V)

C014

C024

V_OUT= 5 V

F_S= 200 kHz

V_OUT= 5 V

F_S= 200 kHz

Figure 61. Output Voltage Regulation

Figure 62. Dropout Curve

1.2

V_{DROP_ON_0.75Ω_LOAD}

1

0.8

0.6

0.4

0.2

0

(750 mV/DIV)

V_OUT(200 mV/DIV)

I_L(1 A/DIV)

R,JA = 10 °C/W

R,JA = 20 °C/W

R,JA = 30 °C/W

Time (200 µs/DIV)

50

60

70

80

90

100

110

120

Temperature (°C)

C001

V_OUT= 5 V

F_S= 200 kHz

V_IN= 24 V

V_OUT= 5 V

F_S= 200 kHz

V_IN= 24 V

Figure 63. Load Transient Between 0.1 A and 1 A

Figure 64. Derating Curve

35

LM46001-Q1

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

www.ti.com.cn

See Table 2 for bill of materials for each V_OUTand F_Scombination. Unless otherwise stated, application performance curves

were taken at T_A= 25°C.

100

90

V_OUT= 5 V F_S= 1 MHz

80

70

L=15 µH

V_OUT

60

LM46001-Q1 SW

RT

C_OUT

R_T

39.2

kΩ

C_BOOT

50

40

30

20

10

0

CBOOT

BIAS

0.47 µF

33 µF

C_BIAS

1 µF

R_FBT

1 MΩ

VIN = 12V

VIN = 18V

VIN = 24V

VIN = 28V

C_FF

VCC

C_VCC

2.2 µF

22 pF

FB

R_FBB

249

kΩ

0.001

0.010

0.100

1.000

Load Current (A)

C005

V_OUT= 5 V

F_S= 1 MHz

V_IN= 24 V

V_OUT= 5 V

F_S= 1 MHz

V_IN= 24 V

Figure 65. BOM for V_OUT= 5 V, F_S= 1 MHz

Figure 66. Efficiency

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

5.2

5.0

4.8

4.6

4.4

4.2

4.0

Load = 0.25A

VIN = 12V

Load = 0.5A

Load = 0.75A

Load = 1A

VIN = 18V

VIN = 24V

VIN = 28V

0.001

0.010

0.100

1.000

5.0

5.5

6.0

6.5

Load Current (A)

VIN (V)

C015

C025

V_OUT= 5 V

F_S= 1 MHz

V_OUT= 5 V

F_S= 1 MHz

Figure 67. Output Voltage Regulation

Figure 68. Dropout Curve

1.2

V_{DROP_ON_0.75Ω_LOAD}

1

0.8

0.6

0.4

0.2

0

(750 mV/DIV)

V_OUT(200 mV/DIV)

I_L(1 A/DIV)

R,JA = 10 °C/W

R,JA = 20 °C/W

R,JA = 30 °C/W

Time (200 µs/DIV)

50

60

70

80

90

100

110

120

Temperature (°C)

C001

V_OUT= 5 V

F_S= 1 MHz

V_IN= 24 V

V_OUT= 5 V

F_S= 1 MHz

V_IN= 24 V

Figure 69. Load Transient Between 0.1 A and 1 A

Figure 70. Derating Curve

36

LM46001-Q1

www.ti.com.cn

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

See Table 2 for bill of materials for each V_OUTand F_Scombination. Unless otherwise stated, application performance curves

were taken at T_A= 25°C.

100

90

V_OUT= 12 V F_S= 500 kHz

80

70

L=47 µH

V_OUT

SW

60

50

40

30

20

10

0

LM46001-Q1

RT

C_OUT

C_BOOT

CBOOT

BIAS

0.47 µF

22 µF

VIN = 24V

VIN = 28V

VIN = 36V

VIN = 42V

VIN = 48V

VIN = 60V

C_BIAS

1 µF

R_FBT

1 MΩ

C_FF

VCC

C_VCC

47 pF

FB

2.2 µF

R_FBB

90.9

kΩ

0.001

0.010

0.100

1.000

Load Current (A)

C007

V_OUT= 12 V

F_S= 500 kHz

V_IN= 24 V

V_OUT= 12 V

F_S= 500 kHz

Figure 71. BOM for V_OUT= 12 V, F_S= 500 kHz

Figure 72. Efficiency

12.5

12.4

12.3

12.2

12.1

12.0

11.9

11.8

11.7

11.6

11.5

12.4

12.2

12.0

11.8

11.6

11.4

11.2

11.0

Load = 0.25A

Load = 0.5A

Load = 0.75A

Load = 1A

VIN = 24V

VIN = 36V

VIN = 48V

VIN = 28V

VIN = 42V

VIN = 60V

0.001

0.010

0.100

1.000

12.0

12.5

13.0

VIN (V)

13.5

14.0

Load Current (A)

C017

C027

V_OUT= 12 V

F_S= 500 kHz

V_OUT= 12 V

F_S= 500 kHz

Figure 73. Output Voltage Regulation

Figure 74. Dropout Curve

1.2

1

0.8

0.6

0.4

0.2

0

I_LOAD(1 A/DIV)

V_OUT(500 mV/DIV)

I_L(1 A/DIV)

R,JA = 10 °C/W

R,JA = 20 °C/W

R,JA = 30 °C/W

Time (200 µs/DIV)

50

60

70

80

90

100

110

120

Temperature (°C)

C001

V_OUT= 12 V

F_S= 500 kHz

V_IN= 24 V

V_OUT= 12 V

F_S= 500 kHz

V_IN= 24 V

Figure 75. Load Transient Between 0.1 A and 1 A

Figure 76. Derating Curve

37

LM46001-Q1

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

www.ti.com.cn

See Table 2 for bill of materials for each V_OUTand F_Scombination. Unless otherwise stated, application performance curves

were taken at T_A= 25°C.

120

V_OUT= 24 V F_S= 500 kHz

100

80

60

40

20

0

L=82 µH

V_OUT

SW

RT LM46001-Q1

C_OUT

15 µF

C_BOOT

0.47 µF

CBOOT

BIAS

VIN = 36V

VIN = 42V

VIN = 48V

VIN = 60V

C_BIAS

1 µF

R_FBT

1 MΩ

C_FF

VCC

C_VCC

2.2 µF

82 pF

FB

R_FBB

43.2

kΩ

0.001

0.010

0.100

1.000

Load Current (A)

C008

V_OUT= 24 V

F_S= 500 kHz

V_IN= 48 V

V_OUT= 24 V

F_S= 500 kHz

Figure 77. BOM for V_OUT= 24 V, F_S= 500 kHz

Figure 78. Efficiency

25.0

24.8

24.6

24.4

24.2

24.0

23.8

23.6

23.4

23.2

23.0

24.5

24.0

23.5

23.0

22.5

22.0

Load = 0.25A

Load = 0.5A

Load = 0.75A

Load = 1A

VIN = 36V

VIN = 42V

VIN = 48V

VIN = 60V

0.001

0.010

0.100

1.000

24.0

24.5

25.0

25.5

26.0

26.5

27.0

Load Current (A)

VIN (V)

C018

C028

V_OUT= 24 V

F_S= 500 kHz

V_OUT= 24 V

F_S= 500 kHz

Figure 79. Output Voltage Regulation

Figure 80. Dropout Curve

1.2

1

0.8

0.6

0.4

0.2

0

I_LOAD(1 A/DIV)

V_OUT(500 mV/DIV)

I_L(1 A/DIV)

R,JA = 10 °C/W

R,JA = 20 °C/W

Time (200 µs/DIV)

50

60

70

80

90

100

110

120

Temperature (°C)

C001

V_OUT= 24 V

F_S= 500 kHz

V_IN= 48 V

V_OUT= 24 V

F_S= 500 kHz

V_IN= 48 V

Figure 81. Load Transient Between 0.1 A and 1 A

Figure 82. Derating Curve

38

LM46001-Q1

www.ti.com.cn

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

See Table 2 for bill of materials for each V_OUTand F_Scombination. Unless otherwise stated, application performance curves

were taken at T_A= 25°C.

1.2

1

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

Vin = 12V

Vin = 24V

Vin = 36V

Vin = 12V

Vin = 24V

Vin = 36V

50

60

70

80

90

100

110

120

50

60

70

80

90

100

110

120

Temperature (°C)

C001

V_OUT= 3.3 V

F_S= 500 kHz

R_θJA= 20°C/W

V_OUT= 5 V

F_S= 500 kHz

R_θJA= 20°C/W

Figure 83. Derating Curve With R_θJA= 20°C/W

Figure 84. Derating Curve With R_θJA= 20°C/W

1.2

1

1.2

1

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

Vin = 12V

Vin = 24V

Vin = 36V

Vin = 12V

Vin = 24V

Vin = 36V

50

60

70

80

90

100

110

120

50

60

70

80

90

100

110

120

Temperature (°C)

C001

V_OUT= 5 V

F_S= 200 kHz

R_θJA= 20°C/W

V_OUT= 5 V

F_S= 1 MHz

R_θJA= 20°C/W

Figure 85. Derating Curve With R_θJA= 20°C/W

Figure 86. Derating Curve With R_θJA= 20 °C/W

1000000

100000

10000

1000000

100000

10000

VIN = 5 V

VIN = 8 V

VIN = 12 V

VIN = 18 V

VIN = 24 V

VIN = 8 V

VIN = 12 V

VIN = 18 V

VIN = 24 V

VIN = 36 V

0.001

0.01

0.1

1

0.001

0.01

0.1

1

Load (A)

C001

V_OUT= 3.3 V

F_S= 500 kHz

V_OUT= 5 V

F_S= 1 MHz

Figure 87. Switching Frequency vs I_OUTin PFM Operation

Figure 88. Switching Frequency vs I_OUTin PFM Operation

39

LM46001-Q1

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

www.ti.com.cn

See Table 2 for bill of materials for each V_OUTand F_Scombination. Unless otherwise stated, application performance curves

were taken at T_A= 25°C.

SW (10 V/DIV)

V_OUT(10 mV/DIV)

I_L(1 A/DIV)

Time (2 µs/DIV)

V_OUT= 3.3 V

F_S= 500 kHz

I_OUT= 1 A

V_OUT= 3.3 V

F_S= 500 kHz

I_OUT= 90 mA

Figure 89. Switching Waveform in CCM Operation

Figure 90. Switching Waveform in DCM Operation

SW (10 V/DIV)

P_GOOD(2 V/DIV)

V_OUT(2 V/DIV)

V_OUT(10 mV/DIV)

I_L(1 A/DIV)

Time (2 µs/DIV)

Time (2 ms/DIV)

V_OUT= 3.3 V

F_S= 500 kHz

I_OUT= 10 mA

V_IN= 24 V

V_OUT= 3.3 V

R_LOAD= 3.3 Ω

Figure 91. Switching Waveform in PFM Operation

Figure 92. Start-up Into Full Load With Internal Soft-Start

Rate

P_GOOD(2 V/DIV)

V_OUT(2 V/DIV)

P_GOOD(2 V/DIV)

V_OUT(2 V/DIV)

I_L(500 mA/DIV)

I_L(200 mA/DIV)

Time (2 ms/DIV)

V_IN= 24 V

V_OUT= 3.3 V

R_LOAD= 6.6 Ω

V_IN= 24 V

V_OUT= 3.3 V

R_LOAD= 33 Ω

Figure 93. Start-up Into Half Load With Internal Soft-Start

Rate

Figure 94. Start-up Into 100 mA With Internal Soft-Start

Rate

40

LM46001-Q1

www.ti.com.cn

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

See Table 2 for bill of materials for each V_OUTand F_Scombination. Unless otherwise stated, application performance curves

were taken at T_A= 25°C.

P_GOOD(2 V/DIV)

P_GOOD(10 V/DIV)

V_OUT(1 V/DIV)

V_OUT(10 V/DIV)

I_L(200 mA/DIV)

I_L(1 A/DIV)

Time (2 ms/DIV)

Time (5 ms/DIV)

V_IN= 24 V

V_OUT= 3.3 V

R_LOAD= Open

V_IN= 24 V

V_OUT= 12 V

R_LOAD= 6 Ω

Figure 95. Start-up Into 1-V Pre-biased Voltage

Figure 96. Start-up With External Capacitor C_SS= 33 nF

V_IN(20 V/DIV)

V_OUT(50 mV/DIV)

I_L(500 mA/DIV)

I_L(1 A/DIV)

Time (2 ms/DIV)

V_OUT= 3.3 V

F_S= 500 kHz

I_OUT= 1 A

V_OUT= 3.3 V

F_S= 500 kHz

I_OUT= 0.5 A

Figure 97. Line Transient: V_INTransitions Between 12 V

and 48 V

Figure 98. Line Transient: V_INTransitions Between 12 V

and 48 V

P_GOOD(5 V/DIV)

V_OUT(5 V/DIV)

I_L(1 A/DIV)

Time (10 ms/DIV)

V_OUT= 3.3 V

F_S= 500 kHz

V_IN= 24 V

Figure 99. Short-Circuit Protection and Recover

41

LM46001-Q1

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

www.ti.com.cn

9 Power Supply Recommendations

The LM46001-Q1 is designed to operate from an input voltage supply range between 3.5 V and 60 V. This input

supply must be able to withstand the maximum input current and maintain a voltage above 3.5 V. The resistance

of the input supply rail must be low enough that an input current transient does not cause a high enough drop at

the LM46001-Q1 supply voltage that can cause a false UVLO fault triggering and system reset.

If the input supply is located more than a few inches from the LM46001-Q1 additional bulk capacitance may be

required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-µF

or 100-µF electrolytic capacitor is a typical choice.

10 Layout

The performance of any switching converter depends as much upon the layout of the PCB as the component

selection. The following guidelines will help users design a PCB with the best power conversion performance,

thermal performance, and minimized generation of unwanted EMI.

10.1 Layout Guidelines

1. Place ceramic high frequency bypass C_INas close as possible to the LM46001-Q1 VIN and PGND pins.

Grounding for both the input and output capacitors should consist of localized top side planes that connect to

the PGND pins and PAD.

2. Place bypass capacitors for VCC and BIAS close to the pins and ground the bypass capacitors to device

ground.

3. Minimize trace length to the FB pin. Both feedback resistors, R_FBTand R_FBBmust be located close to the FB

pin. Place C_FFdirectly in parallel with R_FBT. If V_OUTaccuracy at the load is important, make sure V_OUTsense

is made at the load. Route V_OUTsense path away from noisy nodes and preferably through a layer on the

other side of a shielding layer.

4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.

5. Have a single point ground connection to the plane. The ground connections for the feedback, soft-start, and

enable components should be routed to the ground plane. This prevents any switched or load currents from

flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load

regulation or erratic output voltage ripple behavior.

6. Make V_IN, V_OUTand ground bus connections as wide as possible. This reduces any voltage drops on the

input or output paths of the converter and maximizes efficiency.

7. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the

ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be

connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking

to keep the junction temperature below 125°C.

10.1.1 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger

area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to

minimize radiated EMI is to identify the pulsing current path and minimize the area of the path. In Buck

converters, the pulsing current path is from the V_INside of the input capacitors to HS switch, to the LS switch,

and then return to the ground of the input capacitors, as shown in Figure 100.

BUCK

CONVERTER

L

VIN

SW

V_OUT

C_OUT

V_IN

C_IN

PGND

High di/dt

current

Figure 100. Buck Converter High di / dt Path

42

LM46001-Q1

www.ti.com.cn

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

Layout Guidelines (continued)

High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of

the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the

key to EMI reduction.

The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load

current without excessive heating. Short, thick traces or copper pours (shapes) should be used for high current

conduction path to minimize parasitic resistance. The output capacitors should be place close to the V_OUTend of

the inductor and closely grounded to PGND pin and exposed PAD.

The bypass capacitors on VCC and BIAS pins should be placed as close as possible to the pins respectively and

closely grounded to PGND and the exposed PAD.

10.1.2 Ground Plane and Thermal Considerations

TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for

sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the

AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pins are

connected to the source of the internal LS switch. They must be connected directly to the grounds of the input

and output capacitors. The PGND net contains noise at the switching frequency and may bounce due to load

variations. The PGND trace, as well as PVIN and SW traces, should be constrained to one side of the ground

plane. The other side of the ground plane contains much less noise and should be used for sensitive routes.

It is recommended to provide adequate device heat sinking by utilizing the PAD of the IC as the primary thermal

path. Use a minimum 4 by 4 array of 10 mil thermal vias to connect the PAD to the system ground plane for heat

sinking. The vias should be evenly distributed under the PAD. Use as much copper as possible for system

ground plane on the top and bottom layers for the best heat dissipation. It is recommended to use a four-layer

board with the copper thickness, for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four layer

boards with enough copper thickness and proper layout provides low current conduction impedance, proper

shielding and lower thermal resistance.

The thermal characteristics of the LM46001-Q1 are specified using the parameter R_θJA, which characterize the

junction temperature of the silicon to the ambient temperature in a specific system. Although the value of R_θJAis

dependant on many variables, it still can be used to approximate the operating junction temperature of the

device. To obtain an estimate of the device junction temperature, one may use Equation 27:

T_J= P_D× R_θJA+ T_A

where

•

T_J= junction temperature in °C

P_D= V_IN× I_IN× (1 − Efficiency) − 1.1 x I_OUTx DCR

DCR = inductor DC parasitic resistance in Ω

R_θJA= junction-to-ambient thermal resistance of the device in °C/W

T_A= ambient temperature in °C

(27)

The maximum operating junction temperature of the LM46001-Q1 is 125°C. R_θJAis highly related to PCB size

and layout, as well as environmental factors such as heat sinking and air flow. Figure 101 shows measured

results of R_θJAwith different copper area on a 2-layer board and a 4-layer board.

43

LM46001-Q1

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

www.ti.com.cn

Layout Guidelines (continued)

50.0

45.0

40.0

35.0

30.0

25.0

20.0

1W @ 0fpm - 2 layer

2W @ 0fpm - 2 layer

1W @ 0fpm - 4 layer

2W @ 0fpm - 4 layer

20mm x 20mm 30mm x 30mm 40mm x 40mm 50mm x 50mm

Copper Area

C030

Figure 101. Measured R_θJAvs PCB Copper Area on a 2-layer Board and a 4-layer Board

10.1.3 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and

C_FFclose to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high

impedance node and very sensitive to noise. Placing the resistor divider and C_FFcloser to the FB pin reduces the

trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace

from V_OUTto the resistor divider can be long if short path is not available.

If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for

voltage drops along the traces and provide the best output accuracy. Route the voltage sense trace from the

load to the feedback resistor divider away from the SW node path, the inductor, and V_INpath to avoid

contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most

important when high-value resistors are used to set the output voltage. TI recommends routing the voltage sense

trace on a different layer than the inductor, SW node and V_INpath, such that there is a ground plane in between

the feedback trace and inductor / SW node / V_INpolygon. This provides further shielding for the voltage feedback

path from switching noises.

44

LM46001-Q1

www.ti.com.cn

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

10.2 Layout Example

V_OUTdistribution point

is away from inductor

and past C_OUT

V_OUTsense point is away

from inductor and past C_OUT

GND

V_OUT

GND

C_OUT

As much copper area as possible,

for better thermal performance

L

Place ceramic bypass caps

close to VIN and PGND pins

1

16

SW

PGND

Place C_BOOT

close to pins

C_IN

PAD (17)

SW

15

GND

V_IN

2

3

4

5

6

C_BOOT

+

Route V_OUT

sense trace

away from

SW and VIN

nodes.

VIN

EN

14

13

CBOOT

VCC

C_VCC

Place bypass

caps close to

pins

BIAS

12

11

10

C_BIAS

Place R_FBB

close to FB

and AGND

Preferably

shielded in an

alternative

layer

SS/TRK

AGND

FB

SYNC

RT

Ground

bypass caps

to DAP

7

8

R_FBB

Trace to

FB short

and thin

PGOOD

9

R_FBT

C_FF

V_OUT

sense

GND

As much copper area as possible, for better thermal performance

Preferably use GND Plane as a middle layer for shielding and heat dissipation

Preferably place and route on top layer and use solid copper on bottom layer for heat dissipation

Figure 102. LM46001-Q1 PCB Layout Example

45

LM46001-Q1

ZHCSE20B –JULY 2015–REVISED NOVEMBER 2017

www.ti.com.cn

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 使用 WEBENCH® 工具创建定制设计

请单击此处，使用 LM46001-Q1 器件并借助 WEBENCH® 电源设计器创建定制设计。

1. 首先键入输入电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化关键参数设计，如效率、封装和成本。

3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。

WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案导出至常用 CAD 格式

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的提醒我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.4 商标

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修

订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

46

PACKAGE MATERIALS INFORMATION

www.ti.com

31-Aug-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM46001AQPWPRQ1 HTSSOP PWP

LM46001QPWPRQ1 HTSSOP PWP

16

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

31-Aug-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM46001AQPWPRQ1

LM46001QPWPRQ1

HTSSOP

PWP

16

2000

350.0

43.0

Pack Materials-Page 2

PACKAGE OUTLINE

PWP0016G

PowerPAD ^TMTSSOP - 1.2 mm max height

S

C

A

L

E

2

.

4

0

PLASTIC SMALL OUTLINE

C

6.6

6.2

TYP

SEATING PLANE

PIN 1 ID

AREA

A

0.1 C

14X 0.65

16

1

2X

5.1

4.9

4.55

NOTE 3

8

9

0.30

0.19

4.5

4.3

NOTE 4

16X

B

1.2 MAX

0.1

C A

B

0.18

0.12

TYP

SEE DETAIL A

2X 0.24 MAX

NOTE 6

2X 0.56 MAX

NOTE 6

THERMAL

PAD

0.25

GAGE PLANE

3.29

2.71

0.15

0.05

0 - 8

0.75

0.50

DETAIL A

TYPICAL

(1)

2.41

1.77

4218975/B 01/2016

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

6. Features may not present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0016G

PowerPAD ^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.4)

NOTE 10

(2.41)

SOLDER MASK

OPENING

SOLDER MASK

DEFINED PAD

SEE DETAILS

16X (1.5)

SYMM

1

16

16X (0.45)

(0.95)

TYP

(5)

SYMM

(3.29)

SOLDER MASK

OPENING

14X (0.65)

9

8

(0.95) TYP

METAL COVERED

BY SOLDER MASK

(

0.2) TYP

VIA

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-16

4218975/B 01/2016

NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

9. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

10. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0016G

PowerPAD ^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(2.41)

BASED ON

0.127 THICK

STENCIL

16X (1.5)

1

16

16X (0.45)

(3.29)

SYMM

BASED ON

0.127 THICK

STENCIL

14X (0.65)

(R0.05)

9

8

SYMM

(5.8)

SEE TABLE FOR

METAL COVERED

BY SOLDER MASK

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.69 X 3.68

2.41 X 3.29 (SHOWN)

2.20 X 3.00

0.127

0.152

0.178

2.04 X 2.78

4218975/B 01/2016

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知

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TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款

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型号：	LM46001-Q1
厂家：	TEXAS INSTRUMENTS
描述：	通过汽车级认证的 3.5 至 60V、1A 同步降压电压转换器转换器
文件：	总54页 (文件大小：2484K)
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下载：	下载PDF数据表文档文件

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