LM46002PWPT [TI]
SIMPLE SWITCHER 3.5 V to 60 V 2 A Synchronous Step-Down Voltage Converter;
| 型号： | LM46002PWPT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SIMPLE SWITCHER 3.5 V to 60 V 2 A Synchronous Step-Down Voltage Converter 开关 光电二极管 |
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LM46002
SNVSA13B –APRIL 2014–REVISED SEPTEMBER 2014
LM46002 SIMPLE SWITCHER® 3.5 V to 60 V 2 A Synchronous Step-Down Voltage
Converter
1 Features
3 Description
The LM46002 SIMPLE SWITCHER® regulator is an
easy to use synchronous step-down DC-DC
converter capable of driving up to 2 A of load current
from an input voltage ranging from 3.5 V to 60 V. The
LM46002 provides exceptional efficiency, output
accuracy and drop-out voltage in a very small
solution size. An extended family is available in
various load current options and 36 V maximum input
voltage in pin-to-pin compatible packages, including
LM46001, LM46000, LM43603, LM43602, LM43601
and LM43600. Peak current mode control is
1
•
27 µA Quiescent Current in Regulation
High Efficiency at Light Load (DCM and PFM)
Meets EN55022/CISPR 22 EMI standards
Integrated Synchronous Rectification
•
•
•
•
Adjustable Frequency Range: 200 kHz to 2.2 MHz
(500 kHz default)
•
•
•
Frequency Synchronization to External Clock
Internal Compensation
Stable with Almost Any Combination of Ceramic,
Polymer, Tantalum, and Aluminum Capacitors
employed
to
achieve
simple
control
loop
compensation and cycle-by-cycle current limiting.
Optional features such as programmable switching
•
•
•
•
•
•
•
•
Power-Good Flag
frequency,
synchronization,
power-good
flag,
Soft-Start into Pre-Biased Load
precision enable, internal soft-start, extendable soft-
start, and tracking provide a flexible and easy to use
Internal Soft-Start: 4.1 ms
Extendable Soft-Start Time by External Capacitor
Output Voltage Tracking Capability
Precision Enable to Program System UVLO
Output Short Circuit Protection with Hiccup Mode
Over Temperature Thermal Shutdown Protection
platform for
a
wide range of applications.
Discontinuous conduction and automatic frequency
reduction at light loads improve light load efficiency.
The family requires few external components. Pin
arrangement allows simple, optimum PCB layout.
Protection features include thermal shutdown, VCC
under-voltage lockout, cycle-by-cycle current limit,
and output short circuit protection. The LM46002
device is available in the HTSSOP / PWP 16 leaded
package (5.1 mm x 6.6 mm x 1.2 mm) with 0.65 mm
lead pitch.
2 Applications
•
•
•
•
•
•
Industrial Power Supplies
Telecommunications Systems
Sub-AM Band Automotive
Device Information
Commercial Vehicle Power Supplies
General Purpose Wide VIN Regulation
High Efficiency Point-Of-Load Regulation
ORDER NUMBER
PACKAGE
BODY SIZE
LM46002PWP
HTSSOP (16)
5.1 mm x 6.6 mm
4 Simplified Schematic
Radiated Emission Graph
VIN = 24 V, VOUT = 3.3 V, FS= 500 kHz, IOUT = 2 A
L
VOUT
VIN
80
VIN
SW
Evaluation Board
COUT
CIN
LM46002
CBOOT
70
60
50
40
30
20
10
0
EN 55022 Class B Limit
EN 55022 Class A Limit
CBOOT
BIAS
ENABLE
PGOOD
CBIAS
CFF
RFBT
SS/TRK
RT
FB
VCC
SYNC
AGND
RFBB
CVCC
PGND
0
200
400
600
800
1000
Frequency (MHz)
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM46002
SNVSA13B –APRIL 2014–REVISED SEPTEMBER 2014
www.ti.com
Table of Contents
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 23
Applications and Implementation ...................... 24
9.1 Application Information............................................ 24
9.2 Typical Applications ................................................ 24
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Simplified Schematic............................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Handling Ratings....................................................... 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 6
7.7 Switching Characteristics.......................................... 7
7.8 Typical Characteristics.............................................. 8
Detailed Description ............................................ 14
9
10 Power Supply Recommendations ..................... 41
11 Layout................................................................... 41
11.1 Layout Guidelines ................................................. 41
11.2 Layout Example .................................................... 44
12 Device and Documentation Support ................. 45
12.1 Trademarks........................................................... 45
12.2 Electrostatic Discharge Caution............................ 45
12.3 Glossary................................................................ 45
13 Mechanical, Packaging, and Orderable
8
Information ........................................................... 45
5 Revision History
Changes from Original (April 2014) to Revision A
Page
•
Changed device from Product Preview to Production Data .................................................................................................. 1
Changes from Revision A (April 2014) to Revision B
Page
•
•
•
•
•
•
•
•
Changed this graph .............................................................................................................................................................. 12
Added this equation.............................................................................................................................................................. 31
Added this equation.............................................................................................................................................................. 31
Changed this graph .............................................................................................................................................................. 32
Changed this graph .............................................................................................................................................................. 36
Changed this graph .............................................................................................................................................................. 36
Changed this graph .............................................................................................................................................................. 37
Changed this graph .............................................................................................................................................................. 44
2
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SNVSA13B –APRIL 2014–REVISED SEPTEMBER 2014
6 Pin Configuration and Functions
16-Pin HTSSOP (PWP)
Top View
SW
SW
1
16
15
14
13
12
11
10
9
PGND
PGND
VIN
2
3
4
5
6
7
8
CBOOT
VCC
VIN
PAD
EN
BIAS
SS/TRK
AGND
FB
SYNC
RT
PGOOD
Pin Functions
PIN
(1)
TYPE
DESCRIPTION
NUMB
ER
NAME
SW
Switching output of the regulator. Internally connected to both power MOSFETs. Connect to power
inductor.
1,2
3
P
P
P
Boot-strap capacitor connection for high-side driver. Connect a high quality 470 nF capacitor from CBOOT
to SW.
CBOOT
VCC
Internal bias supply output for bypassing. Connect bypass capacitor from this pin to AGND. Do not connect
external load to this pin. Never short this pin to ground during operation.
4
Optional internal LDO supply input. To improve efficiency, it is recommended to tie to VOUT when 3.3 V ≤
BIAS
5
P
VOUT ≤ 28 V, or tie to an external 3.3 V or 5 V rail if available. When used, place a bypass capacitor (1 to
10 µF) from this pin to ground. Tie to ground when not in use.
Clock input to synchronize switching action to an external clock. Use proper high speed termination to
prevent ringing. Connect to ground if not used.
SYNC
RT
6
7
8
A
A
A
Connect a resistor RT from this pin to AGND to program switching frequency. Leave floating for 500 kHz
default switching frequency.
Open drain output for power-good flag. Use a 10 kΩ to 100 kΩ pull-up resistor to logic rail or other DC
voltage no higher than 12 V.
PGOOD
Feedback sense input pin. Connect to the midpoint of feedback divider to set VOUT. Do not short this pin to
ground during operation.
FB
9
A
G
A
AGND
SS/TRK
10
11
Analog ground pin. Ground reference for internal references and logic. Connect to system ground.
Soft-start control pin. Leave floating for internal soft-start slew rate. Connect to a capacitor to extend soft
start time. Connect to external voltage ramp for tracking.
Enable input to the LM46002: High = ON and Low = OFF. Connect to VIN, or to VIN through resistor
divider, or to an external voltage or logic source. Do not float.
EN
VIN
12
13,14
15,16
-
A
P
G
-
Supply input pins to internal LDO and high side power FET. Connect to power supply and bypass
capacitors CIN. Path from VIN pin to high frequency bypass CIN and PGND must be as short as possible.
Power ground pins, connected internally to the low side power FET. Connect to system ground, PAD,
AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible.
PGND
PAD
Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path of the die.
Must be used for heat sinking to ground plane on PCB.
(1) P = Power, G = Ground, A = Analog
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7 Specifications
7.1 Absolute Maximum Ratings(1)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-3.5
-0.3
-0.3
MAX
65
UNIT
VIN to PGND
EN to PGND
VIN + 0.3
3.6
FB, RT, SS/TRK to AGND
Input Voltages
PGOOD to AGND
SYNC to AGND
15
V
5.5
BIAS to AGND
30
AGND to PGND
0.3
SW to PGND
VIN + 0.3
65
SW to PGND less than 10ns Transients
CBOOT to SW
Output Voltages
V
5.5
VCC to AGND
3.6
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
PARAMETER
DEFINITION
MIN
MAX
+150
2.0
UNIT
Tstg
Storage temperature range
HBM Human body model
CDM Charge device model
-65
°C
(1)(2)
VESD
kV
0.5
(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by assembly line electrostatic discharges into
the device.
(2) ESD testing is performed according to the respective JESD22 JEDEC standard.
7.3 Recommended Operating Conditions(1)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
3.5
-0.3
-0.3
-0.3
-0.3
3.3
-0.1
1.0
0
MAX
60
UNIT
VIN to PGND
EN
VIN
1.1
12
FB
Input Voltages
PGOOD
V
BIAS input not used
0.3
28
BIAS input used
AGND to PGND
0.1
28
Output Voltage
Output Current
Temperature
VOUT
V
A
IOUT
2
Operating junction temperature range, TJ
-40
+125
°C
(1) Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits.
For guaranteed specifications, see Electrical Characteristics.
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SNVSA13B –APRIL 2014–REVISED SEPTEMBER 2014
7.4 Thermal Information
HTSSOP
UNIT
(1)
THERMAL METRIC
(16 PINS)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
38.9(2)
RθJC(top)
RθJB
24.3
19.9
°C/W
0.7
ψJT
ψJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
19.7
1.7
RθJC(bot)
(1) The package thermal impedance is calculated in accordance with JESD 51-7 standard with a 4-layer board and 2 W power dissipation.
(2) θJA is highly related to PCB layout and heat sinking. Please refer to Figure 101 for measured RθJA vs PCB area from a 2-layer board
and a 4-layer board.
R
7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PINS)
ISHDNVIN-MIN-ST
Minimum input voltage for startup
Shutdown quiescent current
3.8
5
V
VEN = 0 V
2.3
7
µA
VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external
Operating quiescent current (non-
switching) from VIN
IQ-NONSW
12
µA
µA
VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external
Operating quiescent current (non-
switching) from external VBIAS
IBIAS-NONSW
87
27
135
VEN = VIN
IOUT = 0 A
IQ-SW
Operating quiescent current (switching) RT = open
VBIAS = VOUT = 3.3 V
µA
RFBT = 1.0 Meg
ENABLE (EN PIN)
Voltage level to enable the internal LDO
output VCC
VEN-VCC-H
VENABLE high level
VENABLE low level
VENABLE high level
1.2
V
V
V
Voltage level to disable the internal LDO
output VCC
VEN-VCC-L
0.4
Precision enable level for switching and
regulator output: VOUT
VEN-VOUT-H
2.00
2.1
2.42
Hysteresis voltage between VOUT
precision enable and disable thresholds
VEN-VOUT-HYS
ILKG-EN
VENABLE hysteresis
VEN = 3.3 V
-294
0.8
mV
µA
Enable input leakage current
1.7
INTERNAL LDO (VCC PIN AND BIAS PIN)
VCC
Internal LDO output voltage VCC
VIN ≥ 3.8 V
3.2
V
V
VCC rising threshold
3.15
Under voltage lock out (UVLO)
thresholds for VCC
VCC-UVLO
Hysteresis voltage between rising and
falling thresholds
-575
2.94
-67
mV
V
VBIAS rising threshold
3.15
Internal LDO input change over
threshold to BIAS
VBIAS-ON
Hysteresis voltage between rising and
falling thresholds
mV
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Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REFERENCE (FB PIN)
TJ = 25ºC
1.004 1.011 1.018
0.994 1.011 1.026
0.994 1.011 1.030
VFB
Feedback voltage
TJ = -40 ºC to 85ºC
TJ = -40 ºC to 125ºC
FB = 1.011 V
V
ILKG-FB
Input leakage current at FB pin
0.2
65
nA
THERMAL SHUTDOWN
Shutdown threshold
Recovery threshold
160
150
ºC
ºC
(1)
TSD
Thermal shutdown
CURRENT LIMIT AND HICCUP
IHS-LIMIT
ILS-LIMIT
SOFT START (SS/TRK PIN)
Peak inductor current limit
3.6
1.8
4.5
5.0
2.3
A
A
Valley inductor current limit
2.05
ISSC
Soft-start charge current
Soft-start discharge resistance
1.45
2.2
16
2.75
µA
RSSD
UVLO, TSD, OCP, or EN = 0 V
kΩ
POWER GOOD (PGOOD PIN)
Power-good flag over voltage tripping
threshold
VPGOOD-HIGH
% of FB voltage
% of FB voltage
110% 113%
Power-good flag under voltage tripping
threshold
VPGOOD-LOW
VPGOOD-HYS
80%
88%
6%
Power-good flag recovery hysteresis
% of FB voltage
VEN = 3.3 V
VEN = 0 V
40
60
125
150
PGOOD pin pull down resistance when
power bad
RPGOOD
Ω
(2)
MOSFETS
IOUT = 1 A
VBIAS = VOUT = 3.3 V
RDS-ON-HS
High-side MOSFET ON-resistance
Low-side MOSFET ON-resistance
210
110
mΩ
mΩ
IOUT = 1 A
VBIAS = VOUT = 3.3 V
RDS-ON-LS
(1) Ensured by design. Not production tested.
(2) Measured at package pins
7.6 Timing Requirements
MIN
TYP
MAX
UNIT
CURRENT LIMIT AND HICCUP
NOC
TOC
Hiccup wait cycles when LS current limit tripped
Hiccup retry delay time
32
Cycles
ms
5.5
SOFT START (SS/TRK PIN)
TSS
Internal soft-start time when SS pin open circuit
4.1
ms
POWER GOOD (PGOOD PIN)
TPGOOD-RISE Power-good flag rising transition deglitch delay
TPGOOD-FALL Power-good flag falling transition deglitch delay
220
220
µs
µs
6
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SNVSA13B –APRIL 2014–REVISED SEPTEMBER 2014
7.7 Switching Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SW (SW
PIN)
Minimum high side MOSFET ON
time
(1)
tON-MIN
125
200
165
250
ns
ns
Minimum high side MOSFET OFF
time
(1)
tOFF-MIN
OSCILLATOR (SW PINS AND SYNC PIN)
FOSC-
DEFAULT
Oscillator default frequency
RT pin open circuit
410
500
590
kHz
Minimum adjustable frequency
200
2200
10%
kHz
kHz
FADJ
Maximum adjustable frequency
Frequency adjust accuracy
With 1% resistors at RT pin
VSYNC-HIGH Sync clock high level threshold
VSYNC-LOW Sync clock low level threshold
DSYNC-MAX Sync clock maximum duty cycle
DSYNC-MIN Sync clock minimum duty cycle
2
V
V
0.4
90%
10%
Mininum sync clock ON and OFF
TSYNC-MIN
time
80
ns
(1) Ensured by design. Not production tested.
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7.8 Typical Characteristics
Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, L = 10 µH, COUT = 150 µF, CFF = 47 pF. Please refer to
Application Performance Curves for Bill of Materials (BOM) for other VOUT and FS combinations.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
0.001
0.01
0.1
1
0.001
0.01
0.1
1
Load Current (A)
Load Current (A)
C001
C002
VOUT = 3.3 V
FS = 500 kHz
VOUT = 5 V
FS = 200 kHz
Figure 1. Efficiency
Figure 2. Efficiency
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
0
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
Load Current (A)
Load Current (A)
C003
C004
VOUT = 5 V
FS = 500 kHz
VOUT = 5 V
FS = 1 MHz
Figure 3. Efficiency
Figure 4. Efficiency
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
0
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
Load Current (A)
Load Current (A)
C005
C006
VOUT = 12 V
FS = 500 kHz
VOUT = 24 V
FS = 500 kHz
Figure 5. Efficiency
Figure 6. Efficiency
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, L = 10 µH, COUT = 150 µF, CFF = 47 pF. Please refer to
Application Performance Curves for Bill of Materials (BOM) for other VOUT and FS combinations.
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
5.07
5.06
5.05
5.04
5.03
5.02
5.01
5.00
4.99
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
0.001
0.01
0.1
Current (A)
1
1
1
0.001
0.01
0.1
Current (A)
1
C001
C001
C001
C008
C001
C001
VOUT = 3.3 V
FS = 500 kHz
VOUT = 5 V
FS = 200 kHz
Figure 7. VOUT Regulation
Figure 8. VOUT Regulation
5.06
5.05
5.04
5.03
5.02
5.01
5.00
4.99
4.98
5.05
5.03
5.01
4.99
4.97
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
4.95
4.97
0.001
0.01
0.1
Current (A)
0.001
0.01
0.1
Current (A)
1
VOUT = 5 V
FS = 500 kHz
VOUT = 5 V
FS = 1 MHz
Figure 9. VOUT Regulation
Figure 10. VOUT Regulation
12.15
12.10
12.05
12.00
11.95
11.90
24.60
24.50
24.40
24.30
24.20
24.10
24.00
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
11.85
0.001
23.90
0.001
0.01
0.1
Current (A)
0.01
0.1
Current (A)
1
VOUT = 12 V
FS = 500 kHz
VOUT = 24 V
FS = 500 kHz
Figure 11. VOUT Regulation
Figure 12. VOUT Regulation
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, L = 10 µH, COUT = 150 µF, CFF = 47 pF. Please refer to
Application Performance Curves for Bill of Materials (BOM) for other VOUT and FS combinations.
3.5
3.3
3.1
2.9
2.7
2.5
2.3
5.2
5.0
4.8
4.6
4.4
4.2
4.0
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
3.5
4.0
4.5
5.0
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.4
VIN (V)
VIN (V)
C013
C002
VOUT = 3.3 V
FS = 500 kHz
VOUT = 5 V
FS = 200 kHz
Figure 14. Drop-Out Curve
Figure 13. Drop-Out Curve
5.2
5.0
4.8
4.6
4.4
4.2
5.2
5.0
4.8
4.6
4.4
4.2
IOUT = 0.1A
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
4.0
5.0
4.0
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.4
5.2
5.4
5.6
5.8
6.0
6.2
6.4
VIN (V)
VIN (V)
C003
C004
VOUT = 5 V
FS = 500 kHz
Figure 15. Drop-Out Curve
VOUT = 5 V
FS = 1 MHz
Figure 16. Drop-Out Curve
12.2
12.0
11.8
11.6
11.4
11.2
24.4
24.2
24.0
23.8
23.6
23.4
23.2
23.0
22.8
22.6
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
11.0
12.0
22.4
24.0
12.2
12.4
12.6
12.8
13.0
13.2
13.4
24.5
25.0
25.5
26.0
VIN (V)
VIN (V)
C005
C006
VOUT = 12 V
FS = 500 kHz
Figure 17. Drop-Out Curve
VOUT = 24 V
FS = 500 kHz
Figure 18. Drop-Out Curve
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, L = 10 µH, COUT = 150 µF, CFF = 47 pF. Please refer to
Application Performance Curves for Bill of Materials (BOM) for other VOUT and FS combinations.
1.E+06
1.0E+06
Load=0.1A
1.E+05
1.E+04
Load=0.01A
Load=0.1A
Load=0.5A
Load=1A
1.0E+05
1.0E+04
Load=0.5A
Load=1A
Load=1.5A
Load=2A
Load=1.5A
Load=2A
5.0
5.5
6.0
6.5
7.0
3.5
3.7
3.9
4.1
4.3
4.5
VIN (V)
VIN (V)
C005
C009
VOUT = 5 V
FS = 1 MHz
VOUT = 3.3 V
FS = 500 kHz
Figure 20. Switching Frequency vs VIN in Drop-Out
Operation
Figure 19. Switching Frequency vs VIN in Drop-Out
Operation
80
80
Evaluation Board
Evaluation Board
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
EN 55022 Class B Limit
EN 55022 Class A Limit
EN 55022 Class B Limit
EN 55022 Class A Limit
0
200
400
600
800
1000
0
200
400
600
800
1000
Frequency (MHz)
Frequency (MHz)
C001
C001
VOUT = 3.3 V
FS = 500 kHz
IOUT = 2 A
VOUT = 5 V
FS = 1 MHz
IOUT = 2 A
Measured on the LM46002PWPEVM with default BOM. No input
filter used.
Measured on the LM46002PWPEVM with L = 6.8 µH, COUT = 47
µF, CFF = 47 pF. No input filter used.
Figure 21. Radiated EMI Curve
Figure 22. Radiated EMI Curve
100
100
Peak Emissions
Peak Emissions
90
90
Quasi Peak Limit
Quasi Peak Limit
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
Average Limit
Average Limit
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
C001
C001
VOUT = 3.3 V
FS = 500 kHz
IOUT = 2 A
VOUT = 5 V
FS = 1 MHz
IOUT = 2 A
Measured on the LM46002PWPEVM with default BOM. Input filter:
Lin = 1 µH Cd = 47 µF CIN4 = 68 µF
Measured on the LM46002PWPEVM with L = 6.8 µH, COUT = 47
µF, CFF = 47 pF. Input filter Lin = 1 µH Cd = 47 µF CIN4 = 68 µF
Figure 23. Conducted EMI Curve
Figure 24. Conducted EMI Curve
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, L = 10 µH, COUT = 150 µF, CFF = 47 pF. Please refer to
Application Performance Curves for Bill of Materials (BOM) for other VOUT and FS combinations.
350
300
250
200
150
100
50
3
2.5
2
1.5
1
HS
LS
VIN = 24V
100 150
0
0.5
±50
0
50
100
150
±50
0
50
Temperature (deg C)
Temperature (deg C)
C001
C001
Figure 25. High-Side and Low-side On Resistance vs
Junction Temperature
Figure 26. Shutdown Current vs Junction Temperature
2.5
1.1
1
2
0.9
0.8
0.7
EN-VOUT Rising TH
1.5
EN-VOUT Falling TH
EN-VCC Rising TH
EN-VCC Falling TH
1
0.5
0
0.6
VEN = 3.3V
0.5
±50
0
50
100
150
±50
0
50
100
150
Temperature (deg C)
Temperature (deg C)
C001
C001
Figure 27. Enable Threshold vs Junction Temperature
Figure 28. Enable Leakage Current vs
Junction Temperature
120.00%
1.030
1.025
1.020
1.015
1.010
1.005
1.000
0.995
0.990
VIN=3.5
110.00%
100.00%
90.00%
80.00%
70.00%
60.00%
50.00%
VIN=5
VIN=8
VIN=12
VIN=24
OVP Trip Level
OVP Recover Level
UVP Recover Level
UVP Trip Level
±50
0
50
Temperature (deg C)
100
150
10
60
110
±40
Junction Temperature (C)
C001
C009
Figure 29. PGOOD Threshold vs Junction Temperature
Figure 30. Feedback Voltage vs Junction Temperature
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, L = 10 µH, COUT = 150 µF, CFF = 47 pF. Please refer to
Application Performance Curves for Bill of Materials (BOM) for other VOUT and FS combinations.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
70
60
50
40
30
20
10
0
IL Peak Limit
IL Valley Limit
50
0
10
20
30
40
60
0
10
20
30
40
50
60
VIN (V)
VIN (V)
C002
C009
VOUT = 3.3 V
FS = 500 kHz
VOUT = 3.3 V
FS = 500 kHz
IOUT = 0 A
EN pin is connected to external 5 V rail
Figure 31. Peak and Valley Current Limits vs VIN
Figure 32. Operation IQ vs VIN with BIAS Connected to VOUT
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8 Detailed Description
8.1 Overview
The LM46002 SIMPLE SWITCHER® regulator is an easy to use synchronous step-down DC-DC converter that
operates from 3.5 V to 60 V supply voltage. It is capable of delivering up to 2 A DC load current with exceptional
efficiency and thermal performance in a very small solution size. An extended family is available in 0.5 A and 1.0
A load options in pin-to-pin compatible packages.
The LM46002 employs fixed frequency peak current mode control with Discontinuous Conduction Mode (DCM)
and Pulse Frequency Modulation (PFM) mode at light load to achieve high efficiency across the load range. The
device is internally compensated, which reduces design time, and requires fewer external components. The
switching frequency is programmable from 200 kHz to 2.2 MHz by an external resistor, RT. It defaults at 500 kHz
without RT. The LM46002 is also capable of synchronization to an external clock within the 200 kHz to 2.2 MHz
frequency range. The wide switching frequency range allows the device to be optimized to fit small board space
at higher frequency, or high efficient power conversion at lower frequency.
Optional features are included for more comprehensive system requirements, including power-good (PGOOD)
flag, precision enable, synchronization to external clock, extendable soft-start time, and output voltage tracking.
These features provide a flexible and easy to use platform for a wide range of applications. Protection features
include over temperature shutdown, VCC under-voltage lockout (UVLO), cycle-by-cycle current limit, and short-
circuit protection with hiccup mode.
The family requires few external components and the pin arrangement was designed for simple, optimum PCB
layout. The LM46002 device is available in the HTSSOP / PWP 16 pin leaded package (5.1 mm x 6.6 mm x 1.2
mm) with 0.65 mm lead pitch.
8.2 Functional Block Diagram
ENABLE
VCC
BIAS
LDO
VCC
Enable
VIN
Internal
SS
ISSC
Precision
Enable
CBOOT
SS/TRK
HS I Sense
+
EA
+
REF
±
RC
CC
+ ±
TSD
UVLO
SW
PWM CONTROL LOGIC
PFM
PGood
Detector
PGOOD
OV/UV
Detector
Slope
Comp
FB
HICCUP
Cross Detector
Freq
Foldback
Zero
Oscillator
LS I Sense
AGND
FB
PGood
SYNC
RT
PGND
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8.3 Feature Description
8.3.1 Fixed Frequency Peak Current Mode Controlled Step-Down Regulator
The following operating description of the LM46002 will refer to the Functional Block Diagram and to the
waveforms in Figure 33. The LM46002 is a step-down Buck regulator with both high-side (HS) switch and low-
side (LS) switch (synchronous rectifier) integrated. The LM46002 supplies a regulated output voltage by turning
on the HS and LS NMOS switches with controlled ON time. During the HS switch ON time, the SW pin voltage
VSW swings up to approximately VIN, and the inductor current IL increases with a linear slope (VIN - VOUT) / L.
When the HS switch is turned off by the control logic, the LS switch is turned on after a anti-shoot-through dead
time. Inductor current discharges through the LS switch with a slope of -VOUT / L. The control parameter of Buck
converters are defined as Duty Cycle D = tON / TSW, where tON is the HS switch ON time and TSW is the switching
period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal
Buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to
the input voltage: D = VOUT / VIN.
V
SW
D = t
ON
/ T
SW
V
IN
t
t
OFF
ON
0
D1
t
-V
T
SW
iL
I
I
LPK
OUT
ûi
L
0
t
Figure 33. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The LM46002 synchronous Buck converter employs peak current mode control topology. A voltage feedback
loop is used to get accurate DC voltage regulation by adjusting the peak current command based on voltage
offset. The peak inductor current is sensed from the HS switch and compared to the peak current to control the
ON time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external
components, makes it easy to design, and provides stable operation with almost any combination of output
capacitors. The regulator operates with fixed switching frequency in Continuous Conduction Mode (CCM) and
Discontinuous Conduction Mode (DCM). At very light load, the LM46002 will operate in PFM to maintain high
efficiency and the switching frequency will decrease with reduced load current.
8.3.2 Light Load Operation
DCM operation is employed in the LM46002 when the inductor current valley reaches zero. The LM46002 will be
in DCM when load current is less than half of the peak-to-peak inductor current ripple in CCM. In DCM, the LS
switch is turned off when the inductor current reaches zero. Switching loss is reduced by turning off the LS FET
at zero current and the conduction loss is lowered by not allowing negative current conduction. Power conversion
efficiency is higher in DCM than CCM under the same conditions.
In DCM, the HS switch ON time will reduce with lower load current. When either the minimum HS switch ON time
(TON-MIN) or the minimum peak inductor current (IPEAK-MIN) is reached, the switching frequency will decrease to
maintain regulation. At this point, the LM46002 operates in PFM. In PFM, switching frequency is decreased by
the control loop when load current reduces to maintain output voltage regulation. Switching loss is further
reduced in PFM operation due to less frequent switching actions. Figure 34 shows an example of switching
frequency decreases with decreased load current.
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Feature Description (continued)
1.E+06
1.E+05
1.E+04
1.E+03
VIN = 12V
VIN = 24V
VIN = 36V
0.001
0.010
0.100
1.000
LOAD CURRENT (A)
C007
Figure 34. Switching Frequency Decreases with Lower Load Current in PFM Operation
VOUT = 5 V FS = 1 MHz
In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. The
lower the frequency in PFM, the more DC offset is needed at VOUT. Please refer to the Typical Characteristics for
typical DC offset at very light load. If the DC offset on VOUT is not acceptable for a given application, a static load
at output is recommended to reduce or eliminate the offset. Lowering values of the feedback divider RFBT and
RFBB can also serve as a static load. In conditions with low VIN and/or high frequency, the LM46002 may not
enter PFM mode if the output voltage cannot be charged up to provide the trigger to activate the PFM detector.
Once the LM46002 is operating in PFM mode at higher VIN, it will remain in PFM operation when VIN is reduced.
8.3.3 Adjustable Output Voltage
The voltage regulation loop in the LM46002 regulates output voltage by maintaining the voltage on FB pin ( VFB
)
to be the same as the internal REF voltage (VREF). A resistor divider pair is needed to program the ratio from
output voltage VOUT to VFB. The resistor divider is connected from the VOUT of the LM46002 to ground with the
mid-point connecting to the FB pin.
VOUT
RFBT
FB
RFBB
Figure 35. Output Voltage Setting
The voltage reference system produces a precise voltage reference over temperature. The internal REF voltage
is 1.011 V typically. To program the output voltage of the LM46002 to be a certain value VOUT, RFBB can be
calculated with a selected RFBT by
VFB
RFBB
RFBT
VOUT ꢀ VFB
(1)
The choice of the RFBT depends on the application. RFBT in the range from 10 kΩ to 100 kΩ is recommended for
most applications. A lower RFBT value can be used if static loading is desired to reduce VOUT offset in PFM
operation. Lower RFBT will reduce efficiency at very light load. Less static current goes through a larger RFBT and
might be more desirable when light load efficiency is critical. But RFBT larger than 1 MΩ is not recommended
because it makes the feedback path more susceptible to noise. Larger RFBT value requires more carefully
designed feedback path on the PCB. The tolerance and temperature variation of the resistor dividers affect the
output voltage regulation. It is recommended to use divider resistors with 1% tolerance or better and temperature
coefficient of 100 ppm or lower.
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Feature Description (continued)
If the resistor divider is not connected properly, output voltage cannot be regulated since the feedback loop is
broken. If the FB pin is shorted to ground, the output voltage will be driven close to VIN, since the regulator sees
very low voltage on the FB pin and tries to regulate it up. The load connected to the output could be damaged
under such a condition. Do not short FB pin to ground when the LM46002 is enabled. It is important to route the
feedback trace away from the noisy area of the PCB. For more layout recommendations, please refer to the
Layout section.
8.3.4 Enable (ENABLE)
Voltage on the ENABLE pin (VEN) controls the ON or OFF functionality of the LM46002. Applying a voltage less
than 0.4 V to the ENABLE input shuts down the operation of the LM46002. In shutdown mode the quiescent
current drops to typically 2.3 µA at VIN = 24 V.
The internal LDO output voltage VCC is turned on when VEN is higher than 1.2 V. The LM46002 switching action
and output regulation are enabled when VEN is greater than 2.1 V (typical). The LM46002 supplies regulated
output voltage when enabled and output current up to 2 A.
The ENABLE pin is an input and cannot be open circuit or floating. The simplest way to enable the operation of
the LM46002 is to connect the ENABLE pin to VIN pins directly. This allows self-start-up of the LM46002 when
VIN is within the operation range.
Many applications will benefit from the employment of an enable divider RENT and RENB in Figure 36 to establish
a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power
as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such
as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection.
VIN
RENT
ENABLE
RENB
Figure 36. System UVLO By Enable Dividers
8.3.5 VCC, UVLO and BIAS
The LM46002 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The nominal
voltage for VCC is 3.2 V. The VCC pin is the output of the LDO and must be properly bypassed. A high quality
ceramic capacitor with 2.2 µF to 10 µF capacitance and 6.3 V or higher rated voltage should be placed as close
as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin should not be
loaded, left floating, or shorted to ground during operation. Shorting VCC to ground during operation may cause
damage to the LM46002.
Under voltage lockout (UVLO) prevents the LM46002 from operating until the VCC voltage exceeds 3.15 V
(typical). The VCC UVLO threshold has 575 mV of hysteresis (typically) to prevent undesired shuting down due to
temperary VIN droops.
The internal LDO has two inputs: primary from VIN and secondary from BIAS input. The BIAS input powers the
LDO when VBIAS is higher than the change-over threshold. Power loss of an LDO is calculated by ILDO * (VIN-LDO
-
VOUT-LDO). The higher the difference between the input and output voltages of the LDO, the more power loss
occur to supply the same output current. The BIAS input is designed to reduce the difference of the input and
output voltages of the LDO to reduce power loss and improve LM46002 efficiency, especially at light load. It is
recommended to tie the BIAS pin to VOUT when VOUT ≥ 3.3V. The BIAS pin should be grounded in applications
with VOUT less than 3.3 V. BIAS input can also come from an external voltage source, if available, to reduce
power loss. When used, a 1µF to 10µF high quality ceramic capacitor is recommended to bypass the BIAS pin to
ground.
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Feature Description (continued)
8.3.6 Soft-Start and Voltage Tracking (SS/TRK)
The LM46002 has a flexible and easy to use start up rate control pin: SS/TRK. Soft-start feature is to prevent
inrush current impacting the LM46002 and its supply when power is first applied. Soft-start is achieved by slowly
ramping up the target regulation voltage when the device is first enabled or powered up.
The simplest way to use the device is to leave the SS/TRK pin open circuit or floating. The LM46002 will employ
the internal soft-start control ramp and start up to the regulated output voltage in 4.1 ms typically.
In applications with a large amount of output capacitors, or higher VOUT, or other special requirements, the soft-
start time can be extended by connecting an external capacitor CSS from SS/TRK pin to AGND. Extended soft-
start time further reduces the supply current needed to charge up output capacitors and supply any output
loading. An internal current source (ISSC = 2.2 µA) charges CSS and generates a ramp from 0 V to VFB to control
the ramp-up rate of the output voltage. For a desired soft start time tSS, the capacitance for CSS can be found by
CSS ISSC u tSS
(2)
The soft start capacitor CSS is discharged by an internal FET when VOUT is shutdown by hiccup protection or
ENABLE = logic low. When a large CSS is applied and ENABLE is toggled low only for a short period of time, it
could happen that CSS is not fully discharged and the next soft start ramp will follow internal soft start ramp
before reaching the left-over voltage on CSS and then follow the ramp programmed by CSS. If this is not
acceptable by a certain application, a R-C low-pass filter can be added to ENABLE to slow down the shutting
down of VCC, which allows more time to discharge CSS
.
The LM46002 is capable of start up into prebiased output conditions. When the inductor current reaches zero,
the LS switch will be turned off to avoid negative current conduction. This operation mode is also called diode
emulation mode. It is built-in by the DCM operation in light loads. With a prebiased output voltage, the LM46002
will wait until the soft-start ramp allows regulation above the prebiased voltage and then follow the soft-start ramp
to the regulation level.
When an external voltage ramp is applied to the SS/TRK pin, the LM46002 FB voltage follows the ramp if the
ramp magnitude is lower than the internal soft-start ramp. A resistor divider pair can be used on the external
control ramp to the SS/TRK pin to program the tracking rate of the output voltage. The final voltage seen by the
SS/TRK pin should not fall below 1.2 V to avoid abnormal operation.
EXT RAMP
RTRT
SS/TRK
RTRB
Figure 37. Soft Start Tracking External Ramp
VOUT tracked to an external voltage ramp has the option of ramping up slower or faster than the internal voltage
ramp. VFB always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin.
Figure 38 shows the case when VOUT ramps slower than the internal ramp, while Figure 39 shows when VOUT
ramps faster than the internal ramp. Faster start up time may result in inductor current tripping current protection
during start-up. Use with special care.
Enable
Internal SS Ramp
Ext Tracking Signal to SS pin
VOUT
Figure 38. Tracking with Longer Start-up Time Than The Internal Ramp
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Feature Description (continued)
Enable
Internal SS Ramp
Ext Tracking Signal to SS pin
VOUT
Figure 39. Tracking with Shorter Start-up Time Than The Internal Ramp
8.3.7 Switching Frequency (RT) and Synchronization (SYNC)
The switching frequency of the LM46002 can be programmed by the impedance RT from the RT pin to ground.
The frequency is inversely proportional to the RT resistance. The RT pin can be left floating and the LM46002 will
operate at 500 kHz default switching frequency. The RT pin is not designed to be shorted to ground.
For a desired frequency, typical RT resistance can be found by Equation 3.
RT(kΩ) = 40200 / Freq (kHz) - 0.6
(3)
Figure 40 shows RT resistance vs switching frequency FS curve.
250
200
150
100
50
0
0
500
1000
1500
2000
2500
Switching Frequency (kHz)
C008
Figure 40. RT Resistance vs Switching Frequency
Table 1 provides typical RT values for a given FS.
Table 1. Typical Frequency Setting RT Resistance
FS (kHz)
RT (kΩ)
200
200
350
115
500
80.6
53.6
39.2
26.1
19.6
17.8
750
1000
1500
2000
2200
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Feature Description (continued)
The LM46002 switching action can also be synchronized to an external clock from 200 kHz to 2.2 MHz. Connect
an external clock to the SYNC pin, with proper high speed termination, to avoid ringing. The SYNC pin should be
grounded if not used.
SYNC
EXT CLOCK
RTERM
Figure 41. Frequency Synchronization
The recommendations for the external clock include high level no lower than 2 V, low level no higher than 0.4 V,
duty cycle between 10% and 90% and both positive and negative pulse width no shorter than 80 ns. When the
external clock fails at logic high or low, the LM46002 will switch at the frequency programmed by the RT resistor
after a time-out period. It is recommended to connect a resistor RT to the RT pin such that the internal oscillator
frequency is the same as the target clock frequency when the LM46002 is synchronized to an external clock.
This allows the regulator to continue operating at approximately the same switching frequency if the external
clock fails.
The choice of switching frequency is usually a compromise between conversion efficiency and the size of the
circuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switch
transition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allows
use of smaller LC output filters and hence a more compact design. Lower inductance also helps transient
response (higher large signal slew rate of inductor current), and reduces the DCR loss. The optimal switching
frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis.
It is related to the input voltage, output voltage, most frequent load current level(s), external component choices,
and circuit size requirement. The choice of switching frequency may also be limited if an operating condition
triggers TON-MIN or TOFF-MIN
.
8.3.8 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Drop-Out Conditions
Minimum ON-time, TON-MIN, is the smallest duration of time that the HS switch can be on. TON-MIN is typically 125
ns in the LM46002. Minimum OFF-time, TOFF-MIN, is the smallest duration that the HS switch can be off. TOFF-MIN
is typically 200 ns in the LM46002.
In CCM operation, TON-MIN and TOFF-MIN limits the voltage conversion range given a selected switching frequency.
The minimum duty cycle allowed is
DMIN = TON-MIN × FS
(4)
And the maximum duty cycle allowed is
DMAX = 1 - TOFF-MIN × FS
(5)
Given fixed TON-MIN and TOFF-MIN, the higher the switching frequency the narrower the range of the allowed duty
cycle. In the LM46002, frequency foldback scheme is employed to extend the maximum duty cycle when TOFF-MIN
is reached. The switching frequency will decrease once longer duty cycle is needed under low VIN conditions.
The switching frequency can be decreased to approximately 1/10 of the programmed frequency by RT or the
synchronization clock. Such wide range of frequency foldback allows the LM46002 output voltage to stay in
regulation with a much lower supply voltage VIN. This leads to a lower effective drop-out voltage. Please refer to
Typical Characteristics for more details.
Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution
size and efficiency. The maximum operatable supply voltage can be found by
VIN-MAX = VOUT / (FS * TON-MIN
)
(6)
At lower supply voltage, the switching frequency will decrease once TOFF-MIN is tripped. The minimum VIN without
frequency foldback can be approximated by
VIN-MIN = VOUT / (1 - FS * TOFF-MIN
)
(7)
Taking considerations of power losses in the system with heavy load operation, VIN-MIN is higher than the result
calculated in Equation 7 . With frequency foldback, VIN-MIN is lowered by decreased FS. Figure 42 gives an
example of how FS decreases with decreasing supply voltage VIN at drop-out operation.
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Feature Description (continued)
1.0E+06
1.0E+05
1.0E+04
Load=0.1A
Load=0.5A
Load=1A
Load=1.5A
Load=2A
5.0
5.5
6.0
6.5
7.0
VIN (V)
C005
Figure 42. Switching Frequency Decreases in Drop-Out Operation
VOUT = 5 V FS = 1 MHz
8.3.9 Internal Compensation and CFF
The LM46002 is internally compensated with RC = 400 kΩ and CC = 50 pF as shown in Functional Block
Diagram. The internal compensation is designed such that the loop response is stable over the entire operating
frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can
be low with all ceramic capacitors. An external feed-forward cap CFF is recommended to be placed in parallel
with the top resistor divider RFBT for optimum transient performance.
VOUT
RFBT
CFF
FB
RFBB
Figure 43. Feed-Forward Capacitor for Loop Compensation
The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the cross over frequency of
the control loop to boost phase margin. The zero frequency can be found by
fZ-CFF = 1 / ( 2π × RFBT × CFF ).
(8)
An additional pole is also introduced with CFF at the frequency of
fP-CFF = 1 / ( 2π × CFF × ( RFBT // RFBB )).
(9)
The CFF should be selected such that the bandwidth of the control loop without the CFF is centered between fZ-CFF
and fP-CFF. The zero fZ-CFF adds phase boost at the crossover frequency and improves transient response. The
pole fP-CFF helps maintaining proper gain margin at frequency beyond the crossover.
Designs with different combinations of output capacitors need different CFF. Different types of capacitors have
different Equivalent Series Resistance (ESR). Ceramic capacitors have the smallest ESR and need the most
CFF. Electrolytic capacitors have much larger ESR and the ESR zero frequency
fZ-ESR = 1 / ( 2π × ESR × COUT
)
(10)
would be low enough to boost the phase up around the crossover frequency. Designs using mostly electrolytic
capacitors at the output may not need any CFF.
The CFF creates a time constant with RFBT that couples in the attenuated output voltage ripple to the FB node. If
the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. It could also couple
too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, CFF should be calculated
based on output capacitors used in the system. At cold temperatures, the value of CFF might change based on
the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB
node. To avoid this, more capacitance can be added to the output or the value of CFF can be reduced. Please
refer to the Detailed Design Procedure for the calculation of CFF.
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Feature Description (continued)
8.3.10 Bootstrap Voltage (BOOT)
The driver of the HS switch requires a bias voltage higher than VIN when the HS switch is ON. The capacitor
connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to (VSW
+
VCC). The boot diode is integrated on the LM46002 die to minimize the Bill-Of-Material (BOM). A synchronous
switch is also integrated in parallel with the boot diode to reduce voltage drop on CBOOT. A high quality ceramic
0.47 µF 6.3 V or higher capacitor is recommended for CBOOT
.
8.3.11 Power Good (PGOOD)
The LM46002 has a built in power-good flag shown on PGOOD pin to indicate whether the output voltage is
within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault
protection. The PGOOD pin is an open-drain output that requires a pull-up resistor to an appropriate DC voltage.
Voltage seen by the PGOOD pin should never exceed 12 V. A resistor divider pair can be used to divide the
voltage down from a higher potential. A typical range of pull-up resistor value is 10 kΩ to 100 kΩ.
When the FB voltage is within the power-good band, +4% above and -7% below the internal reference VREF
typically, the PGOOD switch will be turned off and the PGOOD voltage will be pulled up to the voltage level
defined by the pull up resistor or divider. When the FB voltage is outside of the tolerance band, +10 % above or -
13 % below VREF typically, the PGOOD switch will be turned on and the PGOOD pin voltage will be pulled low to
indicate power bad. Both rising and falling edges of the power-good flag have a built-in 220 µs (typical) deglitch
delay.
8.3.12 Over Current and Short Circuit Protection
The LM46002 is protected from over-current conditions by cycle-by-cycle current limiting on both peak and valley
of the inductor current. Hiccup mode will be activated if a fault condition persists to prevent over heating.
High-side MOSFET over-current protection is implemented by the nature of the Peak Current Mode control. The
HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is
compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. Please refer
to Functional Block Diagram for more details. The peak current of the HS switch is limited by the maximum EA
output voltage minus the slope compensation at every switching cycle. The slope compensation magnitude at the
peak current is proportional to the duty cycle.
When the LS switch is turned on, the current going through it is also sensed and monitored. The LS switch will
not be turned OFF at the end of a switching cycle if its current is above the LS current limit ILS-LIMIT. The LS
switch will be kept ON so that inductor current keeps ramping down, until the inductor current ramps below ILS-
LIMIT. Then the LS switch will be turned OFF and the HS switch will be turned on after a dead time. If the current
of the LS switch is higher than the LS current limit for 32 consecutive cycles and the power-good flag is low,
hiccup current protection mode will be activated. In hiccup mode, the regulator will be shutdown and kept off for
5.5 ms typically before the LM46002 tries to start again. If over-current or short-circuit fault condition still exist,
hiccup will repeat until the fault condition is removed. Hiccup mode reduces power dissipation under severe over-
current conditions, prevents over heating and potential damage to the device.
Hiccup is only activated when power-good flag is low. Under non-severe over-current conditions when VOUT has
not fallen outside of the PGOOD tolerance band, the LM46002 will reduce the switching frequency and keep the
inductor current valley clamped at the LS current limit level. This operation mode allows slight over current
operation during load transients without tripping hiccup. If the power-good flag becomes low, hiccup operation
will start after LS current limit is tripped 32 consecutive cycles.
8.3.13 Thermal Shutdown
Thermal shutdown is a built-in self protection to limit junction temperature and prevent damages due to over
heating. Thermal shutdown turns off the device when the junction temperature exceeds 160°C typically to
prevent further power dissipation and temperature rise. Junction temperature will reduce after thermal shutdown.
The LM46002 will attempt to restart when the junction temperature drops to 150°C.
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8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the LM46002. When VEN is below 0.4 V, the device is in
shutdown mode. Both the internal LDO and the switching regulator are off. In shutdown mode the quiescent
current drops to 2.3 µA typically with VIN = 24 V. The LM46002 also employs under voltage lock out protection. If
VCC voltage is below the UVLO level, the output of the regulator will be turned off.
8.4.2 Stand-by Mode
The internal LDO has a lower enable threshold than the regulator. When VEN is above 1.2 V and below the
precision enable falling threshold (1.8 V typically), the internal LDO regulates the VCC voltage at 3.2 V. The
precision enable circuitry is turned on once VCC is above the UVLO threshold. The switching action and voltage
regulation are not enabled unless VEN rises above the precision enable threshold (2.1 V typically).
8.4.3 Active Mode
The LM46002 is in Active Mode when VEN is above the precision enable threshold and VCC is above its UVLO
level. The simplest way to enable the LM46002 is to connect the EN pin to VIN. This allows self start-up of the
LM46002 when the input voltage is in the operation range: 3.5 V to 60 V. Please refer to Enable (ENABLE) and
VCC, UVLO and BIAS for details on setting these operating levels.
In Active Mode, depending on the load current, the LM46002 will be in one of four modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
peak-to-peak inductor current ripple;
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of
the peak-to-peak inductor current ripple in CCM operation;
3. Pulse Frequency Modulation (PFM) when switching frequency is decreased at very light load;
4. Fold-back mode when switching frequency is decreased to maintain output regulation at lower supply voltage
VIN.
8.4.4 CCM Mode
Continuous Conduction Mode (CCM) operation is employed in the LM46002 when the load current is higher than
half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed unless the
minimum HS switch ON-time (TON_MIN), the mininum HS switch OFF-time (TOFF_MIN) or LS current limit is
exceeded. Output voltage ripple will be at a minimum in this mode and the maximum output current of 2 A can
be supplied by the LM46002.
8.4.5 Light Load Operation
When the load current is lower than half of the peak-to-peak inductor current in CCM, the LM46002 will operate
in Discontinuous Conduction Mode (DCM), also known as Diode Emulation Mode (DEM). In DCM operation, the
LS FET is turned off when the inductor current drops to 0 A to improve efficiency. Both switching losses and
conduction losses are reduced in DCM, comparing to forced PWM operation at light load.
At even lighter current loads, Pulse Frequency Mode (PFM) is activated to maintain high efficiency operation.
When the HS switch ON-time reduces to TON_MIN or peak inductor current reduces to its minimum IPEAK-MIN, the
switching frequency will reduce to maintain proper regulation. Efficiency is greatly improved by reducing
switching and gate drive losses.
8.4.6 Self-Bias Mode
For highest efficiency of operation, it is recommended that the BIAS pin be connected directly to VOUT when 3.3
V ≤ VOUT ≤ 28 V. In this Self-Bias Mode of operation, the difference between the input and output voltages of the
internal LDO are reduced and therefore the total efficiency of the LM46002 is improved. These efficiency gains
are more evident during light load operation. During this mode of operation, the LM46002 operates with a
minimum quiescent current of 27 µA (typical). Please refer to VCC, UVLO and BIAS for more details.
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LM46002 is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum output current of 2 A. The following design procedure can be used to select
components for the LM46002. Alternately, the WEBENCH® software may be used to generate complete designs.
When generating a design, the WEBENCH® software utilizes iterative design procedure and accesses
comprehensive databases of components. Please go to www.ti.com for more details.
This section presents a simplified discussion of the design process.
9.2 Typical Applications
The LM46002 only requires a few external components to convert from a wide range of supply voltage to output
voltage. Figure 44 shows a basic schematic when BIAS is connected to VOUT . This is recommended for VOUT
3.3 V. For VOUT < 3.3 V, BIAS should be connected to ground, as shown in Figure 45.
≥
L
L
VOUT
VOUT
VIN
VIN
VIN
SW
VIN
SW
COUT
COUT
CIN
LM46002
CIN
LM46002
CBOOT
CBOOT
CBOOT
BIAS
CBOOT
BIAS
ENABLE
PGOOD
ENABLE
PGOOD
CBIAS
CFF
CFF
RFBT
RFBT
SS/TRK
RT
SS/TRK
RT
FB
FB
VCC
VCC
SYNC
AGND
SYNC
AGND
RFBB
RFBB
CVCC
CVCC
PGND
PGND
Figure 44. LM46002 Basic Schematic for
OUT ≥ 3.3 V, Tie BIAS to VOUT
Figure 45. LM46002 Basic Schematic for
VOUT < 3.3 V, t-Tie BIAS to Ground
V
The LM46002 also integrates a full list of optional features to aid system design requirements, such as precision
enable, VCC UVLO, programmable soft-start, output voltage tracking, programmable switching frequency, clock
synchronization and power-good indication. Each application can select the features for a more comprehensive
design. A schematic with all features utilized is shown in Figure 46.
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Typical Applications (continued)
L
VOUT
RFBT CFF
RFBB
VIN
SW
VIN
COUT
LM46002
RENT
CIN
CBOOT
CBOOT
FB
ENABLE
RENB
VCC
CVCC
SS/TRK
RT
CSS
BIAS
RT
CBIAS
PGOOD
PGND
SYNC
RPG
RSYNC
Tie BIAS to PGND
when VOUT < 3.3V
AGND
Figure 46. LM46002 Schematic with All Features
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Typical Applications (continued)
The external components have to fulfill the needs of the application, but also the stability criteria of the device's
control loop. The LM46002 is optimized to work within a range of external components. The LC output filter's
inductance and capacitance have to be considered in conjunction, creating a double pole, responsible for the
corner frequency of the converter (see Output Filter And Loop Stability section). Table 2 can be used to simplify
the output filter component selection.
Table 2. L, COUT and CFF Typical Values
(2)
(3)(4)
(3)(4)
FS (kHz)
VOUT = 1 V
L (µH)(1)
COUT (µF)
CFF (pF)
RT (kΩ)
RFBB (kΩ)
200
500
8.2
3.3
560
470
220
150
none
none
none
none
200
80.6 or open
39.2
100
100
100
100
1000
1.8
2200
0.68
17.8
VOUT = 3.3 V
200
27
10
250
150
100
47
56
47
33
22
200
80.6 or open
39.2
432
432
432
432
500
1000
4.7
2.2
2200
17.8
VOUT = 5 V
200
33
15
200
100
47
68
47
47
33
200
80.6 or open
39.2
249
249
249
249
500
1000
6.8
3.3
2200
33
17.8
VOUT = 12 V
200
(5)
56
22
10
68
47
33
see note
68
200
80.6 or open
39.2
90.9
90.9
90.9
500
1000
47
VOUT = 24 V
200
(5)
(5)
(5)
180
47
68
47
33
see note
see note
see note
200
80.6 or open
39.2
43.2
43.2
43.2
500
1000
22
(1) Inductor values are calculated based on typical VIN = 24 V.
(2) All the COUT values are after derating. Add more when using ceramics
(3) RFBT = 0 Ω for VOUT = 1 V. RFBT = 1 MΩ for all other VOUT settings.
(4) For designs with RFBT other than 1 MΩ, please adjust CFF such that (CFF × RFBT) is unchanged and adjust RFBB such that (RFBT / RFBB
)
is unchanged.
(5) High ESR COUT will give enough phase boost and CFF not needed.
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Typical Applications (continued)
9.2.1 Design Requirements
A detailed design procedure is described based on a design example. For this design example, use the
parameters listed in Table 3 as the input parameters.
Table 3. Design Example Parameters
DESIGN PARAMETER
Input Voltage VIN
VALUE
24 V typical, range from 3.8 V to 60 V
Output Voltage VOUT
Input Ripple Voltage
Output ripple voltage
Output Current Rating
Operating Frequency
Soft-start time
3.3 V
400 mV
30 mV
2 A
500 kHz
10 ms
9.2.2 Detailed Design Procedure
9.2.2.1 Output Voltage Set-Point
The output voltage of the LM46002 device is externally adjustable using a resistor divider network. The divider
network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. The following equation is
used to determine the output voltage of the converter:
VFB
RFBB
RFBT
VOUT ꢀ VFB
(11)
Choose the value of the RFBT to be 1 MΩ to minimize quiescent current to improve light load efficiency in this
application. With the desired output voltage set to be 3.3 V and the VFB = 1.011 V, the RFBB value can then be
calculated using Equation 11. The formula yields a value of 434.78 kΩ. Choose the closest available value of 432
kΩ for the RFBB. Please refer to Adjustable Output Voltage for more details.
9.2.2.2 Switching Frequency
The default switching frequency of the LM46002 device is set at 500 kHz when RT pin is open circuit. The
switching frequency is selected to be 500 kHz in this application for one less passive components. If other
frequency is desired, use Equation 12 to calculate the required value for RT.
RT(kΩ) = 40200 / Freq (kHz) - 0.6
(12)
For 500 kHz, the calculated RT is 79.8 kΩ and standard value 80.6 kΩ can also be used to set the switching
frequency at 500 kHz.
9.2.2.3 Input Capacitors
The LM46002 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor, depending
on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7 µF to 10
µF. A high-quality ceramic type X5R or X7R with sufficiency voltage rating is recommended. The voltage rating
must be greater than the maximum input voltage. To compensate the derating of ceramic capactors, a voltage
rating of twice the maximum input voltage is recommended. Additionally, some bulk capacitance can be required,
especially if the LM46002 circuit is not located within approximately 5 cm from the input voltage source. This
capacitor is used to provide damping to the voltage spiking due to the lead inductance of the cable or trace. The
value for this capacitor is not critical but must be rated to handle the maximum input voltage including ripple.
For this design, a 10 µF, X7R dielectric capacitor rated for 100 V is used for the input decoupling capacitor. The
equivalent series resistance (ESR) is approximately 3 mΩ, and the current-rating is 3 A. Include a capacitor with
a value of 0.1 µF for high-frequency filtering and place it as close as possible to the device pins.
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NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore the right capacitor
value has to be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.
9.2.2.4 Inductor Selection
The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is
based on the desired peak-to-peak ripple current, ΔiL, that flows in the inductor along with the DC load current.
As with switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductance
gives lower ripple current and hence lower output voltage ripple with the same output capacitors. Lower
inductance could result in smaller, less expensive component. An inductance that gives a ripple current of 20% to
40% of the 2 A at the typical supply voltage is a good starting point. ΔiL = (1/5 to 2/5) x IOUT. The peak-to-peak
inductor current ripple can be found by Equation 13 and the range of inductance can be found by Equation 14
with the typical input voltage used as VIN.
(VIN ꢀ VOUT )uD
'iL
L uFS
(13)
(VIN ꢀ VOUT )uD
0.4uFS uILꢀMAX
(VIN ꢀ VOUT )uD
0.2uFS uILꢀMAX
d L d
(14)
D is the duty cycle of the converter which in a buck converter it can be approximated as D = VOUT / VIN, assuming
no loss power conversion. By calculating in terms of amperes, volts, and megahertz, the inductance value will
come out in micro henries. The inductor ripple current ratio is defined by:
'iL
IOUT
r
(15)
The second criterion is the inductor saturation current rating. The inductor should be rated to handle the
maximum load current plus the ripple current:
IL-PEAK = ILOAD-MAX + Δ iL
(16)
The LM46002 has both valley current limit and peak current limit. During an instantaneous short, the peak
inductor current can be high due to a momentary increase in duty cycle. The inductor current rating should be
higher than the HS current limit. It is advised to select an inductor with a larger core saturation margin and
preferably a softer roll off of the inductance value over load current.
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low
of an inductance can generate too large of an inductor current ripple such that over current protection at the full
load could be falsely triggered. It also generates more conduction loss, since the RMS current is slightly higher
relative that with lower current ripple at the same DC current. Larger inductor current ripple also implies larger
output voltage ripple with the same output capacitors. With peak current mode control, it is not recommended to
have too small of an inductor current ripple. Enough inductor current ripple improves signal-to-noise ratio on the
current comparator and makes the control loop more immune to noise.
Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core
losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and
preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when
the peak design current is exceeded. The ‘hard’ saturation results in an abrupt increase in inductor ripple current
and consequent output voltage ripple. Do not allow the core to saturate!
For the design example, a standard 10 μH inductor from Wurth, Coiltronics, or Vishay can be used for the 3.3 V
output with plenty of current rating margin.
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9.2.2.5 Output Capacitor Selection
The device is designed to be used with a wide variety of LC filters. It is generally desired to use as little output
capacitance as possible to keep cost and size down. The output capacitor (s), COUT, should be chosen with
care since it directly affects the steady state output voltage ripple, loop stability and the voltage over/undershoot
during load current transients.
The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going
through the Equivalent Series Resistance (ESR) of the output capacitors:
ΔVOUT-ESR = ΔiL× ESR
(17)
The other is caused by the inductor current ripple charging and discharging the output capacitors:
ΔVOUT-C = ΔiL/ ( 8 × FS × COUT
)
(18)
The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of the two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation in the presence of large current steps and fast slew rates. When a fast large load transient happens,
output capacitors provide the required charge before the inductor current can slew to the appropriate level. The
initial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to droop until
the control loop response increases or decreases the inductor current to supply the load. To maintain a small
over- or under-shoot during a transient, small ESR and large capacitance are desired. But these also come with
higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output voltage
deviation.
For a given input and output requirement, the following inequality gives an approximation for an absolute
minimum output cap required:
2
ª
«
º
»
§
·
1
r
c
c
COUT
!
u
u(1ꢂ D ) ꢂ D u(1ꢂ r)
¨
¨
¸
ꢀ
ꢁ
¸
(FS ur u 'VOUT / IOUT
)
12
«
¬
»
¼
©
¹
(19)
(20)
Along with this for the same requirement, the max ESR should be calculated as per the following inequality
c
D
1
ESR ꢀ
u( ꢁ 0.5)
FS uCOUT
r
where
r = Ripple ratio of the inductor ripple current (ΔIL / IOUT
ΔVOUT = Target output voltage undershoot
D’ = 1 – Duty cycle
)
FS = Switching Frequency
IOUT = Load Current
A general guide line for COUT range is that COUT should be larger than the minimum required output capacitance
calculated by Equation 19, and smaller than 10 times the minimum required output capacitance or 1 mF. In
applications with VOUT less than 3.3 V, it is critical that low ESR output capacitors are selected. This will limit
potential output voltage overshoots as the input voltage falls below the device normal operating range. To
optimize the transient behavior a feed-forward capacitor could be added in parallel with the upper feedback
resistor. For this design example, three 47 µF,10 V, X7R ceramic capacitors are used in parallel.
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9.2.2.6 Feed-Forward Capacitor
The LM46002 is internally compensated and the internal R-C values are 400 kΩ and 50 pF respectively.
Depending on the VOUT and frequency FS, if the output capacitor COUT is dominated by low ESR (ceramic types)
capacitors, it could result in low phase margin. To improve the phase boost an external feedforward capacitor
CFF can be added in parallel with RFBT. CFF is chosen such that phase margin is boosted at the crossover
frequency without CFF. A simple estimation for the crossover frequency without CFF (fx) is shown in Equation 21,
assuming COUT has very small ESR.
4.35
fx
VOUT uCOUT
(21)
The following equation for CFF was tested:
1
1
CFF
u
2Sfx
RFBT u(RFBT / /RFBB
)
(22)
This equation indicates that the crossover frequency is geometrically centered on the zero and pole frequencies
caused by the CFF capacitor.
For designs with higher ESR, CFF is not neeed when COUT has very high ESR and CFF calculated from
Equation 22 should be reduced with medium ESR. Table 2 can be used as a quick starting point.
For the application in this design example, a 47 pF COG capacitor is selected.
9.2.2.7 Bootstrap Capacitors
Every LM46002 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is 0.47 μF
and rated at 6.3 V or higher. The bootstrap capacitor is located between the SW pin and the CBOOT pin. The
bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature
stability.
9.2.2.8 VCC Capacitor
The VCC pin is the output of an internal LDO for LM46002. The input for this LDO comes from either VIN or
BIAS (please refer to Functional Block Diagram for LM46002). To insure stability of the part, place a minimum of
2.2 µF, 10 V capacitor from this pin to ground.
9.2.2.9 BIAS Capacitors
For an output voltage of 3.3 V and greater, the BIAS pin can be connected to the output in order to increase light
load efficiency. This pin is an input for the VCC LDO. When BIAS is not connected, the input for the VCC LDO
will be internally connected into VIN. Since this is an LDO, the voltage differences between the input and output
will affect the efficiency of the LDO. If necessary, a capacitor with a value of 1 μF can be added close to the
BIAS pin as an input capacitor for the LDO.
9.2.2.10 Soft-Start Capacitors
The user can leave the SS/TRK pin floating and the LM46002 will implement a soft start time of 4.1 ms typically.
In order to use an external soft start capacitor, the capacitor should be sized such that the soft start time will be
longer than 4.1 ms. Use the following equation in order to calculate the soft start capacitor value:
CSS ISSC u tSS
(23)
Where,
CSS = Soft start capacitor value (µF)
ISSC = Soft start charging current (µA)
tSS = Desired soft start time (s)
For the desired soft start time of 10 ms and soft start charging current of 2.2 µA, the equation above yield a soft
start capacitor value of 0.022 µF.
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9.2.2.11 Under Voltage Lockout Set-Point
The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. RENT
is connected between the VIN pin and the EN pin of the LM46002. RENB is connected between the EN pin and
the GND pin. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. The following equation can be used to determine the VIN
UVLO level.
VIN-UVLO-RISING = VENH × (RENB + RENT) / RENB
(24)
The EN rising threshold (VENH) for LM46002 is set to be 2.1 V (typical). Choose the value of RENB to be 1 MΩ to
minimize input current from the supply. If the desired VIN UVLO level is at 5.0 V, then the value of RENT can be
calculated using the equation below:
RENT = (VIN-UVLO-RISING / VENH -1) × RENB
(25)
The above equation yields a value of 1.38 MΩ. The resulting falling UVLO threshold, equals 4.3 V, can be
calculated by below equation, where EN falling threshold (VENL) is 1.8 V (typical).
VIN-UVLO-FALLING = VENL × (RENB + RENT) / RENB
(26)
9.2.2.12 PGOOD
A typical pull-up resistor value is 10 kΩ to 100 kΩ from the PGOOD pin to a voltage no higher than 12 V. If it is
desired to pull up the PGOOD pin to a voltage higher than 12 V, a resistor can be added from the PGOOD pin to
ground to divide the voltage seen by the PGOOD pin to a value no higher than 12 V.
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9.2.3 Application Performance Curves
Please refer to Table 2 for Bill of materials for each VOUT and FS combination. Unless otherwise stated, application
performance curves were taken at TA = 25 °C.
100
90
VOUT = 3.3 V FS = 500 kHz
80
70
L=10 µH
LM46002
VOUT
SW
60
50
40
30
20
10
0
RT
COUT
CBOOT
CBOOT
0.47 µF
150 µF
BIAS
FB
CBIAS
1 µF
RFBT
1 M
CFF
VCC
VIN = 12V
CVCC
47 pF
2.2 µF
VIN = 18V
VIN = 24V
VIN = 28V
RFBB
432
k
0.001
0.01
0.1
Load Current (A)
FS = 500 kHz
1
C001
VOUT = 3.3 V
FS = 500 kHz
VIN = 24 V
VOUT = 3.3 V
Figure 47. BOM for VOUT = 3.3 V FS = 500 kHz
Figure 48. Efficiency
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.5
3.3
3.1
2.9
2.7
2.5
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
2.3
3.5
4.0
4.5
5.0
0.001
0.01
0.1
Current (A)
1
VIN (V)
C001
C013
VOUT = 3.3 V
FS = 500 kHz
VOUT = 3.3 V
FS = 500 kHz
Figure 49. Output Voltage Regulation
Figure 50. Drop-Out Curve
2.5
2.0
1.5
1.0
0.5
0.0
VOUT (200 mV/DIV)
VDROP-ON-0.75-LOAD (1 A/DIV)
R,JA=10C/W
R,JA=20C/W
R,JA=30C/W
IINDUCTOR (1 A/DIV)
Time (100 µs/DIV)
50
60
70
80
90
100
110
120
Ta (C)
C013
VOUT = 3.3 V
FS = 500 kHz
VIN = 24 V
VOUT = 3.3 V
FS = 500 kHz
VIN = 24 V
Figure 51. Load Transient Between 0.1 A and 2 A
Figure 52. Derating Curve
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Please refer to Table 2 for Bill of materials for each VOUT and FS combination. Unless otherwise stated, application
performance curves were taken at TA = 25 °C.
100
90
VOUT = 5 V FS = 500 kHz
80
70
L=15 µH
VOUT
LM46002
SW
60
50
40
30
20
10
0
RT
COUT
100 µF
CBOOT
0.47 µF
CBOOT
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
BIAS
FB
CBIAS
1 µF
RFBT
1 M
CFF
VCC
CVCC
2.2 µF
47 pF
RFBB
249
k
0.001
0.01
0.1
Load Current (A)
FS = 500 kHz
1
C003
VOUT = 5 V
FS = 500 kHz
VIN = 24 V
VOUT = 5 V
Figure 53. BOM for VOUT = 5 V FS = 500 kHz
Figure 54. Efficiency
5.2
5.05
5.03
5.01
4.99
4.97
4.95
5.0
4.8
4.6
4.4
4.2
4.0
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.4
0.001
0.01
0.1
Current (A)
1
VIN (V)
C001
C003
VOUT = 5 V
FS = 500 kHz
VOUT = 5 V
FS = 500 kHz
Figure 55. Output Voltage Regulation
Figure 56. Drop-Out Curve
2.5
VOUT (200 mV/DIV)
2.0
1.5
1.0
0.5
0.0
IINDUCTOR (2 A/DIV)
R,JA=10C/W
R,JA=20C/W
R,JA=30C/W
VDROP-ON-0.75ꢀ-LOAD (2 V/DIV)
Time (100 µs/DIV)
50
60
70
80
90
100
110
120
Ta (C)
C013
VOUT = 5 V
FS = 500 kHz
VIN = 24 V
VOUT = 5 V
FS = 500 kHz
VIN = 24 V
Figure 57. Load Transient Between 0.1 A and 2 A
Figure 58. Derating Curve
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Please refer to Table 2 for Bill of materials for each VOUT and FS combination. Unless otherwise stated, application
performance curves were taken at TA = 25 °C.
100
90
VOUT = 5 V FS = 200 kHz
80
70
LM46002
L=33 µH
VOUT
60
50
40
30
20
10
0
SW
RT
COUT
RT
200
k
CBOOT
0.47 µF
CBOOT
200 µF
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
BIAS
FB
CBIAS
1 µF
RFBT
1 M
CFF
VCC
CVCC
2.2 µF
68 pF
RFBB
249
k
0.001
0.01
0.1
Load Current (A)
FS = 200 kHz
1
C002
VOUT = 5 V
FS = 200 kHz
VIN = 24 V
VOUT = 5 V
Figure 59. BOM for VOUT = 5 V FS = 200 kHz
Figure 60. Efficiency
5.07
5.06
5.05
5.04
5.03
5.02
5.01
5.00
4.99
5.2
5.0
4.8
4.6
4.4
4.2
4.0
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.4
0.001
0.01
0.1
Current (A)
1
VIN (V)
C008
C002
VOUT = 5 V
FS = 200 kHz
VOUT = 5 V
FS = 200 kHz
Figure 61. Output Voltage Regulation
Figure 62. Drop-Out Curve
2.5
VOUT (200 mV/DIV)
2.0
1.5
1.0
0.5
0.0
IINDUCTOR (2 A/DIV)
R,JA=10C/W
R,JA=20C/W
R,JA=30C/W
VDROP-ON-0.75ꢀ-LOAD (2 V/DIV)
Time (100 µs/DIV)
50
60
70
80
90
100
110
120
Ta (C)
C013
VOUT = 5 V
FS = 200 kHz
VIN = 24 V
VOUT = 5 V
FS = 200 kHz
Figure 63. Load Transient Between 0.1 A and 2 A
Figure 64. Derating Curve
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Please refer to Table 2 for Bill of materials for each VOUT and FS combination. Unless otherwise stated, application
performance curves were taken at TA = 25 °C.
100
90
VOUT = 5 V FS = 1 MHz
80
70
LM46002
L=6.8 µH
VOUT
60
50
40
30
20
10
0
SW
RT
COUT
47 µF
RT
39.2
k
CBOOT
0.47 µF
CBOOT
BIAS
FB
CBIAS
1 µF
RFBT
1 M
CFF
VCC
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
CVCC
2.2 µF
47 pF
RFBB
249
k
0.001
0.01
0.1
Load Current (A)
FS = 1 MHz
1
C004
VOUT = 5 V
FS = 1 MHz
VIN = 24 V
VOUT = 5 V
VIN = 24 V
Figure 65. BOM for VOUT = 5 V FS = 1 MHz
Figure 66. Efficiency
5.06
5.05
5.04
5.03
5.02
5.01
5.00
4.99
4.98
4.97
5.2
5.0
4.8
4.6
4.4
4.2
4.0
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.4
0.001
0.01
0.1
Current (A)
1
VIN (V)
C001
C004
VOUT = 5 V
FS = 1 MHz
VOUT = 5 V
FS = 1 MHz
Figure 67. Output Voltage Regulation
Figure 68. Drop-Out Curve
2.5
2.0
1.5
1.0
0.5
0.0
VOUT (200 mV/DIV)
IINDUCTOR (2 A/DIV)
R,JA=10C/W
R,JA=20C/W
R,JA=30C/W
VDROP-ON-0.75ꢀ-LOAD (2 V/DIV)
Time (100 µs/DIV)
40
50
60
70
80
90
100 110 120
Ta (C)
C013
VOUT = 5 V
FS = 1 MHz
VIN = 24 V
VOUT = 5 V
FS = 1 MHz
VIN = 24 V
Figure 69. Load Transient Between 0.1 A and 2 A
Figure 70. Derating Curve
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Please refer to Table 2 for Bill of materials for each VOUT and FS combination. Unless otherwise stated, application
performance curves were taken at TA = 25 °C.
100
90
VOUT = 12 V FS = 500 kHz
80
70
60
50
40
30
20
10
0
L=22 µH
VOUT
LM46002
SW
RT
COUT
47 µF
CBOOT
0.47 µF
CBOOT
BIAS
FB
CBIAS
1 µF
RFBT
1 M
CFF
VIN = 24V
VCC
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
CVCC
2.2 µF
68 pF
RFBB
90.9
k
0.001
0.01
0.1
Load Current (A)
FS = 500 kHz
1
C005
VOUT = 12 V
FS = 500 kHz
VIN = 24 V
VOUT = 12 V
Figure 71. BOM for VOUT = 12 V FS = 500 kHz
Figure 72. Efficiency
12.15
12.10
12.05
12.00
11.95
11.90
11.85
12.2
12.0
11.8
11.6
11.4
11.2
11.0
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
12.0
12.2
12.4
12.6
12.8
13.0
13.2
13.4
0.001
0.01
0.1
Current (A)
1
VIN (V)
C001
C005
VOUT = 12 V
FS = 500 kHz
VOUT = 12 V
FS = 500 kHz
Figure 74. Drop-Out Curve
Figure 73. Output Voltage Regulation
2.50
VOUT (1 V/DIV)
2.00
1.50
1.00
0.50
0.00
IINDUCTOR (1 A/DIV)
,JA=10C/W
,JA=20C/W
,JA=30C/W
ILOAD (1 A/DIV)
40
50
60
70
80
90
100
110
120
130
Ta (deg C)
Time (200 µs/DIV)
C001
VOUT = 12 V
FS = 500 kHz
VIN = 24 V
VOUT = 12 V
FS = 500 kHz
VIN = 24 V
Figure 76. Derating Curve
Figure 75. Load Transient Between 0.1 A and 2 A
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Please refer to Table 2 for Bill of materials for each VOUT and FS combination. Unless otherwise stated, application
performance curves were taken at TA = 25 °C.
100
90
VOUT = 24 V FS = 500 kHz
80
70
60
50
40
30
20
10
0
L = 47 µH
VOUT
LM46002
SW
RT
COUT
47 µF
CBOOT
0.47 µF
CBOOT
BIAS
FB
CBIAS
1 µF
RFBT
1 M
VCC
CVCC
2.2 µF
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
RFBB
43.2
k
0.001
0.01
0.1
Load Current (A)
FS = 500 kHz
1
C006
VOUT = 24 V
FS = 500 kHz
VIN = 48 V
VOUT = 24 V
Figure 77. BOM for VOUT = 24 V FS = 500 kHz
Figure 78. Efficiency
24.60
24.50
24.40
24.30
24.20
24.10
24.00
23.90
24.4
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
24.2
24.0
23.8
23.6
23.4
23.2
23.0
22.8
22.6
22.4
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
24.0
24.5
25.0
VIN (V)
25.5
26.0
0.001
0.01
0.1
Current (A)
1
C001
C006
VOUT = 24 V
FS = 500 kHz
VOUT = 24 V
FS = 500 kHz
Figure 79. Output Voltage Regulation
Figure 80. Drop-Out Curve
2.50
2.00
1.50
1.00
0.50
0.00
VOUT (2 V/DIV)
IINDUCTOR (1 A/DIV)
R,JA=10C/W
R,JA=20C/W
60 70
ILOAD (1 A/DIV)
40
50
80
90
100
110
120
130
Ta (C)
C001
Time (200 µs/DIV)
VOUT = 24 V
FS = 500 kHz
Figure 82. Derating Curve
VIN = 48 V
VOUT = 24 V
FS = 500 kHz
VIN = 48 V
Figure 81. Load Transient Between 0.1 A and 2 A
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Please refer to Table 2 for Bill of materials for each VOUT and FS combination. Unless otherwise stated, application
performance curves were taken at TA = 25 °C.
2.5
2.0
1.5
1.0
0.5
0.0
2.5
2.0
1.5
1.0
0.5
0.0
VIN=12V
VIN=24V
VIN=36V
VIN=12V
VIN=24V
VIN=36V
50
60
70
80
90
100
110
120
50
60
70
80
90
100
110
120
Ta (C)
Ta (C)
C013
C013
VOUT = 3.3 V
FS = 500 kHz
RθJA = 20 °C/W
VOUT = 5 V
FS = 500 kHz
RθJA = 20 °C/W
Figure 83. Derating Curve with RθJA = 20 °C/W
Figure 84. Derating Curve with RθJA = 20 °C/W
2.5
2.0
1.5
1.0
0.5
0.0
2.5
2.0
1.5
1.0
0.5
0.0
VIN=12V
VIN=24V
VIN=36V
VIN=12V
VIN=24V
VIN=36V
50
60
70
80
90
100
110
120
40
50
60
70
80
90
100 110 120
Ta (C)
Ta (C)
C013
C013
VOUT = 5 V
FS = 200 kHz
RθJA = 20 °C/W
VOUT = 5 V
FS = 1 MHz
RθJA = 20 °C/W
Figure 85. Derating Curve with RθJA = 20 °C/W
Figure 86. Derating Curve with RθJA = 20 °C/W
1.E+06
1.E+05
1.E+04
1.E+03
1.E+06
1.E+05
1.E+04
1.E+03
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 8V
VIN = 12V
VIN = 24V
0.001
0.010
0.100
1.000
0.001
0.010
0.100
1.000
LOAD CURRENT (A)
LOAD CURRENT (A)
C006
C007
VOUT = 3.3 V
FS = 500 kHz
VOUT = 5 V
FS = 1 MHz
Figure 87. Switching Frequency vs IOUT in PFM Operation
Figure 88. Switching Frequency vs IOUT in PFM Operation
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Please refer to Table 2 for Bill of materials for each VOUT and FS combination. Unless otherwise stated, application
performance curves were taken at TA = 25 °C.
SW Node
(10 V/DIV)
SW Node
(10 V/DIV)
VOUT Ripple
(5 mV/DIV)
VOUT Ripple
(5 mV/DIV)
IINDUCTOR
IINDUCTOR
(2 A/DIV)
(2 A/DIV)
Time (2 µs/DIV)
Time (2 µs/DIV)
VOUT = 3.3 V
FS = 500 kHz
IOUT = 2 A
VOUT = 3.3 V
FS = 500 kHz
IOUT = 130 mA
Figure 89. Switching Waveform in CCM Operation
Figure 90. Switching Waveform in DCM Operation
VOUT (2 V/DIV)
SW Node
(10 V/DIV)
IINDUCTOR (1 A/DIV)
PGOOD (5 V/DIV)
VOUT Ripple
(5 mV/DIV)
IINDUCTOR
(0.5 A/DIV)
Time (1 ms/DIV)
Time (50 µs/DIV)
VOUT = 3.3 V
FS = 500 kHz
IOUT = 5 mA
VIN = 24 V
VOUT = 3.3 V
RLOAD = 1.65 Ω
Figure 91. Switching Waveform in PFM Operation
Figure 92. Startup Into Full Load with Internal Soft-Start
Rate
VOUT (2 V/DIV)
VOUT (2 V/DIV)
IINDUCTOR (500 mA/DIV)
PGOOD (5 V/DIV)
IINDUCTOR (1 A/DIV)
PGOOD (5 V/DIV)
Time (1 ms/DIV)
Time (1 ms/DIV)
VIN = 24 V
VOUT = 3.3 V
RLOAD = 3.3 Ω
VIN = 24 V
VOUT = 3.3 V
RLOAD = 33 Ω
Figure 93. Startup Into Half Load with Internal Soft-Start
Rate
Figure 94. Startup Into 100 mA with Internal Soft-Start Rate
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Please refer to Table 2 for Bill of materials for each VOUT and FS combination. Unless otherwise stated, application
performance curves were taken at TA = 25 °C.
VOUT (5 V/DIV)
VOUT (2 V/DIV)
IINDUCTOR (1 A/DIV)
IINDUCTOR (500 mA/DIV)
PGOOD (5 V/DIV)
PGOOD (5 V/DIV)
Time (1 ms/DIV)
Time (2 ms/DIV)
VIN = 24 V
VOUT = 3.3 V
RLOAD = Open
VIN = 24 V
VOUT = 12 V
RLOAD = 6 Ω
Figure 95. Startup Into 1.5 V Pre-biased Voltage
Figure 96. Startup with External Capacitor CSS
VOUT (200 mV/DIV)
VOUT (200 mV/DIV)
VIN (20 V/DIV)
VIN (20 V/DIV)
IINDUCTOR (1 A/DIV)
IINDUCTOR (1 A/DIV)
Time (500 µs/DIV)
Time (200 µs/DIV)
VOUT = 3.3 V
FS = 500 kHz
IOUT = 0.5 A
VOUT = 3.3 V
FS = 500 kHz
IOUT = 2 A
Figure 98. Line Transient: VIN Transitions Between 12 V
and 36 V, 1 V/µs Slew Rate
Figure 97. Line Transient: VIN Transitions Between 12 V
and 36 V, 1 V/µs Slew Rate
VOUT (2 V/DIV)
PGOOD (5 V/DIV)
IINDUCTOR (2 A/DIV)
Time (2 ms/DIV)
VOUT = 3.3 V
FS = 500 kHz
VIN = 24 V
Figure 99. Short Circuit Protection and Recover
40
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10 Power Supply Recommendations
The LM46002 is designed to operate from an input voltage supply range between 3.5 V and 60 V. This input
supply should be able to withstand the maximum input current and maintain a voltage above 3.5 V. The
resistance of the input supply rail should be low enough that an input current transient does not cause a high
enough drop at the LM46002 supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few inches from the LM46002 additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47 µF
or 100 µF electrolytic capacitor is a typical choice.
11 Layout
The performance of any switching converter depends as much upon the layout of the PCB as the component
selection. The following guidelines will help users design a PCB with the best power conversion performance,
thermal performance, and minimized generation of unwanted EMI.
11.1 Layout Guidelines
1. Place ceramic high frequency bypass CIN as close as possible to the LM46002 VIN and PGND pins.
Grounding for both the input and output capacitors should consist of localized top side planes that connect to
the PGND pins and PAD.
2. Place bypass capacitors for VCC and BIAS close to the pins and ground the bypass capacitors to device
ground.
3. Minimize trace length to the FB pin. Both feedback resistors, RFBT and RFBB should be located close to the
FB pin. Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT
sense is made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on
the other side of a shieldig layer.
4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.
5. Have a single point ground connection to the plane. The ground connections for the feedback, soft-start, and
enable components should be routed to the ground plane. This prevents any switched or load currents from
flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load
regulation or erratic output voltage ripple behavior.
6. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
7. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the
ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be
connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking
to keep the junction temperature below 125°C.
11.1.1 Compact Layout for EMI Reduction
Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to
minimize radiated EMI is to identify the pulsing current path and minimize the area of the path. In Buck
converters,the pulsing current path is from the VIN side of the input capacitors to HS switch, to the LS switch, and
then return to the ground of the input capacitors, as shown in Figure 100.
BUCK
CONVERTER
L
VIN
SW
VOUT
COUT
VIN
CIN
PGND
PGND
High di/dt
current
Figure 100. Buck Converter High di / dt Path
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Layout Guidelines (continued)
High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of
the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the
key to EMI reduction.
The SW pin connecting to the inductor should be as short as possible, and just wide enough to carry the load
current without excessive heating. Short, thick traces or copper pours (shapes) should be used for high current
condution path to minimize parasitic resistance. The output capacitors should be place close to the VOUT end of
the inductor and closely grounded to PGND pin and exposed PAD.
The bypass capacitors on VCC and BIAS pins should be placed as close as possible to the pins respectively and
closely grounded to PGND and the exposed PAD.
11.1.2 Ground Plane and Thermal Considerations
It is recommended to use one of the middle layers as a solid ground plane. Ground plane provides shielding for
sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. The AGND and
PGND pins should be connected to the ground plane using vias right next to the bypass capacitors. PGND pins
are connected to the source of the internal LS switch. They should be connected directly to the grounds of the
input and output capacitors. The PGND net contains noise at the switching frequency and may bounce due to
load variations. The PGND trace, as well as PVIN and SW traces, should be constrained to one side of the
ground plane. The other side of the ground plane contains much less noise and should be used for sensitive
routes.
It is recommended to provide adequate device heat sinking by utilizing the PAD of the IC as the primary thermal
path. Use a minimum 4 by 4 array of 10 mil thermal vias to connect the PAD to the system ground plane for heat
sinking. The vias should be evenly distributed under the PAD. Use as much copper as possible for system
ground plane on the top and bottom layers for the best heat dissipation. It is recommended to use a four-layer
board with the copper thickness, for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four layer
boards with enough copper thickness and proper layout provides low current conduction impedance, proper
shielding and lower thermal resistance.
The thermal characteristics of the LM46002 are specified using the parameter RθJA, which characterize the
junction temperature of the silicon to the ambient temperature in a specific system. Although the value of RθJA is
dependant on many variables, it still can be used to approximate the operating junction temperature of the
device. To obtain an estimate of the device junction temperature, one may use the following relationship:
TJ = PD× RθJA + TA
(27)
where
TJ = Junction temperature in °C
PD = VIN x IIN x (1 − Efficiency) − 1.1 x IOUT x DCR
DCR = Inductor DC parasitic resistance in Ω
RθJA = Junction-to-ambient thermal resistance of the device in °C/W
TA = Ambient temperature in °C.
The maximum operating junction temperature of the LM46002 is 125°C. RθJA is highly related to PCB size and
layout, as well as enviromental factors such as heat sinking and air flow. Figure 101 shows measured results of
RθJA with different copper area on a 2-layer board and a 4-layer board.
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Layout Guidelines (continued)
50.0
45.0
40.0
35.0
30.0
25.0
20.0
1W @ 0fpm - 2 layer
2W @ 0fpm - 2 layer
1W @ 0fpm - 4 layer
2W @ 0fpm - 4 layer
20mm x 20mm 30mm x 30mm 40mm x 40mm 50mm x 50mm
Copper Area
C007
Figure 101. Measured RθJA vs PCB Copper Area on a 2-layer Board and a 4-layer Board
11.1.3 Feedback Resistors
To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and
CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high
impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the
trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace
from VOUT to the resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so will correct
for voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to
the feedback resistor divider should be routed away from the SW node path, the inductor and VIN path to avoid
contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most
important when high value resistors are used to set the output voltage. It is recommended to route the voltage
sense trace on a different layer than the inductor, SW node and VIN path, such that there is a ground plane in
between the feedback trace and inductor / SW node / VIN polygon. This provides further shielding for the voltage
feedback path from switching noises.
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11.2 Layout Example
VOUT distribution point
is away from inductor
VOUT sense point is away
from inductor and past COUT
and past COUT
GND
VOUT
GND
COUT
As much copper area as possible,
for better thermal performance
L
Place ceramic bypass caps
close to VIN and PGND pins
1
16
SW
PGND
PGND
Place CBOOT
close to pins
CIN
PAD (17)
SW
15
GND
VIN
2
3
4
5
6
CBOOT
+
Route VOUT
VIN
VIN
EN
14
13
CBOOT
VCC
sense trace
away from
SW and VIN
nodes.
CVCC
Place bypass
caps close to
pins
BIAS
12
11
10
CBIAS
Place RFBB
close to FB
and AGND
Preferably
shielded in an
alternative
layer
SS/TRK
AGND
FB
SYNC
RT
Ground
bypass caps
to DAP
7
8
RFBB
Trace to
FB short
and thin
PGOOD
9
RFBT
CFF
VOUT
sense
GND
As much copper area as possible, for better thermal performance
Preferably use GND Plane as a middle layer for shielding and heat dissipation
Preferably place and route on top layer and use solid copper on bottom layer for heat dissipation
Figure 102. LM46002 PCB Layout Example and Guidelines
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12 Device and Documentation Support
12.1 Trademarks
SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2014
PACKAGING INFORMATION
Orderable Device
LM46002PWP
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
HTSSOP
HTSSOP
HTSSOP
PWP
16
16
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
LM46002
LM46002PWPR
LM46002PWPT
ACTIVE
ACTIVE
PWP
PWP
2000
250
Green (RoHS
& no Sb/Br)
-40 to 125
LM46002
LM46002
Green (RoHS
& no Sb/Br)
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM46002PWPR
LM46002PWPT
HTSSOP PWP
HTSSOP PWP
16
16
2000
250
330.0
180.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM46002PWPR
LM46002PWPT
HTSSOP
HTSSOP
PWP
PWP
16
16
2000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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