LM48100Q-Q1 [TI]
具有输出故障检测的 1.3W 单声道、模拟输入 AB 类音频放大器;
| 型号： | LM48100Q-Q1 |
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TEXAS INSTRUMENTS |
| 描述： | 具有输出故障检测的 1.3W 单声道、模拟输入 AB 类音频放大器 放大器 音频放大器 |
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LM48100Q
www.ti.com
SNAS470D –OCTOBER 2008–REVISED MARCH 2013
LM48100Q Boomer™ Mono, 1.3W Audio Power Amplifier with Output Fault Detection and
Volume Control
Check for Samples: LM48100Q
1
FEATURES
DESCRIPTION
The LM48100Q is a single supply, mono, bridge-tied
load amplifier with I2C volume control, ideal for
automotive applications. A comprehensive output
fault detection system senses the load conditions,
protecting the device during short circuit events, as
well as detecting open circuit conditions.
23
•
Output Fault Detection
•
•
•
•
•
•
•
•
I2C Volume and Mode Control
Input Mixer/Multiplexer
High PSRR
Individual 32-Step Volume Control
Short Circuit and Thermal Protection
Advanced Click-and-Pop Suppression
Low Power Shutdown Mode
Available in 14-pin HTSSOP Package
Operating from a single 5V supply, the LM48100Q
delivers 1.3W of continuous output power to an 8Ω
load with < 1% THD+N. Flexible power supply
requirements allow operation from 3.0V to 5.5V. High
power supply rejection ratio (PSRR), 74dB at 1kHz,
allows the device to operate in noisy environments
without additional power supply conditioning.
APPLICATIONS
The LM48100Q features dual audio inputs that can
be mixed/multiplexed to the device output. Each input
path has its own independent, 32-step volume
control. The mixer, volume control and device mode
select are controlled through an I2C compatible
interface. An open drain FAULT output indicates
when a fault has occurred. Comprehensive output
short circuit and thermal overload protection prevent
the device from being damaged during a fault
condition.
•
•
•
Automotive Instrument Clusters
Hands-free Car Kits
Medical
KEY SPECIFICATIONS
•
Output Power at VDD = 5V, RL = 8Ω, THD+N ≤
1% 1.3W (typ)
•
Quiescent Power Supply Current at 5V 6mA
(Typ)
A low power shutdown mode reduces supply current
consumption to 0.01µA. Superior click and pop
suppression eliminates audible transients on power-
up/down and during shutdown. The LM48100Q is
available in an 14-pin HTSSOP package
•
•
PSRR at 1kHz 74dB (Typ)
Shutdown current 0.01μA (Typ)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
Boomer is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
LM48100Q
SNAS470D –OCTOBER 2008–REVISED MARCH 2013
www.ti.com
Typical Application
3.0V to 5.5V
C
C
B
B
0.1 mF
1 mF
PV
V
DD
DD
C
IN1
0.1 mF
IN1
BIAS
IN2
VOLUME CONTROL
-80 dB TO +18 dB
OUTA
BIAS
MIXER/MULITPLEXER
+6 dB
C
BIAS
2.2 mF
C
IN2
OUTB
0.1 mF
VOLUME CONTROL
-80 dB TO +18 dB
+1.8V to +5.5V
V
DD
C
B
0.1 mF
R
PU
2
I CV
DD
1.5 kW
SDA
SCL
FAULT
DETECTION
2
I C CONTROL
FAULT
ADR
GND
PGND
Figure 1. Typical Audio Amplifier Application Circuit
Connection Diagram
FAULT
SCL
1
2
3
4
5
6
7
14
13
12
11
10
9
V
DD
BIAS
IN1
SDA
2
I CV
DD
IN2
GND
ADR
PV
DD
OUTB
PGND
OUTA
8
Figure 2. HTSSOP Package
Top View
See Package Number PWP0014A
2
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Product Folder Links: LM48100Q
LM48100Q
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SNAS470D –OCTOBER 2008–REVISED MARCH 2013
BUMP DESCRIPTIONS
Pin
Pin Name
Description
Open-Drain output fault flag. FAULT = 0 indicates that a fault
condition has occurred.
1
FAULT
2
3
4
5
SCL
SDA
I2CVDD
I2C Clock Input
I2C Serial Data Input
I2C Interface Power Supply
Ground
GND
I2C Address Bit. Connect to I2CVDD to set address bit, B1 = 1.
Connect to GND to set address bit B1 = 0
6
ADR
7
OUTA
PGND
OUTB
PVDD
Non-Inverting Audio Output
Power Ground
8
9
Inverting Audio Output
Output Amplifier Power Supply
Audio Input 2
10
11
12
13
14
—
IN2
IN1
Audio Input 1
BIAS
Bias Bypass
VDD
Power Supply
Exposed Pad
Exposed paddle. Connect to GND.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)
Supply Voltage, continuous(1)
Storage Temperature
Input Voltage
Power Dissipation(4)
ESD Rating(5)
6V
−65°C to +150°C
−0.3V to VDD + 0.3V
Internally Limited
2500V
ESD Rating(6)
300V
Junction Temperature
150°C
(7)
θJA
θJC
37.8°C/W
Thermal Resistance
5.2°C/W
Lead Temperature (Soldering 4 sec)
260°C
For detailed information on soldering plastic HTSSOP and LLP packages, refer to the Packaging Data Book available from Texas
Instruments.
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) θJA measured with a 4 layer JEDEC board.
(5) Human body model, applicable std. JESD22-A114C.
(6) Machine model, applicable std. JESD22-A115-A.
(7) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
Copyright © 2008–2013, Texas Instruments Incorporated
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Operating Ratings(1)(2)
Temperature Range
Supply Voltage
T
MIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ +105°C
3.0V ≤ VDD ≤ 5.5V
1.8V ≤ I2CVDD ≤ 5.5V
I2CVDD ≤ VDD
VDD and PVDD
I2C Supply Voltage
I2CVDD
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Audio Amplifier Electrical Characteristics VDD = 5.0V(1)(2)
The following specifications apply for Programmable Gain = 0dB, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply
for TA = 25°C.
LM48100Q
Typical Room
Extended
Units
(Limits)
(3)
Symbol
Parameter
Conditions
Temp Temp Limits
(4) (5)
Limits
(4)
VIN = 0V, Both channels active
RL = 8Ω
RL = ∞
Quiescent Power Supply
Current
IDD
4.4
4.2
9
6
10.8
7.9
mA (max)
mA (max)
Diagnostic Mode Quiescent
Power Supply Current
IDD
ISD
Diagnostic Mode Enabled, RL = ∞
Shutdown Enabled
12.5
0.01
8.8
14.5
1
mA (max)
µA (max)
mV (max)
ms (max)
Shutdown Current
Differential Output Offset
Voltage
VOS
TWU
VIN = 0V, RL = 8Ω
50
75
Wake-Up Time
Time from shutdown to audio available
Minimum Gain Setting
11.6
–54
50
dB (max)
dB (min)
±1.0
±2.0
AV
Gain
dB (max)
dB (min)
Maximum Gain Setting
18
±1.0
–77
±1.0
–74
Mute
RIN
Mute Attenuation
Input Resistance
–80
12.5
dB (max)
11.5
13.5
kΩ (min)
kΩ (max)
AV = 18dB
98
120
89
130
kΩ (min)
kΩ (max)
AV = –54dB
110
RL = 8Ω, f = 1kHz
THD+N = 10%
THD+N = 1%
PO
Output Power
1.6
1.3
W
W (min)
1.05
0.96
Total Harmonic Distortion +
Noise
THD+N
PO = 850mW, f = 1kHz, RL = 8Ω
0.04
%
VRIPPLE = 200mVP-P Sine, Inputs AC GND, CIN_= 1μF, input referred, CBIAS = 2.2μF
Power Supply Rejection
Ratio
PSRR
f = 217Hz
f = 1kHz
79
74
66
63
dB (min)
dB
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not specified.
(4) Datasheet min/max specification limits are specified by test or statistical analysis.
(5) Min/max specification limits specified for TA = –40°C to 105°C.
4
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SNAS470D –OCTOBER 2008–REVISED MARCH 2013
Audio Amplifier Electrical Characteristics VDD = 5.0V(1)(2) (continued)
The following specifications apply for Programmable Gain = 0dB, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply
for TA = 25°C.
LM48100Q
Typical Room
Extended
Units
(Limits)
(3)
Symbol
Parameter
Conditions
Temp Temp Limits
(4) (5)
Limits
(4)
SNR
Signal-to-Noise-Ratio
Output Noise
POUT = TBDmW, f = 1kHz
AV = 0dB, A-weighted Filter
FAULT = 0, VOUT(FAULT)= 0.4V
104
12
3
dB
μV
∈
OS
IOUT(FAULT)
FAULT Output Current
mA
Short between either OUTA to VDD or
GND, or OUTB to VDD or GND
Short Circuit
Output to Supply Short
Circuit Detection Threshold
RFAULT
3
7.5
3
7.5
kΩ (min)
kΩ (max)
Open Circuit
Short between both OUTA and OUTB to
VDD or GND
Short Circuit
Output to Supply Short
Circuit Detection Threshold
RFAULT
6
15
kΩ (min)
kΩ (max)
Open Circuit
Open Circuit Detection
Threshold
100
200
Ω (min)
Ω (max)
ROPEN
Open circuit between OUTA and OUTB
Short circuit between OUTA and OUTB
Output to Output Short
Circuit Detection Threshold
2
6
Ω (min)
Ω (max)
RSHT
ISHTCKT
TSD
Short Circuit Current Limit
1.47
170
58
1.67
2
A (max)
Thermal Shutdown
Threshold
°C
tDIAG
Diagnostic Time
ms
Audio Amplifier Electrical Characteristics VDD = 3.6V(1)(2)
The following specifications apply for Programmable Gain = 0dB, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply
for TA = 25°C.
LM48100Q
Typical
Room
Temp
Extended
Temp
Units
(Limits)
(3)
Symbol
Parameter
Conditions
Limits
Limits
(4)
(4) (5)
VIN = 0V, Both channels active
RL = 8Ω
RL = ∞
Quiescent Power Supply
Current
IDD
3.8
3.6
8.5
5
10.8
7
mA (max)
mA (max)
Diagnostic Mode Quiescent
Power Supply Current
IDD
ISD
Diagnostic Mode Enabled
Shutdown Enabled
11.7
0.01
8.8
14.5
1
mA (max)
µA (max)
mV (max)
ms (max)
Shutdown Current
Differential Output Offset
Voltage
VOS
TWU
VIN = 0V, RL = 8Ω
50
50
76
Wake-Up Time
Time from shutdown to audio available
11.5
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not specified.
(4) Datasheet min/max specification limits are specified by test or statistical analysis.
(5) Min/max specification limits specified for TA = –40°C to 105°C.
Copyright © 2008–2013, Texas Instruments Incorporated
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Audio Amplifier Electrical Characteristics VDD = 3.6V(1)(2) (continued)
The following specifications apply for Programmable Gain = 0dB, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply
for TA = 25°C.
LM48100Q
Typical
Room
Temp
Extended
Temp
Units
(Limits)
(3)
Symbol
Parameter
Conditions
Limits
Limits
(4)
(4) (5)
dB (max)
dB (min)
Minimum Gain Setting
–54
±1
AV
Gain
dB (max)
dB (min)
Maximum Gain Setting
18
±1
Mute
RIN
Mute Attenuation
Input Resistance
–79
12.5
–77
dB (max)
11.5
13.5
kΩ (min)
kΩ (max)
AV = 18dB
98
120
89
135
kΩ (min)
kΩ (max)
AV = –54dB
110
RL = 8Ω, f = 1kHz
THD+N = 10%
THD+N = 1%
PO
Output Power
820
660
mW
mW (min)
480
Total Harmonic Distortion +
Noise
THD+N
PO = 400mW, f = 1kHz, RL = 8Ω
0.04
% (max)
VRIPPLE = 200mVP-P Sine, Inputs AC GND, CIN_= 1μF, input referred, CBIAS = 2.2μF
Power Supply Rejection
Ratio
PSRR
SNR
f = 217Hz
f = 1kHz
78
75
66
60
dB (min)
dB
Signal-to-Noise-Ratio
Output Noise
POUT = TBDmW, f = 1kHz
AV = 0dB, A-weighted Filter
FAULT = 0, VOUT(FAULT) = 0.4V
106
12.5
3
dB
μV
∈
OS
IOUT(FAULT)
FAULT Output Current
mA
Short between either OUTA to VDD or
GND, or OUTB to VDD or GND
Short Circuit
Output to Supply Short
Circuit Detection Threshold
RFAULT
3
7.5
kΩ (min)
kΩ (max)
Open Circuit
Short between both OUTA and OUTB to
VDD or GND
Short Circuit
Output to Supply Short
Circuit Detection Threshold
RFAULT
6
15
kΩ (min)
kΩ (max)
Open Circuit
Open Circuit Detection
Threshold
100
200
Ω (min)
Ω (max)
ROPEN
RSHT
Open circuit between OUTA and OUTB
Short circuit between OUTA and OUTB
Output to Output Short
Circuit Detection Threshold
2
6
Ω (min)
Ω (max)
ISHTCKT
TSD
Short Circuit Current Limit
Diagnostic Time
1.43
170
63
A
°C
ms
tDIAG
6
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SNAS470D –OCTOBER 2008–REVISED MARCH 2013
I2C Interface Characteristics VDD = 5V, 2.2V ≤ I2CVDD ≤ 5.5V(1)(2)
The following specifications apply for AV = 0dB, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C.
LM48100Q
Units
Symbol
Parameter
Conditions
Typical
Limits
(Limits)
(3)
(4)
t1
SCL period
2.5
μs (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
V (min)
t2
SDA Setup Time
100
t3
SDA Stable Time
0
100
t4
Start Condition Time
Stop Condition Time
SDA Data Hold Time
Logic High Input Threshold
Logic Low Input Threshold
t5
100
t6
100
VIH
VIL
0.7 x I2CVDD
0.3 x I2CVDD
V (max)
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not specified.
(4) Datasheet min/max specification limits are specified by test or statistical analysis.
I2C Interface Characteristics VDD = 5V, 1.8V ≤ I2CVDD ≤ 2.2V(1)(2)
The following specifications apply for AV = 0dB, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C.
LM48100Q
Units
Symbol
Parameter
Conditions
Typical
Limits
(Limits)
(3)
(4)
t1
SCL period
2.5
μs (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
V (min)
t2
SDA Setup Time
250
t3
SDA Stable Time
0
250
t4
Start Condition Time
Stop Condition Time
SDA Data Hold Time
Logic High Input Threshold
Logic Low Input Threshold
t5
250
t6
250
VIH
VIL
0.7 x I2CVDD
0.3 x I2CVDD
V (max)
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not specified.
(4) Datasheet min/max specification limits are specified by test or statistical analysis.
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Typical Performance Characteristics
THD+N vs Frequency
VDD = 3.6V, POUT = 600mW, RL = 4Ω
THD+N vs Frequency
VDD = 3.6V, POUT = 400mW, RL = 8Ω
100
10
100
10
1
1
0.1
0.1
0.01
0.001
0.01
0.001
10
100
1000
10000
100000
10
100
1000
10000
100000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 3.
Figure 4.
THD+N vs Frequency
VDD = 5.0V, POUT = 1.2W, RL = 4Ω
THD+N vs Frequency
VDD = 5.0V, POUT = 850mW, RL = 8Ω
100
10
100
10
1
1
0.1
0.1
0.01
0.001
0.01
0.001
10
100
1000
10000
100000
10
100
1000
10000
100000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5.
Figure 6.
THD+N vs Output Power
THD+N vs Output Power
f = 1kHz, RL = 4Ω
f = 1kHz, RL = 8Ω
100
10
100
10
V
= 5V
DD
V
= 5V
DD
V
DD
= 3.6V
V
= 3.6V
DD
1
1
0.1
0.01
0.1
0.01
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
Power Dissipation vs Output Power
Power Dissipation vs Output Power
f = 1kHz, RL = 4Ω
f = 1kHz, RL = 8Ω
800
700
600
500
400
300
200
100
0
1400
1200
1000
800
600
400
200
0
V = 5V
DD
V
= 5V
DD
V
= 3.6V
DD
V
= 3.6V
DD
0
250
500
750 1000 1250 1500
0
500
1000
1500
2000
2500
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 9.
Figure 10.
Output Power vs Supply Voltage
Output Power vs Supply Voltage
f = 1kHz, RL = 4Ω
f = 1kHz, RL = 8Ω
3.5
3
2
THD+N = 10%
THD+N = 10%
1.5
1
2.5
2
1.5
1
THD+N = 1%
0.5
0
THD+N = 1%
0.5
0
3
3.5
4
4.5
5
5.5
3
3.5
4
4.5
5
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 11.
Figure 12.
PSRR vs Frequency
VDD = 3.6V, VRIPPLE = 200mVP-P, RL = 8Ω
0
-20
-40
-60
-80
-100
-120
10
100
1000
10000
100000
FREQUENCY (Hz)
Figure 13.
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APPLICATION INFORMATION
WRITE-ONLY I2C COMPATIBLE INTERFACE
The LM48100Q is controlled through an I2C compatible serial interface that consists of a serial data line (SDA)
and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The
LM48100Q and the master can communicate at clock rates up to 400kHz. Figure 14 shows the I2C interface
timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM48100Q is a
transmit/receive slave-only device, reliant upon the master to generate the SCL signal. Each transmission
sequence is framed by a START condition and a STOP condition (Figure 15). Each data word, device address
and data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 16).
The LM48100Q device address is 111110X, where X is determined by ADR (Table 2). ADR = 1 sets the device
address to 1111101. ADR = 0 sets the device address to 1111100.
I2C BUS FORMAT
The I2C bus format is shown in Figure 16. The START signal, the transition of SDA from HIGH to LOW while
SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0
indicates the master is writing to the slave device, RW = 1 indicates the master wants to read data from the slave
device. Set R/W = 0; the LM48100Q is a WRITE-ONLY device and will not respond the R/W = 1. The data is
latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last
address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is
generated by the slave device. If the LM48100Q receives the correct address, the device pulls the SDA line low,
generating an acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable
while SCL is HIGH. After the 8-bit register data word is sent, the LM48100Q sends another ACK bit. Following
the acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high.
Figure 14. I2C Timing Diagram
SDA
SCL
S
P
START condition
STOP condition
Figure 15. Start and Stop Diagram
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SCL
SDA
R/W ACK
ACK
START
MSB
DEVICE ADDRESS
LSB
MSB
REGISTER DATA
LSB
STOP
Figure 16. Example Write Sequence
Table 1. Device Address
B7
B6
1
B5
1
B4
1
B3
1
B2
0
B1
0
B0 R/W
ADR = 0
ADR = 1
1
1
0
0
1
1
1
1
0
1
Table 2. I2C Control Registers
Register
Address
Register Name
B7
B6 B5
B4
B3
B2
B1
B0
0
0
MODE CONTROL
0
0
0
0
0
1
POWER_ON
DG_EN
INPUT_2
DG_CONT
INPUT_1
0
DIAGNOSTIC
CONTROL
1
2
3
4
DG_RESET
ILIMIT
0
FAULT DETECTION
CONTROL
OUTPUT
_OPEN
OUTPUT
_SHORT
0
0
1
1
1
0
0
1
0
TSD
OCF
RAIL_SHT
VOL1_2
VOLUME CONTROL
1
VOL1_4
VOL2_4
VOL1_3
VOL2_3
VOL1_1
VOL_2
VOL1_0
VOL2_0
VOLUME CONTROL
2
VOL2_2
Table 3. Mode Control Registers
BIT
NAME
VALUE
DESCRIPTION
Unused
B0, B1
RESERVED
0
0
1
0
1
0
1
IN1 Input unselected
IN1 Input selected
IN2 Input unselected
IN2 Input selected
Device Disabled
Device Enabled
B2
B3
B4
INPUT_1
INPUT_2
POWER_ON
DIAGNOSTIC CONTROL
The LM48100Q output fault diagnostics are controlled through the I2C interface. When power is initially applied to
the device, the LM48100Q initializes, performing the full diagnostic sequence; output short to VDD and GND,
outputs shorted together, and no load condition, is performed. The device remains in shutdown while the initial
diagnostic check is performed. Any I2C commands written to the device during this time are stored and
implemented once the diagnostic check is complete. The initial diagnostic sequence can be terminated by setting
DG_RESET = 1.
The Diagnostic Control register, register 1, controls the LM48100Q diagnostic process. Bit B4, DG_EN, enables
the output fault detection. Set DG_EN = 1 to enable the output diagnostic test sequence. The LM48100Q treats
the DG_EN bit as rising-edge-sensitive; once DG_EN = 1 is clocked into the device, the diagnostic test is
performed. If the LM48100Q is in one-shot mode, once the test sequence is performed, the DG_EN bit is ignored
and the test sequence will not be run again. Cycle DG_EN from high-to-low-to-high to re-enable the one-shot
diagnostic test sequence.
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In continuous diagnostic mode, the test sequence is repeated until either a fault condition occurs, DG_RESET is
cycled, or the device is taken out of continuous diagnostic mode. Set DG_CONT = 1 before setting DG_EN = 1
to initiate a continuous diagnostic. Set DG-CONT = 0 to disable continuous diagnostic mode. When the device is
active and DG_EN = 0, the LM48100Q does not perform the output short, or no load diagnostics, however, the
thermal overload and output over current protection circuitry remains active, and disables the device should a
thermal or over-current fault occur. The initial diagnostic operation when power is applied to the device occurs
regardless of the state of DG_EN. The LM48100Q output fault detection can be set to either continuous mode
where the output diagnostic occurs every 60ms, or a one-shot mode. Set bit B3 (DG_CONT) to 1 for continuous
mode, set B3 = 0 for one-shot mode.
Bit B2, DG_RESET, restores the LM48100Q to normal operation after an output fault is detected. Toggle
DG_RESET to re-enable the device outputs and set FAULT high.
Table 4. Diagnostic Control Register
BIT
NAME
VALUE
DESCRIPTION
B0
RESERVED
0
0
1
Unused
Fixed output current limit
B1
ILIMIT
Supply dependent output current limit
Normal operation. FAULT remains low and device is disabled
once a fault occurs.
0
DG
_RESET
B2
1
0
1
0
1
Reset FAULT output. Device returns to pre-fault operation.
One shot diagnostic
DG
_CONT
B3
B4
Continuous diagnostic
Disable diagnostic
DG_EN
Enable diagnostic
FAULT DETECTION CONTROL REGISTER
The LM48100Q output fault tests are individually controlled through the Fault Detection Control register, register
2. Setting any of the bits in the Fault Detection Control register to 1 causes the FAULT circuitry to ignore the
associated test. For example, if B2 (RAIL_SHT) = 1 and the output is shorted to VDD, the FAULT output remains
high. Although the FAULT circuitry ignores the selected test, the LM48100Q protection circuitry remains active,
and disables the device. This feature is useful for diagnosing which fault caused a FAULTcondition.
If DG_EN = 1, and a diagnostic sequence is initiated, all the tests are performed regardless of their state in the
Fault Detection Control register. If DG_EN = 0, the RAIL_SHT, OUTPUT_OPEN and OUTPUT_SHT tests are
not performed, however, the thermal overload and output over-current detection circuitry remains active.
Table 5. Fault Detection Control Register
BIT
NAME
VALUE
DESCRIPTION
0
1
0
1
0
1
0
1
0
1
Normal operation
B0
OUTPUT_SHT
Ignore output short circuit fault (outputs shorted together)
Normal operation
B1
B2
B3
B4
OUTPUT_OPEN
Ignore output short circuit fault
Normal operation
RAIL
_SHT
Ignore output short to VDD or GND fault
Normal operation
OVF
TSD
Ignore output over-current fault
Normal operation
Ignore thermal overload fault
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GENERAL AMPLIFIER FUNCTION
Bridge Configuration Explained
The LM48100Q is designed to drive a load differentially, a configuration commonly referred to as a bridge-tied
load (BTL). The BTL configuration differs from the single-ended configuration, where one side of the load is
connected to ground. A BTL amplifier offers advantages over a single-ended device. By driving the load
differentially, the output voltage is doubled, compared to a single-ended amplifier under similar conditions. This
doubling of the output voltage leads to a quadrupling of the output power. For example, the theoretical maximum
output power for a single-ended amplifier driving 8Ω and operating from a 5V supply is 158mW, while the
theoretical maximum output power for a BTL amplifier operating under the same conditions is 633mW. Since the
amplifier outputs are both biased about VDD/2, there is no net DC voltage across the load, eliminating the DC
blocking capacitors required by single-ended, single-supply amplifiers.
Input Mixer/Multiplexer
The LM48100Q features an input mixer/multiplexer controlled through the I2C interface. The mixer/multiplexer
allows either input, or the combination of both inputs to appear at the device output. Bits B2 (INPUT_1) and B3
(INPUT_2) of the Mode Control Register select the individual input channels. Set INPUT_1 = 1 to select the
audio signal on IN1. Set INPUT_2 = 1 to select the audio signal on IN2. Setting both INPUT_1 and INPUT_2 = 1
mixes VIN1 and VIN2, and the LM48100Q outputs the result as a mono signal (Table 7).
Table 6. Input Multiplexer Control
INPUT_1
INPUT_2
LM48100Q OUTPUT
MUTE. No input selected
IN1 ONLY
0
1
0
1
0
0
1
1
IN2 ONLY
IN1 + IN2
OUTPUT FAULT DETECTION
Output Short to Supplies (VDD or GND)
With a standard speaker load (6Ω - 100Ω) connected between OUTA and OUTB, the LM48100Q can detect a
short between the outputs and either VDD or GND. A short is detected if the impedance between either OUTA or
OUTB and VDD or GND is less than 3kΩ. A short is also detected if the impedance between BOTH OUTA and
OUTB and either VDD or GND is less than 6kΩ. Under either of these conditions, the amplifier outputs are
disabled and FAULT is driven low. No short is detected if the impedance between either output and VDD or GND
is greater than 7.5kΩ. Likewise, no short is detected if the impedance between BOTH outputs and VDD or GND is
greater than 15kΩ.
Output Short Circuit and Open Circuit Detection
The LM48100Q can detect whether the amplifier outputs have been shorted together or, an output open circuit
condition has occurred. An output short circuit is detected if the impedance between OUTA and OUTB is less
than 2Ω. An open circuit is detected if the impedance between OUTA and OUTB is greater than 200Ω. Under
either of these conditions, the amplifier outputs are disabled and FAULT is driven low. The device remains in
normal operation if the impedance between OUTA and OUTB is in the range of 6Ω to 100Ω. The output open
circuit test is only performed during the initial diagnostic sequence during power up, or when DG_ENABLE is set
to 1.
Output Over-Current Detection
The LM48100Q has two over current detection modes, a fixed current limit, and a supply dependent current limit.
Bit B1 (ILIMIT) of the Diagnostic Control Register selects the over-current detection mode. Set ILIMIT = 0 to
select a fixed current limit of 1.47A (typ). Set ILIMIT = 1 to select the supply dependent current limit mode. In
supply dependent mode, the current limit is determined by Equation 1:
ISHTCKT = 0.264 x VDD
(A)
(1)
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If the output current exceeds the current limit, the device outputs are disabled and FAULT is driven low. The
output over-current detection circuitry remains active when the diagnostics have been disabled (DG_EN = 0).
Thermal Overload Detection
The LM48100Q has thermal overload threshold of 170°C (typ). If the die temperature exceeds 170°C, the outputs
are disabled and FAULT is driven low. The thermal overload detection circuitry remains active when the
diagnostics have been disabled (DG_EN = 0).
OPEN FAULT OUTPUT
The LM48100Q features an open drain, fault indication output, FAULT , that asserts when a fault condition is
detected by the device. FAULT goes low when either an output short, output open, over current, or thermal
overload fault is detected, and the diagnostic test is not ignored, see FAULT DETECTION CONTROL
REGISTER section. FAULT remains low even after the fault condition has been cleared and the diagnostic tests
are repeated. Toggle DG_RESET to clear FAULT .
Connect a 1.5kΩ or higher pull-up resistor between FAULT and VDD
.
VOLUME CONTROL
Table 7. Volume Control
Volume Step
VOL4
0
VOL3
0
VOL2
0
VOL1
VOL0
0
Gain (dB)
–80
–54
–40.5
–34.5
–30
–27
–24
–21
–18
–15
–13.5
–12
–10.5
–9
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
2
0
0
0
1
3
0
0
0
0
4
0
0
0
1
5
0
0
1
0
6
0
0
1
1
7
0
0
1
0
8
0
0
1
1
9
0
1
0
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
1
0
–7.5
–6
0
1
1
1
1
0
0
0
–4.5
–3
1
0
0
1
1
0
0
0
–1.5
0
1
0
0
1
1
0
1
0
1.5
1
0
1
1
3
1
0
1
0
4.5
1
0
1
1
6
1
1
0
0
7.5
1
1
0
1
9
1
1
0
0
10.5
12
1
1
0
1
1
1
1
0
13.5
15
1
1
1
1
1
1
1
0
16.5
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Table 7. Volume Control (continued)
Volume Step
32
VOL4
VOL3
VOL2
VOL1
VOL0
Gain (dB)
1
1
1
1
1
18
SHUTDOWN FUNCTION
The LM48100Q features an I2C selectable low power shutdown mode that disables the device, reducing
quiescent current consumption to 0.01μA. Set bit B4 (POWER_ON) in the Mode Control Register to 0 to disable
the device. Set B0 to 1 to enable the device.
POWER DISSIPATION
The increase in power delivered by a BTL amplifier leads to a direct increase in internal power dissipation. The
maximum power dissipation for a BTL amplifier for a given supply voltage and load is given by Equation 2:
PDMAX = 4 x VDD2 / 2π2RL (Watts)
(2)
The maximum power dissipation of the HTSSOP package is calculated by Equation 3:
PDMAX (PKG) = TJMAX — TA / θJA (Watts)
(3)
where TJMAX is 150°C, TA is the ambient temperature and θJA is the thermal resistance specified in the Absolute
Maximum Ratings.
If the power dissipation for a given operating condition exceeds the package maximum, either decrease the
ambient temperature, increase air flow, add heat sinking to the device, or increase the load impedance and/or
supply voltage. The LM48100Q HTSSOP package features an exposed die attach pad (DAP) that can be used
to increase the maximum power dissipation of the package, see Exposed DAP Mounting Considerations.
The LM48100Q features thermal overload protection that disables the amplifier output stage when the die
temperature exceeds +170°C. See the Thermal Overload Detection section.
PROPER SELECTION OF EXTERNAL COMPONENTS
Power Supply Bypassing/Filtering
Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass
capacitors as close to the device as possible. Place a 1µF ceramic capacitor from VDD to GND. Additional bulk
capacitance may be added as required.
Input Capacitor Selection
Input capacitors may be required for some applications, or when the audio source is single-ended. Input
capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of
the audio source and the bias voltage of the LM48100Q. The input capacitors create a high-pass filter with the
input resistors RIN. The -3dB point of the high-pass filter is found using Equation 4 below.
f = 1 / 2πRINCIN (Hz)
(4)
Where the value of RIN is given in the Electrical Characteristics Table.
High pass filtering the audio signal helps protect the speakers. When the LM48100Q is using a single-ended
source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the
power supply noise frequencies, filters out the noise such that it is not amplified and heard on the output.
Capacitors with a tolerance of 10% or better are recommended for impedance matching and improved PSRR.
Bias Capacitor Selection
The LM48100Q internally generates a VDD/2 common-mode bias voltage. The BIAS capacitor CBIAS, improves
PSRR and THD+N by reducing noise at the BIAS node. Use a 2.2µF ceramic placed as close to the device as
possible.
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PCB Layout Guidelines
Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due
to trace resistance between the LM48100Q and the load results in decreased output power and efficiency. Trace
resistance between the power supply and ground has the same effect as a poorly regulated supply, increased
ripple and reduced peak output power. Use wide traces for power supply inputs and amplifier outputs to minimize
losses due to trace resistance, as well as route heat away from the device. Proper grounding improves audio
performance, minimizes crosstalk between channels and prevents digital noise from interfering with the audio
signal. Use of power and ground planes is recommended.
Place all digital components and route digital signal traces as far as possible from analog components and
traces. Do not run digital and analog traces in parallel on the same PCB layer. If digital and analog signal lines
must cross either over or under each other, ensure that they cross in a perpendicular fashion.
Exposed Dap Mounting Considerations
The LM48100Q HTSSOP-EP package features an exposed die-attach (thermal) pad on its backside. The
exposed pad provides a direct heat conduction path from the die to the PCB, reducing the thermal resistance of
the package. Connect the exposed pad to GND with a large pad and via to a large GND plane on the bottom of
the PCB for best heat distribution.
LM48100QTL Demoboard Bill of Materials
Designator
Quantity
Description
C1
C2
1
1
10µF ±10% 16V Tantalum Capacitor (B Case) AVX TPSB106K016R0800
1µF ±10% 16V X7R Ceramic Capacitor (603) Murata GRM188R71C105KA12D
0.1µF ±10% 16V X7R Ceramic Capacitor (603) Murata GRM188R71C104KA01D
Panasonic ECJ-1VB1C104K
C3, C5
C4
2
1
2
2.2 µF ±10% 16V X7R Ceramic Capacitor (603) Murata GRM188R71A225KE15D
0.1µF ±10% 50V X5R Ceramic Capacitor (1206) Murata
GRM319R71H104KA01D
C6, C7
R1, R2
R3
2
1
5kΩ ±5% 1/10W Thick Film Resistor (603) Vishay CRCW06035R1KJNEA
1.5kΩ ±5% 1/10W Thick Film Resistor (603) Vishay CRCW06031K50JNEA
16-Pin Boardmount Socket 3M 8516-4500JL
3-Pin Header
J2
1
JU1
1
JU2–JU12
LM48100QMH
11
U1
2 Pin Header
LM48100QMH (14-Pin HTSSOP-EP)
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Demo Board Schematic
U1
VDD
VDD
+
14
5
10
8
VDD
GND
BIAS
IN1
PVDD
PGND
C3
0.1 mF
C2
1 mF
C1
10 mF
VDD
GND
C4
2.2 mF
13
12
C7
9
7
OUTA
OUTB
0.1 mF
IN1
IN2
OUTA
OUTB
C6
11
IN2
0.1 mF
I2CVDD
I2CVDD VDD
JU1
1
3
6
4
2
ADR
I2CVDD
C5
0.1 mF
I2CVDD
VDD
2
3
SCL
SCL
I2CVDD
R3
1.5k
1
SDA
SDA
FAULT
R1
5k
R2
5k
FAULT
J2
LM48100
JU2
SDA
SCL
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
MOUNTING
SUPPORT
Figure 17. LM48100Q Demo Board Schematic
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PC Board Layout
Figure 18. Top Silkscreen
Figure 19. Top Layer
Figure 20. Layer 2
Figure 21. Layer 3
Figure 22. Bottom Layer
Figure 23. Bottom Silkscreen
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Revision History
Rev
1.0
Date
Description
10/14/08
10/20/08
11/07/08
11/12/08
03/21/2013
Initial release.
Text edits.
1.01
1.02
1.03
D
Added a column (Limits) in the Electrical tables.
Text edits.
Changed layout of National Data Sheet to TI format
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
LM48100QMH/NOPB
LM48100QMHE/NOPB
LM48100QMHX/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 105
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
HTSSOP
HTSSOP
HTSSOP
PWP
14
14
14
94
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
L48100Q
ACTIVE
ACTIVE
PWP
PWP
250
Green (RoHS
& no Sb/Br)
-40 to 105
L48100Q
L48100Q
2500
Green (RoHS
& no Sb/Br)
-40 to 105
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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21-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM48100QMHE/NOPB HTSSOP PWP
LM48100QMHX/NOPB HTSSOP PWP
14
14
250
178.0
330.0
12.4
12.4
6.95
6.95
8.3
8.3
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM48100QMHE/NOPB
LM48100QMHX/NOPB
HTSSOP
HTSSOP
PWP
PWP
14
14
250
210.0
367.0
185.0
367.0
35.0
35.0
2500
Pack Materials-Page 2
MECHANICAL DATA
PWP0014A
MXA14A (Rev A)
www.ti.com
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