LM4867LQ [TI]
3W, 2 CHANNEL, AUDIO AMPLIFIER, PQCC24, EXPOSED PAD, LLP-24;
| 型号： | LM4867LQ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3W, 2 CHANNEL, AUDIO AMPLIFIER, PQCC24, EXPOSED PAD, LLP-24 放大器 商用集成电路 |
| 文件： | 总36页 (文件大小：1375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OBSOLETE
LM4867
www.ti.com
SNAS117B –MAY 2004–REVISED OCTOBER 2004
LM4867
Output-Transient-Free Dual 2.1W Audio Amplifier
Plus No Coupling Capacitor Stereo Headphone Function
Check for Samples: LM4867
1
FEATURES
DESCRIPTION
The LM4867 is a dual bridge-connected audio power
2
•
Advanced “Click and Pop” Suppression
Circuitry
amplifier which, when connected to a 5V supply, will
(1)
(2)
deliver 2.1W to a 4Ω load
or 2.4W to a 3Ω load
•
Eliminates Headphone Amplifier Output
Coupling Capacitors (Patent Pending)
with less than 1.0% THD+N (see notes below). The
LM4867 uses advanced, latest generation circuitry to
eliminate all traces of clicks and pops when the
supply voltage is first applied. The amplifier has a
headphone-amplifier-select input pin. It is used to
switch the amplifiers from bridge to single-ended
mode for driving headphones. A new circuit topology
eliminates headphone output coupling capacitors
(patent pending). A MUX control pin allows selection
between the two sets of stereo input signals. The
MUX control can also be used to select between two
different customer-specified closed-loop responses.
•
•
Stereo Headphone Amplifier Mode
Input Mux Control and Two Separate Inputs
Per Channel
•
•
Thermal Shutdown Protection Circuitry
WQFN, TSSOP, and HTSSOP Packaging
Available
APPLICATIONS
•
•
•
Multimedia Monitors
Boomer audio power amplifiers are designed
specifically to provide high quality output power from
a surface mount package and require few external
components. To simplify audio system design, the
LM4867 combines dual bridge speaker amplifiers and
stereo headphone amplifiers in one package.
Portable and Desktop Computers
Portable Audio Systems
KEY SPECIFICATIONS
•
PO at 1% THD+N
The LM4867 features an externally controlled power-
–
–
–
–
LM4867LQ, 3Ω Load, 2.4W (Typ)
LM4867LQ, 4Ω Load, 2.1W (Typ)
LM4867MTE, 4Ω, 1.9W (Typ)
LM4867MT, 8Ω, 1.1W (Typ)
saving micropower shutdown mode,
a
stereo
headphone amplifier mode, and thermal shutdown
protection.
(1) An LM4867LQ or LM4867MTE that has been properly
mounted to a circuit board will deliver 2.1W into 4Ω. The Mux
control can also be used to select two different closed-loop
responses. LM4867MT will deliver 1.1W into 8Ω. See the
Application Information sections for further information
concerning the LM4867LQ and the LM4867MT.
(2) An LM4867LQ or LM4867MTE that has been properly
mounted to a circuit board and forced-air cooled will deliver
2.4W into 3Ω.
•
•
Single-Ended Mode - THD+N at 75mW into
32Ω, 0.5% (Max)
Shutdown Current, 0.7µA (Typ)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
OBSOLETE
LM4867
SNAS117B –MAY 2004–REVISED OCTOBER 2004
www.ti.com
Connection Diagram
Figure 1. Top View
See Package Number PW for TSSOP
See Package Number PWP for HTSSOP
Figure 2. Top View
See Package Number NHW0024B for WQFN
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Typical Application
* Refer to the Application Information section titled PROPER SELECTION OF EXTERNAL COMPONENTS for details
concerning the value of CB.
Figure 3. Typical Audio Amplifier Application Circuit
(Pin out shown for the 24-pin WQFN package. Numbers in ( ) are for the 20-pin MTE and MT packages.)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)
Supply Voltage
6.0V
−65°C to +150°C
−0.3V to VDD +0.3V
Internally limited
2000V
Storage Temperature
Input Voltage
Power Dissipation(3)
ESD Susceptibility(4)
All pins except Pin 3 (MT, MTE), Pin 2 (LQ)
Pin 3 (MT, MTE), Pin 2 (LQ)
8000V
ESD Susceptibility(5)
Junction Temperature
200V
150°C
Vapor Phase (60 sec.)
Infrared (15 sec.)
θJC (typ)—PW
215°C
Solder Information
Small Outline Package
220°C
20°C/W
θJA (typ)—PW
80°C/W
θJC (typ)—PWP
2°C/W
θJA (typ)—PWP
41°C/W(6)
51°C/W(7)
90°C/W(8)
3.0°C/W
Thermal Resistance
θJA (typ)—PWP
θJA (typ)—PWP
θJC (typ)—NHW0024B
θJA (typ)—NHW0024B
42°C/W(9)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device operates within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given. The typical value however, is a good indication
of device performance.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX − TA)/θJA. For the LM4867, TJMAX = 150°C. For the θJAs for different
packages, please see the Application Information section or the Absolute Maximum Ratings section.
(4) Human body model, 100pF discharged through a 1.5kΩ resistor.
(5) Machine model, 220pF–240pF discharged through all pins.
(6) The given θJA is for an LM4867 packaged in an PWP with the Exposed-DAP soldered to an exposed 2in2 area of 1oz printed circuit
board copper.
(7) The given θJA is for an LM4867 packaged in an PWP with the Exposed-DAP soldered to an exposed 1in2 area of 1oz printed circuit
board copper.
(8) The given θJA is for an LM4867 packaged in an PWP with the Exposed-DAP not soldered to printed circuit board copper.
(9) The given θJA is for an LM4867 packaged in an WQFN with the Exposed-DAP soldered to an exposed 2in2 area of 1oz printed circuit
board copper.
Operating Ratings
Temperature Range
TMIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ 85°C
2.0V ≤ VDD ≤ 5.5V
Supply Voltage
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Electrical Characteristics for Entire IC(1)(2)
The following specifications apply for VDD= 5V unless otherwise noted. Limits apply for TA= 25°C.
Symbol
Parameter
Conditions
LM4867
Units
(Limits)
Typical(3)
Limit(4)
VDD
Supply Voltage
2
5.5
15
6
V (min)
V (max)
IDD
Quiescent Power Supply Current
VIN = 0V, IO = 0A(5), HP-IN = 0V
VIN = 0V, IO = 0A(5), HP-IN = 4V
VDD applied to the SHUTDOWN pin
7.5
3.0
0.7
mA (max)
mA (max)
μA (max)
ISD
Shutdown Current
2
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device operates within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given. The typical value however, is a good indication
of device performance.
(2) All voltages are measured with respect to the ground (GND) pins, unless otherwise specified.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are ensured to Texas Instruments' AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are ensured
by design, test, or statistical analysis.
(5) The quiescent power supply current depends on the offset voltage when a practical load is connected to the amplifier.
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Electrical Characteristics for Bridged-Mode Operation(1)(2)
The following specifications apply for VDD= 5V unless otherwise specified. Limits apply for TA= 25°C.
Symb
ol
Parameter
Conditions
LM4867
Units
(Limits)
Typical Limit(4)
(3)
VOS
PO
Output Offset Voltage
Output Power(5)
VIN = 0V
5
50
mV
(max)
THD = 1%, f = 1kHz(6)
LM4867MTE, RL
=
2.2
W
3Ω
LM4867LQ, RL = 3Ω
2.4
1.9
2.1
1.1
3.0
3.0
2.6
2.6
1.5
0.34
W
W
LM4867MTE, RL = 4Ω
LM4867LQ, RL = 4Ω
LM4867, RL = 8Ω
W
1.0
W (min)
W
THD+N = 10%, f = 1kHz(6)
LM4867MTE, RL = 3Ω
LM4867LQ, RL = 3Ω
LM4867MTE, RL = 4Ω
LM4867LQ, RL = 4Ω
LM4867, RL = 8Ω
W
W
W
W
THD+N = 1%, f = 1 kHz,
W
RL = 32Ω
THD+ Total Harmonic
Distortion+Noise
20Hz ≤ f ≤ 20kHz, AVD = 2
LM4867MTE, RL = 4Ω, PO
= 2W
0.3
0.3
0.3
67
%
N
LM4867LQ, RL = 4Ω, PO
= 2W
LM4867, RL = 8Ω, PO
=
1W
PSRR Power Supply Rejection
Ratio
VDD = 5V, VRIPPLE = 200 mVRMS, RL = 8Ω,
CB = 2.2μF
dB
XTALK Channel Separation
f = 1 kHz, CB = 2.2μF
80
97
dB
dB
SNR
Signal To Noise Ratio
VDD = 5V, PO = 1.1W, RL = 8Ω
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device operates within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given. The typical value however, is a good indication
of device performance.
(2) All voltages are measured with respect to the ground (GND) pins, unless otherwise specified.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are ensured to Texas Instruments' AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are ensured
by design, test, or statistical analysis.
(5) Output power is measured at the device terminals.
(6) When driving 3Ω or 4Ω loads and operating on a 5V supply, the LM4867LQ and LM4867MTE must be mounted to a circuit board that
has a minimum of 2.5in2 of exposed, uniterrupted copper area connected to the WQFN or TSSOP package's exposed DAP.
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Electrical Characteristics for Single-Ended Operation(1)(2)
The following specifications apply for VDD= 5V unless otherwise specified. Limits apply for TA= 25°C.
Symbol
Parameter
Conditions
LM4867
Units
(Limits)
Typical(3)
Limit(4)
VOS
PO
Output Offset Voltage
VIN = 0V
5
50
mV (max)
mW (min)
mW
Output Power
THD = 0.5%, f = 1kHz, RL = 32Ω
THD+N = 1%, f = 1kHz, RL = 8Ω(5)
THD+N = 1%, f = 1kHz, RL = 16Ω
THD+N = 1%, f = 1kHz, RL = 32Ω
THD+N = 10%, f = 1kHz, RL = 16Ω
THD+N = 10%, f = 1kHz, RL = 32Ω
THD = 0.05%, RL = 5kΩ
85
75
180
165
88
mW
mW
208
114
1
mW
mW
VOUT
Output Voltage Swing
VP-P
THD+N
Total Harmonic Distortion+Noise
AV = −1, PO = 75mW, 20 Hz ≤ f ≤ 20kHz,
RL = 32Ω
0.2
%
PSRR
Power Supply Rejection Ratio
CB = 2.2μF, VRIPPLE = 200mVRMS
,
52
dB
f = 1kHz
XTALK
SNR
Channel Separation
Signal To Noise Ratio
f = 1kHz, CB = 2.2μF
60
94
dB
dB
VDD = 5V, PO = 340mW, RL = 8Ω
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device operates within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given. The typical value however, is a good indication
of device performance.
(2) All voltages are measured with respect to the ground (GND) pins, unless otherwise specified.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are ensured to Texas Instruments' AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are ensured
by design, test, or statistical analysis.
(5) See Application Information section SINGLE-ENDED OUTPUT POWER PERFORMANCE AND MEASUREMENT CONSIDERATIONS
for more information.
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Typical Performance Characteristics
MTE- and LQ- Specific Characteristics
LM4867MTE
THD+N vs Output Power
LM4867MTE
THD+N vs Frequency
Figure 4.
Figure 5.
LM4867LQ
THD+N vs Output Power
LM4867LQ
THD+N vs Frequency
Figure 6.
Figure 7.
LM4867MTE
THD+N vs Output Power
LM4867LQ
THD+N vs Output Power
Figure 8.
Figure 9.
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Typical Performance Characteristics
MTE- and LQ- Specific Characteristics (continued)
LM4867LQ, LM4867MTE
Power Dissipation vs Power Output
LM4867MTE
Power Derating Curve
Figure 10.
Figure 11.
LM4867LQ
Power Derating Curve
Figure 12.
This curve shows the LM4867MTE's thermal dissipation ability at different ambient temperatures given these
conditions:
500LFPM + JEDEC board: The part is soldered to a 1S2P 20-lead HTSSOP test board with 500 linear feet per
minute of forced-air flow across it.
Board information - copper dimensions: 74x74mm, copper coverage: 100% (buried layer) and 12% (top/bottom
layers), 16 vias under the exposed-DAP.
500LFPM + 2.5in2: The part is soldered to a 2.5in2, 1 oz. copper plane with 500 linear feet per minute of forced-air
flow across it.
2.5in2: The part is soldered to a 2.5in2, 1oz. copper plane.
Not Attached: The part is not soldered down and is not forced-air cooled.
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Typical Performance Characteristics
THD+N vs Frequency
THD+N vs Frequency
Figure 13.
Figure 14.
THD+N vs Frequency
THD+N vs Output Power
Figure 15.
Figure 16.
THD+N vs Output Power
THD+N vs Output Power
Figure 17.
Figure 18.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
THD+N vs Frequency
Figure 19.
Figure 20.
THD+N vs Output Power
THD+N vs Frequency
Figure 21.
Figure 22.
Output Power
vs Load Resistance
Power Dissipation
vs Supply Voltage
Figure 23.
Figure 24.
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Typical Performance Characteristics (continued)
Output Power
vs Supply Voltage
Output Power vs
Supply Voltage
Figure 25.
Figure 26.
Output Power vs
Supply Voltage
Output Power vs
Load Resistance
Figure 27.
Figure 28.
Output Power vs
Load Resistance
Power Dissipation vs
Output Power
Figure 29.
Figure 30.
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Typical Performance Characteristics (continued)
Dropout Voltage vs
Supply Voltage
Power Derating Curve
Figure 31.
Figure 32.
Power Dissipation vs
Output Power
Noise Floor
Figure 33.
Figure 34.
Channel Separation
Channel Separation
Figure 35.
Figure 36.
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Typical Performance Characteristics (continued)
Power Supply
Rejection Ratio
Open Loop
Frequency Response
Figure 37.
Figure 38.
Supply Current vs
Supply Voltage
Figure 39.
External Components Description
See Figure 3
Components
Functional Description
1.
2.
Ri
Inverting input resistance which sets the closed-loop gain in conjunction with Rf. This resistor
also forms a high pass filter with C i at fc = 1/(2πRiCi).
Ci
Input coupling capacitor which blocks the DC voltage at the amplifier's input terminals. Also
creates a highpass filter with Ri at fc = 1/(2πRiCi). Refer to the section, Proper Selection of
External Components, for an explanation of how to determine the value of Ci.
3.
4.
Rf
Feedback resistance which sets the closed-loop gain in conjunction with Ri.
Cs
Supply bypass capacitor which provides power supply filtering. Refer to the POWER
SUPPLY BYPASSING section for information concerning proper placement and selection of
the supply bypass capacitor.
5.
CB
Bypass pin capacitor which provides half-supply filtering. Refer to the section, Proper
Selection of External Components, for information concerning proper placement and
selection of CB.
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APPLICATION INFORMATION
ELIMINATING OUTPUT COUPLING CAPACITORS
Typical single-supply audio amplifiers that can switch between driving bridge-tied-load (BTL) speakers and
single-ended (SE) headphones use a coupling capacitor on each SE output. This capacitor blocks the half-supply
voltage to which the output amplifiers are typically biased and couples the audio signal to the headphones. The
signal return to circuit ground is through the headphone jack's sleeve.
The LM4867 eliminates these coupling capacitors. Amp2A is internally configured to apply VDD/2 to a stereo
headphone jack's sleeve. This voltage matches the quiescent voltage present on the Amp1A and Amp1B outputs
that drive the headphones. The headphones operate in a manner very similar to a bridge-tied-load (BTL). The
same DC voltage is applied to both headphone speaker terminals. This results in no net DC current flow through
the speaker. AC current flows through a headphone speaker as an audio signal's output amplitude increases on
the speaker's terminal.
When operating as a headphone amplifier, the headphone jack sleeve is not connected to circuit ground. Using
the headphone output jack as a line-level output will place the LM4867's one-half supply voltage on a plug's
sleeve connection. Driving a portable notebook computer or audio-visual display equipment is possible. This
presents no difficulty when the external equipment uses capacitively coupled inputs. For the very small minority
of equipment that is DC-coupled, the LM4867 monitors the current supplied by the amplifier that drives the
headphone jack's sleeve. If this current exceeds 500mAPK, the amplifier is shutdown, protecting the LM4867 and
the external equipment. For more information, see the section titled SINGLE-ENDED OUTPUT POWER
PERFORMANCE AND MEASUREMENT CONSIDERATIONS.
OUTPUT TRANSIENT ("POPS AND CLICKS") ELIMINATED
The LM4867 contains advanced circuitry that eliminates output transients ("pop and click"). This circuitry
prevents all traces of transients when the supply voltage is first applied, when the part resumes operation after
shutdown, or when switching between BTL speakers and SE headphones. Two circuits combine to eliminate pop
and click. One circuit mutes the output when switching between speaker loads. Another circuit monitors the input
signal. It maintains the muted condition until there is sufficient input signal magnitude (>60mVRMS, typ) to mask
any remaining transient that may occur.
Figure 40 shows the LM4867's lack of transients in the differential signal (Trace B) across a BTL 8Ω load. The
LM4867's active-high SHUTDOWN pin is driven by the logic signal shown in Trace A. Trace C is the VOUT-
output signal and trace D is the VOUT+ output signal. The shutdown signal frequency is 1Hz with a 50% duty
cycle. Figure 41 is generated with the same conditions except that the output drives a 32Ω single-ended (SE)
load. Again, no trace of output transients is seen.
USING THE LM4867 TO UPGRADE LM4863 AND LM4873 DESIGNS
The LM4867's noise-free operation plus coupling-capacitorless headphone operation and functional compatibility
with the LM4873 and the LM4863 simplifies upgrading systems using these parts. Upgrading older designs that
use either the LM4863 or the LM4873 is easy. Simply remove and short the coupling capacitors located between
the LM4873's or LM4863's Amp1A and Amp1B outputs and the headphone connections. Also remove the 1kΩ
resistor between each headphone connection and ground. Finally, remove any resistors connected to the HP-IN
pin (typically two 100kΩ resistors). Connect the HP-IN pin directly to the headphone jack control pin as shown in
Figure 42.
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Figure 40. Differential output signal (Trace B) is devoid of transients. The SHUTDOWN pin is driven by a
shutdown signal (Trace A). The inverting output (Trace C) and the non-inverting output (Trace D) are
applied across an 8Ω BTL load.
The LM4867's pin configuration simplifies the process of upgrading systems that use the LM4863. Except for its
four MUX function pins, the LM4867's pin configuration matches the LM4863's pin configuration. If the LM4867's
MUX functionality is not needed when replacing an LM4863, connect the MUX CTRL pin to either VDD or ground.
To ensure correct amplifier operation, unused MUX inputs must be tied to GND. As shown in Table 1,
grounding the MUX CTRL pin selects stereo input 1 (−IN A1 and −IN B1), whereas applying VDD to the MUX
CTRL pin selects stereo input 2 (−IN A2 and −IN B2).
The LM4867's unique headphone sense circuit requires a dual switch headphone jack. Replace the four-terminal
headphone jack used with the LM4863 and LM4873 with the five-terminal headphone jack, such as the
Switchcraft 35RAPC4BH3, shown in Figure 40. Connect the +OUT A (Amp2A) pin to the five-terminal headphone
jack's sleeve pin.
Figure 41. Single-ended output signal (Trace B) is devoid of transients. The SHUTDOWN pin is driven by
a shutdown signal (Trace A). The inverting output (Trace C) and the VBYPASS output (Trace D) are applied
across a 32Ω BTL load.
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Figure 42. Typical Audio Amplifier Application Circuit
(Pin out shown for the 24-pin WQFN package. Numbers in ( ) are for the 20-pin MTE and MT packages.)
STEREO-INPUT MULTIPLEXER (STEREO MUX)
The LM4867 has two stereo inputs. The MUX CTRL Pin controls which stereo input is active. As shown in the
Table 1, applying 0V to the MUX CTRL input activates stereo input 1, whereas applying VDD to the MUX CTRL
inputs activates stereo input 2. To ensure correct amplifier operation, unused MUX inputs must be tied to
GND.
Figure 43. Input MUX Example
Typical LM4867 applications use the MUX to switch between two stereo input signals. Each stereo channel's
gain can be tailored to produce the required output signal level by choosing the appropriate input and feedback
resistor ratio.
Another configuration uses the MUX to select two different gains or frequency compensated gains that amplify a
single pair of stereo input signals. Figure 43 shows two different feedback networks, Network 1 and Network 2.
Network 1 produces increasing gain as the input signal's frequency decreases. This can be used to compensate
a small, full-range speaker's low frequency response roll-off. Network 2 sets the gain for an alternate load such
as headphones. The circuit in Figure 44 uses Network 1 when driving external speakers, switching to Network 2
when headphones are connected. The normally closed control switch in Figure 44's headphone jack connects to
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the MUX CTRL pin. When headphones are connected, the LM4867's internal pull-up that applies VDD to the HP-
IN and the external 100kΩ resistor applies VDD to MUX CTRL pin. Simultaneously applying these control
voltages automatically selects the amplifier (headphone or bridge) and switches the gain (MUX channel
selection). Alternatively, leaving the MUX CTRL pin independently accessible allows a user to select bass boost
as needed. This alternative user-selectable bass-boost scheme requires connecting equal ratio resistor feedback
networks to each MUX input channel. The value of the resistor in the RC network is chosen to give a gain that is
necessary to achieve the desired bass-boost.
Switching between the MUX channels may change the input signal source or the feedback resistor network.
During the channel switching transition, the average voltage level present on the internal amplifier's input may
change. This change can slew at a rate that may produce audible voltage transients or clicks in the amplifier's
output signal. Using the MUX to select between two vastly dissimilar gains is a typical transient-producing
situation. As the MUX is switched, an audible click may occur as the gain suddenly changes.
PIN OUT COMPATIBILITY WITH THE LM4863
The LM4867 pin out was designed to simplify replacing the LM4863: except for the four Pins(-IN A2, MUX CTRL,
-IN B2, and NC) that implement the LM4867's extra functionality, the LM4867MT/MTE and LM4863MT/MTE pin
(1)
outs match.
Figure 44. As configured, connecting headphones to this jack automatically selects the stereo
headphone amplifier and, with the additional NC switch, changes MUX channels (Network 2 in Figure 43)
EXPOSED-DAP MOUNTING CONSIDERATIONS
The LM4867's exposed-DAP (die attach paddle) packages (MTE and LQ) provide a low thermal resistance
between the die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the
die to the surrounding PCB copper area heatsink, copper traces, ground plane, and finally, surrounding air. The
result is a low voltage audio power amplifier that produces 2.4W dissipation in a 4Ω load at ≤ 1% THD+N and
over 3W in a 3Ω load at 10% THD+N. This high power is achieved through careful consideration of necessary
thermal design. Failing to optimize thermal design may compromise the LM4867's high power performance and
activate unwanted, though necessary, thermal shutdown protection.
The MTE and LQ packages must have their DAPs soldered to a copper pad on the PCB. The DAP's PCB copper
pad is then, ideally, connected to a large plane of continuous unbroken copper. This plane forms a thermal mass,
heat sink, and radiation area. Place the heat sink area on either outside plane in the case of a two-sided or multi-
layer PCB. (The heat sink area can also be placed on an inner layer of a multi-layer board. The thermal
resistance, however, will be higher.) Connect the DAP copper pad to the inner layer or backside copper heat sink
area with 32 (4 X 8) (MTE) or 6 (3 X 2) (LQ) vias. The via diameter should be 0.012in - 0.013in with a 1.27mm
pitch. Ensure efficient thermal conductivity by plugging and tenting the vias with plating and solder mask,
respectively.
Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and
amplifier share the same PCB layer, a nominal 2.5in2 (min) area is necessary for 5V operation with a 4Ω load.
Heatsink areas not placed on the same PCB layer as the LM4867 should be 5in2 (min) for the same supply
voltage and load resistance. The last two area recommendations apply for 25°C ambient temperature. Increase
the area to compensate for ambient temperatures above 25°C. In systems using cooling fans, the LM4867MTE
(1) If the LM4867 replaces an LM4863 and the input MUX circuitry is not being used, the LM4867 MUX CTRL pin must be tied to VDD or
GND and the unused MUX inputs must be connected to GND.
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can take advantage of forced air cooling. With an air flow rate of 450 linear-feet per minute and a 2.5in2 exposed
copper or 5.0in2 inner layer copper plane heatsink, the LM4867MTE can continuously drive a 3Ω load to full
power. The LM4867LQ achieves the same output power level without forced-air cooling. In all circumstances and
under all conditions, the junction temperature must be held below 150°C to prevent activating the LM4867's
thermal shutdown protection. The LM4867's power de-rating curve in the Typical Performance Characteristics
shows the maximum power dissipation versus temperature. Example PCB layouts for the HTSSOP and LQ
packages are shown in the Demonstration Board Layout section. Further detailed and specific information
concerning PCB layout and fabrication and mounting an LQ (WQFN) is found in Texas Instruments AN1187
(SNOA401).
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω
LOADS
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by a 4Ω load from 2.1W to 2.0W. The problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 42, the LM4867 consists of two pairs of operational amplifiers, forming a two-channel
(channel A and channel B) stereo amplifier. (Though the following discusses channel A, it applies equally to
channel B.) External resistors Rf and Ri set the closed-loop gain of Amp1A, whereas two internal 20kΩ resistors
set Amp2A's gain at -1. The LM4867 drives a load, such as a speaker, connected between the two amplifier
outputs, -OUTA and +OUTA.
Figure 42 shows that Amp1A's output serves as Amp2A's input. This results in both amplifiers producing signals
identical in magnitude, but 180° out of phase. Taking advantage of this phase difference, a load is placed
between -OUTA and +OUTA and driven differentially ("commonly referred to as bridge mode"). This results in a
differential gain of
AVD = 2 * (Rf/R i)
(1)
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the single-
ended configuration: its differential output doubles the voltage swing across the load. This produces four times
the output power when compared to a single-ended amplifier under the same conditions. This increase in
attainable output power assumes that the amplifier is not current limited or that the output signal is not clipped.
To ensure minimum output signal clipping when choosing an amplifier's closed-loop gain, refer to the AUDIO
POWER AMPLIFIER DESIGN section.
A bridge amplifier design has a few distinct advantages over the single-ended configuration, as it provides
differential drive to the load, thus doubling the output swing for a specified supply voltage. Four times the output
power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable
output power assumes that the amplifier is not current limited or clipped. In order to choose an amplifier's closed-
loop gain without causing excessive clipping, please refer to the AUDIO POWER AMPLIFIER DESIGN section.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing channel A's and channel B's outputs at half-supply. This eliminates the coupling capacitor that single
supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a single-ended configuration
forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power
dissipation and may permanently damage loads such as speakers.
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POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. Equation 2
states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and
driving a specified output load.
PDMAX = (VDD)2/(2π2RL): Single-Ended
(2)
However, a direct consequence of the increased power delivered to the load by a bridge amplifier is higher
internal power dissipation for the same conditions.
The LM4867 has two operational amplifiers per channel. The maximum internal power dissipation per channel
operating in the bridge mode is four times that of a single-ended amplifier. From Equation 3, assuming a 5V
power supply and an 4Ω load, the maximum single channel power dissipation is 1.27W or 2.54W for stereo
operation.
PDMAX = 4 * (VDD)2/(2π2RL): Bridge Mode
(3)
The LM4867's power dissipation is twice that given by Equation 2 or Equation 3 when operating in the single-
ended mode or bridge mode, respectively. Twice the maximum power dissipation point given by Equation 3 must
not exceed the power dissipation given by Equation 4:
PDMAX' = (TJMAX − TA)/θJA
(4)
The LM4867's TJMAX = 150°C. In the LQ package soldered to a DAP pad that expands to a copper area of 5in2
on a PCB, the LM4867's θJA is 20°C/W. In the MTE package soldered to a DAP pad that expands to a copper
area of 2in2 on a PCB, the LM4867's θJA is 41°C/W. At any given ambient temperature TA, use Equation 4 to find
the maximum internal power dissipation supported by the IC packaging. Rearranging Equation 4 and substituting
PDMAX for PDMAX' results in Equation 5. This equation gives the maximum ambient temperature that still allows
maximum stereo power dissipation without violating the LM4867's maximum junction temperature.
TA = TJMAX − 2 X PDMAX θJA
(5)
For a typical application with a 5V power supply and an 4Ω load, the maximum ambient temperature that allows
maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 99°C
for the LQ package and 45°C for the MTE package.
TJMAX = PDMAX θJA + TA
(6)
Equation 6 gives the maximum junction temperature TJMAX. If the result violates the LM4867's 150°C, reduce the
maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further
allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases.
If the result of Equation 2 is greater than that of Equation 3, then decrease the supply voltage, increase the load
impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to
reduce θJA. The heat sink can be created using additional copper area around the package, with connections to
the ground pin(s), supply pin and amplifier output pins. External, solder attached SMT heatsinks such as the
Thermalloy 7106D can also improve power dissipation. When adding a heat sink, the θJA is the sum of θJC, θCS
,
and θSA. (θJC is the junction−to−case thermal impedance, θCS is the case−to−sink thermal impedance, and θSA is
the sink−to−ambient thermal impedance.) Refer to the Typical Performance Characteristics curves for power
dissipation information at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitance connected
between the LM4867's supply pins and ground. Do not substitute a ceramic capacitor for the tantalum. Doing so
may cause oscillation. Keep the length of leads and traces that connect capacitors between the LM4867's power
supply pin and ground as short as possible. Connecting a 1µF capacitor, CB, between the BYPASS pin and
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ground improves the internal bias voltage's stability and improves the amplifier's PSRR. The PSRR
improvements increase as the bypass pin capacitor value increases. Too large, however, increases turn−on time
and can compromise the amplifier's click and pop performance. The selection of bypass capacitor values,
especially CB, depends on desired PSRR requirements, click and pop performance (as explained in the section,
Proper Selection of External Components), system cost, and size constraints.
MICRO−POWER SHUTDOWN
The voltage applied to the SHUTDOWN pin controls the LM4867's shutdown function. Activate micro−power
shutdown by applying VDD to the SHUTDOWN pin. When active, the LM4867's micro−power shutdown feature
turns off the amplifier's bias circuitry, reducing the supply current. The logic threshold is typically VDD/2. The low
0.7µA typical shutdown current is achieved by applying a voltage that is as near as VDD as possible to the
SHUTDOWN pin. A voltage that is less than VDD may increase the shutdown current. Table 1 shows the logic
signal levels that activate and deactivate micro−power shutdown and headphone amplifier operation. To ensure
that the output signal remains transient−free, do not cycle the shutdown function faster than 1Hz.
There are a few ways to control the micro−power shutdown. These include using a single−pole, single, throw
switch, a microprocessor, or a microcontroller. When using a switch, connect an external 100kΩ pull−up resistor
between the SHUTDOWN pin and VDD. Connect the switch between the SHUTDOWN pin and ground. Select
normal amplifier operation by closing the switch. Opening the switch connects the SHUTDOWN pin to VDD
through the pull−up resistor, activating micro−power shutdown. The switch and resistor ensure that the
SHUTDOWN pin will not float. This prevents unwanted state changes. In a system with a microprocessor or a
microcontroller, use a digital output to apply the control voltage to the SHUTDOWN pin. Driving the SHUTDOWN
pin with active circuitry eliminates the pull up resistor.
Table 1. Truth Table for Logic Inputs
SHUTDOWN
PIN
HP-IN
PIN
MUX CHANNEL
INPUT SELECT
OPERATIONAL MODE (MUX
INPUTCHANNEL #)
Logic Low
Logic Low
Logic Low
Logic Low
Logic High
= −OUTB signal
= −OUTB signal
≠ −OUTB signal
≠ −OUTB signal
X
Logic Low
Logic High
Logic Low
Logic High
X
Bridged amplifiers (1)
Bridged amplifiers (2)
Single-ended amplifiers (1)
Single-ended amplifiers (2)
Micro−power shutdown
HEADPHONE (SINGLE-ENDED) AMPLIFIER OPERATION
An internal pull−up circuit is connected to the HP−IN (pin 20) headphone amplifier control pin. When this pin is
left unconnected, VDD is applied to the HP−IN. This turns off Amp2B and switches Amp2A's input signal from an
audio signal to the VDD/2 voltage present on pin 14. The result is muted bridge-connected loads. Quiescent
current consumption is reduced when the IC is in this single−ended mode.
Figure 46 shows the implementation of the LM4867's headphone control function. An internal comparator with a
nominal 400mV offset monitors the signal present at the −OUTB output. It compares this signal against the signal
applied to the HP−IN pin. When these signals are equal, as is the case when a BTL is connected to the amplifier,
the comparator forces the LM4867 to maintain bridged−amplifier operation. When the HP−IN pin is externally
floated, such as when headphones are connected to the jack shown in Figure 46, and internal pull−up forces VDD
on the internal comparator's HP−IN inputs. This changes the comparator's output state and enables the
headphone function: it turns off Amp2B, switches Amp2A's input signal from an audio signal to the VDD/2 voltage
present on pin 14, and mutes the bridge-connected loads. Amp1A and Amp1B drive the headphones.
Figure 46 also shows the suggested headphone jack electrical connections. The jack is designed to mate with a
three−wire plug. The plug's tip and ring should each carry one of the two stereo output signals, whereas the
sleeve provides the return to Amp2A. A headphone jack with one control pin contact is sufficient to drive the
HP−IN pin when connecting headphones.
A switch can replace the headphone jack contact pin. When a switch shorts the HP−IN pin to VDD
,
bridge−connected speakers are muted and Amp1A and Amp2A drive a pair of headphones. When a switch
shorts the HP−IN pin to GND, the LM4867 operates in bridge mode. If headphone drive is not needed, short the
HP−IN pin to the −OUTB pin.
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Figure 43 shows an optional resistor connected between the amplifier output that drives the headphone jack
sleeve and ground. This resistor provides a ground path that supressed power supply hum. This hum may occur
in applications such as notebook computers in a shutdown condition and connected to an external powered
speaker. The resistor's 100Ω value is a suggested starting point. Its final value must be determined based on the
tradeoff between the amount of noise suppression that may be needed and minimizing the additional current
drawn by the resistor (25mA for a 100Ω resistor and a 5V supply).
ESD PROTECTION
As stated in the Absolute Maximum Ratings, pin 28 on the MT and MH packages have a maximum ESD
susceptibility rating of 8000V. For higher ESD voltages, the addition of a PCDN042 dual transil (from California
Micro Devices), as shown in Figure 43, will provide additional protection.
Figure 45. The PCDN042 provides additional ESD protection beyond the 8000V shown in the Absolute
Maximum Ratings for the AMP2A output
SINGLE-ENDED OUTPUT POWER PERFORMANCE AND MEASUREMENT CONSIDERATIONS
The LM4867 delivers clean, low distortion SE output power into loads that are greater than 10Ω. As an example,
output power for 16Ω and 32Ω loads are shown in the Typical Performance Characteristic curves. For loads
less than 10Ω, the LM4876 can typically supply 180mW of low distortion power. However, when higher
dissipation is desired in loads less than 10Ω, a dramatic increase in THD+N may occur. This is normal operation
and does not indicate that proper functionality has ceased. When a jump from moderate to excessively high
distortion is seen, simply reducing the output voltage swing will restore the clean, low distortion SE operation.
The dramatic jump in distortion for loads less than 10Ω occurs when current limiting circuitry activates. During SE
operation, AMP2A (refer to Figure 42) drives the headphone sleeve. An on-board circuit monitors this amplifier's
output current. The sudden increase in THD+N is caused by the current limit circuitry forcing AMP2A into a
high−impedance output mode. When this occurs, the output waveform has discontinuities that produce large
amounts of distortion. It has been observed that as the output power is steadily increased, the distortion may
jump from 5% to greater than 35%. Indeed, 10% THD+N may not actually be achievable.
USING THE SINGLE−ENDED OUTPUT FOR LINE LEVEL APPLICATIONS
Some samples of the LM4867 may exhibit small amplitude, high frequency oscillation when the SE output is
connected to a line-level input. This oscillation can be eliminated by connecting a 5%, 300Ω resistor between
Amp2A's output pin and each amplifier, AMP1A and AMP1B, output.
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Figure 46. Headphone Circuit
(Pin numbers in ( ) are for the 20-pin MTE and MT packages.)
INPUT CAPACITOR VALUE SELECTION
Amplifying the lowest audio frequencies requires high value input coupling capacitor (Ci in Figure 42). A high
value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases,
however, the speakers used in portable systems, whether internal or external, have little ability to reproduce
signals below 150Hz. Applications using speakers with this limited frequency response reap little improvement by
using large input capacitor.
Besides effecting system cost and size, Ci has an affect on the LM4867's click and pop performance. When the
supply voltage is first applied, a transient (pop) is created as the charge on the input capacitor changes from zero
to a quiescent state. The magnitude of the pop is directly proportional to the input capacitor's size. Higher value
capacitors need more time to reach a quiescent DC voltage (usually VDD/2) when charged with a fixed current.
The amplifier's output charges the input capacitor through the feedback resistor, Rf. Thus, pops can be
minimized by selecting an input capacitor value that is no higher than necessary to meet the desired −3dB
frequency and is between 0.14CB and 0.20CB.
A shown in Figure 42, the input resistor (RI) and the input capacitor, CI produce a −3dB high pass filter cutoff
frequency that is found using Equation 7.
f−3dB = 1/(2πRINCI)
(7)
As an example when using a speaker with a low frequency limit of 150Hz, Ci, using Equation 4 is 0.063µF. The
1.0µF Ci shown in Figure 42 allows the LM4867 to drive high efficiency, full range speaker whose response
extends below 30Hz.
BYPASS CAPACITOR VALUE SELECTION
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor
connected to the BYPASS pin. Since CB determines how fast the LM4867 settles to quiescent operation, its
value is critical when minimizing turn-on pops. The slower the LM4867's outputs ramp to their quiescent DC
voltage (nominally 1/2 VDD), the smaller the turn-on pop. Choosing CB equal to 1.0µF along with a small value of
Ci (in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above,
choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value
should be in the range of 5 times to 7 times the value of Ci. This ensures that output transients are eliminated
when power is first applied or the LM4867 resumes operation after shutdown.
OPTIMIZING CLICK AND POP REDUCTION PERFORMANCE
The LM4867 contains circuitry that eliminates turn-on and shutdown transients (“clicks and pops“) and transients
that could occur when switching between BTL speakers and single-ended headphones. For this discussion, turn-
on refers to either applying the power supply voltage or when the shutdown mode is deactivated. While the
power supply is ramping to its final value, the LM4867's internal amplifiers are configured as unity gain buffers
and are disconnected from the -OUT and +OUT pins. An internal current source changes the voltage of the
BYPASS pin in a controlled, linear manner. Ideally, the input and outputs track the voltage applied to the
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BYPASS pin. The gain of the internal amplifiers remains unity until the voltage on the bypass pin reaches 1/2
VDD. As soon as the voltage on the bypass pin is stable, the device becomes fully operational and the amplifier
outputs are reconnected to the -OUT and +OUT pins. Although the BYPASS pin current cannot be modified,
changing the size of CB alters the device's turn-on time. There is a linear relationship between the size of CB and
the turn-on time. Here are some typical turn-on times for various values of CB:
CB
TON
0.01µF
0.1µF
3ms
30ms
0.22µF
0.47µF
1.0µF
63ms
134ms
300ms
630ms
2.2µF
In order eliminate “clicks and pops“, all capacitors must be discharged before turn-on. Rapidly switching VDD may
not allow the capacitors to fully discharge, which may cause “clicks and pops“.
NO LOAD STABILITY
The LM4867 may exhibit low level oscillation when the load resistance is greater than 10kΩ. This oscillation only
occurs as the output signal swings near the supply voltages. Prevent this oscillation by connecting a 5kΩ
between the output pins and ground.
AUDIO POWER AMPLIFIER DESIGN
Audio Amplifier Design: Driving 1W into an 8Ω Load
The following are the desired operational parameters:
Power Output:
Load Impedance:
Input Level:
1 WRMS
8Ω
1 VRMS
Input Impedance:
Bandwidth:
20 kΩ
100 Hz−20 kHz ± 0.25 dB
The design begins by specifying the minimum supply voltage necessary to obtain the specified output power.
One way to find the minimum supply voltage is to use the Output Power vs Supply Voltage curve in the Typical
Performance Characteristics section. Another way, using Equation 8, is to calculate the peak output voltage
necessary to achieve the desired output power for a given load impedance. To account for the amplifier's dropout
voltage, two additional voltages, based on the Dropout Voltage vs Supply Voltage in the Typical Performance
Characteristics curves, must be added to the result obtained by Equation 8. The result is Equation 9.
(8)
V
DD ≥ (VOUTPEAK+ (VOD + VODBOT))
(9)
TOP
The Output Power vs Supply Voltage graph for an 8Ω load indicates a minimum supply voltage of 4.6V. This is
easily met by the commonly used 5V supply voltage. The additional voltage creates the benefit of headroom,
allowing the LM4867 to produce peak output power in excess of 1W without clipping or other audible distortion.
The choice of supply voltage must also not create a situation that violates of maximum power dissipation as
explained above in the POWER DISSIPATION section.
After satisfying the LM4867's power dissipation requirements, the minimum differential gain needed to achieve
1W dissipation in an 8Ω load is found using Equation 10.
(10)
Thus, a minimum gain of 2.83 allows the LM4867's to reach full output swing and maintain low noise and THD+N
performance. For this example, let AVD = 3.
The amplifier's overall gain is set using the input (Ri) and feedback (Ri) resistors. With the desired input
impedance set at 20kΩ, the feedback resistor is found using Equation 11.
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Rf/Ri = AVD/2
(11)
The value of Rf is 30kΩ.
The last step in this design example is setting the amplifier's −3dB frequency bandwidth. To achieve the desired
±0.25dB pass band magnitude variation limit, the low frequency response must extend to at least one-fifth the
lower bandwidth limit and the high frequency response must extend to at least five times the upper bandwidth
limit. The gain variation for both response limits is 0.17dB, well within the ±0.25dB desired limit. The results are
an
fL = 100Hz/5 = 20Hz
(12)
and an
fH = 20kHz x 5 = 100kHz
(13)
As mentioned in the Selecting Proper External Components section, Ri and Ci create a highpass filter that
sets the amplifier's lower bandpass frequency limit. Find the coupling capacitor's value using Equation 12.
Ci≥ 1/(2πR ifL)
(14)
(15)
The result is
1/(2π*20kΩ*20Hz) = 0.397μF
Use a 0.39μF capacitor, the closest standard value.
The product of the desired high frequency cutoff (100kHz in this example) and the differential gain AVD
,
determines the upper passband response limit. With AVD = 3 and fH = 100kHz, the closed-loop gain bandwidth
product (GBWP) is 300kHz. This is less than the LM4867's 3.5MHz GBWP. With this margin, the amplifier can
be used in designs that require more differential gain while avoiding performance,restricting bandwidth
limitations.
RECOMMENDED PRINTED CIRCUIT BOARD LAYOUT
Figure 47 through Figure 51 show the recommended four-layer PC board layout that is optimized for the 24-pin
LQ-packaged LM4867 and associated external components. Figure 52 through Figure 56 show the
recommended four-layer PC board layout that is optimized for the 24-pin MTE-packaged LM4867 and associated
external components. Figure 57 through Figure 59 show the recommended two-layer PC board layout that is
optimized for the 20-pin MT-packaged LM4867 and associated external components. These circuits are designed
for use with an external 5V supply and 4Ω speakers.
These circuit boards are easy to use. Apply 5V and ground to the board's VDD and GND pads, respectively.
Connect 4Ω speakers between the board's −OUTA and +OUTA and OUTB and +OUTB pads.
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Figure 47. Recommended LQ PC Board Layout:
Component-Side Silkscreen
Figure 48. Recommended LQ PC Board Layout:
Component-Side Layout
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Figure 49. Recommended LQ PC Board Layout:
Upper Inner-Layer Layout
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Figure 50. Recommended LQ PC Board Layout:
Lower Inner-Layer Layout
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Figure 51. Recommended LQ PC Board Layout:
Bottom-Side Layout
Figure 52. Recommended MTE PC Board Layout:
Component-Side Silkscreen
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Figure 53. Recommended MTE PC Board Layout:
Component-Side Layout
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Figure 54. Recommended MTE PC Board Layout:
Upper Inner-Layer Layout
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Figure 55. Recommended MTE PC Board Layout:
Lower Inner-Layer Layout
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LM4867
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Figure 56. Recommended MTE PC Board Layout:
Bottom-Side Layout
Figure 57. Recommended MT PC Board Layout:
Component-Side Silkscreen
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Figure 58. Recommended MT PC Board Layout:
Component-Side Layout
34
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LM4867
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Figure 59. Recommended MT PC Board Layout:
Bottom-Side Layout
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