LM48903TLE/NOPB [TI]
AUDIO AMPLIFIER;型号: | LM48903TLE/NOPB |
厂家: | TEXAS INSTRUMENTS |
描述: | AUDIO AMPLIFIER |
文件: | 总59页 (文件大小:887K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
April 12, 2012
LM48903
Stereo Class D Spatial Array
General Description
Features
The LM48903 is a stereo Class D amplifier that utilizes TI’s
proprietary spatial sound processor to create an enhanced
sound stage for portable multimedia devices. The Class D
output stages feature National’s edge rate control (ERC)
PWM architecture that significantly reduces RF emissions
while preserving audio quality and efficiency.
The LM48903’s flexible I2S interface is compatible with stan-
dard serial audio interfaces. A stereo differential-input ADC
gives the device the ability to process analog stereo audio
signals.
The LM48903 is configured through an I2C compatible inter-
face and is capable of delivering 1.7W/channel of continuous
output power into an 8Ω load with less than 10% THD+N.
Output short circuit and thermal overload protection prevent
the device from being damaged during fault conditions. Click
and pop suppression eliminates audible transients on power-
up/down and during shutdown. The LM48903 is available in
space saving micro SMD package.
Spatial Sound Processing
■
■
I2S Input
Stereo, Analog, Differential-Input ADC
■
■
■
■
■
■
■
Edge Rate Control
Short Circuit and Thermal Overload Protection
Minimum external components
Click and Pop suppression
Micro-power shutdown
Available in space-saving micro SMD package
Applications
Smart Phones
■
■
■
■
Portable Gaming
Tablets
Multimedia Devices
MP3 Player Accessories
■
Key Specifications
■ꢀSNR (A-Weighted)
■ꢀOutput Power/channel, PVDD = 5V
RL = 8Ω, THD+N ≤ 1%
■ꢀTHD+N
■ꢀEfficiency/Channel
■ꢀPSRR at 217Hz
90dBA (typ)
1.3W (typ)
0.08% (typ)
91% (typ)
69dB (typ)
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2012 Texas Instruments Incorporated
301858 SNAS587
www.ti.com
Typical Application
301858f7
FIGURE 1. Typical Audio Amplifier Application Circuit
www.ti.com
2
Connection Diagrams
micro SMD Package
30–Bump micro SMD Marking
30185844
Top View
XY = Date code
TT = Die traceability
G = Boomer Family
K6 = LM48903TL
30185843
Top View
Order NumberLM48903TL
See NS Package Number TLA30HHA
Ordering Information
Ordering Information Table
Package
MSL
Level
Order Number
Package
Drawing
Number
Transport Media
Green Status
250 and 2500 units
on tape and reel
LM48903TL
micro SMD
TLA30HHA
1
RoHS & no Sb/Br
3
www.ti.com
TABLE 1. Bump Description
BUMP
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
F1
NAME
DGND
MCLK
IOVDD
DESCRIPTION
Digital Ground
Master Clock
Digital Interface Power Supply
I2C Serial Data Input
I2C Clock Input
SDA
SCL
DVDD
Digital Power Supply
SHDN
SDIO
Active Low Shutdown. Connect to VDD for normal operation.
I2S Serial Data Input/Output
I2S Word Select Input
WS
SCLK
PLLVDD
GAIN0
GAIN1
MODE0
MODE1
AVDD2
AGND2
AGND1
OUT1-
OUT1+
INL-
Serial Clock Input
PLL Power Supply
Gain Setting Input 0
Gain Setting Input 1
Spatial Mode Control Input 0
Spatial Mode Control Input 1
ADC Analog Power Supply
ADC Analog Ground
Modulator Analog Ground
Channel 1 Inverting Output. Connect to OUT2- in Parallel Mode
Channel 1 Non-Inverting Output. Connect to OUT2+ in Parallel Mode
Left Channel Inverting Analog Input
Left Channel Non-Inverting Analog Input
Modulator Analog Power Supply
Power Ground
INL+
AVDD1
PGND
PVDD
Class D Power Supply
INR-
Right Channel Inverting Analog Input
Right Channel Non-Inverting Analog Input
ADC Reference Bypass
F2
INR+
F3
REF
F4
OUT2-
OUT2+
Channel 2 Inverting Output. Connect to OUT1- in Parallel Mode.
Channel 2 Non-Inverting Output. Connect to OUT1+ in Parallel Mode.
F5
www.ti.com
4
Thermal Resistance
Absolute Maximum Ratings (Note 1, Note
2)
ꢁθJA (TLA30)
54°C/W
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Operating Ratings
Temperature Range
TMIN ≤ TA ≤ TMAX
Supply Voltage
AVDD
−40°C ≤ TA ≤ +85°C
Supply Voltage
AVDD, PVDD, PLVDD, IOVDD (Note 1)
Supply Voltage, DVDD (Note 1)
Storage Temperature
6V
2.2V
2.7V ≤ AVDD ≤ 5.5V
2.7V ≤ PVDD ≤ 5.5V
2.7V ≤ PLLVDD ≤ 5.5V
1.62V ≤ IOVDD ≤ 5.5V
1.62V ≤DVDD ≤1.98V
PVDD
−65°C to + 150°C
−0.3V to VDD + 0.3V
Internally limited
2000V
Input Voltage
PLLVDD
IOVDD
DVDD
Power Dissipation (Note 3)
ESD Susceptibility (Note 4)
ESD Susceptibility (Note 5)
Junction Temperature
150V
150°C
Electrical Characteristics PVDD = AVDD , IOVDD = PLLVDD = 3.6V, DVDD = 1.8
(Note 2, Note 8)
The following specifications apply for AV = 0dB, CREF = 4.7µF, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply for TA
= 25°C.
LM48903
Units
Symbol
AVDD
Parameter
Conditions
Min
(Note 8)
Typ
Max
(Limits)
(Note 7)
(Note 8)
Analog Supply Voltage Range
Amplifier Supply Voltage Range
PLL Supply Voltage Range
2.7
2.7
5.5
5.5
5.5
5.5
1.98
19
V
V
PVDD
PLLVDD
IOVDD
DVDD
AIDD
2.7
V
Interface Supply Voltage Range
Digital Supply Voltage Range
Analog Quiescent Supply Current
1.62
1.62
V
V
15.2
2.6
mA
Amplifier Quiescent Supply
Current
PIDD
RL = 8Ω
mA
mA
mA
PLLIDD
DIDD
PLL Quiescent Supply Current
1.3
5.4
Quiescent Digital Power Supply
Current
5.8
3.5
Shutdown Current (Analog,
Amplifier and PLL Supplies)
ISD
Shutdown Enabled
Shutdown Enabled
0.4
μA
DISTBY
DISD
VOS
Digital Standby Current
Digital Shutdown Current
30
6.6
μA
μA
10
Differential Output Offset Voltage VIN = 0
–7.5
0.8
7.5
mV
ms
ms
kHz
Power Up (Device Initialization)
150
28.5
384
TWU
fSW
Wake-up Time
From Shutdown
fS = 48kHz
Switching Frequency
5
www.ti.com
LM48903
Units
(Limits)
Symbol
Parameter
Conditions
Min
Typ
(Note 7)
Max
(Note 8)
(Note 8)
RL = 4Ω, THD+N = 10%
f = 1kHz, 22kHz BW
VDD = 5V
2.8
1.4
W
W
VDD = 3.6V
RL = 4Ω, THD+N = 1%
f = 1kHz, 22kHz BW
VDD = 5V
2.2
1.2
W
W
VDD = 3.6V
PO
Output Power/Channel
RL = 8Ω, THD+N = 10%
f = 1kHz, 22kHz BW
VDD = 5V
1.7
W
VDD = 3.6V
860
mW
RL = 8Ω, THD+N = 1%
f = 1kHz, 22kHz BW
VDD = 5V
1.3
W
VDD = 3.6V
500
650
mW
RL = 4Ω, THD+N = 10%, f = 1kHz, 22kHz BW
VDD = 5V
3.3
1.7
W
W
VDD = 3.6V
PO
Output Power (Parallel Mode)
RL = 4Ω, THD+N = 1%, f = 1kHz, 22kHz BW
VDD = 5V
2.5
1.2
W
W
VDD = 3.6V
Total Harmonic Distortion +
Noise
THD+N
PSRR
PO = 350mW, f = 1kHz, RL = 8Ω
0.08
%
VRIPPLE = 200mVP-P sine, Inputs AC GND, CIN = 1μF
fRIPPLE = 217Hz, Applied to PVDD
fRIPPLE = 217Hz, Applied to DVDD
fRIPPLE = 1kHz, Applied to PVDD
fRIPPLE = 1kHz, Applied to DVDD
fRIPPLE = 10kHz, Applied to PVDD
fRIPPLE = 10kHz, Applied to DVDD
69
64
68
62
62
52
dB
dB
dB
dB
dB
dB
Power Supply Rejection Ratio
(ADC Path)
60
56
VRIPPLE = 200mVP-P sine, Inputs –∞dBFS
fRIPPLE = 217Hz, Applied to PVDD
fRIPPLE = 217Hz, Applied to DVDD
68
72
67
69
58
56
dB
dB
dB
dB
dB
dB
Power Supply Rejection Ratio
(I2S Path)
PSRR
fRIPPLE = 1kHz, Applied to PVDD
fRIPPLE = 1kHz, Applied to DVDD
fRIPPLE = 10kHz, Applied to PVDD
fRIPPLE = 10kHz, Applied to DVDD
60
55
VRIPPLE = 1VP-P, fRIPPLE = 217Hz,
AV = 0dB
CMRR
Common Mode Rejection Ratio
Efficiency/Channel
Efficiency
78
dB
VDD = 5V, PO = 1.1W
VDD = 3.6V, PO = 400mW
VDD = 5V, PO = 1.1W
VDD = 3.6V, PO = 400mW
ADC Input, PO = 1W
I2S Input, PO = 1W
91
90
86
83
89
90
%
%
η
%
η
%
dB
dB
SNR
Signal-to-NoiseRatio
www.ti.com
6
LM48903
Units
(Limits)
Symbol
Parameter
Conditions
Min
Typ
(Note 7)
Max
(Note 8)
(Note 8)
Inputs AC GND, A-weighted,
AV = 0dB
130
μV
εOS
XTALK
Output Noise
I2S Input
72
72
μV
Crosstalk
dB
I2C Interface Characteristics (Note 1, Note 2)
The following specifications apply for RPU = 1kΩ to IOVDD, unless otherwise specified. Limits apply for TA = 25°C.
LM48903
Symbol
Parameter
Conditions
Units
Min
Typ
Max
(Note 7)
(Note 6)
(Note 7)
VIH
VIL
0.7*IOVDD
Logic Input High Threshold
Logic Input Low Threshold
Logic Output Low Threshold
Logic Output High Current
SCL Frequency
SDA, SCL
SDA, SCL
V
mV
V
0.3
0.35
2
VOL
IOH
SDA, ISDA = 3.6mA
SDA, SCL
μA
kHz
400
Hold Time
(repeated START Condition)
1
0.6
µs
2
3
Clock Low Time
Clock High Time
1.3
µs
ns
600
Setup Time for Repeated
START condition
4
600
ns
5
6
7
8
9
Data Hold Time
Output
300
100
900
ns
ns
ns
ns
ns
Data Setup Time
SDA Rise Time
300
300
SDA Fall Time
Setup Time for STOP Condition
600
1.3
Bus Free Time Between STOP
and START Condition
10
µs
I2S Timing Characteristics (Note 2, Note 8)
The following specifications apply for DVDD = 1.8V, unless otherwise specified. Limits apply for TA = 25°C.
LM48903
Units
(Limits)
Symbol
Parameter
Conditions
Min
Typ
(Note 6)
Max
(Note 7)
(Note 7)
tMCLKL
tMCLKH
tMCLKY
tBCLKR
tBCLKCF
tBCLKDS
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Period
16
16
27
ns
ns
ns
ns
ns
%
SCLK rise time
3
3
SCLK fall time
SCLK Duty Cycle
50
LRC Propagation Delay from
SCLK falling edge
TDL
TDST
TDHT
10
ns
ns
ns
DATA Setup Time to SCLK
Rising Edge
10
10
DATA Hold Time from SCLK
Rising Edge
7
www.ti.com
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX − TA) / θJA or the given in Absolute Maximum Ratings, whichever is lower.
Note 4: Human body model, applicable std. JESD22-A114C.
Note 5: Machine model, applicable std. JESD22-A115-A.
Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 7: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 8: RL is a resistive load in series with two inductors to simulate an actual speaker load. For RL = 8Ω, the load is 15μH+8Ω+15μH. For RL = 4Ω, the load is
15μH+4Ω+15μH.
www.ti.com
8
Typical Performance Characteristics
THD+N vs FREQUENCY
VDD = 3.6V, POUT = 400mW, RL = 8Ω
Stereo Mode, I2S Input
THD+N vs FREQUENCY
VDD = 3.6V, POUT = 500mW, RL = 4Ω
Stereo Mode, I2S Input
301858e6
301858e4
THD+N vs FREQUENCY
VDD = 3.6V, POUT = 250mW, RL = 4Ω
Stereo Mode, ADC Input
THD+N vs FREQUENCY
VDD = 3.6V, POUT = 200mW, RL = 8Ω
Stereo Mode, ADC Input
301858e0
301858d9
THD+N vs FREQUENCY
VDD = 5V, POUT = 1.2W, RL = 4Ω
Stereo Mode, I2S Input
THD+N vs FREQUENCY
VDD = 5V, POUT = 800mW, RL = 8Ω
Stereo Mode, I2S Input
301858e5
301858e7
9
www.ti.com
THD+N vs FREQUENCY
VDD = 5V, POUT = 550mW, RL = 4 Ω
Stereo Mode, ADC Input
THD+N vs FREQUENCY
VDD = 5V, POUT = 350mW, RL = 8Ω
Stereo Mode, ADC Input
30185857
301858e1
THD+N vs FREQUENCY
VDD = 3.6V, POUT = 800mW, RL = 4Ω
Parallel Mode, I2S Input
THD+N vs FREQUENCY
VDD = 3.6V, POUT = 350mW, RL = 4Ω
Parallel Mode, ADC Input
301858e2
301858e8
THD+N vs FREQUENCY
VDD = 5V, POUT = 800mW, RL = 4Ω
Parallel Mode, I2S Input
THD+N vs FREQUENCY
VDD = 5V, POUT = 1.7W, RL = 4Ω
Parallel Mode, I2S Input
301858e9
301858e3
www.ti.com
10
THD+N vs OUTPUT POWER
RL = 4Ω, f = 1kHz, Stereo Mode, I2S Input
THD+N vs OUTPUT POWER
RL = 8Ω, f = 1kHz, Stereo Mode, I2S Input
301858d6
301858d5
THD+N vs OUTPUT POWER
RL = 4Ω, f = 1kHz, Parallel Mode, I2S Input
THD+N vs OUTPUT POWER
RL = 4Ω, f = 1kHz, Stereo Mode, ADC Input
301858d7
301858d3
THD+N vs OUTPUT POWER
RL = 8Ω, f = 1kHz, Stereo Mode, ADC Input
THD+N vs OUTPUT POWER
RL = 4Ω, f = 1kHz, Parallel Mode, ADC Input
301858d2
301858d4
11
www.ti.com
EFFICIENCY vs OUTPUT POWER
RL = 4Ω, f = 1kHz, Stereo Mode, ADC Input
EFFICIENCY vs OUTPUT POWER
RL = 8Ω, f = 1kHz, Stereo Mode, ADC Input
301858f0
301858f1
POWER DISSIPATION vs OUTPUT POWER
RL = 4Ω, Per Channel, Stereo Mode, ADC Input
POWER DISSIPATION vs OUTPUT POWER
RL = 8Ω, Per Channel, Stereo Mode, ADC Input
301858f3
301858f2
OUTPUT POWER vs SUPPLY VOLTAGE
OUTPUT POWER vs SUPPLY VOLTAGE
RL = 4Ω, Stereo Mode, ADC Input
RL = 4Ω, Stereo Mode, ADC Input
301858f5
301858f4
www.ti.com
12
OUTPUT POWER vs SUPPLY VOLTAGE
PSRR vs FREQUENCY
PVDD = 5V, VRIPPLE = 200mVP-P, RL = 8Ω,
ADC Input = AC GND
RL = 8Ω, Stereo Mode, ADC Input
301858f6
301858c1
PSRR vs FREQUENCY
DVDD = 1.8V, VRIPPLE = 200mVP-P, RL = 8Ω,
ADC Input = AC GND
PSRR vs FREQUENCY
PVDD = 5V, VRIPPLE = 200mVP-P, RL = 8Ω,
I2S input = –120dBFS
301858c2
301858c3
PSRR vs FREQUENCY
DVDD = 1.8V, VRIPPLE = 200mVP-P, RL = 8Ω,
I2S input = –120dBFS
CMRR vs FREQUENCY
VRIPPLE = 200mVP-P, RL = 8Ω,
301858c5
301858c4
13
www.ti.com
SUPPLY CURRENT vs SUPPLY VOLTAGE
ADC Mode
ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE
ADC Mode
301858c6
301858c7
PLL SUPPLY CURRENT vs SUPPLY VOLTAGE
DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGE
30185859
30185858
SHUTDOWN CURRENT vs SUPPLY VOLTAGE
DIGITAL SHUTDOWN CURRENT vs SUPPLY VOLTAGE
301858d0
301858d1
www.ti.com
14
as the I2C master, generating the SCL signal. Each transmis-
sion sequence is framed by a START condition and a STOP
condition Figure 3.
Application Information
I2C COMPATIBLE INTERFACE
Due to the number of data registers, the LM48903 employs a
page mode scheme. Each data write consists of 7, 8 bit data
bytes, device address (1 byte), 16 bit register address (2
bytes), and 32 bit register data (4 bytes). Each byte is followed
by an acknowledge pulse Figure 4. Single byte read and write
commands are ignored. The LM48903 device address is
0110000X.
The LM48903 is controlled through an I2C compatible serial
interface that consists of a serial data line (SDA) and a serial
clock (SCL). The clock and data lines are bi-directional (open
drain). The LM48903 communicates at clock rates up to
400kHz. Figure 2 shows the I2C interface timing diagram. Da-
ta on the SDA line must be stable during the HIGH period of
SCL. The LM48903 is a transmit/receive device, and can act
30185840
FIGURE 2. I2C Timing Diagram
30185841
FIGURE 3. Start and Stop Diagram
15
www.ti.com
WRITE SEQUENCE
Once the master device registers the ACK bit, the first 8-bit
register address word is sent, MSB first [15:8]. Each data bit
should be stable while SCL is HIGH. After the first 8-bit reg-
ister address is sent, the LM48903 sends another ACK bit.
Upon receipt of acknowledge, the second 8-bit register ad-
dress word is sent [7:0], followed by another ACK bit. The
register data is sent, 8-bits at a time, MSB first in the following
order [7:0], [15:8], [23:16], [31.24]. Each 8-bit word is followed
by an ACK, upon receipt of which the successive 8-bit word
is sent. Following the acknowledgement of the last register
data word [31:24], the master issues a STOP bit, allowing
SDA to go high while SDA is high.
The example write sequence is shown in Figure 4. The
START signal, the transition of SDA from HIGH to LOW while
SDA is HIGH, is generated, altering all devices on the bus that
a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant
bit (MSB) first, followed by the R/W bit (R/W = 0 indicating the
master is writing to the LM48903). The data is latched in on
the rising edge of the clock. Each address bit must be stable
while SDA is HIGH. After the R/W\ bit is transmitted, the mas-
ter device releases SDA, during which time, an acknowledge
clock pulse is generated by the slave device. If the LM48903
receives the correct address, the device pulls the SDA line
low, generating and acknowledge bit (ACK).
301858g0
FIGURE 4. Example I2C Write Sequence
READ SEQUENCE
LM48903. Upon receipt of the acknowledge, the second 8-bit
register address word is sent [7:0], followed by another ACK
bit. Following the acknowledgment of the last register ad-
dress, the master initiates a REPEATED START, followed by
the 7-bit device address, followed by R/W = 1 (R/W = 1 indi-
cating the master wants to read data from the LM48903). The
LM48903 sends an ACK, followed by the selected register
data. The register data is sent, 8-bits at a time, MSB first in
the following order [7:0], [15:8], [23:16], [31:24]. Each 8-bit
word is followed by an ACK, upon receipt of which the suc-
cessive 8-bit word is sent. Following the acknowledgement of
the last register data word [7:0], the master issues a STOP
bit, allowing SDA to go high while SDA is high.
The example read sequence is shown in Figure 5. The
START signal, the transition of SDA from HIGH to LOW while
SDA is HIGH, is generated, altering all devices on the bus that
a device address is being written to the bus.
The 7-bit device address is written to the bus, followed by the
R/W = 0. After the R/W bit is transmitted, the master device
releases SDA, during which time, an acknowledge clock
pulse is generated by the slave device. If the LM48903 re-
ceives the correct address, the device pulls the SDA line low,
generating and acknowledge bit (ACK). Once the master de-
vice registers the ACK bit, the first 8-bit register address word
is sent, MSB first [15:8], followed by and ACK from the
301858g1
FIGURE 5. Example I2C Read Sequence
www.ti.com
16
I2S DATA FORMAT
Mode, the audio data format is similar to the Normal Mode,
without the delay between the LSB and the change in
I2S_WS. In Right Justified Mode, the audio data MSB is trans-
mitted after a delay of a preset number of bits.
The LM48903 supports three I2S formats: Normal Mode Fig-
ure 6, Left Justified Mode Figure 7, and Right Justified Mode
Figure 8. In Normal Mode, the audio data is transmitted MSB
first, with the unused bits following the LSB. In Left Justified
301858b4
FIGURE 6. I2S Normal Input Format
301858b5
FIGURE 7. I2S Left Justified Input Format
301858b6
FIGURE 8. I2S Right Justified Input Format
17
www.ti.com
MEMORY ORGANIZATION
configuration settings, and a 48-bit wide Audio Sample Space
that holds the current audio data sampled from either the AD-
Cs or the I2S interface, organized as shown in Figure 9.
The LM48903 memory is organized into three main regions:
a 32-bit wide Coefficient Space that holds the spatial coeffi-
cients, a 32-bit wide Register Space that holds the device
301858g4
FIGURE 9. LM48903 Memory Organization
COEFFICIENT MEMORY
Register 1 (0x504h) = 1 to enable Debug mode. The Coeffi-
cient Memory Space is organized as follows.
The device must be in Debug mode in order to write to the
Coefficient memory. Set Bit 7 (DBG_ENABLE) in Filter Debug
TABLE 2. Coefficient Memory Space
REGISTER ADDRESS
(31:16)
REGISTER CONTENTS
(15:0)
256x16 bit Array Taps
0x000h - 0x0FFh
256x16 bit Array Taps
(Left Input to OUT2)
(Right Input to OUT2)
256x16 bit Array Taps
0x100h - 0x1FFh
256x16 bit Array Taps
(Left Input to OUT1)
(Right Input to OUT1)
C2 128x16 bit Prefilter Taps
0x400h - 0x47Eh (EVEN)
C0 128x16 bit Prefilter FIR Taps
(Left to Left)
(Right to Right)
C3 128x16 bit Prefilter Taps
0x441h - 0x47Fh (ODD)
C1 128x16 bit Prefilter FIR Taps
(Left to Right)
(Right to Left)
www.ti.com
18
CONTROL REGISTERS
TABLE 3. Register Map
Register Register
Default
Value
7
6
5
4
3
2
1
0
Name
Address
0x500h
[7:0]
0xFFh
ARRAY_TAP
0x500h
[15:8]
0x7Fh
0xE4h
0xC1h
0x98h
0x11h
0x00h
0x00h
0XB8h
0x11h
0XB8h
0x11h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x80h
0x00h
0x80h
UNUSED
ARRAY_
PRE_TAP
CH2_SEL
FILTER
CONTRO
L
0x500h
[23:16]
UNUSED
CH1_SEL
PRE_
ARRAY_
BYPASS
PRE_
0x500h
[31:24]
UNUSED
ENABLE ENABLE
BYPASS
0x501h
[7:0]
G1_GAIN
COMP_TH
0x501h
[15:8]
UNUSED
POST_GAIN
UNUSED
COMP_RATIO
FILTER
COMP1
0x501h
[23:16]
ARRAY_COMP_SELECT
UNUSED
0x501h
[31:24]
0x502h
[7:0]
G1_GAIN
UNUSED
COMP_TH
COMP_TH
0x502h
[15:8]
POST_GAIN
UNUSED
UNUSED
COMP_RATIO
COMP_RATIO
FILTER
COMP2
0x502h
[23:16]
G1_GAIN
0x502h
[31:24]
UNUSED
POST_GAIN
0x503h
[7:0]
DBG_DATA [7:0]
0x503h
[15:8]
DBG_DATA [15:8]
DBG_DATA [23:16]
UNUSED
FILTER
DEBUG0
0x503h
[23:16]
0x503h
[31:24]
DBG_
STEP_
FILTER_
SELECT
0x504h
[7:0]
UNUSED
ACC_ADDR
ENABLE ENABLE
0x504h
[15:8]
UNUSED
UNUSED
UNUSED
FILTER
DEBUG1
0x504h
[23:16]
0x504h
[31:24]
0x505h
[7:0]
PCOUNT1_MODE
UNUSED
PCH_SEL
PCOUNT2_MODE
ACH_SEL
0x505h
[15:8]
PCLEAR
ACLEAR
FILTER
STATS
0x505h
[23:16]
ACOUNT1_MODE
UNUSED
0x505h
[31:24]
ACOUNT2_MODE
19
www.ti.com
Register Register
Default
Value
7
6
5
4
3
2
1
0
Name
Address
0x506h
[7:0]
0x00h
0x00h
0x00h
0x00h
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
DBG_DATA [7:0]
DBG_DATA [15:8]
DBG_DATA [23:16]
DBG_DATA [31:24]
DBG_ACCL [7:0]
DBG_ACCL [15:8]
DBG_ACCL [23:16]
DBG_ACCL [31:24]
DBG_ACC [39:32]
DBG_ACC [47:40]
UNUSED
0x506h
[15:8]
FILTER
DEBUG1
0x506h
[23:16]
0x506h
[31:24]
0x509h
[7:0]
0x509h
[15:8]
ACCUML
DEBUG
(READ-
ONLY)
0x509h
[23:16]
0x509h
[31:24]
0x50Ah
[7:0]
0x50Ah
[15:8]
ACCUMH
DEBUG
(READ-
ONLY)
0x50Ah
[23:16]
0x50Ah
[31:24]
UNUSED
0x50Bh
[7:0]
DBG_SAT [7:0]
DBG_SAT [15:8]
DBG_SAT [23:16]
UNUSED
0x50Bh
[15:8]
DBG
SAT
(READ-
ONLY)
0x50Bh
[23:16]
0x50Bh
[31:24]
0x50Ch
[7:0]
COUNT [7:0]
0x50Ch
[15:8]
STAT
PCNT1
(READ-
ONLY)
COUNT [15:8]
0x50Ch
[23:16]
COUNT [23:16]
COUNT [31:24]
COUNT [7:0]
0x50Ch
[31:24]
0x50Dh
[7:0]
0x50Dh
[15:8]
STAT
PCNT2
(READ-
ONLY)
COUNT [15:8]
0x50Dh
[23:16]
COUNT [23:16]
COUNT [31:24]
0x50Dh
[31:24]
www.ti.com
20
Register Register
Default
Value
7
6
5
4
3
2
1
0
Name
Address
0x50Eh
[7:0]
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0xXXh
0X00h
0X00h
0X00h
0X00h
COUNT [7:0]
0x50Eh
[15:8]
STAT
ACNT1
(READ-
ONLY)
COUNT [15:8]
COUNT [23:16]
COUNT [31:24]
COUNT [7:0]
0x50Eh
[23:16]
0x50Eh
[31:24]
0x50Fh
[7:0]
0x50Fh
[15:8]
STAT
ACNT2
(READ-
ONLY)
COUNT [15:8]
0x50Fh
[23:16]
COUNT [23:16]
COUNT [31:24]
ADCR_VOS [7:0]
ADCR_VOS [15:8]
ADCL_VOS [7:0]
ADCL_VOS [15:8]
0x50Fh
[31:24]
0x510h
[7:0]
0x510h
[15:8]
ADC
OFFSET
0x510h
[23:16]
0x510h
[31:24]
0x511h
[7:0]
0X00h
0X00h
0X00h
OUT1_VOS [7:0]
OUT1_VOS [15:8]
OUT2_VOS [7:0]
0x511h
[15:8]
CLASS D
OFFSET
0x511h
[23:16]
0x511h
[31:24]
0X00h
0x06h
OUT2_VOS [15:8]
0x520h
[7:0]
POWER_UP_DELAY [7:0]
0x520h
[15:8]
0x00h
0x20h
0x09h
POWER_UP_DELAY [15:8]
DEGLITCH_DELAY
STATE_DELAY
DELAY
0x520h
[23:16]
0x520h
[31:24]
PWM_DC
_CORREC
T
VREF_
DELAY
0x521h
[7:0]
ADC_SYN ADC_DC_ ADC_DC_
0x00h
0x20h
PULSE
FORCE ENABLE
MCLK_RATE
C_SEL CORRECT
CAL
QSA_
PCM_
0x521h
[15:8]
QSA_MBI
CLK_STO
ST
ENABLE
&
HIFI
I2S_CLK
CLK_SEL
P
CLOCKS
0x521h
[23:16]
ADC_HPF ADC_HPF
_TO_1_4 _ENABLE
0x00h
0x00h
UNUSED
ADC_HPF_MODE
0x521h
[31:24]
UNUSED
OFFSET_READBACK_SELECT
21
www.ti.com
Register Register
Default
Value
7
6
5
4
3
2
1
0
Name
Address
ZERO_
CROSS
0x522h
[7:0]
0x33h
0x33h
0x02h
0x05h
0x00h
0x10h
0x00h
0x00h
MUTE
ADC_LVL
I2S_LVL
0x522h
[15:8]
UNUSED
DIGITAL
MIXER
0x522h
[23:16]
ADC_DS
P
UNUSED
UNUSED
I2SA_TX_SEL
OUT2_SEL
I2S_DSP
0x522h
[31:24]
OUT1_SEL
ANA_LVL
0x523h
[7:0]
BYPASS_
MOD
ZERO_DI ZERO_AN PARALL
AUTO_SD ADCTRIM
SCAN_TRI
G
A
EL
PMC_
TEST
0x523h
[15:8]
SCKT_DI
UNUSED
SE_MOD
TSD_DIS
TST_SHT
G
S
ANALOG
0x523h
[23:16]
UNUSED
UNUSED
0x523h
[31:24]
I2C_ANA
_LEVEL
STEREO_
SYNC_
SYNC_
MODE
CLOCK_
PHASE
TX_
RX_
0x524h
[7:0]
0x01h
SYNC_MS CLK_MS
STEREO
PHASE
ENABLE ENABLE
HALF_CYCLE_DIVIDER
0x524h
[15:8]
0x00h
0x00h
0x00h
0x00h
UNUSED
SYNTH_
DENOM
0x524h
[23:14]
UNUSED
SYNTH_NUM
SYNC_RATE
RX_WIDTH
0x524h
[31:24]
UNUSED
TX_BIT
MONO_SYNC_WIDTH
TX_WIDTH
I2S PORT
0x525h
[7:0]
RX_
A/µLAW
TX_
RX_
0x525h
[15:8]
RX_MOD
E
0x02h
RX_MSB_POSITION
COMPAN
D
TX_
COMPAN
D
0x525h
[23:16]
TX_MOD
E
0x02h
0x00h
0x00h
TX_MSB_POSITION
UNUSED
A/µLAW
0x525h
[31:24]
0x526h
[7:0]
ADC_COMP_COEFF_C0 [7:0]
0x526h
[15:8]
0x00h
0x00h
ADC_COMP_COEFF_C0 [15:8]
ADC_COMP_COEFF_C1 [7:0]
0x526h
[23:14]
0x526h
[31:24]
ADC
TRIM
CO-EF
FICIENT
0x00h
0x00h
0x00h
0x00h
0x00h
ADC_COMP_COEFF_C1 [15:8]
ADC_COMP_COEFF_C2 [7:0]
ADC_COMP_COEFF_C2 [15:8]
UNUSED
0x527h
[7:0]
0x527h
[15:8]
0x527h
[23:16]
0x527h
[31:24]
UNUSED
www.ti.com
22
Register Register
Default
Value
7
6
5
4
3
2
1
0
Name
Address
ADCR_L
VL
I2SL_LVL I2SR_LVL ADCL_LVL
ADCL_
CLIP
ADCR_
CLIP
0x528h
[7:0]
0x00h
UNUSED
CLIP
CLIP
CLIP
CLIP
READ
BACK0
(READ-
ONLY)
0x528h
[15:8]
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x30h
UNUSED
THERMAL
SHORT2 SHORT1
0x528h
[23:14]
SPARE
UNUSED
0x528h
[31:24]
0x529h
[7:0]
OFF_RD_BACK [3:0]
CE_STATE
0x529h
[15:8]
READ
BACK1
(READ-
ONLY)
OFF_RD_BACK [11:4]
OFF_RD_BACK [19:12]
SPARE_RD_BACK
DEVICE_ID
0x529h
[23:14]
0x529h
[31:24]
0x530h
[7:0]
I2C_MCL
K_REQ
USE_22C
_ROM_S
EL
0x530h
[15:8]
USE_RA
M
0x00h
0x8Ch
UNUSED
I2C_SP_MOD
SYS
CONFIG
0x530h
[23:16]
W_CLE
_EN
UNUSED
MBIST1_ MBIST0_
ENABLE ENABLE
0x530h
[31:24]
UNUSED
0x00h
0x65h
0x531h
[7:0]
W2
RL_RES
MAX_GAIN
FS SINP_MODE
W1
SPEAKE
R
OVER
DRIVE
CONTRO
L
0x531h
[15:8]
0x43h
0x83h
0x27h
0x70h
0x20h
0x64h
0x64h
0x00h
0x09h
0x00h
UNUSED
UNUSED
UNUSED
AT_RES
AT_GAIN
INT_GAIN
0x531h
[23:16]
0x531h
[31:24]
SODP_E
NABLE
0x532h
[7:0]
LEVEL1
0x532h
[15:8]
LEVEL2
INT_TH1
INT_TH2
SODP
THRES
HOLD
0x532h
[23:16]
0x532h
[31:24]
0x533h
[7:0]
AUDET
_ENABLE
UNUSED
LOW_PWR_MODE
ADC_TH [3:0]
UNUSED
AUDET_LEVEL
0x533h
[15:8]
TIMEOUT_DELAY
LOW
POWER
CONTRO
L
0x533h
[23:16]
ADC_TH [11:4]
OVR_AD OVR_ADC
CL_ENAB R_ENABL
OVR_VRE
F_ENABL
E
OVR_OU
T2_ENAB
LE
0x533h
[31:24]
OVR_PLL
_ENABLE
OVR_OUT
1_ENABLE
OVR_OU OVR_OU
T1_RST T2_RST
0x00h
LE
E
23
www.ti.com
Register Register
Default
Value
7
6
5
4
3
2
1
0
Name
Address
0x538h
[7:0]
0x00h
0x00h
0x00h
0x00h
0XA0h
0x3Ah
0x90h
0x48h
2b0
MBIST_ENABLE
UNUSED
MBIST_GO
MBIST_DONE
0x538h
[15:8]
CL_ACTI BUS_ER DEV_EXI
VE ROR STS
SYSTEM
STATUS
0x538h
[23:16]
MEM_ADDR [7:0]
MEM_ADDR [15:8]
CHIP_ID [7:0]
0x538h
[31:24]
0x539h
[7:0]
0x539h
[15:8]
CHIP_ID [15:8]
DEVICE
ID
0x539h
[23:16]
CHIP_ID [23:16]
CHIP_ID [31:24]
SODP_INT [7:0]
SODP_INT [15:8]
SODP_INT[23:16]
GAIN_INT_MAG
0x539h
[31:24]
0x53Ah
[7:0]
SPEAKE
R
OVER
DRIVE
DEBUG
0x53Ah
[15:8]
0x53Ah
[23:16]
0x53Ah
[31:24]
FILTER CONTROL REGISTER (0x500h)
Configures the LM48903 Array and Pre-Array filters (Spatial Engine). The Filter Control Register sets the length of the Array and
Pre-Array filter taps, and selects the filter channel source for each audio output. Set PRE_BYPASS and ARRAY_BYPASS to 1 to
bypass the Spatial Engine, disabling the spatial effect without modifying the coefficients. Set PRE_ENABLE and ARRAY_ENABLE
to 1 to enable the Spatial Engine. Set PRE_ENABLE and ARRAY_ENABLE to 0 to disable the spatial engine. Disabling the Spatial
Engine does not affect the register contents. Disable the Spatial Engine during coefficient programming.
TABLE 4. Filter Control Register
BIT
NAME
VALUE
DESCRIPTION
Array Filter Tap Length
7:0
ARRAY_TAP
Pre-filter Tap Length. Pre-filter tap length should be
less than or equal to the Array filter tap length
14:8
15
PRE_TAP
UNUSED
Channel 1 Output Routing Selection
Array Filter Channel 0 Output Select
Array Filter Channel 1 Output Select
Channel 2 Output Routing Selection
Array Filter Channel 0 Output Select
Array Filter Channel 1 Output Select
17:16
19:18
CH1_SEL
CH2_SEL
0
1
0
1
27:20
28
UNUSED
0
1
0
1
Pre-Array filter not bypassed
Pre-Array filter bypassed
Array filter not bypassed
Array filter bypassed
PRE_BYPASS
29
ARRAY_BYPASS
www.ti.com
24
BIT
NAME
VALUE
DESCRIPTION
Pre-Array filter disabled. Disable the Pre-Array Filter
during filter and coefficient programming. Disabling
the Pre-Array Filter does not affect the device
memory contents.
0
30
PRE_ENABLE
1
0
1
Pre-Array filter enabled
Array filter disabled. Disable the Array Filter during
filter and coefficient programming. Disabling the Array
Filter does not affect the device memory contents.
31
ARRAY_ENABLE
Array filter enabled
COMPRESSOR CONTROL REGISTER 1 (FILTER COMP1) (0x501h)
TABLE 5. Compressor Control Register
BIT
NAME
VALUE
DESCRIPTION
4:0
COMP_TH
Pre-Filter Compressor Threshold
Pre-Compression Gain
000
001
010
011
100
101
110
111
2
4
8
7:5
G1_GAIN
16
32
64
128
256
Compression Ratio
000
001
010
011
100
101
110
111
1:1
2:1
2.66:1
4:1
10:8
11
COMP_RATIO
UNUSED
5.33:1
8:1
10.66:1
16:1
Post Compression Gain (V/V)
000
001
010
011
100
101
110
111
1
1.25
1.5
2
14:12
POST_GAIN
2.5
3
4
8
15
UNUSED
ARRAY_COMP_SELECT
UNUSED
23:16
31:24
Array Filter Compression Control Register Select
25
www.ti.com
COMPRESSOR CONTROL REGISTER 2 (FILTER COMP2) (0x502h)
TABLE 6. Compressor Control Register 2
BIT
NAME
VALUE
DESCRIPTION
4:0
COMP_TH
Pre-Filter Compressor Threshold
Pre-Compression Gain
000
001
010
011
100
101
110
111
2
4
8
7:5
G1_GAIN
16
32
64
128
256
Compression Ratio
000
001
010
011
100
101
110
111
1:1
2:1
2.66:1
4:1
10:8
11
COMP_RATIO
UNUSED
5.33:1
8:1
10.66:1
16:1
Post Compression Gain (V/V)
0
1
1.25
1.5
2
1
10
14:12
POST_GAIN
11
100
101
110
111
2.5
3
4
8
15
UNUSED
20:16
COMP_TH
Pre-Filter Compressor Threshold
Pre-Compression Gain
0
2
4
1
10
8
23:21
G1_GAIN
11
16
32
64
128
256
100
101
110
111
www.ti.com
26
BIT
24:26
27
NAME
COMP_RATIO
UNUSED
VALUE
DESCRIPTION
Compression Ratio
000
001
010
011
100
101
110
111
1:001
2:001
2.66:1
4:001
5.33:1
8:001
10.66:1
16:1
Post Compression Gain (V/V)
000
001
010
011
100
101
110
111
1
1.25
1.5
2
30:28
POST_GAIN
2.5
3
4
8
31
UNUSED
FILTER DEBUG REGISTER 0 (FILT_DBG0) (0x503h)
TABLE 7. Filter Debug Register 0
BIT
23:0
NAME
VALUE
DESCRIPTION
Audio Data. Common data for both left and right audio
channels
DBG_DATA
UNUSED
31:24
FILTER DEBUG REGISTER 1 (FILT_DBG1) (0x504h)
TABLE 8. Filter Debug Register 1
BIT
NAME
VALUE
DESCRIPTION
Accumulator Address. Selects which accumulator is
read during debug mode
3:0
ACC_ADDR
0
1
Selects Pre-Filter Accumulators
Selects Array Filter Accumulators
4
5
6
FILTER_SELECT
UNUSED
0
1
0
1
Single Step Disabled
Single Step Enabled
Debug Mode Disabled
Debug Mode Enabled
STEP_ENABLE
7
DBG_ENABLE
UNUSED
31:8
27
www.ti.com
FILTER STATISTICS CONTROL REGISTER (FILT_STC) (0x505h)
TABLE 9. Filter Statistics Control Register
VALUE
BIT
NAME
DESCRIPTION
PRE-FILTER Counter
Channel Select
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
000
001
010
011
100
101
110
111
3:0
PCH_SEL
Counter 1 Mode Select. Specifies input of Counter 1
Sample Count Mode. Every audio sample is counted
Overflow. Overflow events counted
0000
0001
Frequency Error. Indicates input frequency not
sufficient for given filter length
0010
1000
1001
1010
1011
1100
1101
1110
1111
MAGN[7}
MAGN[7:6]
7:4
PCOUNT1_MODE
MAGN[7:5}
MAGN[7:4}
MAGN[7:3}
MAGN[7:2]
MAGN[7:1}
MAGN[7:0]
Counter 2 Mode Select. Specifies input of Counter 2
Sample Count Mode. Every audio sample is counted
Overflow. Overflow events counted
0000
0001
Frequency Error. Indicates input frequency not
sufficient for given filter length
0010
1000
1001
1010
1011
1100
1101
1110
1111
MAGN[7}
MAGN[7:6]
MAGN[7:5}
MAGN[7:4}
MAGN[7:3}
MAGN[7:2]
MAGN[7:1}
MAGN[7:0]
11:8
PCOUNT2_MODE
14:12
15
UNUSED
PCLEAR
0
1
Counter Enabled
Counter Cleared
ARRAY-FILTER Counter
www.ti.com
28
BIT
NAME
VALUE
DESCRIPTION
Channel Select
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
000
001
010
011
100
101
110
111
19:16
ACH_SEL
Counter 1 Mode Select. Specifies input of Counter 1
Sample Count Mode. Every audio sample is counted
Overflow. Overflow events counted
0000
0001
Frequency Error. Indicates input frequency not
sufficient for given filter length
0010
1000
1001
1010
1011
1100
1101
1110
1111
MAGN[7}
MAGN[7:6]
23:20
ACOUNT1_MODE
MAGN[7:5}
MAGN[7:4}
MAGN[7:3}
MAGN[7:2]
MAGN[7:1}
MAGN[7:0]
Counter 2 Mode Select. Specifies input of Counter 2
Sample Count Mode. Every audio sample is counted
Overflow. Overflow events counted
0000
0001
Frequency Error. Indicates input frequency not
sufficient for given filter length
0010
1000
1001
1010
1011
1100
1101
1110
1111
MAGN[7}
MAGN[7:6]
MAGN[7:5}
MAGN[7:4}
MAGN[7:3}
MAGN[7:2]
MAGN[7:1}
MAGN[7:0]
27:24
ACOUNT2_MODE
30:28
31
UNUSED
ACLEAR
0
1
Counter Enabled
Counter Cleared
FILTER DEBUG REGISTER 2 (FILTER DEBUG 2) (0x506h)
TABLE 10. Filter Debug Register 2
VALUE
BIT
NAME
DESCRIPTION
31:0
DGB_DATA
Debug Data. Read Only
ACCUMULATOR DEBUG LOWER REGISTER (ACCUML DEBUG) (0x509h)
TABLE 11. Accumulator Debug Lower Register
BIT
NAME
VALUE
DESCRIPTION
31:0
DBG_ACCL
Accumulator Debug Data. Read Only
29
www.ti.com
ACCUMULATOR DEBUG UPPER REGISTER (ACCUML DEBUG) (0x50Ah)
TABLE 12. Accumulator Debug Upper Register
BIT
NAME
VALUE
DESCRIPTION
31:0
DBG_ACCL
Accumulator Debug Data. Read Only
COMPRESSOR OUTPUT DATA REGISTER (DBG_SAT) (0x50Bh)
TABLE 13. Compressor Output Data Register
VALUE
BIT
23:0
NAME
DESCRIPTION
DBG_SAT
UNUSED
24-Bit Compressor Output Data. Read Only
31:24
FILTER STATISTICS COUNTER (STAT_ACNT) (0x50Ch)
TABLE 14. Filter Statistics Counter Register
VALUE
BIT
NAME
DESCRIPTION
Statistics of Post-Processed Array and Pre-Filter Data.
Read Only
31:0
COUNT
FILTER STATISTICS COUNTER (STAT_ACNT) (0x50Dh)
TABLE 15. Filter Statistics Counter Register
VALUE
BIT
NAME
DESCRIPTION
Statistics of Post-Processed Array and Pre-Filter Data.
Read Only
31:0
COUNT
FILTER STATISTICS COUNTER (STAT_ACNT) (0x50Eh)
TABLE 16. Filter Statistics Counter Register
VALUE
BIT
NAME
DESCRIPTION
Statistics of Post-Processed Array and Pre-Filter Data.
Read Only
31:0
COUNT
FILTER STATISTICS COUNTER (STAT_ACNT) (0x50Fh)
TABLE 17. Filter Statistics Counter Register
VALUE
BIT
NAME
DESCRIPTION
Statistics of Post-Processed Array and Pre-Filter Data.
Read Only
31:0
COUNT
ADC DC OFFSET REGISTER (ADC OFFSET) (0x510h)
TABLE 18. ADC DC Offset Register
BIT
15:0
NAME
VALUE
DESCRIPTION
ADC Right Channel Output DC Offset
ADC Left Channel Output DC Offset
ADCR_VOS
ADCL_VOS
31:16
CLASS D DC OFFSET REGISTER (CLASS D OFFSET) (0x511h)
TABLE 19. Class D DC Offset Register
VALUE
BIT
15:0
NAME
DESCRIPTION
OUT1 Output DC Offset
OUT2 Output DC Offset
OUT1_VOS
OUT2_VOS
31:16
www.ti.com
30
DELAY REGISTER (DELAY) (0x520h)
TABLE 20. Delay Register
VALUE
BIT
15:0
NAME
DESCRIPTION
Sets I2C Delay Time. Default 10ms delay.
POWER_UP_DELAY
DEGLITCH_DELAY
STATE_DELAY
23:16
31:24
Sets ENABLE Bit Polling Timeout. Default 32ms delay
Sets Delay Between Power Up/Down States
ENABLE AND CLOCK CONFIGURATION REGISTER (ENABLE & CLOCKS) (0x521h)
TABLE 21. Enable and Clock Configuration Register
BIT
NAME
VALUE
DESCRIPTION
Device Disabled in Manual Mode
Device Enabled in Manual Mode
Device Enabled Via SHDN Pin
Device Enabled Via I2C
0
1
0
1
0
1
0
ENABLE
1
2
FORCE
PULSE
SHDN Requires a Stable Logic Level
SHDN Accepts a Pulse Input
Device waits for delay time determined by
STATE_DELAY to enable.
0
3
RELY_ON_VREF
1
0
1
0
1
0
1
0
Device waits for stable VREF
Disable Class D Offset Correction
Enable Class D Offset Correction
Disable ADC Offset Calibration
Enable ADC Offset Calibration
Disable ADC Offset Correction
Enable ADC Offset Correction
Normal Operation
4
5
6
PWM_DC_CORRECT
ADC_DC_CAL
ADC_DC_CORRECT
7
ADC_SYNC_SEL
Invert SYNC Signal. Increases timing margin at low
supplies
1
Selects PLL Input Divider
32fs (1.536MHz)
000
001
010
011
100
101
110
111
0
64fs (3.072MHz)
128fs (6.114MHz)
10:8
MCLK_RATE
256fs (12.288MHz)
512fs (24.576MHz)
UNUSED
UNUSED
UNUSED
MCLK Input to PLL
I2S_CLK Input to PLL
Oscillator Clock Input to Power Management Circuitry
11
12
I2S_CLK
1
0
MCLK or I2S_CLK Input to Power Management
Circuitry. Clock source depends on the state of
I2S_CLK
PMC_CLK_SEL
1
0
1
HiFi Mode Disabled
13
HIFI
HiFi Mode Enabled. PLL always produces a 4096fs
clock.
0
1
0
1
SAP Clock Enabled
14
15
SAP_CLK_STOP
SAP_MBIST
SAP Clock Disabled Following Device Configuration
Disable MBIST
Enable MBIST
31
www.ti.com
BIT
NAME
VALUE
DESCRIPTION
ADC High Pass Filter Mode
000
001
010
011
100
101
110
111
0
18:16
ADC_HPF_MODE
ADC High Pass Filter Disabled
ADC High Pass Filter Enabled
19
ADC_HPF_ENABLE
UNUSED
1
31:20
DIGITAL MIXER CONTROL REGISTER (DIGITAL MIXER) (0x522h)
TABLE 22. Digital Mixer Control Register
BIT
NAME
VALUE
DESCRIPTION
Sets the Gain of the ADC Path (dB)
000000
-76.5
000001
-75
-
1.5dB steps
5:0
ADC_LVL
110010
-1.5
110011
0
110100
1.5
-
1.5dB Steps
111111
18
0
1
0
1
Normal Operation
6
7
MUTE
Mute
Zero Crossing Detection Enabled
ZXD_DISABLE
Zero Crossing Detection Disabled
Sets the Gain of the I2S Path (dB)
000000
000001
-
-76.5
-75
1.5dB steps
13:8
I2S_LVL
110010
110011
110100
-
-1.5
0
1.5
1.5dB Steps
18
111111
15:14
16
UNUSED
I2S_DSP
I2S Data Not Passed to DSP
0
1
0
1
I2S Data Passed to DSP
ADC Output Not Passed to DSP
17
ADC_DSP
ADC Output Passed to DSP
Selects Input of Primary I2S Transmitter
00
01
10
11
None
19:18
23:20
ISA_TX_SEL
UNUSED
ADC
DSP
UNUSED
www.ti.com
32
BIT
NAME
VALUE
DESCRIPTION
Selects OUT1 Amplifier Input Source
00
01
10
11
OUT1 Disabled
DSP
I2S
25:24
OUT1_SEL
ADC
Selects OUT2 Amplifier Input Source
00
01
10
11
OUT2 Disabled
DSP
I2S
27:26
31:28
OUT2_SEL
UNUSED
ADC
ANALOG CONFIGURATION REGISTER (ANALOG) (0x523h)
TABLE 23. Analog Configuration Register
BIT
NAME
VALUE
DESCRIPTION
Sets ADC Preamplifier Gain (dB)
00
11
10
11
0
1:00
ANA_LVL
2.4
3.5
6
Normal Operation. OUT1 and OUT2 operate as separate
amplifiers.
0
2
PARALLEL
Parallel Operation. OUT1 and OUT2 operate in parallel
as a single amplifier.
1
0
1
0
1
0
1
Normal Operation
3
4
ZERO_ANA
ZERO_DIG
Auto-Shutdown Mode. Automatically disables the
amplifiers when no analog input is detected.
Normal Operation
Auto-Shutdown Mode. Automatically disables the
amplifiers when there is no I2S input.
ADC Trim Disabled
5
6
ADCTRIM
AUTO_SD
ADC Trim Enabled. Use ADC_COMP_COEFF_C0-C2
to trim ADC.
0
1
0
Normal Operation
Fault Conditions Disable the Amplifiers
Normal Operation
Pulse Correction Bypass. Amplifier output stages act as
a buffer, passing PWM signal without correction to
output.
7
8
BYPASS_MOD
TST_SHT
1
0
1
Normal Operation
Short Amplifier Inputs. Sets amplifier outputs to 50% duty
cycle, minimizing click and pop during power up/down.
0
1
0
1
0
1
0
1
Normal Operation
9
SCKT_DIS
TSD_DIS
Output Short Circuit Protection Disabled
Normal Operation
10
11
12
Thermal Shutdown Disabled
Normal Operation
PMC_TEST
SE_MOD
PMC uses PLL Source Clock
Normal Operation
Single Edge Modulation Mode
33
www.ti.com
BIT
NAME
VALUE
DESCRIPTION
23:13
UNUSED
0
1
External ADC Gain Control. ADC gain set by G0 and G1
Internal ADC Gain Control. ADC gain set by ANA_LVL.
24
I2C_ANA_LVL
UNUSED
31:25
I2S PORT CONFIGURATION REGISTER (I2S PORT) (0x524h/0x525h)
TABLE 24. I2S Port Configuration Register
VALUE
0x524h
BIT
NAME
DESCRIPTION
0
1
0
1
0
1
Mono Mode
Stereo Mode
0
1
2
STEREO
Receive Mode Disabled
RX_ENABLE
TX_ENABLE
Receive Mode Enabled
Transmit Mode Disabled
Transmit Mode Enabled
I2S Clock Slave. Device requires an external SCLK for
proper operation.
I2S Clock Master. Device generates SCLK and transmits
when either RX or TX mode are enabled.
I2S WS Slave. Device requires an external WS for proper
operation.
I2S WS Master. Device generates WS and transmits
when either RX or TX mode are enabled.
I2S Clock Phase. Transmit on falling edge, receive on
rising edge.
0
1
0
1
0
1
3
4
5
CLK_MS
SYNC_MS
CLOCK_PHASE
PCM Clock Phase. Transmit on rising edge, receive on
falling edge.
I2S Data Format: Left, Right
I2S Data Format: Right, Left
0
STEREO_SYNC
_PHASE
6
7
1
Mono
0
Rising edge indicates start of data word.
SYNC_MODE
SYNC low = Left, SYNC high = Right
1
SYNC low = Right, SYNC high = left
Configures the I2S port master clock half-cycle divider.
Program the half-cycle divider by: (ReqDiv*2) 1
000000
000001
000010
000011
-
BYPASS
1
1.5
2
HALF_CYCLE
_DIVIDER
13:8
-
111101
111110
111111
31
31.5
32
15:14
UNUSED
www.ti.com
34
BIT
NAME
VALUE
DESCRIPTION
Sets the Clock Generator Numerator
SYNTH_DENOM (1/)
000
001
010
011
100
101
110
111
0
100/SYNTH_DENOM
96/SYNTH_DENOM
18:16
SYNTH_NUM
80/SYNTH_DENOM
72/SYNTH_DENOM
64/SYNTH_DENOM
48/SYNTH_DENOM
0/SYNTH_DENOM
Clock Generator Denominator = 128
Clock Generator Denominator = 125
19
SYNTH_DENOM
UNUSED
1
23:20
Sets number of clock cycles before SYNC pattern
repeats.
MONO MODE
000
001
010
011
100
101
110
111
8
12
16
18
20
24
25
26:24
SYNC_RATE
32
STEREO MODE
000
001
010
011
100
101
110
111
16
24
32
36
40
48
50
64
Sets SYNC symbol width in Mono Mode
000
001
010
011
100
101
110
111
1
2
4
29:27
31:30
MONO_SYNC_WIDTH
7
8
11
15
16
UNUSED
0x525h
35
www.ti.com
BIT
NAME
VALUE
DESCRIPTION
Sets number of valid RECEIVE bits.
000
001
010
011
100
101
110
111
24
20
18
2:0
RX_WIDTH
16
14
13
12
8
Sets number of TRANSMIT bits.
000
001
010
011
100
101
110
111
24
20
18
5:3
TX_WIDTH
16
14
13
12
8
Sets number of pad bits after the valid Transmit bits.
00
01
10
11
0
0
7:6
8
TX_BIT
1
High-Z
High-Z
MSB Justified Receive Mode
LSB Justified Receive Mode
RX_MODE
1
www.ti.com
36
BIT
NAME
VALUE
DESCRIPTION
MSB location from the frame start (MSB Justified) or LSB
location from the frame end (LSB Justified)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
0
0 (DSP/PCM LONG)
1 (I2S/PCM SHORT)
2
3
4
5
6
7
8
9
10
11
12
13
14
13:9
RX_MSB_POSITION
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Normal Operation
Audio Data Companded
µLaw Compand Mode
A-Law Compand Mode
MSB Justified Transmit Mode
LSB Justified Transmit Mode
14
15
16
RX_COMPAND
RX_A/µLAW
TX_MODE
1
0
1
0
1
37
www.ti.com
BIT
NAME
VALUE
DESCRIPTION
MSB location from the frame start (MSB Justified) or LSB
location from the frame end (LSB Justified)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
0
0 (DSP/PCM LONG)
1 (I2S/PCM SHORT)
2
3
4
5
6
7
8
9
10
11
12
13
14
21:17
TX_MSB_POSITION
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Normal Operation
Audio Data Companded
µLaw Compand Mode
A-Law Compand Mode
22
TX_COMPAND
1
0
23
TX_A/µLAW
UNUSED
1
31:24
www.ti.com
38
ADC TRIM COEFFICIENT REGISTER (ADC_TRIM) (0x526h/0x527)
TABLE 25. ADC Trim Coefficient Register
VALUE
BIT
NAME
DESCRIPTION
0x526h
15:0
ADC_COMP_COEFF_C0
ADC_COMP_COEFF_C1
Sets ADC Trim Coefficient C0
Sets ADC Trim Coefficient C1
31:16
0x527h
15:0
ADC_COMP_COEFF_C2
UNUSED
Sets ADC Trim Coefficient C2
31:16
READBACK REGISTER 0(READBACK0) (0x528h) READ-ONLY
TABLE 26. Readback Register 0
BIT
NAME
VALUE
DESCRIPTION
0
ADCR_CLIP
1
1
1
1
1
1
Right Channel ADC Input Clipped
Left Channel ADC Input Clipped
Right Channel ADC Output Clipped
Left Channel ADC Output Clipped
Right Channel I2S Output Clipped
Left Channel I2S Output Clipped
1
2
ADCL_CLIP
ADCR_LVLCLIP
ADCL_LVLCLIP
I2SR_LVLCLIP
I2SL_LVLCLIP
3
4
5
7:6
8
UNUSED
UNUSED
SHORT1
SHORT2
1
1
OUT1 Output Short Circuit
OUT2 Output Short Circuit
9
11:10
12
THERMAL
SPARE
1
Thermal Shutdown Threshold Exceeded
23:13
31:24
UNUSED
READBACK REGISTER 1(READBACK1) (0x528h) READ-ONLY
TABLE 27. Readback Register 1
BIT
NAME
VALUE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1111
DESCRIPTION
Wait for supply
Wait For I2C CLK REQ
Enable I2C CLOCK
Power up delay
Standby
Enable REF
Enable Inputs
Enable Outputs
Unmute
3.0
CE_STATE
Enabled
Off Deglitch
Mute
Disable Outputs
Disable Inputs
UNUSED
31:4
UNUSED
39
www.ti.com
SYSTEM CONFIGURATION REGISTER (SYS_CONFIG) (0x530h)
TABLE 28. System Configuration Register
BIT
NAME
VALUE
DESCRIPTION
Sets LM48903 Device ID in slave mode. Default is
0x30h.
6:0
DEVICE_ID
I2C does not require MCLK
0
1
0
1
0
1
7
8
9
I2C_MCLK_REQ
USE_RAM
I2C requires MCLK
Disable RAM Memory Usage
Enable RAM Memory Usage
MODE0, MODE1, Selects SPATIAL mode
I2C_SP_MD, Selects Spatial mode
USE_I2C_ROM_SEL
ROM mode spatial effects select. Selects which ROM
page is loaded into coefficient memory.
00
01
10
11
4.5cm speaker spacing
6cm speaker spacing
11:10
I2C_SP_MD
11.5cm speaker spacing
DSP bypassed, stereo mode
22
23
UNUSED
0
1
0
1
0
1
Write clock disabled
W_CLE_EN
Write clock enabled
Memory BIST Controller 0 Disabled
Memory BIST Controller 0 Enabled.
Memory BIST Controller 1 Disabled
Memory BIST Controller 1 Enabled.
24
MBIST0_ENABLE
25
MBIST1_ENABLE
UNUSED
31:26
SPEAKER OVERDRIVE CONTROL REGISTER (SPEAKER OVERDRIVE) (0x531h)
TABLE 29. Speaker Overdrive Protection Register
BIT
NAME
VALUE
DESCRIPTION
Window 1. Sets the sample window time the device uses
to estimate audio energy for samples between LEVEL1
and LEVEL2 (0x532h)
0000
0001
5ms
10ms
20ms
50ms
100ms
200ms
500ms
800ms
1s
0010
0011
0100
3:0
W1
0101
0110
0111
1000
1001
2s
1010
5s
1011
10s
1100-1111
UNUSED
www.ti.com
40
BIT
NAME
VALUE
DESCRIPTION
Window 2. Sets the sample window time the device uses
to estimate audio energy for samples above INT_TH1
(0x532h)
0000
0001
5ms
10ms
0010
20ms
0011
50ms
0100
100ms
7:4
W2
0101
200ms
0110
500ms
0111
800ms
1000
1s
1001
2s
1010
5s
1011
10s
1100-1111
UNUSED
Attack Time Resolution
000
001
010
011
100
101
110
111
1ms
2ms
5ms
10:8
11
AT_RES
UNUSED
RL_RES
10ms
20ms
50ms
100ms
200ms
Release Time Resolution
000
001
010
011
100
101
110
111
1ms
2ms
5ms
14:12
10ms
20ms
50ms
100ms
200ms
15
UNUSED
AT_GAIN
Attack Mode Gain Reduction
000
001
—
110
111
0dB. No gain reduction
3dB
19:16
3dB steps
18dB
21dB
Maximum Gain
0dB
000
001
—
110
111
3dB
23:17
MAX_GAIN
3dB steps
18dB
21dB
41
www.ti.com
BIT
NAME
VALUE
DESCRIPTION
Integrator Gain
0dB
000
001
—
110
111
6dB
26:24
INT_GAIN
6dB steps
36dB
42dB
27
UNUSED
SODP Input Mode
No Signal Applied
00
01
10
11
0
29:28
SINP_MODE
OUT1 Input to SODP
OUT2 Input to SODP
Average (OUT1+OUT2/2)
48ksps
30
31
FS
1
44.1ksps
0
Speaker Overdrive protection Disabled
Speaker Overdrive protection Enabled
SODP_EN
1
SPEAKER OVERDRIVE PROTECTION THRESHOLD REGISTER (SODP_THRESHOLD) (0x532h)
TABLE 30. Filter Debug Register 1
BIT
NAME
VALUE
DESCRIPTION
Output Level Threshold. Set LEVEL1 such that signals
above LEVEL1 increase die temperature. Signal levels
above LEVEL1 are added to the estimated audio energy
in a given time window.
7:0
LEVEL1
Output Level Threshold. Set LEVEL2 such that signals
below LEVEL2 reduce die temperature. Signal levels
below LEVEL2 are subtracted from the estimated audio
energy in a given time window.
15:8
LEVEL2
Attack Threshold. Integrator level above INT_TH1
enables the SOPD, reducing device gain.
23:16
31:24
INT_TH1
INT_TH2
Release Threshold. Integrator level below INT_TH2
disables the SOPD, increasing device gain.
LOW POWER CONTROL REGISTER (0x533h)
TABLE 31. Low Power Configuration Register
VALUE DESCRIPTION
BIT
NAME
0
1
Disable Wake up On Audio Signal
0
AUDET_EN
Enable Wake up On Audio Signal
Wake Up Detection Threshold
00
01
10
11
25mV
50mV
75mV
100mV
2:1
3
AUDET_LEVEL
UNUSED
www.ti.com
42
BIT
5:4
7:6
NAME
LPWR_MODE
UNUSED
VALUE
DESCRIPTION
Low Power Mode
00
01
10
11
Normal Mode. No power saving modes enabled
Analog Audio Detect Mode. Input signal compared to
AUDET_LEVEL.
ADC Audio Detect Mode
Digital Audio Detect Mod. Rising edge on I2S WS
enables the device.
Time Out Delay. Delay time between no audio detected
and the device entering low power mode.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
10ms
20ms
50ms
100ms
200ms
500ms
1s
11:8
TIMEOUT_DLY
2s
5s
10s
20s
50s
60s
80s
100s
200s
23:12
24
ADC_TH
ADC Audio Detection Threshold
Override OUT2 Reset
Override OUT1 Reset
Override OUT1 Enable
Override OUT2 Enable
Override Reference Enable
Override PLL Enable
Override Right Channel ADC Enable
Override Left Channel ADC Enable
OVR_OUT2_RST
OVR_OUT1_RST
OVR_OUT1_EN
OVR_OUT2_EN
OVR_VREF_EN
OVR_PLL_EN
1
1
1
1
1
1
1
1
25
26
27
28
29
30
OVR_ADCR_EN
OVR_ADCL_EN
31
43
www.ti.com
SYSTEM STATUS REGISTER (SYS_STAT) (0x538h) READ ONLY
TABLE 32. MBIST Status Register
BIT
NAME
VALUE
DESCRIPTION
1:0
MBIST_DONE
Logic HIGH indicates memory test complete
Logic Low indicates memory fault when MBIST_DONE
is HIGH
3:2
5:4
MBIST_GO
MBIST_EN
0
1
MBIST Read-back Disabled
MBIST Read-back Enabled
8:6
9
UNUSED
DEV_EXISTS
Logic HIGH indicates the presence of an EEPROM
Logic HIGH indicates an I2C bus error during EEPROM
read
Logic HIGH indicates the I2C master is active and
loading from the EEPROM
10
11
BUS_ERR
CL_ACTIVE
16:12
31:16
UNUSED
MEM_ADDR
Memory Address
DEVICE ID REGISTER (0x539h) READ ONLY
TABLE 33. Device ID Register
VALUE
BIT
NAME
DESCRIPTION
DESCRIPTION
31:0
CHIP_ID
4890_3AA0h
32-bit Device ID
SPEAKER OVERDRIVE PROTECTION DEBUG REGISTER (0x53Ah) READ ONLY
TABLE 34. Speaker Overdrive Debug Register
BIT
NAME
VALUE
23:0
SODP_INT
Current Integrator Value
Integrator Magnitude. 8 most significant bits of the
integrator magnitude
31:24
GAINED_INT_MAG
DEVICE ADDRESS
The 0110000X is the defaultLM48903 I2C address hard coded into the device. An alternate device address can be programmed,
via the SYS CONFIG (0x530h) Register. Use the default address during initial device configuration.
www.ti.com
44
GENERAL AMPLIFIER FUNCTION
Class D Amplifier
The LM48903 features stereo efficiency Class D audio power amplifiers that utilizes Texas Instruments’ filterless modulation
scheme external component count, conserving board space and reducing system cost. The Class D outputs transition from VDD
to GND with a 384kHz switching frequency. With no signal applied, the outputs switch with a 50% duty cycle, in phase, causing
the two outputs to cancel. This cancellation results in no net voltage across the speaker, thus there is no current to the load in the
idle state.
With the input signal applied, the duty cycle (pulse width) of the LM48903 outputs changes. For increasing output voltage, the duty
cycle of OUT_+ increases while the duty cycle of OUT_- decreases. For decreasing output voltages, the converse occurs. The
difference between the two pulse widths yield the differential output voltage.
Edge Rate Control (ERC)
The LM48903 features Texas Instruments’ advanced edge rate control (ERC) that reduces EMI, while maintaining high quality
audio reproduction and efficiency. The LM48903 ERC greatly reduces the high frequency components of the output square waves
by controlling the output rise and fall times, slowing the transitions to reduce RF emissions, while maximizing THD+N and efficiency
performance. The overall result of the E2S system is a filterless Class D amplifier that passes FCC Class B radiated emissions
standards with 24in of twisted pair cable, with excellent 0.08% THD+N and high 91% efficiency.
POWER DISSIPATION AND EFFICIENCY
The major benefit of a Class D amplifier is increased efficiency versus a Class AB. The efficiency of the LM48903 is attributed to
the region of operation of the transistors in the output stage. The Class D output stage acts as current steering switches, consuming
negligible amounts of power compared to their Class AB counterparts. Most of the power loss associated with the output stage is
due to the IR loss of the MOSFET on-resistance, along with switching losses due to gate charge.
ANALOG INPUT
The LM48903 features a stereo, 18-bit, differential ADC for systems without a digital audio source. The ADC front end includes a
variable gain preamplifier with 4 gain settings, 0dB, 2.4dB, 3.5dB, and 6dB. The preamplifier gain is controlled by bits 0 and 1
(ANA_LVL) of the Analog Configuration Register (0x523h). The analog inputs can be configured as either differential or single
ended inputs. The differential configuration SNR is 6dB higher than single-ended configuration. The differential input configuration
also offers improved common mode rejection (CMRR). The increased CMRR reduces sensitivity to ground offset related noise
injection. Configure the LM48903 for single-ended inputs as shown in Figure 10.
The ADC input range is dependent on AVDD. The maximum input swing of each single ADC input, ie INL+, referenced to GND is
0.7*AVDD . This gives a maximum differential input of 7VP-P when AVDD = 5V.
301858g5
FIGURE 10. ADC Input Configurations
45
www.ti.com
POWER SUPPLY REQUIREMENTS
At power up, sequence the LM48903 power supplies in the following order:
1) PVDD
2) AVDD/PLLVDD
3) DVDD/IOVDD
Ensure PVDDis higher or equal to AVDD/PLLVDD, and PVDD is always higher than DVDD
.
MODULATOR POWER SUPPLY
The AVDD1 powers the class D modulators. For maximum output swing, set AVDD1 and PVDD to the same voltage. Table 35 shows
the output voltage for different AVDD1 levels.
TABLE 35. Amplifier Output Voltage with variable AVDD1 Voltage
AVDD1 (V)
VOUT (VRMS) @PVDD = 5V, THD+N = 1%
VOUT (VRMS) @PVDD = 3.6V, THD+N = 1%
5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1
—
—
4.5
4.2
4
—
—
3.6
3.3
3
2.4
2.2
2.1
1.9
2.8
www.ti.com
46
PARALLEL MODE
In Parallel mode, channels OUT1 and OUT2 are driven from the same audio source, allowing the two channels to be connected
in parallel, increasing output power to 3.3W into 4Ω at 10% THD+N. Set bit 2 (PARALLEL) of the Analog Configuration Register
(0x532h) = 1 to configured the device in Parallel mode. After the device is set to Parallel mode, make an external connection
between OUT1+ and OUT2+, and a connection between OUT1- and OUT2- Figure 11. In Parallel mode, the combined channels
are driven from the OUT1 source. Signal routing, mixing, filtering, and equalization are done through the Spatial Engine.
Make sure the device is configured in Parallel mode, before connecting OUT1 and OUT2 and enabling the outputs. Do not make
a connection between OUT1 and OUT2 together while the outputs are enabled. Disable the outputs first, then make the connections
between OUT1 and OUT2.
301858g2
FIGURE 11. Parallel Mode
47
www.ti.com
GAIN SETTING
I2C Gain Setting
The LM48903 has three gain stages, the ADC preamplifier, and two independent volume controls in the Digital Mixer, one for the
ADC path and one for the I2S path. The ADC preamplifier has four gain settings (0dB, 2.4dB, 3.5dB, and 6dB). The preamplifier
gain is set by bits 0 and 1 (ANA_LVL) of the Analog Configuration Register (0x523h). The Digital Mixer has two 64 step volume
controls. The ADC path volume control is set by bits 5:0 (ADC_LVL) in the Digital Mixer Control Register (0x522h). The I2S path
volume control is set by bits 13:8 (I2S_LVL) in the Digital Mixer Control Register (0x522h). Both volume controls have a range of
-76.5dB to 18dB in 1.5dB increments.
GAIN1 and GAIN0 Gain Setting
For systems without I2C control, the ADC preamplifier gain is set by GAIN1 and GAIN0. The gain settings are shown in Table
36. The I2C preamplifier gain settings override GAIN1 and GAIN0.
TABLE 36. Hardware Gain Setting
GAIN1
GAIN0
GAIN (dB)
0
0
1
1
0
1
0
1
0
2.4
3.5
6
ROM MODE
The LM48903 features a ROM with four preset operating modes; three spatial modes, and a stereo mode. The spatial modes are
designed for three different speaker distances, 4.5cm, 6cm and 11.5cm. Due to the spatial processing, there may be a perceived
Left/Right channel swap when switching between Stereo and the three preset spatial configurations in ROM mode.
The ROM modes are selected through both the I2C interface and by MODE1/MODE0. For systems without I2C, MODE1 and
MODE0 select the ROM mode as shown in Table 37. For systems with I2C, bits 11:10 (I2C_SP_MD1 and I2C_SP_MD0) of the
SYS_CONFIG register (0x530h) select the ROM mode as shown in Table 38. Set bit 9 (USE_I2C_SP_MD) of the SYS_CONFIG
register = 1 to select the ROM mode through I2C. Set bit 8 (USE_RAM) of the SYS_CONFIG register = 0 (default) to use the preset
ROM modes. Set USE_RAM = 1 to use custom spatial coefficients. The LM48903 only accepts analog inputs in ROM mode, I2S
inputs are ignored.
TABLE 37. ROM Settings, Hardware Mode (USE_I2C_SP_MD = 0)
MODE1
MODE0
DESCRIPTION
4.5cm Speaker Spacing
6cm Speaker Spacing
11.5 Speaker Spacing
DSP Bypassed, Stereo Mode
0
0
1
1
0
1
0
1
TABLE 38. ROM Settings, I2C Mode (USE_I2C_SP_MD = 1)
USE_RAM
I2C_SP_MD1
I2C_SP_MD0
DESCRIPTION
4.5cm Speaker Spacing
6cm Speaker Spacing
11.5 Speaker Spacing
DSP Bypassed, Stereo Mode
0
0
0
0
0
0
1
1
0
1
0
1
Custom Spatial Mode. The device
bypasses the ROM and loads coefficients
from an external source.
1
X
X
www.ti.com
48
SPEAKER OVERDRIVE PROTECTION
Speaker overdrive protection (SODP) monitors the DSP outputs and adjusts the signal path gain to prevent speaker overheating.
SODP monitors two levels, LEVEL1, the output amplitude above which the voice coil temperature rises, and LEVEL2 the output
amplitude below which the voice coil temperature falls. Speaker Overdrive Protection Threshold Register (0x532h) bits 7:0 set
LEVEL1. Bits 15:8 set LEVEL2.
The difference between LEVEL1 and LEVEL2 is the amplitude where the voice coil temperature remains stable. The device inte-
grates the difference between the output signal and LEVEL1 for signals above LEVEL1, and the difference between the output
signal and LEVEL2 for signals below LEVEL2. There are two integration time windows. Bits 3:0, (W1), of the Speaker Overdrive
Control Register (0x531h), set the duration of Window 1. Window 1 is integration time when during normal operation. Bits 7:4 (W2)
set the duration of Window 2. Window 2 is the integration time when the SODP is active, and the device gain is reduced.
At the end of Window 1, the device compares the integrator output the INT_TH1 (0x532h, bits 23:16), or the attack threshold. Bits
19:16, (AT_GAIN), of register 0x531h, set the gain reduction step. Bits 10:8 (AT_RES) set the attack time. For example, if AT_GAIN
= 6dB and AT_RES = 5ms, once the integrator output exceeds INT_TH1, the signal path gain is reduced by 6dB in 1.5dB steps
over 5ms. Following the gain reduction, the device switches to integrator Window 2. If the integrator output exceeds INT_TH1
again, the gain reduction is repeated until the integrator output no longer exceeds INT_TH1.
The device remains in the reduced gain state until the integrator output falls below INT_TH2 (0x532h, bits 31:24), or the release
threshold. Once the integrator output falls below INT_TH2, the device gain is increased to the original gain setting in 1.5dB steps.
The release time set by bits 14:12 (RL_RES). Following the gain release, the device switches back to integrator Window 1.
Set register 0x531h bit 21 (SODP_EN) = 1 to enable the speaker overdrive protection.
DSP Output Selection
The DSP outputs to the Digital Mixer can be selected from either of the two Array Filter signal paths. This allows the left and right
inputs to be swapped or mixed before being output to the Class Ds. Filter Control Register (0x500h) bits 17:16 (CH1_SEL) the
select the Array filter source for DSP1. Bits 19:18 (CH2_SEL) select the Array filter source for DSP2. Use channel routing to correct
the perceived left/right channel swap that can occur with certain spatial configurations.
Low Power Mode
The LM48903 features three low power modes that enable and disable the device based on the presence of an input signal. Mode
1 monitors the ADC input signal. Mode 2 monitors the ADC output, and offers a faster wake up time (<10ms) compared to Mode
1. Mode 3 monitors the I2S interface and enables the device on the rising edge of WS.
The low power mode is configured through the Low Power Control Register (0x533h) (Table 29). Bit 0 (AUDET_EN) enables the
automatic signal detection. Bits 2:1 (AUDET_LEVEL) set the ADC input threshold. Bits 5:4 (LPWR_MODE) select the operating
mode. Bits 11:8 (TIMEOUT_DLY) sets the delay time between loss of audio signal/WS clock to device disable. Bits 23:12 (ADC_TH)
sets the ADC output threshold.
49
www.ti.com
DIGITAL MIXER
The digital mixer Figure 12 is responsible for routing the digital audio signals within the LM48903. The digital mixer is configured
through the Digital Mixer register (0x522h). There are six inputs to the digital mixer, left and right ADC data, left and right I2S RX
data, and two DSP output channels. ADC and I2S RX data can be routed to the DSP inputs (DSP_L and DSP_R), the class D
amplifiers (OUT1-OUT2), and the I2S TX buses. The DSP output data can be routed to the class D amplifiers, and the I2S TX bus.
The digital mixer includes independent digital gain blocks for the ADC and I2S RX data. The gain range is -76.5dB to 18dB in 1.5dB
steps. The ADC gain is set by bits 5:0 (ADC_LVL) of the Digital Mixer Control Register (0x522h). The I2S gain is set by bits 13:8
(I2S_LVL) of the Digital Mixer Control Register. With a 0dBFS input and I2S_LVL = 110011 (0dB), the output voltage is
3.36VRMS
.
For additional output routing flexibility, use the digital mixer in conjunction with the Array filter channel routing. The Array filter
channel routing control selects which filter channel is output on each DSP output. The DSP must be active to use the Array filter
channel routing, however, no coefficients are required. With no spatial effect, Array filter channel contains left channel audio data,
channel contains right channel audio data. The Array filter channel routing is controlled by bits 19:16 in the Filter Control Register
(0X500h). See DSP Output Selection section.
301858g3
FIGURE 12. Digital Mixer
www.ti.com
50
SPATIAL ENGINE (DSP)
The LM48903 Spatial Engine is a specialized DSP that is optimized for TI’s proprietary spatial audio algorithm. The Spatial Engine
consists of two processing stages, the Pre Filter and Array Filter (Figure 14). The filters perform different portions of the spatial
processing, and are configured and controlled independent of each other. The Pre Filter uses virtual speaker positioning to set the
width of the sound stage. The Array Filter is responsible for equalization and positioning the audio content within the virtual sound
stage created by the Pre Filter.
301858f9
FIGURE 13. DSP Routing
51
www.ti.com
Filter Enable and Filter Bypass
The Pre Filter and Array Filter are enabled independently. Filter Control Register (0x500h) bit 30 (PRE_ENABLE) enables the Pre
Filter, bit 31 (ARRAY_ENABLE) enables the Array Filter. The independent filter enables maximize power savings when only a
portion of the LM48903’s DSP processing is required.
The filter bypass allows audio data to pass through the DSP without any processing. The Pre Filter and Array Filter can be inde-
pendently bypassed. Filter Control Register (0x500h) bit 28 (PRE_BYPASS) bypasses the Pre Filter, bit 29 (ARRAY_BYPASS)
bypasses the Array Filter. When using a portion of the DSP path, bypass the filter that is not in use. Audio data will not pass through
the disabled filter. For example, if the Pre Filter is disabled while the Array Filter is enabled, bypass the Pre Filter.
Compressor
The Pre filter and Array filter each have a compressor that monitors the filter output and maintains the amplitude below the set
threshold (Figure 15). The compressors have four user configurable settings, compressor threshold (COMP_TH), pre-compression
gain (G1_GAIN), compression ratio (COMP_RATIO), and post compression gain (POST_GAIN). COMP_TH sets the threshold
above which the compression is applied to the filter output signal. G1_GAIN sets the gain applied before compression. COMP_RA-
TIO sets the linear compression ratio applied to the filter output signal. POST_GAIN sets the post compression gain, increasing
the compressor output signal when either COMP_TH is low or COMP_RATIO is high.
Compressor Control Register 1 (0x501h) configures the Pre Filter compressor. Bits 4:0 (COMP_TH) set the Pre Filter compressor
threshold. Bits 7:5 (G1_GAIN set the Pre Filter pre-compression gain. Bits 10:8 (COMP_RATIO) set the Pre Filter compression
ratio. Bits 14:12 (POST_GAIN) set the post compression gain.
The Array Filter outputs can be routed through one of two compressors, allowing different signal paths to have different compression
profiles. This feature is useful if the LM48903 outputs are driving different speakers, for example, two tweeters and two subwoofers.
One compression profile is applied to the tweeter channels, while the second compression profile is applied to the subwoofer
channels. Bits 19:16 of Compressor Control Register 1 and Compressor Control Register 2 (0x502h) configure the Array Filter.
Bits 14:0 of the Compressor Control Register 2 configure the Array Filter compressor 0. Bits 30:16 configure the Array Filter
compressor 1. The Compressor Control Register 1 bits 17:16 (ARRAY_COMP_SELECT) selects the compressor setting used by
each Array Filter channel. Bit 16 controls DSP channel 1, bit 17 controls DSP channel 2. Set the desired channel
ARRAY_COMP_SELECT bit = 0 to select compressor 0, set the desired channel ARRAY_COMP_SELECT bit = 1 to select com-
pressor 1.
301858g7
FIGURE 14. DSP Core Diagram
www.ti.com
52
DSP Output Selection
CLOCK REQUIREMENTS
The LM48903 requires an external clock source for proper operation, regardless of input source or device configuration. The device
derives the ADC, digital mixer, DSP, I2S port, and PWM clocks from the external clock. The clock can be derived from either MCLK
or SCLK inputs. Set bit 11 (I2S_CLK) of the Enable and Clock configuration register (0x521h) to 0 to select MCLK, set I2S_CLK to
1 to select SCLK. The LM48903 accepts five different clock frequencies, 1.536, 3.072, 6.114, 12.288, and 24.576MHz. Set bits
10:8 (MCLK_RATE) of the Enable and Clock Configuration Register to the appropriate clock frequency. In systems where both
MCLK and SCLK are available, choose the lower frequency clock for improved power consumption.
SHUTDOWN FUNCTION
There are two ways to shutdown the LM48903, hardware mode, and software mode. The default is hardware mode.
Set bit 1 (FORCE) of the Enable and Clock Configuration Register (0x521h) to 0 to enable hardware shutdown mode. In hardware
mode, the device is enabled and disabled through SHDN. Connect SHDN to VDD for normal operation. Connect SHDN to GND to
disable the device. Hardware shutdown mode supports a one shot, or momentary switch SHDN input. When bit 2 (PULSE) of the
Enable and Clock Configuration Register (0x521h) is set to 1, the LM48903 responds to a rising edge on SHDN to change the
device state. When PULSE = 0, the device requires a stable logic level on SHDN.
Set FORCE = 1 to enable software shutdown mode. In software shutdown mode, the device is enabled and disabled through bit
0 (ENABLE) of the Enable and Clock Configuration Register (0x512h). Set ENABLE = 0 to disable the LM48903. Set ENABLE =
1 to enable the LM48903.
In either hardware or software mode, the content of the LM48903 memory registers is retained after the device is disabled, as long
as power is still applied to the device. Minimize power consumption by disabling the PMC clock oscillator when the LM48903 is
shutdown. Set bit 12 (PMC_CLK_SEL) and bit 14 (QSA_CLK_STOP) of the Enable and Clock configuration Register (0x521h) =
1 to disable the PMC clock oscillator.
EXTERNAL CAPACITOR SELECTION
Power Supply Bypassing and Filtering
Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close
to the device as possible. Typical applications employ a voltage regulator with 10μF and 0.1μF bypass capacitors that increase
supply stability. These capacitors do not eliminate the need for bypassing of the LM48903 supply pins. A 1μF capacitor is recom-
mended for IOVDD, PLLVDD, DVDD, and AVDD. A 2.2μF capacitor is recommended for PVDD
.
REF and BYPASS Capacitor Selection
For best performance, bypass REF with a 4.7μF ceramic capacitor.
53
www.ti.com
INPUT CAPACITOR SELECTION
The LM48903 analog inputs require input coupling capacitors. Input capacitors block the DC component of the audio signal, elim-
inating any conflict between the DC component of the audio source and the bias voltage of the LM48903. The input capacitors
create a high-pass filter with the input resistors RIN. The -3dB point of the high pass filter is found using Equation (1) below.
f = 1 / 2πRINCIN
Where the value of RIN is 20kΩ.
The input capacitors can also be used to remove low frequency content from the audio signal. Small speakers cannot reproduce,
and may even be damaged by low frequencies. High pass filtering the audio signal helps protect the speakers. When the LM48903
is using a single-ended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above
the power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not amplified and
heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance matching and improved CMRR
and PSRR.
PCB LAYOUT GUIDELINES
As output power increases, interconnect resistance (PCB traces and wires) between the amplifier, load, and power supply create
a voltage drop. The voltage loss due to the traces between the LM48903 and the load results in lower output power and decreased
efficiency. Higher trace resistance between the supply and the LM48903 has the same effect as a poorly regulated supply, in-
creasing ripple on the supply line, and reducing peak output power. The effects of residual trace resistance increases as output
current increases due to higher output power, decreased load impedance or both. To maintain the highest output voltage swing
and corresponding peak output power, the PCB traces that connect the output pins to the load and the supply pins to the power
supply should be as wide as possible to minimize trace resistance.
The use of power and ground planes will give the best THD+N performance. In addition to reducing trace resistance, the use of
power planes creates parasitic capacitors that help to filter the power supply line.
The inductive nature of the transducer load can also result in overshoot on one of both edges, clamped by the parasitic diodes to
GND and VDD in each case. From an EMI standpoint, this is an aggressive waveform that can radiate or conduct to other compo-
nents in the system and cause interference. In is essential to keep the power and output traces short and well shielded if possible.
Use of ground planes beads and micros-strip layout techniques are all useful in preventing unwanted interference.
As the distance from the LM48903 and the speaker increases, the amount of EMI radiation increases due to the output wires or
traces acting as antennas become more efficient with length. Ferrite chip inductors places close to the LM48903 outputs may be
needed to reduce EMI radiation.
www.ti.com
54
Revision History
Rev
Date
04/12/12
Description
1.0
Initial WEB released.
55
www.ti.com
Physical Dimensions inches (millimeters) unless otherwise noted
30–pin micro SMD
Order NumberLM48903TL
NS Package Number TLA30HHA
X1 = 2670±0.03mmꢀX2 = 3179±0.03mmꢀX3 = 0.6±0.075mm
www.ti.com
56
Notes
57
www.ti.com
Notes
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Medical
Logic
Security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
相关型号:
©2020 ICPDF网 联系我们和版权申明