LM4930ITLX/NOPB [TI]
具有立体声耳机和单声道扬声器放大器的音频子系统 | YZR | 36 | -30 to 85;
| 型号： | LM4930ITLX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有立体声耳机和单声道扬声器放大器的音频子系统 | YZR | 36 | -30 to 85 放大器 |
| 文件： | 总41页 (文件大小：929K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
LM4930 Boomer™ Audio Power Amplifier Series Audio Subsystem with Stereo
Headphone & Mono Speaker Amplifiers
Check for Samples: LM4930
1
FEATURES
DESCRIPTION
The LM4930 is an integrated audio subsystem that
supports voice and digital audio functions. The
LM4930 includes a high quality I2S input stereo DAC,
a voice band codec, a stereo headphone amplifier
and a high-power mono speaker amplifier. It is
primarily designed for demanding applications in
mobile phones and other portable devices.
23
•
16-bit Resolution 48kHz Stereo DAC
16-bit Resolution 8kHz Voice Codec
I2S Digital Audio Data Serial Interface
Two-wire Serial Control Interface
•
•
•
•
•
•
•
PCM Voice Audio Data Serial Interface
25mW/channel Stereo Headphone Amplifier
330mW Mono 8Ω Amplifier (at AVDD = 3.0V)
The LM4930 features an I2S serial interface for full
range audio,
a 16-bit PCM bi-directional serial
32-step Volume Control for Audio Output
Amplifiers
interface for the voice band codec and an two-wire
interface for control. The full range music path
features an SNR of 86dB with a 16-bit 48kHz input.
The stereo DAC can also be used while the voice
codec is in use. The headphone amplifier delivers
25mWRMS to a 32Ω single-ended stereo load with
less than 0.5% distortion (THD+N) when AVDD = 3V.
The mono speaker amplifier delivers up to 330mW
into an 8Ω load with less than 1% distortion when
AVDD = 3V.
•
No Snubber Networks or Bootstrap Capacitors
are Required by the Headphone or Hands-free
Amplifiers
•
•
•
Digital Sidetone Generation with Adjustable
Attenuation
Gain Controllable Headphone Amp, Mono BTL
Amp, Mic Preamp
The LM4930 employs advanced techniques to reduce
power consumption, to reduce controller overhead
and to eliminate click and pop. Boomer audio power
amplifiers were designed specifically to provide high
quality output power with a minimal amount of
external components. It is, therefore, ideally suited for
mobile phone and other low voltage applications
where minimal power consumption is a primary
requirement.
Available in the 36–bump DSBGA and 44–lead
WQFN Packages
APPLICATIONS
•
•
•
Mobile Phones
Mobile/low Power Audio Appliances
PDAs
KEY SPECIFICATIONS
•
•
•
•
PLS OUT at AVDD = 5.0V, 8Ω 1% THD+N 1W
(typ)
PLS OUT at AVDD = 3.0V, 8Ω 1% THD+N
330mW (typ)
PH/P OUT at AVDD = 3.0V, 32Ω 0.5% THD+N
25mW (typ)
Supply Voltage Range
–
–
DVDD(1) 2.6V to 4.5V
AVDD(1) 2.6V to 5.5V
•
•
Total Shutdown Current 2μA (typ)
PSRR at 217Hz, AVDD = 3V 50dB (typ)
(1) Best operation is achieved by maintaining 3.0V ≤ AVDD ≤ 5.0
and 3.0V ≤ DVDD ≤ 3.6V. AVDD must be equal to or greater
than DVDD. for proper operation.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Boomer is a trademark of Texas Instruments Incorporated.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
Typical Application
IRQ
DAC_REF
BYPASS CAP
MIC_REF
Click and pop
suppression and
REFERENCE
CIRCUIT
SDA
SCL
power up circuits
CTRL
MIC BIAS
ADDR
_
XTAL IN
HP SENSE IN
XTAL
OSC
Power Management and Control
1M
HP SENSE OUT
_
XTAL OUT
MIC+
16
PCMSYNC
22 pF
22 pF
Microphone
Speaker
ADC
MIC-
LS+
PCM
PCMCLK
8 kHz
InOut
LPF
LPF
PCMSDI
DAC
+
AB
AB
AB
PCMSDO
LS-
16
16
HPL
MIXER
I2S
STEREO
DAC
I2SSDI
I2SWS
I2SCLK
16
48 kHz
Input
Headphones
2 x 25 mW
HPR
Figure 1. Typical I2S + Voice Codec Application Circuit for Mobile Phones
Connection Diagrams
Top View
Top View
44
38
43 42 41 40 39
37 36 35
34
33
32
NC
1
2
DV _D
DD
MCLK/XTAL_IN
XTAL_OUT
PCM_SYNC
SCL
3
DGND_D
4
31
30
29
28
27
26
25
24
23
SDA
HPSENSE_IN
HPSENSE_OUT
ADDR
5
BYPASS
DAC_REF
6
AV _MIC
DD
7
AV _HP
DD
8
AV _LS
DD
LS+
LS+
LS-
LS-
MIC_REF
MIC_P
9
10
11
12
MIC_N
MIC_BIAS
13
19
14 15 16 17 18
20 21 22
Figure 2. 36 - Bump DSBGA Package
See Package Number YZR0036KRA
Figure 3. 44 - Lead WQFN Package
See Package Number NJN0044A
2
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
Pin Descriptions
Pin No.
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
Pin Name
MIC_P
Description
Microphone positive differential input
MIC_N
Microphone negative differential input
Analog Vdd for microphone preamp
D/A converter reference voltage
AVDD_MIC
DAC_REF
SDA
Two-wire control interface serial data pin
Two-wire control interface serial clock pin
Analog ground for microphone preamp
Microphone bias supply output (2V)
SCL
AGND_MIC
MIC_BIAS
MIC_REF
ADDR
Internal fixed-reference bypass capacitor decoupling pin
Control bus address select pin
PCM serial data in
PCM_SDI
PCM_CLK
AVDD_HP
NC
PCM Serial clock pin
Analog Vdd for headphone amplifier
No Connect
BYPASS
PCM_SYNC
I2S_DATA
DGND_D
HP_L
Half-supply bypass capacitor decoupling pin
PCM Frame sync pin
I2S serial data input
Digital ground
Headphone amplifier connection (Left)
Headphone amplifier connection (Right)
Connection for sense pin of headphone jack
PCM serial data out
HP_R
HPSENSE_IN
PCM_SDO
I2S_CLK
DVDD_D
AGND_HP
LS-
I2S serial bit clock
Digital Vdd
Analog ground for headphone amplifier
Loudspeaker amplifier BTL negative out (-)
HPSENSE_OUT
Logic output pin to indicate headphone connection status. Outputs logic high when HPSENSE_IN is
high and outputs logic low when HPSENSE_IN is low. See Figure 50 for suggested application circuit
E4
E5
E6
F1
F2
F3
F4
F5
F6
IRQ
LM4930 mode status indicator pin
I2S word select
I2S_WS
XTAL_OUT
AGND_LS
LS+
Negative feedback source for external crystal MCLK
Analog ground for loudspeaker amplifier
Loudspeaker amplifier BTL positive out (+)
Analog VDD for loudspeaker amplifier
Digital ground
AVDD_LS
DGND_X
DVDD_X
MCLK/XTAL_IN
Digital VDD
12.288MHz or 24.576MHz Master Clock from crystal (via XTAL OUT) or external source
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
System Control Registers
The LM4930 is controlled with a two-wire serial interface. This interface is used to configure the operating mode,
digital interfaces, and delta-sigma modulators. The LM4930 is controlled by writing information into a series of
write-only registers, each with its own unique 7 bit address. The following registers are programmable:
Table 1. BASIC CONFIGURATION Registers(1)
BASIC CONFIGURATION (XX1000). (Set = logic 1, Clear = logic 0)
BIT
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
RESET
Address
Register
Description
3:0
MODE
The LM4930 can be placed in one of several modes that dictate the basic operation. When a new
mode is selected the LM4930 will change operation silently and will re-configure the power
management profile automatically. The modes are described as follows:(2)
Mode
Mono Speaker
Amplifier Source
Headphone Left
Source
Headphone Right Comment
Source
0000
0001
0010
None
None
Voice
None
None
None
None
None
None
Powerdown mode
Standby mode
Mono speaker
mode
0011
0100
0101
0110
0111
None
Voice
Voice
Headphone call
mode
Voice
Voice
Voice
Conference call
mode
Audio (L+R)
None
None
None
L+R mixed to mono
speaker
Audio (Left)
Audio (Left)
Audio (Right)
Audio (Right)
Headphone stereo
audio
Audio (L+R)
L+R mixed to mono
speaker + stereo
headphone audio
1000
1001
1010
Audio (Left)
Voice
Voice
Mixed Mode
Mixed mode
Mixed Mode
Voice + Audio (Left) Voice
Voice Audio (Left)
Voice
Audio (Left)
4
SOFT_RESET
PCM_LONG
Resets the LM4930, excluding the control registers
If set the PCM interface uses a long frame sync.(3)
5
6
PCM_COMPANDED
PCM_LAW
If set the 8 MSBs are presumed to be companded data and the 8 LSBs are ignored.(3)
If set, the companded G711 data is set to be A-law, else µ-law is assumed(3)
7
8:9
PCM_SYNC_MODE
Sets 1 (00h), 2 (01h) or 4(10h) 16 bit frames per sync. The PCM_SDO pin is tri-stated during the
latter frames.(3)
10
PCM_ALWAYS_ON
This bit should be set if another codec is using the PCM bus. When set, the LM4930 will drive the
clock and sync signals in all modes except Powerdown(3)
11
12
13
14
15
I2S_M/S
I2S_RES
RSVD
I2S master or slave select. If set then I2S = master. Cleared = slave
I2S resolution select. If set then 32 bits per frame. If cleared then 16 bits per frame
RESERVED(4)
RESERVED(4)
RESERVED(4)
RSVD
RSVD
(1) This register is used to configure the I2S and PCM interfaces as well as the 48kHz DAC module. The 7 bit address for the
BASICCONFIG register is XX10000.
(X = 0 if ADDR is set to logic 0)
(X = 1 if ADDR is set to logic 1)
(2) With the exception of Standby Mode, rapid switching between modes should be avoided. Rapid switching between modes will not
ensure that the desired mode will be activated.
(3) It is recommended to alter this bit only while the part is in Powerdown Mode.
(4) Reserved bits should be set to zero when programming the associated register.
4
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
Table 2. VOICE/TEST CONFIG Registers(1)
VOICETESTCONFIG (XX10001). (Set = logic 1, Clear = logic 0)
BIT
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
RESET
Address
Register
Description
0
CLASS
If set, configures the chip for use with an external class D or linear amplifier and turns the BTL
speaker output into a buffer.(2)
4:1
SIDESTONE_ATTEN
Programs the attenuation of the digital sidetone. Attenuation is set as follows:
4:1
Sidetone
4:1
Sidetone Attenuation
Attenuation
0000
0001
0010
0011
0100
0101
0110
0111
Mute
1000
1001
1010
1011
1100
1101
1110
1111
-9dB
-6dB
-3dB
0dB
-30dB
-27dB
-24dB
-21dB
-18dB
-15dB
-12dB
Mute
Mute
Mute
Mute
5
AUTOSIDE
This feature is included for use with the mono speaker in hands-free applications where sidetones
may not be desirable. If set, the sidetone is always muted in modes when voice is played on the
mono speaker (0010, 0100, 1001, and 1010), otherwise the sidetone is present at whatever level is
set in the attenuation conrol register
6
7
CLOCK_DIV
If set, allows for the use of a 24.576MHz crystal. Default setting is for 12.288MHz crystal.(2)
ZXD_DISABLE
Disables the zero crossing detect in the stereo DAC to ensure immediate mode changes rather than
waiting for a zero cross.(3)
8:9
RSVD
RESERVED(4)
10:11
CAP_SIZE
Set to accomodate different bypass capacitor values to give correct turn-off delay and click/pop
performance. Value is set as follows:(2)
10:11
00
Delay
Bypass Capacitor Size
25ms
0.1µF
01
50ms
0.39µF
1µF
10
85ms
11
RESERVED
RESERVED
12
13
14
15
ZXDS_SLOW
MUTE_LS
If set, this forces the stereo DAC outputs to wait for a zero crossing before powering down
If set, mutes the loudspeaker amplifier in any mode where it is not already muted
If set, mutes the headphone amplifier in any mode where it is not already muted
If set, mutes the microphone preamp
MUTE_HP
MUTE_MIC
(1) This register configures the voiceband codec, sidetone attenuation, and selected control functions. The 7 bit address for the VOICE
TESTCONFIG register is XX10001.
(X = 0 if ADDR is set to logic 0)
(X = 1 if ADDR is set to logic 1)
(2) It is recommended to alter this bit only while the part is in Powerdown Mode.
(3) To ensure a successful transistion into Powerdown Mode, ZXD_DISABLE must be set whenever there is no audio input signal present.
(4) Reserved bits should be set to zero when programming the associated register.
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
Table 3. GAIN CONFIG Registers(1)
GAINCONFIG (XX10010). (Set = logic 1, Clear = logic 0)
BIT
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
RESET
Address
Register
Description
Programs the gain of the loudspeaker amplifier. Gain is set as follows:
4:0
LOUDSPKR_GAIN
4:0
Loudspeaker Gain 4:0
Loudspeaker Gain
-10.5dB
-9dB
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
-34.5dB
-33dB
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
-31.5dB
-30dB
-7.5dB
-6dB
-28.5dB
-27dB
-4.5dB
-3dB
-25.5dB
-24dB
-1.5dB
0dB
-22.5dB
-21dB
1.5dB
3dB
-19.5dB
-18dB
4.5dB
6dB
-16.5dB
-15dB
7.5dB
9dB
-13.5dB
-12dB
10.5dB
12dB
9:5
HP_GAIN
Programs the gain of the headphone amplifier. Gain is set as follows:
9:5
Headphone Gain
-46dB
9:5
Headphone Gain
-22.5dB
-21dB
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
-45dB
-43.5dB
-42db
-19.5dB
-18dB
-40.5dB
-39dB
-16.5dB
-15dB
-37.5dB
-36dB
-13.5dB
-12dB
-34.5dB
-33dB
-10.5dB
-9dB
-31.5dB
-30dB
-7.5dB
-6dB
-28.5dB
-27dB
-4.5dB
-3dB
-25.5dB
-24dB
-1.5dB
0dB
13:10
MIC_GAIN
Programs the gain of the microphone amplifier. Gain is set as follows:
(1) This register is used to control the gain of the headphone amplifier, the loudspeaker amplifier, and the microphone preamplifier. The 7
bit address for the GAINCONFIG register is XX10010.
(X = 0 if ADDR is set to logic 0)
(X = 1 if ADDR is set to logic 1)
6
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
Table 3. GAIN CONFIG Registers(1) (continued)
13:10
0000
Mic Preamp Gain
17dB
0001
19dB
0010
21dB
0011
23dB
0100
25dB
0101
27dB
0110
29dB
0111
31dB
1000
33dB
1001
35dB
1010
37dB
1011
39dB
1100
41dB
1101
43dB
1110
45dB
1111
47dB
15:14
RSVD
RESERVED(2)
(2) Reserved bits should be set to zero when programming the associated register.
Timing Diagrams
Figure 4. Two-Wire Control Interface Timing Diagram
Figure 5. PCM Receive Timing Diagram
Figure 6. I2S Transmit Timing Diagram
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)
Analog Supply Voltage
Digital Storage Supply Voltage
Storage temperature
Power Dissipation(4)
6.0V
6.0V
-65°C to +150°C
Internally Limited
2000V
ESD Susceptibility
Human Body Model(5)
Machine Model(6)
200V
Junction temperature
Thermal Resistance
150°C
θJA - YZR0036KRA
θJA - NJN0044A(7)
105°C/W
27°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specifies specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) All voltages are measured with respect to the relevant GND pin unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM4930, see power derating currents for more information.
(5) Human body model: 100pF discharged through a 1.5kΩ resistor.
(6) Machine model: 220pF - 240pF discharged through all pins.
(7) The given θA is for an LM4930 packaged in an NJN0044A with the Exposed-DAP soldered to an exposed 2in2 area of 1oz printed circuit
board copper with 16 thermal vias as described in AN-1187.
Operating Ratings(1)
Temperature Range
T
MIN ≤ TA ≤ TMAX
−30°C ≤ TA ≤ +85°C
2.6V - 4.5V
(2)
Supply Voltage
DVDD
AVDD
(2)
2.6V - 5.5V
(1) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM4930, see power derating currents for more information.
(2) Best operation is achieved by maintaining 3.0V ≤ AVDD ≤ 5.0 and 3.0V ≤ DVDD ≤ 3.6V. AVDD must be equal to or greater than DVDD. for
proper operation.
8
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
Electrical Characteristics DVDD = 3.3V, AVDD = 5V, RLHP = 32Ω, RLHF = 8Ω(1)(2)(3)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25°C.
LM4930
Units
(Limits)
Parameter
Test Conditions
Typ(4)
Limits(5)(6)
fMCLK = 12.288MHz
Output Mode = "0010"
Output Mode = "0011"
Output Mode = "0100"
2
Output Mode = "0101"
Output Mode = "0110"
Output Mode = "0111"
DIDD
Digital Power Supply Current
4.4
4.9
Output Mode = "1000"
Output Mode = "1001"
Output Mode = "1010"
8
mA (max)
fMCLK = 12.288MHz; No Load
Output Mode = "0010"
Output Mode = "0011"
Output Mode = "0100"
Output Mode = "0101"
Output Mode = "0110"
Output Mode = "0111"
7.0
6.3
8.0
8.2
7.4
8.7
Analog Power Supply Quiescent
Current
AIDD
Output Mode = "1000"
Output Mode = "1001"
Output Mode = "1010"
9.5
1
14
7
mA (max)
µA (max)
DISD
Digital Powerdown Current
Analog Powerdown Current
Digital Standby Current
Analog Standby Current
fMCLK = 12.288MHz
Output Mode = "0000" Powerdown Mode
AISD
fMCLK = 12.288MHz
Output Mode = "0000" Powerdown Mode
1
2
2
µA (max)
mA (max)
DIST
fMCLK = 12.288MHz
Output Mode = "0001" Standby Mode
1.4
AIST
fMCLK = 12.288MHz
Output Mode = "0001" Standby Mode
CLASS = 0; 0dB gain setting; 8Ω BTL load(7)
0dB gain setting; 32Ω Stereo Load(7)
230
2.5
1000
µA (max)
VP-P
VFS_LS
VFS_HP
Full-Scale Output Voltage
(Mono speaker amplifier)
Full-Scale Output Voltage
(Headphone amplifier)
2.5
VP-P
VMIC_BIAS Mic Bias Voltage
2.0
V
THD+N
Headphone Amplifier Total
Harmonic Motion Distortion + Noise
fIN = 1 kHz, POUT = 7.5mW; 32Ω Stereo Load
0.07
%
POHP
POLS
Headphone Amplifier Output Power THD+N = 0.5%, fOUT = 1kHz
27
1
20
45
mW (min)
W
Mono Speaker Amplifier Output
Power
THD+N = 1%, fOUT = 1kHz
PSRR
Power Supply Rejection Ratio
CBYPASS = 1.0µF
55
dB (min)
CDAC_REF = 1.0µF
VRIPPLE = 200mVP-P @ 217Hz, MIC_P,
MIC_N terminated with 10Ω to ground
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specifies specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) All voltages are measured with respect to the relevant GND pin unless otherwise specified.
(3) Best operation is achieved by maintaining 3.0V ≤ AVDD ≤ 5.0 and 3.0V ≤ DVDD ≤ 3.6V. AVDD must be equal to or greater than DVDD. for
proper operation.
(4) Typicals are measured at 25°C and represent the parametric norm.
(5) Limits are specified to Texas Instrument’s AOQL (Average Outgoing Quality Level).
(6) Datasheet min/max specification limits are ensured by design, test, or statistical analysis.
(7) This value represents the 0dB output level of the given amplifier for the given analog supply voltage. Gain values given in the
GAINCONFIG register are relative to these full-scale values for each output amplifier.
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
Electrical Characteristics DVDD = 3.3V, AVDD = 5V, RLHP = 32Ω, RLHF = 8Ω(1)(2)(3) (continued)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25°C.
LM4930
Units
(Limits)
Parameter
Test Conditions
Typ(4)
Limits(5)(6)
SNR
(Voice)
Signal-to-Noise Ratio
(Voice DAC Path)
Signal = Vo at f = 1kHz @1% THD+N, 32Ω
Stereo Load; Noise = digital zero, A-
weighted, 0dB gain setting
72
86
72
86
75
dB
dB
dB
dB
dB
SNR
(Music)
Signal-to-Noise Ratio (Music Audio
Path)
Signal = Vo at f = 1kHz @1% THD+N, 32Ω
Stereo Load; Noise = digital zero, A-
weighted; 0dB gain setting
DR
(Voice)
Dynamic Range (Voice DAC Path)
Signal = Vo at f = 1kHz @1% THD+N, 32Ω
Stereo Load; Noise for -60dBFS digital input;
A-weighted; 0dB gain setting
DR
(Music)
Dynamic Range (Music Audio Path) Signal = Vo at f=1kHz @1% THD+N, 32Ω
Stereo Load; Noise for -60dBFS digital input;
A-weighted, 0dB gain setting
SNRADC Signal-to-Noise Ratio
(Voice ADC Path)
Reference signal = 0dBFS
MIC_P, MIC_N terminated with 10Ω to
ground;
A-weighted; 47dB MIC preamp gain setting
DRADC
Dynamic Range
Reference signal = 0dBFS
75
dB
(Voice ADC Path)
Noise for -60dBFS digital input;
A-weighted; 47dB MIC preamp gain setting
XTALK
Stereo Channel-to-Channel
Crosstalk
fS = 48kHz, fIN = 1kHz sinewave at -3dBFS
75
dB
VMIC-IN
Maximum Differential MIC Input
Voltage
17dB MIC Preamp gain setting
570
mVP-P
RVDAC
RVADC
PBVDAC
Voice DAC Ripple
Voice ADC Ripple
Voice DAC Passband
300Hz - 3.3kHz through head-phone output.
300Hz - 3.3kHz through head-phone output.
-3dB Point
+/-0.15
+/-0.25
3.46
+/-0.2
+/-0.3
dB (max)
dB (max)
kHz
SBAVDAC Voice DAC Stopband Attenuation
Above 4kHz
72
dB
UPBVADC Voice ADC Upper Passband Cutoff
Frequency.
Upper -3dB Point
3.47
kHz
LPBVADC Voice ADC Lower Passband Cutoff
Frequency.
Lower -3dB Point
0.230
kHz
SBAVADC Voice ADC Stopband Attenuation
Above 4kHz
65
58
dB
dB
SBANOTC Voice ADC Notch Attenuation
H
Centered on 55Hz, figure gives worst case
attenuation for 50Hz & 60Hz.
RDAC
Audio DAC Ripple
20Hz - 20kHz through head-phone output.
+/-0.1
22.7
76
+/-0.2
dB (max)
kHz
PBDAC
SBADAC
DRDAC
Audio DAC Passband Width
Audio DAC Stopband Attenuation
-3dB point
Above 24kHz
dB
Audio DAC Dynamic Range Digital
Filter Section
Signal = VO at f = 1kHz @ 1% THD+N;
f = 1kHz; Noise for -60dBFS digital input;
0dB gain; A-weighted
97
dB
SNRDAC Audio DAC SNR Digital Filter
Section
Signal = VO at f = 1kHz @ 1% THD+N;
f = 1kHz; Noise for -60dBFS digital input;
0dB gain; A-weighted
97
dB
ΔACH-CH Stereo Channel-to-Channel Gain
0.3
0.4
1.4
dB
V
Mismatch
VIL
VIH
Digital Input: Logic Low Voltage
Level
Digital Input: Logic High Voltage
Level
V
Volume Control Range (Headphone Maximum Attenuation
-46.5
0
dB
dB
amplifiers)
Minimum Attenuation
Volume Control Range (Mono
speaker amplifier)
Minimum Gain
Maximum Gain
-34.5
12
dB
dB
10
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
Electrical Characteristics DVDD = 3.3V, AVDD = 5V, RLHP = 32Ω, RLHF = 8Ω(1)(2)(3) (continued)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25°C.
LM4930
Units
(Limits)
Parameter
Test Conditions
Typ(4)
Limits(5)(6)
Volume Control Step Size (Output
amplifiers)
1.5
dB
Volume Control Range (Microphone Minimum Gain
17
47
dB
dB
Preamp)
Maximum Gain
Volume Control Step Size
(Microphone Preamp)
2
dB
Side Tone Attenuation Range
Maximum Attenuation
Minimum Attenuation
-30
0
dB
dB
Side Tone Attenuation Step Size
MCLK frequency
3
dB
fMCLK
CLOCK_DIV = 0
CLOCK_DIV = 1
12.288
24.576
MHz
MHz
MCLK Duty Cycle
50
40
60
% (min)
% (max)
fCONV
Sampling Clock Frequency(8)
SCL_CLK Frequency
48
kHz
kHz
ns
fCLKSCL
tRISESCL
tFALLSCL
tSDAH
400
300
300
500
500
SCL_CLK, SCL_DATA Rise Time
SCL_CLK, SDA_DATA Fall Time
SDA_DATA Hold Time
ns
ns
tSDAS
SDA_DATA Setup Time
ns
fCLKPCM
PCM_CLK Frequency
PCM_SYNC_MODE = 00
PCM_SYNC_MODE = 01
PCM_SYNC_MODE = 10
128
256
512
kHz
PCM_CLK Duty Cycle
I2S_CLK Frequency
I2S_CLK Duty Cycle
50
40
60
% (min)
% (max)
fCLKI2S
I2S_RES = 0
I2S_RES = 1
1.536
3.072
MHz
50
40
60
% (min)
% (max)
(8) The sampling clock frequency is equal to the master clock frequency divided by 256. (fconv = fMCLK/256)
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
Electrical Characteristics DVDD = 3V, AVDD = 3V, RLHP = 32Ω, RLHF = 8Ω(1)(2)(3)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25°C.
LM4930
Units
(Limits)
Parameter
Test Conditions
Typ(4)
Limits(5)(6)
fMCLK = 12.288MHz
Output Mode = "0010"
Output Mode = "0011"
Output Mode = "0100"
1.6
3.8
4.2
Output Mode = "0101"
Output Mode = "0110"
Output Mode = "0111"
DIDD
Digital Power Supply Current
Output Mode = "1000"
Output Mode = "1001"
Output Mode = "1010"
7
mA (max)
fMCLK = 12.288MHz; No Load
Output Mode = "0010"
Output Mode = "0011"
Output Mode = "0100"
Output Mode = "0101"
Output Mode = "0110"
Output Mode = "0111"
5.8
5.1
6.5
6.4
5.8
7.0
Analog Power Supply Quiescent
Current
AIDD
Output Mode = "1000"
Output Mode = "1001"
Output Mode = "1010"
7.5
1
12
7
mA (max)
µA (max)
DISD
Digital Powerdown Current
Analog Powerdown Current
Digital Standby Current
Analog Standby Current
fMCLK = 12.288MHz
Output Mode = "0000" Powerdown Mode
AISD
fMCLK = 12.288MHz
Output Mode = "0000" Powerdown Mode
0.6
1.1
1.5
1.7
300
µA (max)
mA (max)
DIST
fMCLK = 12.288MHz
Output Mode = "0001" Standby Mode
AIST
fMCLK = 12.288MHz
Output Mode = "0001" Standby Mode
CLASS = 0; 0dB gain setting; 8Ω BTL load(7)
0dB gain setting; 32Ω Stereo Load(7)
100
2.5
µA (max)
VP-P
VFS_LS
VFS_HP
Full-Scale Output Voltage
(Mono speaker amplifier)
Full-Scale Output Voltage
(Headphone amplifier)
2.5
VP-P
VMIC_BIAS Mic Bias Voltage
2
V
THD+N
Headphone Amplifier Total
Harmonic Distortion + Noise
fIN = 1kHz, POUT = 7.5mW
0.07
%
POHP
POLS
Headphone Amplifier Output Power THD+N = 0.5%, fOUT = 1kHz
25
15
mW (min)
mW (min)
Mono Speaker Amplifier Output
Power
THD+N = 1%, fOUT = 1kHz
330
270
PSRR
Power Supply Rejection Ratio
CBYPASS = 1.0µF
50
42
dB (min)
CDAC_REF = 1.0µF
VRIPPLE = 200mVP-P @ 217Hz
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specifies specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) All voltages are measured with respect to the relevant GND pin unless otherwise specified.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM4930, see power derating currents for more information.
(4) Typicals are measured at 25°C and represent the parametric norm.
(5) Limits are specified to Texas Instrument’s AOQL (Average Outgoing Quality Level).
(6) Datasheet min/max specification limits are ensured by design, test, or statistical analysis.
(7) This value represents the 0dB output level of the given amplifier for the given analog supply voltage. Gain values given in the
GAINCONFIG register are relative to these full-scale values for each output amplifier.
12
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
Electrical Characteristics DVDD = 3V, AVDD = 3V, RLHP = 32Ω, RLHF = 8Ω(1)(2)(3) (continued)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25°C.
LM4930
Units
(Limits)
Parameter
Test Conditions
Typ(4)
Limits(5)(6)
SNR
(Voice)
Signal-to-Noise Ratio
(Voice DAC Path)
Signal = Vo at f = 1kHz @1% THD+N, 32Ω
Stereo Load; Noise = digital zero, A-
weighted; 0dB gain setting
72
86
72
86
75
dB
dB
dB
dB
dB
SNR
(Music)
Signal-to-Noise Ratio (Music Audio
Path)
Signal = Vo at f = 1kHz @1% THD+N, 32Ω
Stereo Load; Noise = digital zero, A-
weighted; 0dB gain setting
DR
(Voice)
Dynamic Range (Voice DAC Path)
Signal = Vo at f = 1kHz @1% THD+N, 32Ω
Stereo Load; Noise for -60dBFS digital input;
A-weighted, 0dB gain setting
DR
(Music)
Dynamic Range (Music Audio Path) Signal = Vo at f=1kHz @1% THD+N, 32Ω
Stereo Load; Noise for -60dBFS digital input;
A-weighted, 0dB gain setting
SNRADC Signal-to-Noise Ratio
(Voice ADC Path)
Reference signal = 0dBFS
MIC_P, MIC_N terminated with 10Ω to
ground;
A-weighted; 47dB MIC preamp gain setting
DRADC
Dynamic Range
Reference signal = 0dBFS
75
dB
(Voice ADC Path)
Noise for -60dBFS digital input;
A-weighted; 47dB MIC preamp gain setting
XTALK
Stereo Channel-to-Channel
Crosstalk
fS = 48kHz, fIN = 1kHz sinewave at -3dBFS
73
dB
VMIC-IN
Maximum Differential MIC Input
Voltage
17dB MIC Preamp gain setting
570
mVP-P
RVDAC
RVADC
PBVDAC
Voice DAC Ripple
Voice ADC Ripple
Voice DAC Passband
300Hz - 3.3kHz through head-phone output.
300Hz - 3.3kHz through head-phone output.
-3dB Point
+/-0.15
+/-0.25
3.46
+/-0.2
+/-0.3
dB (max)
dB (max)
kHz
SBAVDAC Voice DAC Stopband Attenuation
Above 4kHz
72
dB
UPBVADC Voice ADC Upper Passband Cutoff
Frequency.
Upper -3dB Point
3.47
kHz
LPBVADC Voice ADC Lower Passband Cutoff
Frequency.
Lower -3dB Point
0.230
kHz
SBAVADC Voice ADC Stopband Attenuation
Above 4kHz
65
58
dB
dB
SBANOTC Voice ADC Notch Attenuation
H
Centered on 55Hz, figure gives worst case
attenuation for 50Hz & 60Hz.
RDAC
Audio DAC Ripple
20Hz - 20kHz through head-phone output.
+/-0.1
22.7
76
+/-0.2
dB (max)
kHz
PBDAC
SBADAC
DRDAC
Audio DAC Passband Width
Audio DAC Stopband Attenuation
-3dB point
Above 24kHz
dB
Audio DAC Dynamic Range Digital
Filter Section
Signal = VO at f = 1kHz @ 1% THD+N;
f = 1kHz; Noise for -60dBFS digital input;
0dB gain; A-weighted
97
dB
SNRDAC Audio DAC SNR Digital Filter
Section
Signal = VO at f = 1kHz @ 1% THD+N;
f = 1kHz; Noise for -60dBFS digital input;
0dB gain; A-weighted
97
dB
ΔACH-CH Stereo Channel-to-Channel Gain
0.3
0.4
1.4
dB
V
Mismatch
VIL
VIH
Digital Input: Logic Low Voltage
Level
Digital Input: Logic High Voltage
Level
V
Volume Control Range (Headphone Maximum Attenuation
-46.5
0
dB
dB
amplifiers)
Minimum Attenuation
Volume Control Range (Mono
speaker amplifier)
Minimum Gain
Maximum Gain
-34.5
12
dB
dB
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
Electrical Characteristics DVDD = 3V, AVDD = 3V, RLHP = 32Ω, RLHF = 8Ω(1)(2)(3) (continued)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25°C.
LM4930
Units
(Limits)
Parameter
Test Conditions
Typ(4)
Limits(5)(6)
Volume Control Step Size (Output
amplifiers)
1.5
dB
dB
dB
Volume Control Range (Microphone Minimum Gain
Preamp)
17
47
Maximum Gain
Volume Control Step Size
(Microphone Preamp)
2
Side Tone Attenuation Range
Maximum Attenuation
Minimum Attenuation
-30
0
dB
dB
Side Tone Attenuation Step Size
MCLK frequency
3
dB
fMCLK
CLOCK_DIV = 0
CLOCK_DIV = 1
12.288
24.576
MHz
MHz
40
60
% (min)
% (max)
MCLK Duty Cycle
50
fCONV
Sampling Clock Frequency
SCL_CLK Frequency
See(8)
48
kHz
kHz
ns
fCLKSCL
tRISESCL
tFALLSCL
tSDAH
400
300
300
500
500
SCL_CLK, SCL_DATA Rise Time
SCL_CLK, SDA_DATA Fall Time
SDA_DATA Hold Time
ns
ns
tSDAS
SDA_DATA Setup Time
PCM_CLK Frequency
ns
fCLKPCM
PCM_SYNC_MODE = 00
PCM_SYNC_MODE = 01
PCM_SYNC_MODE = 10
128
256
512
kHz
kHz
kHz
40
60
% (min)
% (max)
PCM_CLK Duty Cycle
I2S_CLK Frequency
50
fCLKI2S
I2S_RES = 0
I2S_RES = 1
1.536
3.072
MHz
MHz
40
60
% (min)
% (max)
I2S_CLK Duty Cycle
50
(8) The sampling clock frequency is equal to the master clock frequency divided by 256. (fconv = fMCLK/256)
14
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
(1)
Typical Performance Characteristics
MIC PreAmp + ADC Frequency Response
(MIC Gain = 17dB)
MIC PreAmp + ADC Frequency Response Zoom
(MIC Gain = 17dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
20
50 100 200
500 1k 2k 4k
500 1k 1.5k 2k 2.5k 3k 3.5k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7.
Figure 8.
MIC PreAmp + ADC Frequency Response
(MIC Gain = 47dB)
MIC PreAmp + ADC Frequency Response Zoom
(MIC Gain = 47dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
20
50 100 200 500 1k
2k 4k
500 1k 1.5k 2k 2.5k 3k 3.5k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9.
Figure 10.
MIC PreAmp + ADC Frequency Response High Cutoff
(MIC Gain = 17dB)
MIC PreAmp + ADC Frequency Response High Cutoff
(MIC Gain = 47dB)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-
10
-
20
-
30
-
40
-
50
-
60
-
70
-
80
3k
3.5k
4k
4.5k
5k
3k
3.5k
4k
4.5k
5k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11.
Figure 12.
(1) 0dBm0 = -3dBFS for the PCM voice codec and 0dBm0 = -1dBFS for the I2S DAC, unless otherwise specified.
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
15
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (1) (continued)
MIC PreAmp + ADC Frequency Response Low Cutoff
(MIC Gain = 17dB)
MIC PreAmp + ADC Frequency Response Low Cutoff
(MIC Gain = 47dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
-30
-40
-50
-60
-70
-80
100
200
300
400
500
100
200
300
400
500
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13.
Figure 14.
ADC THD+N
vs
MIC Input Voltage
(MIC Gain = 17dB)
ADC THD+N
vs
MIC Input Voltage
(MIC Gain = 47dB)
10
10
5
5
2
1
0.5
2
1
0.5
0.2
0.1
0.05
0.2
0.1
0.02
0.01
0.05
0.005
0.02
0.01
0.002
0.001
600m 1m 2m
5m 10m 20m 50m
1m 2m 5m10m 20m 50m100m 500m 1
MIC INPUT VOLTAGE (V )
PP
MIC INPUT VOLTAGE (V
)
PP
Figure 15.
Figure 16.
MIC PreAmp + ADC PSRR
vs
Frequency
Headphone Sense In Hysteresis Loop
(AVDD = 3V)
Top Trace = 47dB MIC Gain, Bottom Trace = 17dB MIC Gain
0
3
2.5
2
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1.5
1
0.5
0
200 300 500 800 1k
2k 3k
0
0.5
1
1.5
2
2.5
3
HEADPHONE SENSE IN (V)
FREQUENCY (Hz)
Figure 17.
Figure 18.
16
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
Typical Performance Characteristics (1) (continued)
Headphone Sense In Hysteresis Loop
I2S DAC Frequency Response
( Handsfree Output)
(AVDD = 5V)
5
1
0
4
3
2
1
0
-1
-2
-3
-4
-5
-6
0
1
2
3
4
5
20 50 100 200 500 1k 2k 5k 10k 20k
HEADPHONE SENSE IN (V)
FREQUENCY (Hz)
Figure 19.
Figure 20.
I2S DAC Frequency Response Zoom
I2S DAC Frequency Response Zoom
(Handsfree Output)
(Headphone Output)
0.4
1
0.3
0.2
0.1
0
0
-1
-2
-3
-4
-5
-0.1
-0.2
-0.3
-0.4
-6
5k
10k
15k
20k
20 50 100 200 500 1k 2k 5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21.
Figure 22.
THD+N
vs
I2S DAC Frequency Response Zoom
I2S Input Voltage
(Headphone Output)
(Handsfree Output, 0dB Handsfree Gain)
0.4
10
5
0.3
0.2
0.1
0
2
1
0.5
0.2
0.1
0.05
-0.1
-0.2
-0.3
-0.4
0.02
0.01
0.005
0.002
0.001
5k
10k
15k
20k
1m 2m 5m10m 20m50m100m 500m 1
FREQUENCY (Hz)
2
I S INPUT VOLTAGE (FFS)
Figure 23.
Figure 24.
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (1) (continued)
THD+N
vs
I2S Input Voltage
I2S DAC Crosstalk
(Headphone Output, 0dB Headphone Gain)
(Top Trace = Left to Right, Bottom Trace = Right to Left)
0
10
5
-10
-20
-30
-40
-50
-60
-70
-80
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
-90
20 50 100 200 500 1k 2k 5k 10k 20k
1m 2m 5m10m 20m 50m100m 500m 1
2
FREQUENCY (Hz)
I S INPUT VOLTAGE (FFS)
Figure 25.
Figure 26.
MIC Bias Dropout Voltage vs
MIC Bias Current
PCM DAC Frequency Response
(Handsfree Output)
2.5
2
0
-10
-20
-30
-40
-50
-60
-70
-80
1.5
1
0.5
0
20
50 100 200 500 1k
2k 4k
0
2
4
6
8
10 12 14 16 18
FREQUENCY (Hz)
MIC BIAS CURRENT (mA)
Figure 27.
Figure 28.
PCM DAC Frequency Response Zoom
PCM DAC Frequency Response
(Headphone Output)
0
(Handsfree Output)
0.
4
0.
3
0.
2
0.
1
0
-
0.1
-
0.2
-
0.3
-
-10
-20
-30
-40
-50
-60
-70
-80
0.4
20
50 100 200 500 1k 2k 4k
FREQUENCY (Hz)
2
0
5
0
10 20
50
0
1
k
2
k
4
k
0
0
FREQUENCY (Hz)
Figure 29.
Figure 30.
18
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
Typical Performance Characteristics (1) (continued)
THD+N
vs
PCM DAC Frequency Response Zoom
PCM Input Voltage
(Headphone Output)
(Handsfree Output, 0dB Handsfree Gain)
0.4
10
5
0.3
0.2
0.1
0
2
1
0.5
0.2
0.1
0.05
-0.1
-0.2
-0.3
-0.4
0.02
0.01
0.005
0.002
0.001
1k
2k
3k
4k
1m 2m 5m10m 20m 50m100m 500m 1
FREQUENCY (Hz)
PCM INPUT VOLTAGE (FFS)
Figure 31.
Figure 32.
THD+N
vs
PCM Input Voltage
Crosstalk
(Headphone Output, 0dB Headphone Gain)
(AVDD = 5V and AVDD = 3V, Headphone Output)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
20
100
1k
10k 20k
1m 2m 5m10m 20m 50m100m 500m 1
FREQUENCY (Hz)
PCM INPUT VOLTAGE (FFS)
Figure 33.
Figure 34.
PSRR
PSRR
vs
vs
Frequency
(AVDD = 3V, RL = 16Ω, Headphone Output)
Frequency
(AVDD = 3V, RL = 32Ω, Headphone Output)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
100
1k
10k
100k
20
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 35.
Figure 36.
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (1) (continued)
PSRR
PSRR
vs
vs
Frequency
(AVDD = 3V, RL = 8Ω, Handsfree Output)
Frequency
(AVDD = 5V, RL = 16Ω, Headphone Output)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
100
1k
10k
100k
20
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 37.
Figure 38.
PSRR
vs
PSRR
vs
Frequency
Frequency
(AVDD = 5V, RL = 32Ω, Headphone Output)
(AVDD = 5V, RL = 8Ω, Handsfree Output)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
100
1k
10k
100k
20
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 39.
Figure 40.
THD+N
vs
THD+N
vs
Frequency
Frequency
(AVDD = 5V and AVDD = 3V, RL = 16Ω, PO = 15mW,
(AVDD = 3V, RL = 8Ω, PO = 150mW, Handsfree Output)
Headphone Output)
10
10
5
2
1
1
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
20
100
1k
10k 20k
20 50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 41.
Figure 42.
20
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
Typical Performance Characteristics (1) (continued)
THD+N
THD+N
vs
Frequency
vs
Frequency
(AVDD = 5V and AVDD = 3V, RL = 32Ω, PO = 7.5mW,
Headphone Output)
(AVDD = 5V, RL = 8Ω, PO = 250mW, Handsfree Output)
10
10
5
2
1
1
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
20
100
1k
10k 20k
20 50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 43.
Figure 44.
THD+N
vs
THD+N
vs
Output Power
Output Power
AVDD = 3V, RL = 16Ω, f = 1kHz, Headphone Output)
(AVDD = 3V, RL = 8Ω, f = 1kHz, Handsfree Output)
10
10
5
2
1
1
0.1
0.5
0.2
0.1
0.05
0.02
0.01
0.01
1
10
100
10m 20m
50m 100m 200m 500m
1
OUTPUT POWER (mW)
OUTPUT POWER (W)
Figure 45.
Figure 46.
THD+N
vs
THD+N
vs
Output Power
Output Power
(AVDD = 5V and AVDD = 3V, RL = 32Ω, f = 1kHz, Headphone
(AVDD = 5V and AVDD = 3V, RL = 16Ω, f = 1kHz, Headphone
Output)
Output)
10
10
1
1
0.1
0.01
0.1
0.01
1
10
OUTPUT POWER (mW)
Figure 47.
50
1
10
100
OUTPUT POWER (mW)
Figure 48.
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (1) (continued)
THD+N
vs
Output Power
(AVDD = 5V, RL = 8Ω, f = 1kHz, Handsfree Output)
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
10m 20m 50m 100m 200m 500m
1
2
OUTPUT POWER (W)
Figure 49.
22
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
APPLICATION INFORMATION
REFERENCE DESIGN BOARD AND LAYOUT
LM4930ITL Board Layout
Figure 50. LM4930ITL Demo Board Schematic
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
Figure 51. LM4930ITL Demo Board Composite View
Figure 52. LM4930ITL Demo Board Silkscreen
24
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
Figure 53. LM4930ITL Demo Board Top Layer
Figure 54. LM4930ITL Demo Board Bottom Layer
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
Figure 55. LM4930ITL Demo Board Inner Layer 1
Figure 56. LM4930ITL Demo Board Inner Layer 2
26
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
Figure 57. Pin Markings for LM4930ITL demo board
BILL OF MATERIALS FOR LM4930
Table 4. LM4930 Demo Board Bill Of Materials
Comment
1k
Footprint
0805
0805
0805
0805
0805
1210
1210
1210
1210
7243
7243
Designators
R6, R7
2k
R2, R3
20k
R1
100k
R5
1M
R4
22pF
C6, C7
0.01µF cer
0.1µF cer
1µF
C16, C17
C14, C15
C1, C2, C3, C4, C5, C10, C11, C12, C13
220µF
CRYSTAL
C8, C9
Y1
PHONE JACK STEREO SW STEREO HEADPHONE JACK (3.5MM) J8
Table 5. Two-Wire Control Interface (J1)
Pin
1
Function
DVDD
SCL
2
3
DGND
NC
4
5
DGND
SDA
6
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
Table 6. PCM Interface (P4, P3, P1, P2)
Header
P1
Function
PCM_SDI
PCM_CLK
PCM_SYNC
PCM_SDO
P2
P3
P4
Table 7. I2S Interface (J2)
Pin
1
Function
MCLK
2
I2S-CLK
I2S-DATA
I2S-WS
DGND
3
4
5
6
DGND
7
DGND
8
DGND
9
DGND
10
DGND
Table 8. MIC Jack
Pin
1
Function
AGND
MIC-
2
3
MIC+
Table 9. Misc Jumpers and Headers
DVDD/DGND (J10)
Pin
1
Function
DGND
2
AVDD
Table 10. Misc Jumpers and Headers
AVDD/AGND (J9)
Pin
1
Function
AGND
2
AVDD
Table 11. Misc Jumpers and Headers
MCLK/XTAL_IN (P5)
Pin
1
Function
DGND
2
MCLK/XTAL_IN
28
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
ADR SELECT (S1)
Jumper IN = LOW
Control interface responds to addresses 001000b (BASICCONFIG), 0010001b (VOICETESTCONFIG)), and
0010010b (GAINCONFIG)
Jumper OUT = HIGH
Control interface responds to addresses 111000b (BASICCONFIG), 1110001b (VOICETESTCONFIG)), and
1110010b (GAINCONFIG)
Table 12. HP Sense Out (J6)
Pin
1
Function
AGND
2
HPSense_Out
Table 13. IRQ (J4)
Pin
1
Function
DGND
IRQ
2
Onboard MCLK Select (S2)
Jumper IN = Onboard MCLK
Jumper OUT = External MCLK
LM4930ITL DEMO BOARD OPERATION
The LM4930ITL demo board is a complete evaluation platform, designed to give easy access to the control pins
of the part and comprise all the necessary external passive components. Besides the separate analog (J9) and
digital (J10) supply connectors, the board features seven other major input and control blocks: a two wire
interface bus (J1) for the control lines, a PCM interface bus (P1-P4) for voiceband digital audio, an I2S interface
bus (J2) for full-range digital audio, an analog mic jack input (J3) for connection to an external microphone, a
BTL mono output (J7) for connection to an external speaker, a stereo headphone output (J8), and an external
MCLK input (P5) for use in place of the crystal on the demoboard.
Two-wire Interface Bus (J1)
This is the main control bus for the LM4930. It is a two-wire interface with an SDA line (data) and SCL line
(clock). Each transmission from the baseband controller to the LM4930 is given MSB first and must follow the
timing intervals given in the Electrical Characteristics section of the datasheet to create the start and stop
conditions for a proper transmission. The start condition is detected if SCL is high on the falling edge of SDA.
The stop condition is detected if SCL is high on the rising edge of SDA. Repeated start signals are handled
correctly. Data is then transmitted as shown in Figure 4. After the start condition has been achieved the chip
address is sent, followed by a set write bit, wait for ack (SDA will be pulled low by LM4930), data bits 15-8, wait
for ACK (SDA will be pulled low by LM4930), data bits 7-0, wait for ACK (SDA will be pulled low by LM4930)and
finally the stop condition is given.
This same sequence follows for any control bus transmission to the LM4930. The chip address is hardwire
selected by the ADR Select pin which may be jumpered high or low with its application at S1 on the demo board.
The chip address is then given as a combination of the identifying bits for the LM4930 plus the 2-bit address of
the desired control register (00b = BasicConfig, 01b = VoicetestConfig, 10b = GainConfig). Acceptable addresses
are shown here in Table 14.
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
Table 14. LM4930 Control Bus Addresses
Address Bits
ADR = 0
Register Address
6
5
0
0
0
4
1
1
1
3
0
0
0
2
0
0
0
1
0
0
0
0
1
0
1
0
0
0
ADR = 1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
Data is sampled only if the address is in range and the R/W bit is clear. Data for each register is given in the
System Control Registers section of the datasheet. Texas Instruments also features a special control board for
quick evaluation of the LM4930 demo board with your PC. This is a serial control interface board, complete with
header compatible with the interface header (J1) on the LM4930 board. This also features demonstration
software to allow for complete control and evaluation of the various modes and functions of the LM4930 through
the bus.
Pullup resistors are required to achieve reliable operation. 750Ω pullup resistors on the SDA and SCL lines
achieves best results when used with TI's parallel-to-serial interface board. Lower value pullup resistors will
decrease the rise and fall times on the bus which will in turn decrease susceptibility to bus noise that may cause
a false trigger. The cost comes at extra current use. Control bus reliability will thus depend largely on bus noise
and may vary from design to design. Low noise is critical for reliable operation.
PCM Bus Interface (P1, P2, P3, P4)
PCM_SDO (P4), PCM_SYNC (P3), PCM_SDI (P1), and PCM_CLK (P2) form the PCM interface bus for simple
communication with most baseband ICs with voiceband communications and follow the PCM-1900
communications standard. The PCM interface features frame lengths of 16, 32, or 64 bits, A-law and u-law
companding, linear mode, short or long frame sync, an energy-saving power down mode, and master only
operation.
The PCM bus does not support a slave mode. It operates as a master only. Thus PCM_SYNC and PCM_CLK
are solely generated by the LM4930. PCM_SYNC is the word sync line for the bus. It operates at a fixed
frequency of 8kHz and may be set in the BASICCONFIG register (bit 5 PCM_LONG) for short or long frame
sync. A short frame sync is 1 PCM_CLK cycle (PCM_LONG=0), a long frame sync is 2 PCM_CLK cycles long
(PCM_LONG=1). A long sync pulse is also delayed one clock cycle relative to a short sync pulse. This is
illustrated in Figure 5. PCM_CLK is the bit clock for the bus. It's frequency depends on the number of 16-bit
frames per sync pulse and can be 128kHz, 256kHz, 512kHz.
The other two lines, PCM_SDO and PCM_SDI, are for serial data out and serial data in, respectively. The type of
data may also be set in the BASICCONFIG register by bits 6 and 7. Bit 6 controls whether the data is linear or
companded. If set to 1, the 8 MSBs are presumed to be companded data and the 8 LSBs are ignored. If cleared
to 0, the data is treated as 2's complement PCM data. Bit 7 controls which PCM law is used if Bit 6 is set for
companded (G711) data. If set to 1, the companded data is assumed to be A-law. If cleared to 0, the companded
data is treated as µ-law.
Bits 8:9 of the BASICCONFIG register set the PCM_SYNC_MODE settings. This controls the number of 16 bit
frames per sync pulse. The feature allows the LM4930 to function harmoniously with other devices or channels
on the PCM bus by adjusting the number of 16 bit frames per sync pulse to 1 (00b), 2 (01b), or 4 (10b). The
LM4930 will transmit PCM data in the first frame and then tri-state the PCM_SDO pin on later frames.
In addition, the LM4930 provides control to allow the PCM_CLK and PCM_SYNC clocks to continue functioning
even when the LM4930 is in Standby mode. By setting bit 10 of the BASICCONFIG register to 1
PCM_ALWAYS_ON is enabled and the LM4930 will continue to drive the PCM clock and sync lines when in
Standby mode. This bit should be set if another codec is using the PCM bus. Powerdown mode will disable these
outputs.
30
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
I2S Interface Bus (J2)
The I2S standard provides a uni-directional serial interface designed specifically for digital audio. For the
LM4930, the interface provides access to a 48kHz, 16 bit full-range stereo audio DAC. This interface uses a
three port system of clock (I2S_CLK), data (I2S_DATA), and word (I2S_WS). The clock and word lines can be
either master or slave as set by bit 11 in the BASICCONFIG register.
A bit clock (I2S_CLK) at 32 or 64 times the sample frequency is established by the I2S system master and a
word select (I2S_WS) line is driven at a frequency equal to the sampling rate of the audio data, in this case
48kHz. The word line is registered to change on the negative edge of the bit clock. The serial data (I2S_DATA) is
sent MSB first, again registered on the negative edge of the bit clock, delayed by 1 bit clock cycle relative to the
changing of the word line (typical I2S format - see Figure 6).
The resolution of the I2S interface may be set by modifying the I2S_RES bit (bit 12) in the BASICCONFIG
register. If set to 1, the LM4930 operates at 32 bits per frame (3.072MHz). If cleared to 0, then 16 bits per frame
is selected (1.536MHz). This has a corresponding effect on the bit clock.
The I2S Interface Bus also provides for an additional MCLK connection to an external device from the LM4930
demo board. This may be used in conjunction with Texas Instruments' SPDIF->I2S Conversion Board for quick
evaluation. This board features a connection header that interfaces with pins 1-5 of the I2S Interface Bus. Pins 6-
10 are provided as digital ground references for the case of discrete connections.
MCLK/XTAL_IN (P5)
This is the input for an external Master Clock. The jumper at S2 must be removed (disconnecting the onboard
crystal from the circuit) when using an external Master Clock.
BTL Mono Out (J7)
This is the mono speaker output, designed for use with an 8 ohm speaker. The outputs are driven in bridge-tied-
load (BTL) mode, so both sides have signal. Outputs are normally biased at one half AVDD when the LM4930 is
in active mode.
Additionally, if the CLASS bit is set to 1 in the VOICETESTCONFIG register (bit 0) the BTL mono output is
internally configured as a buffer amplifier designed for use with an external class D amp.
Stereo Headphone Out (J8)
This is the stereo headphone output. Each channel is single-ended, with 220uF DC blocking capacitors mounted
on the demo board. The jack features a typical stereo headphone pinout.
A headphone sense pin is provided at J6. This pin provides a clean logic high or low output to indicate the
presence of headphones in the headphone jack. A common application circuit for this is given in the Reference
Board Schematic shown in Figure 50. In this application HPSENSE_IN is pulled low by the 1k ohm resistor when
no headphone is present. This gives a corresponding logic low output on the HPSENSE_OUT pin. When a
headphone is placed in the jack the 1k ohm pull-down is disconnected and a 100k ohm pull-up resistor creates a
high voltage condition on HPSENSE_IN. This in turn creates a logic high on HPSENSE_OUT. This output may
be used to reliably drive an external microcontroller with headphone status.
MIC Jack (J3)
This jack is for connection to an external microphone like the kind typically found in mobile phones. Pin 1 is
GND, pin 2 is the negative input pin, and pin 3 is the positive pin, with phantom voltage supplied by MIC_BIAS
on the LM4930.
IRQ (J4)
This pin provides simple status updates from the LM4930 to an external microcontroller if desired. IRQ is logic
high when the LM4930 is in a stable state and changes to low when changing modes. This can also be useful for
simple software/driver development to monitor mode changes, or as a simple debugging tool.
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
BASIC OPERATION
The LM4930 is a highly integrated audio subsystem with many different operating modes available. These
modes may be controlled in the BASICCONFIG register in bits 3:0. These mode settings are shown in the
BASICCONFIG register table and are described here below:
Powerdown Mode (0000b)
Part is powered down, analog outputs are not biased. This is a minimum current mode. All part features are shut
down.
Standby Mode (0001b)
The LM4930 is powered down, but outputs are still biased at one half AVDD. This comes at some current cost,
but provides a much faster turn-on time with zero "click and pop" transients on the headphone out. Standby
mode can be toggled into and out of rapidly and is ideal for saving power whenever continuous audio is not a
requirement. All other part functions are suspended unless PCM_ALWAYS_ON (bit 10 in BASICCONFIG
register) is enabled, in which case PCM_CLK and PCM_SYNC will continue to function.
Mono Speaker Mode (0010b)
Part is active. All analog outputs are biased. Audio from the voiceband codec is routed to the mono speaker out.
Stereo headphone out is silent.
Headphone Call Mode (0011b)
Part is active. All analog outputs are biased. Audio from voiceband codec is routed to the stereo headphones.
Both left and right channels are the same. Mono speaker out is silent.
Conference Call Mode (0100b)
Part is active. All analog outputs are biased. Audio from the voiceband codec is routed to the mono speaker out
and to the stereo headphones.
L+R Mixed to Mono Speaker (0101b)
Part is active. All analog outputs are biased. Full-range audio from the 16bit/48kHz audio DAC is mixed together
and routed to the mono speaker out. Stereo headphones are silent.
Headphone Stereo Audio (0110b)
Part is active. All analog outputs are biased. Full-range audio from the 16bit/48kHz audio DAC is sent to the
stereo headphone jack. Each channel is heard discretely. The mono speaker is silent.
L+R Mixed to Mono Speaker + Stereo Headphone Audio (0111b)
Part is active. All analog outputs are biased. Full-range audio from the 16bit/48kHz audio DAC is sent discretely
to the stereo headphone jack and also mixed together and sent to the mono speaker out.
Mixed Mode (1000b)
Part is active. All analog outputs are biased. This provides one channel (the left channel) of full range audio to
the mono speaker out. Audio from the voiceband codec is then sent to the stereo headphones, the same on
each channel.
Mixed Mode (1001b)
Part is active. All analog outputs are biased. Mixed voiceband and full-range audio (left channel only) is sent to
the mono speaker out. Audio from the voiceband codec only is sent to the stereo headphones, the same on each
channel.
32
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
LM4930
www.ti.com
SNAS212C –JULY 2003–REVISED MAY 2013
Mixed Mode (1010b)
Part is active. All analog outputs are biased. Audio from the voiceband codec is sent to the mono speaker out.
The left channel only of the full range audio is then sent to both the left and right channels of the stereo
headphone out.
REGISTERS
The LM4930 starts on power-up with all registers cleared in Powerdown mode. Powerdown mode is the
recommended time to make setup changes to the digital interfaces (PCM bus, I2S bus). Although the
configuration registers can be changed in any mode, changes made during Standby or Powerdown prevent
unwanted audio artifacts that may occur during rapid mode changes with the outputs active. The LM4930 also
features a soft reset. This reset is enabled by setting bit 4 of the BASICCONFIG register.
The VOICETESTCONFIG register is used to set various configuration parameters on the voiceband and full-
range audio codecs. SIDETONE_ATTEN (bits 4:1) refers to the level of signal from the MIC input that is fed back
into the analog audio output path (commonly used in headphone applications and killed in hands-free
applications). Setting the AUTOSIDE bit (bit 5) automatically mutes the sidetone in voice over mono speaker
modes so feedback isn't an issue.
Quick mute functions are also located in this register, with bits 13:15 muting the mono speaker amp, the
headphone amp, and the mic preamp respectively.
This register also has a CLOCK_DIV bit (bit 6) which, if set, allows for the use of a 24.576MHz clock instead of
the default 12.288MHz.
The GAINCONFIG register is used to control the gain of the mono speaker amp , the headphone amp, and the
mic preamp. This allows flexible mono speaker gains from -34.5dB to +12dB in 1.5dB steps, headphone amp
gains of -46.5dB to 0dB in 1.5dB steps, and mic preamp gains of 17dB to 47dB in 2dB steps. Gain levels may be
modified in any mode, but may wait for a zero cross detect in the DAC to eliminate volume control artifacts. This
wait for zero cross may be disabled by setting the ZXD_DISABLE bit (bit 7) in the VOICETESTCONFIG register
to allow immediate changes.
ANALOG INPUTS AND OUTPUTS
The LM4930 features an analog mono BTL output for connection to an 8Ω external speaker. This output can
provide up to 1W of power into an 8Ω load with a 5V analog supply. A single-ended stereo headphone output is
also featured, providing up to 30mW of power per channel into 32Ω with a 5V analog supply.
A Headphone Sense output is provided on J6 for connection to an external controller. This pin goes high when a
heaphone is present (when used as shown in Figure 50) and will function in all modes independent of other
operations the LM4930 may be currently processing.
The MIC Jack input (J3) provides for a low level analog input. Pin 3 provides the power to the MIC and the
positive input of the LM4930. Gain for the MIC preamp is set in the GAINCONFIG register.
Copyright © 2003–2013, Texas Instruments Incorporated
Submit Documentation Feedback
33
Product Folder Links: LM4930
LM4930
SNAS212C –JULY 2003–REVISED MAY 2013
www.ti.com
REVISION HISTORY
Changes from Revision B (May 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 33
34
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4930
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM4930ITLX/NOPB
LM4930LQ/NOPB
ACTIVE
DSBGA
WQFN
YZR
36
44
1000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-30 to 85
-30 to 85
G
B6
ACTIVE
NJN
SN
L4930LQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM4930ITLX/NOPB
LM4930LQ/NOPB
DSBGA
WQFN
YZR
NJN
36
44
1000
250
178.0
178.0
12.4
16.4
3.43
7.3
3.59
7.3
0.76
1.3
8.0
12.0
16.0
Q1
Q1
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM4930ITLX/NOPB
LM4930LQ/NOPB
DSBGA
WQFN
YZR
NJN
36
44
1000
250
208.0
208.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NJN0044A
LQA44A (REV B)
www.ti.com
MECHANICAL DATA
YZR0036xxx
D
0.600±0.075
E
TLA36XXX (Rev D)
D: Max = 3.458 mm, Min =3.397 mm
E: Max = 3.292 mm, Min =3.232 mm
4215058/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
LM49321
Audio Sub-System with Stereo DAC, Mono Class AB Loudspeaker Amplifier, OCL/SE Stereo Headphone Output and RF Suppression
NSC
LM49321RL
Audio Sub-System with Stereo DAC, Mono Class AB Loudspeaker Amplifier, OCL/SE Stereo Headphone Output and RF Suppression
NSC
LM49321RLX/NOPB
Audio Sub-Sys w/ Stereo DAC Mono Class AB Loudspkr Amp OCL/SE Stereo Headph Output & RF Suppression 36-DSBGA -40 to 85
TI
©2020 ICPDF网 联系我们和版权申明