LM4947TL/NOPB [TI]
具有 87mW 耳机放大器和 3D 增强功能的 2.2W 单声道、模拟输入 D 类放大器 | YZR | 25 | -40 to 85;
| 型号： | LM4947TL/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 87mW 耳机放大器和 3D 增强功能的 2.2W 单声道、模拟输入 D 类放大器 | YZR | 25 | -40 to 85 放大器 商用集成电路 |
| 文件： | 总36页 (文件大小：1446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM4947, LM4947TLEVAL
www.ti.com
SNAS349D –JUNE 2006–REVISED MAY 2013
LM4947
Mono Class D and Stereo Audio Sub-System
with OCL Headphone Amplifier and TI 3D
Check for Samples: LM4947, LM4947TLEVAL
1
FEATURES
DESCRIPTION
The LM4947 is an audio subsystem capable of
•
I2C Control Interface
2
efficiently delivering 500mW (Class D operation) of
continuous average power into a mono 8Ω bridged-
tied load (BTL) with 1% THD+N, 37mW (Class AB
operation) power channel of continuous average
power into stereo 32Ω single-ended (SE) loads with
1% THD+N, or an output capacitor-less (OCL)
configuration with identical specification as the SE
configuration, from a 3.3V power supply.
•
I2C Programmable Texas Instruments 3D
Audio
I2C Controlled 32 Step Digital Volume Control
(-59.5dB to +18dB)
•
•
Three Independent Volume Channels (Left,
Right, Mono)
•
•
•
•
•
•
•
•
Eight Distinct Output Modes
Small, 25–Bump DSBGA Packaging
“Click and Pop” Suppression Circuitry
Thermal Shutdown Protection
Low Shutdown Current (0.1μA, typ)
RF Suppression
The LM4947 has six input channels: one pair for a
two-channel stereo signal, the second pair for a
secondary two-channel stereo input, and the third pair
for
Additionally, the two sets of stereo inputs may be
configured as single stereo differential input
a
differential single-channel mono input.
a
(differential left and differential right). The LM4947
features a 32-step digital volume control and eight
distinct output modes. The digital volume control, 3D
enhancement, and output modes are programmed
through a two-wire I2C compatible interface that
allows flexibility in routing and mixing audio channels.
Differential Mono and Stereo Inputs
Stereo Input Mux
KEY SPECIFICATIONS
•
THD+N at 1kHz, 500mW into 8Ω BTL (3.3V):
1.0% (typ)
The RF suppression circuitry in the LM4947 makes it
well-suited for GSM mobile phones and other
portable applications in which strong RF signals
generated by an antenna (and long output traces)
may couple audibly into the amplifier.
•
THD+N at 1kHz, 37mW into 32Ω SE (3.3V):
1.0% (typ)
•
•
Single Supply Operation (VDD): 2.7 to 5.5 V
I2C Single Supply Operation: 2.2 to 5.5 V
The LM4947 is designed for cellular phones, PDAs,
and other portable handheld applications. It delivers
high quality output power from a surface-mount
package and requires only eight external components
in the OCL mode (two additional components in SE
mode).
APPLICATIONS
•
•
Mobile Phones
PDAs
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LM4947, LM4947TLEVAL
SNAS349D –JUNE 2006–REVISED MAY 2013
www.ti.com
TYPICAL APPLICATION
V
DD
1 mF
0.1 mF ceramic
optional
capacitors
C
C
S2
Loud
S1
Speaker
1 mF
MIN+
+
LS+
LS-
Volume Control
-59.50 dB to +18 dB
+6 dB
8W
1 mF
MIN-
-
0.22 mF
Mixer
and
R
HP
+
-
LIN1 or L
32W
Volume Control
-59.50 dB to +18 dB
Output
Mode
Select
0.22 mF
0.22 mF
0.22 mF
VOC
LIN2 or L
National
3D
MUX
+
RIN1 or R
L
HP
32W
Volume Control
-59.50 dB to +18 dB
-
RIN2 or R
2
C
B
I CVDD
Click/Pop
Suppression
2
SDA
I C
Interface
C
Bypass
SCL
2.2 mF
ADDR
C
C
3DR
3DL
Figure 1. Typical Audio Amplifier Application Circuit-Output Capacitor-less
V
DD
1 mF
0.1 mF ceramic
optional
capacitors
Loud
C
S1
C
S2
Speaker
1 mF
MIN+
+
-
LS+
LS-
Volume Control
-59.50 dB to +18 dB
+6dB
8W
1 mF
MIN-
Mixer
and
0.22 mF
C
O
R
HP
+
LIN1 or L
32W
Volume Control
-59.50 dB to +18 dB
Output
Mode
Select
100 mF
0.22 mF
0.22 mF
0.22 mF
-
LIN2 or L
National
3D
VOC
MUX
+
C
RIN1 or R
RIN2 or R
O
L
HP
Volume Control
32W
-59.50 dB to +18 dB
-
100 mF
2
C
B
I CVDD
SDA
2
Click/Pop
Suppression
I C
Interface
C
Bypass
SCL
2.2 mF
ADDR
C
C
3DR
3DL
Figure 2. Typical Audio Amplifier Application Circuit-Single Ended
2
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SNAS349D –JUNE 2006–REVISED MAY 2013
CONNECTION DIAGRAM
Top View
A
B
C
D
E
5
4
RHP3D2
LHP3D2
LHP3D1
MIN-
VOC
CBYPASS
SCL
LHP
RHP
AVDD
I2CVDD
LSVDD
RHP3D1
MIN+
GND
LS+
3
2
GND
LIN1
LIN2
SDA
RIN1
RIN2
ADDR
1
AVDD
LS-
Figure 3. 25-Bump DSBGA Package
See Package Number YZR0025BBA
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PIN DESCRIPTIONS
Bump
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
Name
Description
RIN2
LIN1
Right Input Channel 2 or Right Differential Input –
Left Input Channel 1 or Left Differential Input +
Mono Channel Non-inverting Input
Right Headphone 3D Input 1
Right Headphone 3D Input 2
Right Input Channel 1 or Right Differential Input +
Left Input Channel 2 or Left Differential Input–
Mono Channel Inverting Input
Left Headphone 3D Input 2
Left Headphone 3D Input 1
Address Identification
MIN+
RHP3D1
RHP3D2
RIN1
LIN2
MIN-
LHP3D1
LHP3D2
ADDR
SDA
Serial Data Input
SCL
Serial Clock Input
CBYPASS
VOC
Half-Supply Bypass Capacitor
Headphone return bias output
Analog Power Supply
AVDD
LSVDD
I2CVDD
AVDD
RHP
Loudspeaker Power Supply
I2C Interface Power Supply
Analog Power Supply
Right Headphone Output
LS-
Loudspeaker Output Negative
Ground
GND
LS+
Loudspeaker Output Positive
Ground
GND
LHP
Left Headphone Output
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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SNAS349D –JUNE 2006–REVISED MAY 2013
ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage
6.0V
−65°C to +150°C
−0.3 to VDD +0.3
2.0kV
Storage Temperature
Input Voltage
ESD Susceptibility(3)
ESD Machine model(4)
Junction Temperature (TJ)
Solder Information
200V
150°C
Vapor Phase (60 sec.)
Infrared (15 sec.)
215°C
220°C
Thermal Resistance
θJA (typ) - YZR0025BBA
65°C/W
(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, 100pF discharged through a 1.5kΩ resistor.
(4) Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then
discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω).
OPERATING RATINGS
Temperature Range
Supply Voltage (VDD
Supply Voltage (I2C)
−40°C to 85°C
2.7V ≤ VDD ≤ 5.5V
2.2V ≤ VDD ≤ 5.5V
2.7V ≤ VDD ≤ 5.5V
)
Supply Voltage (Loudspeaker VDD
)
ELECTRICAL CHARACTERISTICS 3.3V(1)(2)
The following specifications apply for VDD = 3.3V, TA = 25°C, and all gains are set for 0dB unless otherwise specified.
Symbol
Parameter
Conditions
LM4947
Units
(Limits)
Typical(3)
Limits(4)
Output Modes 2, 4, 6
VIN = 0V; No load,
OCL = 0 (Table 2)
4.5
6.5
6.5
mA (max)
mA (max)
IDDQ
Quiescent Supply Current
Output Modes 1, 3, 5, 7
VIN = 0V; No load, BTL,
OCL = 0 (Table 2)
8
ISD
Shutdown Current
Output Mode 0
0.1
2
1
µA (max)
mV (max)
mV (max)
VIN = 0V, Mode 7, Mono
VIN = 0V, Mode 7, Headphones
15
15
VOS
Output Offset Voltage
2
MONO OUT; RL = 8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1
500
37
400
33
mW (min)
mW (min)
PO
Output Power
ROUT and LOUT; RL = 32Ω
THD+N = 1%; f = 1kHz, SE, Mode 4
MONOOUT
f = 1kHz, POUT = 250mW;
RL = 8Ω, BTL, Mode 1
0.03
0.02
%
%
THD+N Total Harmonic Distortion Plus Noise
ROUT and LOUT
f = 1kHz, POUT = 12mW;
RL = 32Ω, SE, Mode 4
(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to the ground pin, unless otherwise specified.
(3) Typical specifications are specified at +25°C and represent the most likely parametric norm.
(4) Tested limits are specified to AOQL (Average Outgoing Quality Level).
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ELECTRICAL CHARACTERISTICS 3.3V(1)(2) (continued)
The following specifications apply for VDD = 3.3V, TA = 25°C, and all gains are set for 0dB unless otherwise specified.
Symbol
Parameter
Conditions
LM4947
Units
(Limits)
Typical(3)
Limits(4)
A-weighted, 0dB
inputs terminated, output referred
Speaker; Mode 1
39
39
42
38
15
15
17
12
15
17
μV
μV
μV
μV
μV
μV
μV
μV
μV
μV
Speaker; Mode 3
Speaker; Mode 5
Speaker; Mode 7
NOUT
Output Noise
Headphone; SE, Mode 2
Headphone; SE, Mode 4
Headphone; SE, Mode 6
Headphone; OCL, Mode 2
Headphone; OCL, Mode 4
Headphone; OCL, Mode 6
VRIPPLE = 200mVPP; f = 217Hz,
RL = 8Ω, CB = 2.2µF, BTL
All audio inputs terminated to GND;
output referred
Power Supply Rejection Ratio
Loudspeaker out
BTL, Output Mode 1
BTL, Output Mode 3
BTL, Output Mode 5
BTL, Output Mode 7
79
78
79
80
dB
dB
dB
dB
VRIPPLE = 200mVPP; f = 217Hz,
RL = 32Ω, CB = 2.2µF, BTL
All audio inputs terminated to GND;
output referred
PSRR
SE, Output Mode 2
SE, Output Mode 4
SE, Output Mode 6
OCL, Output Mode 2
OCL, Output Mode 4
OCL, Output Mode 6
Output Mode 1, 3, 5
78
71
71
83
74
74
86
dB
dB
dB
dB
dB
dB
%
Power Supply Rejection Ratio
ROUT and LOUT
η
Class D Efficiency
f = 217Hz, VCM = 1Vpp,
Mode 1, BTL, RL = 8Ω
CMRR Common-Mode-Rejection Ratio
–49
–58
–73
dB
dB
dB
Headphone, PO = 12mW,
f = 1kHz, OCL, Mode 4, RL = 32Ω
XTALK Crosstalk
Headphone, PO = 12mW,
f = 1kHz, SE, Mode 4, RL = 32Ω
CB = 2.2µF, OCL, RL = 32Ω
CB = 2.2µF, SE, RL = 32Ω
90
ms
ms
dB
TWU
Wake-Up Time from Shutdown
Volume Control Step Size Error
115
±0.2
–60.25
–58.75
dB (min)
dB (max)
Input referred maximum attenuation
-59.5
Digital Volume Range
Mute Attenuation
17.25
18.75
dB (min)
dB (max)
Input referred maximum gain
Output Mode 1, 3, 5
+18
87
dB (min)
8
14
kΩ (min)
kΩ (max)
Maximum gain setting
12
MONO_IN Input Impedance
RIN and LIN Input Impedance
75
125
kΩ (min)
kΩ (max)
Maximum attenuation setting
100
6
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SNAS349D –JUNE 2006–REVISED MAY 2013
ELECTRICAL CHARACTERISTICS 5V(1)(2)
The following specifications apply for VDD = 5V, TA = 25°C and all gains are set for 0dB unless otherwise specified.
Symbol
Parameter
Conditions
LM4947
Units
(Limits)
Typical(3)
Limits(4)
Output Modes 2, 4, 6
VIN = 0V; No load,
OCL = 0 (Table 2)
5.4
7.6
7.5
mA
IDDQ
Quiescent Supply Current
Output Modes 1, 3, 5, 7
VIN = 0V; No load, BTL,
OCL = 0 (Table 2)
12
mA
ISD
Shutdown Current
Output Mode 0
0.1
2
1
µA (max)
VIN = 0V, Mode 7, Mono
15
mV
(max)
VOS
Output Offset Voltage
VIN = 0V, Mode 7, Headphones
2
15
mV
(max)
MONOOUT; RL = 8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1
1.19
87
W
PO
Output Power
ROUT and LOUT; RL = 32Ω
THD+N = 1%; f = 1kHz, SE, Mode 4
mW
MONOOUT
f = 1kHz, POUT = 500mW;
RL = 8Ω, BTL, Mode 1
0.04
0.01
%
%
THD+N Total Harmonic Distortion + Noise
ROUT and LOUT
f = 1kHz, POUT = 30mW;
RL = 32Ω, SE, Mode 4
A-weighted, 0dB
inputs terminated, output referred
Speaker; Mode 1
38
38
39
36
21
21
24
16
16
19
μV
μV
μV
μV
μV
μV
μV
μV
μV
μV
Speaker; Mode 3
Speaker; Mode 5
Speaker; Mode 7
NOUT
Output Noise
Headphone; SE, Mode 2
Headphone; SE, Mode 4
Headphone; SE, Mode 6
Headphone; OCL, Mode 2
Headphone; OCL, Mode 4
Headphone; OCL, Mode 6
(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to the ground pin, unless otherwise specified.
(3) Typical specifications are specified at +25°C and represent the most likely parametric norm.
(4) Tested limits are specified to AOQL (Average Outgoing Quality Level).
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ELECTRICAL CHARACTERISTICS 5V(1)(2) (continued)
The following specifications apply for VDD = 5V, TA = 25°C and all gains are set for 0dB unless otherwise specified.
Symbol
Parameter
Conditions
LM4947
Typical(3) Limits(4)
Units
(Limits)
VRIPPLE = 200mVPP; f = 217Hz,
RL = 8Ω, CB = 2.2µF, BTL
All audio inputs terminated to GND;
output referred
Power Supply Rejection Ratio
Loudspeaker out
BTL, Output Mode 1
BTL, Output Mode 3
BTL, Output Mode 5
BTL, Output Mode 7
70
61
64
61
dB
dB
dB
dB
VRIPPLE = 200mVPP; f = 217Hz,
RL = 32Ω, CB = 2.2µF, BTL
All audio inputs terminated to GND;
output referred
PSRR
SE, Output Mode 2
SE, Output Mode 4
SE, Output Mode 6
OCL, Output Mode 2
OCL, Output Mode 4
OCL, Output Mode 6
Output Mode 1, 3, 5
72
70
65
76
72
70
86
dB
dB
dB
dB
dB
dB
%
Power Supply Rejection Ratio
ROUT and LOUT
η
Class D Efficiency
f = 1kHz, VCM = 1Vpp, 0dB gain,
Mode 1, BTL, RL = 8Ω
CMRR Common-Mode Rejection Ratio
–49
–55
–72
dB
dB
dB
Headphone, PO = 30mW, f = 1kHz,
OCL, Mode 4
XTALK Crosstalk
Headphone, PO = 30mW, f = 1kHz,
SE, Mode 4
CB = 2.2μF, OCL, RL = 32Ω
CB = 2.2μF, SE, RL = 32Ω
116
150
±0.2
-59.5
+18
90
ms
ms
TWU
Wake-Up Time from Shutdown
Volume Control Step Size Error
Digital Volume Range
dB
Input referred maximum attenuation
Input referred maximum gain
Output Mode 1, 3, 5
dB
dB
Mute Attenuation
dB (min)
kΩ (min)
kΩ (max)
Maximum gain setting
11
MONO_IN Input Impedance
RIN and LIN Input Impedance
kΩ (min)
kΩ (max)
Maximum attenuation setting
100
8
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SNAS349D –JUNE 2006–REVISED MAY 2013
I2C(1)(2)
The following specifications apply for VDD = 5V and 3.3V, TA = 25°C unless otherwise specified.
Symbol
Parameter
Conditions
LM4947
Typical(3) Limits(4)
Units
(Limits)
t1
Clock Period
2.5
100
100
100
100
µs (max)
ns (min)
ns (min)
ns (min)
ns (min)
t2
t3
t4
t5
Clock Setup Time
Data Hold Time
Start Condition Time
Stop Condition Time
0.7xI2C
VDD
0.3xI2C
VDD
VIH
VIL
SPI Input Voltage High
SPI Input Voltage Low
V (min)
V (max)
(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to the ground pin, unless otherwise specified.
(3) Typical specifications are specified at +25°C and represent the most likely parametric norm.
(4) Tested limits are specified to AOQL (Average Outgoing Quality Level).
I2C Protocol Information
The I2C address for the LM4947 is determined using the ID_ENB pin. The LM4947's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1 = 0, if ID_ADDR is logic LOW; and X1 = 1, if ID_ENB is
logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4947's chip address can
be changed to avoid any possible address conflicts.
Figure 4. I2C Bus Format
Figure 5. I2C Timing Diagram
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TYPICAL PERFORMANCE CHARACTERISTICS
THD+N vs Output Power
THD+N vs Output Power
VDD = 3.3V, RL = 8Ω, f = 1kHz
Mode 3, MONO
VDD = 3.3V, RL = 8Ω, f = 1kHz
Mode 1, MONO
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
1m 2m 5m10m 20m 50m 100m 200m 500m1
1m 2m 5m10m 20m 50m 100m 200m 500m1
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 6.
Figure 7.
THD+N vs Output Power
VDD = 3.3V, RL = 8Ω, f = 1kHz
Mode 5, MONO
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz, Diff In
Mode 2, OCL
10
10
5
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
1m 2m
5m 10m 20m
50m 100m
1m 2m 5m10m 20m 50m 100m 200m 500m1
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 8.
Figure 9.
THD+N vs Output Power
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz, Diff In
VDD = 3.3V, RL = 32Ω, f = 1kHz, Diff In
Mode 2, SE
Mode 4, OCL
10
10
5
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
1m 2m
5m 10m 20m
50m 100m
1m 2m
5m 10m 20m
50m 100m
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 10.
Figure 11.
10
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SNAS349D –JUNE 2006–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz, Diff In
Mode 4, SE
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz, Diff In
Mode 6, OCL
10
10
5
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
1m 2m
5m 10m 20m
50m 100m
1m 2m
5m 10m 20m
50m 100m
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 12.
Figure 13.
THD+N vs Output Power
THD+N vs Output Power
VDD = 5V, RL = 8Ω, f = 1kHz
Mode 1, MONO
VDD = 3.3V, RL = 32Ω, f = 1kHz, Diff In
Mode 6, SE
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
2m 5m10m 20m 50m100m 200m 500m 1
2
10m
20m 30m
50m 70m 100m
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 14.
Figure 15.
THD+N vs Output Power
VDD = 5V, RL = 8Ω, f = 1kHz
Mode 3, MONO
THD+N vs Output Power
VDD = 5V, RL = 8Ω, f = 1kHz
Mode 5, MONO
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
1m 2m 5m10m20m 50m100m 200m 500m1
2
1m 2m 5m10m20m 50m100m 200m 500m1
2
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 16.
Figure 17.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz, Diff In
Mode 2, OCL
THD+N vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz, Diff In
Mode 2, SE
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
1m 2m
5m 10m 20m
50m 100m 200m
1m 2m
5m 10m 20m
50m 100m 200m
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 18.
Figure 19.
THD+N vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz, Diff In
Mode 4, OCL
THD+N vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz, Diff In
Mode 4, SE
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
1m 2m
5m 10m 20m
50m 100m 200m
1m 2m
5m 10m 20m
50m 100m 200m
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 20.
Figure 21.
THD+N vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz, Diff In
Mode 6, OCL
THD+N vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz, Diff In
Mode 6, SE
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
1m 2m
5m 10m 20m
50m 100m 200m
1m 2m
5m 10m 20m
50m 100m 200m
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 22.
Figure 23.
12
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SNAS349D –JUNE 2006–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Frequency
VDD = 3.3V, RL = 8Ω, PO = 250mW
Diff In, Mode 1
THD+N vs Frequency
VDD = 3.3V, RL = 8Ω, PO = 250mW
Diff In, Mode 5
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
50 100 200 500 1k 2k
5k 10k 20k
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24.
Figure 25.
THD+N vs Frequency
THD+N vs Frequency
VDD = 3.3V, RL = 8Ω, PO = 250mW
VDD = 3.3V, RL = 32Ω, PO = 12mW
Diff In, Mode 3
Mode 2, OCL
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
50 100 200 500 1k 2k
5k 10k 20k
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 26.
Figure 27.
THD+N vs Frequency
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 2, SE
Mode 4,7, OCL
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
50 100 200 500 1k 2k
5k 10k 20k
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 28.
Figure 29.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 4,7, SE
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 6, OCL
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
50 100 200 500 1k 2k
5k 10k 20k
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30.
Figure 31.
THD+N vs Frequency
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
VDD = 5V, RL = 8Ω, PO = 500mW
Mode 6, SE
Diff In, Mode 1
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
50 100 200 500 1k 2k
5k 10k 20k
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 32.
Figure 33.
THD+N vs Frequency
THD+N vs Frequency
VDD = 5V, RL = 8Ω, PO = 500mW
Diff In, Mode 5
VDD = 5V, RL = 8Ω, PO = 500mW
Diff In, Mode 3
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
50 100 200 500 1k 2k
5k 10k 20k
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 34.
Figure 35.
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SNAS349D –JUNE 2006–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Diff In, Mode 2, OCL
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Diff In, Mode 2, SE
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
50 100 200 500 1k 2k
5k 10k 20k
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 36.
Figure 37.
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Diff In, Mode 4,7, OCL
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Diff In, Mode 4,7, SE
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
50 100 200 500 1k 2k
5k 10k 20k
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 38.
Figure 39.
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Diff In, Mode 6, OCL
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Diff In, Mode 6, SE
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
50 100 200 500 1k 2k
5k 10k 20k
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 40.
Figure 41.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
PSRR vs Frequency
VDD = 3.3V, AV = 0dB
Mode 1, MONO
PSRR vs Frequency
VDD = 3.3V, AV = 0dB
Mode 2, OCL
+0
-10
-20
-30
-40
-50
-60
+0
-10
-20
-30
-40
-50
-60
-70
-80
-70
-80
-90
-90
-100
-100
20 50 100 200 500 1k 2k
5k 10k 20k
20 50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 42.
Figure 43.
PSRR vs Frequency
VDD = 3.3V, AV = 0dB
Mode 2, SE
PSRR vs Frequency
VDD = 3.3V, AV = 0dB
Mode 3, MONO
+0
-10
-20
-30
-40
-50
-60
+0
-10
-20
-30
-40
-50
-60
-70
-80
-70
-80
-90
-90
-100
-100
20 50 100 200 500 1k 2k
5k 10k 20k
20 50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 44.
Figure 45.
PSRR vs Frequency
VDD = 3.3V, AV = 0dB
Mode 4, OCL
PSRR vs Frequency
VDD = 3.3V, AV = 0dB
Mode 4, SE
+0
-10
-20
-30
-40
-50
-60
+0
-10
-20
-30
-40
-50
-60
-70
-80
-70
-80
-90
-90
-100
-100
20 50 100 200 500 1k 2k
5k 10k 20k
20 50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 46.
Figure 47.
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SNAS349D –JUNE 2006–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
PSRR vs Frequency
VDD = 3.3V, AV = 0dB
Mode 5, MONO
PSRR vs Frequency
VDD = 3.3V, AV = 0dB
Mode 6, OCL
+0
-10
-20
-30
-40
-50
-60
+0
-10
-20
-30
-40
-50
-60
-70
-80
-70
-80
-90
-90
-100
-100
20 50 100 200 500 1k 2k
5k 10k 20k
20 50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 48.
Figure 49.
PSRR vs Frequency
VDD = 3.3V, AV = 0dB
Mode 6, SE
PSRR vs Frequency
VDD = 3.3V, AV = 0dB
Mode 7, MONO
+0
-10
-20
-30
-40
-50
-60
+0
-10
-20
-30
-40
-50
-60
-70
-80
-70
-80
-90
-90
-100
-100
20 50 100 200 500 1k 2k
5k 10k 20k
20 50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 50.
Figure 51.
PSRR vs Frequency
VDD = 5V, AV = 0dB
Mode 1, MONO
PSRR vs Frequency
VDD = 5V, AV = 0dB
Mode 2, OCL
+0
-10
-20
-30
-40
-50
-60
+0
-10
-20
-30
-40
-50
-60
-70
-80
-70
-80
-90
-90
-100
-100
20 50 100 200 500 1k 2k
5k 10k 20k
20 50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 52.
Figure 53.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
PSRR vs Frequency
VDD = 5V, AV = 0dB
Mode 2, SE
PSRR vs Frequency
VDD = 5V, AV = 0dB
Mode 3, MONO
+0
-10
-20
-30
-40
-50
-60
+0
-10
-20
-30
-40
-50
-60
-70
-80
-70
-80
-90
-90
-100
-100
20 50 100 200 500 1k 2k
5k 10k 20k
20 50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 54.
Figure 55.
PSRR vs Frequency
VDD = 5V, AV = 0dB
Mode 4, OCL
PSRR vs Frequency
VDD = 5V, AV = 0dB
Mode 4, SE
+0
+0
-10
-10
-20
-30
-40
-50
-60
-20
-30
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
-100
20 50 100 200 500 1k 2k
5k 10k 20k
20 50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 56.
Figure 57.
PSRR vs Frequency
VDD = 5V, AV = 0dB
Mode 5, MONO
PSRR vs Frequency
VDD = 5V, AV = 0dB
Mode 6, OCL
+0
-10
-20
-30
-40
-50
-60
+0
-10
-20
-30
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
-100
20 50 100 200 500 1k 2k
5k 10k 20k
20 50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 58.
Figure 59.
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SNAS349D –JUNE 2006–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
PSRR vs Frequency
VDD = 5V, AV = 0dB
Mode 6, SE
PSRR vs Frequency
VDD = 5V, AV = 0dB
Mode 7, MONO
+0
-10
-20
-30
-40
-50
+0
-10
-20
-30
-40
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-100
20 50 100 200 500 1k 2k
5k 10k 20k
20 50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 60.
Figure 61.
Power Dissipation vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 7, OCL
Power Dissipation vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 7, SE
250
200
150
100
50
100
90
80
70
60
50
40
30
20
10
0
0
0
5
10 15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35 40 45 50
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 62.
Figure 63.
Power Dissipation vs Output Power
VDD = 3.3V, RL = 8Ω, f = 1kHz
Mode 1, 3, 5, MONO
Power Dissipation vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 2, 4, 6, OCL
120
250
100
80
60
40
20
0
200
150
100
50
0
0
100 200 300 400 500 600 700
0
10
20
30
40
50
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 64.
Figure 65.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Power Dissipation vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 2, 4, 6, SE
Power Dissipation vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz
Mode 7, OCL
70
350
60
50
40
30
20
10
0
300
250
200
150
100
50
0
0
10
20
30
40
0
10
20
30
40
50
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 66.
Figure 67.
Power Dissipation vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz
Mode 7, SE
Power Dissipation vs Output Power
VDD = 5V, RL = 8Ω, f = 1kHz
Mode 1, 3, 5, MONO
160
300
140
120
100
80
250
200
150
100
50
60
40
20
0
0
0
10
20
30
40
50
0
400
800
1200
1600
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 68.
Figure 69.
Power Dissipation vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz
Mode 2, 4, 6, OCL
Power Dissipation vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz
Mode 2, 4, 6, SE
500
200
450
400
180
160
140
120
100
80
350
300
250
200
150
100
60
40
20
50
0
0
0
20
40
60
80
100
120
0
20
40
60
80
100
120
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 70.
Figure 71.
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SNAS349D –JUNE 2006–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Crosstalk vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 4, OCL
Crosstalk vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 4, SE
+0
-5
+0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
Left to right
Right to left
Right to left
Left to right
20
50 100 200 500 1k 2k
5k 10k 20k
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 72.
Figure 73.
Crosstalk vs Frequency
Crosstalk vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
VDD = 5V, RL = 32Ω, PO = 30mW
Mode 4, OCL
Mode 4, SE
+0
-5
+0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
Left to right
Right to left
Right to left
Left to right
20
50 100 200 500 1k 2k
5k 10k 20k
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 74.
Figure 75.
Supply Current vs Supply Voltage
No Load, Mode 7, OCL
Supply Current vs Supply Voltage
No Load, Mode 7, SE
12
10
8
14
12
10
8
6
6
4
4
2
2
0
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
Figure 76.
Figure 77.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Supply Current vs Supply Voltage
No Load, Mode 1, 3, 5, MONO
Supply Current vs Supply Voltage
No Load, Mode 2, 4, 6, OCL
10
10
9
8
7
9
8
7
6
6
5
4
3
2
1
0
5
4
3
2
1
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 78.
Figure 79.
Supply Current vs Supply Voltage
Output Power vs Supply Voltage
RL = 8Ω, Mode 1, 3, 5, MONO
No Load, Mode 2, 4, 6, Headphone SE
8
2500
7
6
5
4
3
2
1
2000
1500
1000
500
0
THD+N = 10%
THD+N = 1%
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 80.
Figure 81.
Output Power vs Supply Voltage
RL = 32Ω, Mode 2, 4, 6, OCL
Output Power vs Supply Voltage
RL = 32Ω, Mode 2, 4, 6, SE
180
160
140
120
100
80
180
160
140
120
100
80
THD+N = 10%
THD+N = 10%
60
60
THD+N = 1%
THD+N = 1%
40
40
20
20
0
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 82.
Figure 83.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Output Power vs Supply Voltage
Output Power vs Supply Voltage
RL = 32Ω, Mode 7, OCL
RL = 32Ω, Mode 7, SE
180
160
140
120
100
80
180
160
140
120
100
80
THD+N = 10%
THD+N = 10%
60
60
THD+N = 1%
THD+N = 1%
40
40
20
20
0
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 84.
Figure 85.
Efficiency vs Output Power
Efficiency vs Output Power
VDD = 5V, RL = 8Ω, Mode 1, 3, 5, BTL
VDD = 3.3V, RL = 8Ω, Mode 1, 3, 5, BTL
100
1
90
80
70
60
50
40
30
20
10
0
0.8
0.6
0.4
0.2
0
0
200 400 600 800 1000 1200 1400 1600
0
200
400
600
800
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 86.
Figure 87.
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APPLICATION INFORMATION
I2C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ID_ENB: This is the address select input pin.
I2C COMPATIBLE INTERFACE
The LM4947 uses a serial bus which conforms to the I2C protocol to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4947.
The I2C address for the LM4947 is determined using the ID_ENB pin. The LM4947's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1 = 0, if ID_ADDR is logic LOW; and X1 = 1, if ID_ENB is
logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4947's chip address can
be changed to avoid any possible address conflicts.
The bus format for the I2C interface is shown in Figure 4. The bus format diagram is broken up into six major
sections:
1. The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will
alert all devices attached to the I2C bus to check the incoming address against their own address.
2. The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the
clock. Each address bit must be stable while the clock level is HIGH.
3. After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up
resistor). Then the master sends an acknowledge clock pulse. If the LM4947 has received the address
correctly, then it holds the data line LOW during the clock pulse. If the data line is not held LOW during the
acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4947.
4. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable HIGH.
5. After the data byte is sent, the master must check for another acknowledge to see if the LM4947 received
the data.
6. The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is
HIGH. The data line should be held HIGH when not in use.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM4947's I2C interface is powered up through the I2CVDD pin. The LM4947's I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
Table 1. Chip Address
A7
1
A6
1
A5
1
A4
1
A3
1
A2
0
A1
EC
0
A0
0
Chip Address
ID_ADDR = 0
ID_ADDR = 1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
0
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Table 2. Control Registers
D7
D6
D5
D4
D3
D2
D1
D0
Mode Control
0
0
SE/Diff
(select)
0
OCL (select)
MC2
MC1
MC0
Programmable 3D
0
1
L2R2
L1R1 (select)
N3D3
N3D2
N3D1
N3D0
(select)
Mono Volume Control
Left Volume Control
Right Volume Control
1
1
1
0
1
1
0
0
1
MVC4
LVC4
RVC4
MVC3
LVC3
RVC3
MVC2
LVC2
RVC2
MVC1
LVC1
RVC1
MVC0
LVC0
RVC0
Table 3. Programmable Texas Instruments 3D Audio
N3D3
N3D2
Low
Medium
High
0
0
1
1
0
1
0
1
Maximum
Table 4. Input/Output Control
L2R2
L1R1
SE/DIFF
Select LIN1 and RIN1 Stereo Pair
Select LIN2 and RIN2 Stereo Pair
Select LIN1+LIN2 and RIN1+RIN2 Stereo Pair
Sets Stereo Inputs to Differential
0
1
1
x
1
0
1
x
0
0
0
1
Table 5. Output Volume Control Table
Volume Step
xVC4
0
xVC3
0
xVC2
0
xVC1
0
xVC0
0
Gain, dB
–59.50
–48.00
–40.50
–34.50
–30.00
–27.00
–24.00
–21.00
–18.00
–15.00
–13.50
–12.00
–10.50
–9.00
–7.50
–6.00
–4.50
–3.00
–1.50
0.00
1
2
0
0
0
0
1
3
0
0
0
1
0
4
0
0
0
1
1
5
0
0
1
0
0
6
0
0
1
0
1
7
0
0
1
1
0
8
0
0
1
1
1
9
0
1
0
0
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1.50
1
0
1
0
1
3.00
1
0
1
1
0
4.50
1
0
1
1
1
6.00
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Table 5. Output Volume Control Table (continued)
Volume Step
xVC4
xVC3
xVC2
xVC1
xVC0
Gain, dB
25
26
27
28
29
30
31
32
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7.50
9.00
10.50
12.00
13.50
15.00
16.50
18.00
Table 6. Output Mode Selection
Output Mode MC2
Number
MC1
MC0
Handsfree Mono Output
Right HP Output
Left HP Output
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SD
SD
MUTE
SD
MUTE
2 x GM x M
SD
GL x L + GR x R
SD
GM x M
GM x M
MUTE
MUTE
GR x R
GL x L
GL x L + GR x R + 2(GM x M)
SD
MUTE
MUTE
GR x R + GM x M
GR x R
GL x L + GM x M
GL x L
GR x R + GL x L
TI 3D ENHANCEMENT
The LM4947 features a stereo headphone, 3D audio enhancement effect that widens the perceived soundstage
from a stereo audio signal. The 3D audio enhancement creates a perceived spatial effect optimized for stereo
headphone listening. The LM4947 can be programmed for a “narrow” or “wide” soundstage perception. The
narrow soundstage has a more focused approaching sound direction, while the wide soundstage has a spatial,
theater-like effect. Within each of these two modes, four discrete levels of 3D effect that can be programmed:
low, medium, high, and maximum (Table 2), each level with an ever increasing aural effect, respectively. The
difference between each level is 3dB.
The external capacitors, shown in Figure 88, are required to enable the 3D effect. The value of the capacitors set
the cutoff frequency of the 3D effect, as shown by Equation 1 and Equation 2. Note that the internal 20kΩ
resistor is nominal (±25%).
(internal resistors)
LM4947
C
3DL
C
3DR
C
C
3DR
3DL
Figure 88. External 3D Effect Capacitors
f3DL(-3dB) = 1 / 2π * 20kΩ * C3DL
f3DR(-3dB) = 1 / 2π * 20kΩ * C3DR
(1)
(2)
Optional resistors R3DL and R3DR can also be added (Figure 89) to affect the -3dB frequency and 3D magnitude.
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(internal resistors)
LM4947
C
3DL
C
3DR
R
R
3DR
3DL
Figure 89. External RC Network with Optional R3DL and R3DR Resistors
f3DL(-3dB) = 1 / 2π * (20kΩ + R3DL) * C3DL
f3DR(-3dB) = 1 / 2π * 20kΩ + R3DR) * C3DR
(3)
(4)
ΔAV (change in AC gain) = 1 / 1 + M, where M represents some ratio of the nominal internal resistor, 20kΩ (see
example below).
f3dB (3D) = 1 / 2π (1 + M)(20kΩ * C3D
)
(5)
(6)
CEquivalent (new) = C3D / 1 + M
Table 7. Pole Locations
R3D (kΩ)
(optional)
C3D (nF)
M
ΔAV (dB)
f-3dB (3D)
(Hz)
Value of C3D
to keep same
pole location
(nF)
new Pole
Location
(Hz)
0
1
68
68
68
68
68
0
0
117
111
94
0.05
0.25
0.50
1.00
–0.4
–1.9
–3.5
–6.0
64.8
54.4
45.3
34.0
117
117
117
117
5
10
20
78
59
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8Ω LOAD
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by an 8Ω load from 158.3mW to 156.4mW. The problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
POWER DISSIPATION AND EFFICIENCY
In general terms, efficiency is considered to be the ratio of useful work output divided by the total energy required
to produce it with the difference being the power dissipated, typically, in the IC. The key here is “useful” work. For
audio systems, the energy delivered in the audible bands is considered useful including the distortion products of
the input signal. Sub-sonic (DC) and super-sonic components (>22kHz) are not useful. The difference between
the power flowing from the power supply and the audio band power being transduced is dissipated in the
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LM4947 and in the transducer load. The amount of power dissipation in the LM4947 is very low. This is because
the ON resistance of the switches used to form the output waveforms is typically less than 0.25Ω. This leaves
only the transducer load as a potential "sink" for the small excess of input power over audio band output power.
The LM4947 dissipates only a fraction of the excess power requiring no additional PCB area or copper plane to
act as a heat sink.
The LM4947 also has a pair of single-ended amplifiers driving stereo headphones, RHP and LHP. The maximum
internal power dissipation for RHP and LHP is given by Equation 7 and Equation 8. From Equation 7 and
Equation 8, assuming a 5V power supply and a 32Ω load, the maximum power dissipation for LHP and RHP is
40mW, or 80mW total.
PDMAX-LHP = (VDD)2 / (2π2 RL): Single-ended Mode
PDMAX-RHP = (VDD)2 / (2π2 RL): Single-ended Mode
(7)
(8)
The maximum internal power dissipation of the LM4947 occurs when all 3 amplifiers pairs are simultaneously on;
and is given by Equation 9.
PDMAX-TOTAL = PDMAX-SPKROUT + PDMAX-LHP + PDMAX-RHP
(9)
The maximum power dissipation point given by Equation 9 must not exceed the power dissipation given by
Equation 10:
PDMAX = (TJMAX - TA) / θJA
(10)
The LM4947's TJMAX = 150°C. In the ITL package, the LM4947's θJA is 65°C/W. At any given ambient
temperature TA, use Equation 10 to find the maximum internal power dissipation supported by the IC packaging.
Rearranging Equation 10 and substituting PDMAX-TOTAL for PDMAX' results in Equation 11. This equation gives the
maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4947's
maximum junction temperature.
TA = TJMAX - PDMAX-TOTAL θJA
(11)
For a typical application with a 5V power supply and an 8Ω load, the maximum ambient temperature that allows
maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 104°C
for the ITL package.
TJMAX = PDMAX-TOTAL θJA + TA
(12)
Equation 12 gives the maximum junction temperature TJMAX. If the result violates the LM4947's 150°C, reduce
the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.
Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases. If the result of Equation 9 is greater than that of Equation 10,
then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these
measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional
copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.
External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction-to-case thermal impedance,
θCS is the case-to-sink thermal impedance, and θSA is the sink-to-ambient thermal impedance). Refer to the
TYPICAL PERFORMANCE CHARACTERISTICS curves for power dissipation information at lower output power
levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 1µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.1µF tantalum bypass capacitance connected
between the LM4947's supply pins and ground. Keep the length of leads and traces that connect capacitors
between the LM4947's power supply pin and ground as short as possible. Connecting a 2.2µF capacitor, CB,
between the BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's
PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. Too large, however,
increases turn-on time and can compromise the amplifier's click and pop performance. The selection of bypass
capacitor values, especially CB, depends on desired PSRR requirements, click and pop performance (as
explained in the section, SELECTING EXTERNAL COMPONENTS), system cost, and size constraints.
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SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value input coupling capacitor (Ci in Figure 1 and
Figure 2). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In
many cases, however, the speakers used in portable systems, whether internal or external, have little ability to
reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little
improvement by using large input capacitor.
The internal input resistor (Ri), nominal 20kΩ, and the input capacitor (Ci) produce a high pass filter cutoff
frequency that is found using Equation 13.
fc = 1 / (2πRiCi)
(13)
As an example when using a speaker with a low frequency limit of 150Hz, Ci, using Equation 13 is 0.053µF. The
0.22µF Ci shown in Figure 1 allows the LM4947 to drive high efficiency, full range speaker whose response
extends below 40Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor
connected to the BYPASS bump. Since CB determines how fast the LM4947 settles to quiescent operation, its
value is critical when minimizing turn-on pops. The slower the LM4947's outputs ramp to their quiescent DC
voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CB equal to 1.0µF along with a small value of Ci
(in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above,
choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value
should be in the range of 5 times to 7 times the value of Ci. This ensures that output transients are eliminated
when power is first applied or the LM4947 resumes operation after shutdown.
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DEMO BOARD SCHEMATIC
Figure 90.
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REVISION HISTORY
Rev
1.0
Date
Description
06/16/06
06/19/06
Initial release.
1.1
Changed the Class D Efficiency (n) on Typical limit (from 79 to 86) on the 5V
specification table.
1.2
1.3
1.4
1.5
06/22/06
07/18/06
08/29/06
10/18/06
Added more Typ Perf curves.
Replaced some of the curves.
Text edits.
Edited DSBGA pkg drawing, Figure 1 and Figure 2.
Changed IDDQ typical and limit values on the 3.3V and 5.0V specification table.
Removed CMRR SE condition and changed typical values for CMRR BTL on
3.3V and 5.0V specification table.
Changed Mute Attenuation typical value on 5.0V specification table.
1.6
1.7
1.8
1.9
D
03/02/07
03/02/07
09/06/07
11/09/07
05/03/13
Edited the 3.3V and 5V EC tables.
Composed (CONFIDENTIAL) D/S for customer (SAMSUNG).
Edited Table 4.
Text edits.
Changed layout of National Data Sheet to TI format.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM4947TL/NOPB
ACTIVE
DSBGA
YZR
25
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GH1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM4947TL/NOPB
DSBGA
YZR
25
250
178.0
8.4
2.69
2.69
0.76
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
DSBGA YZR 25
SPQ
Length (mm) Width (mm) Height (mm)
208.0 191.0 35.0
LM4947TL/NOPB
250
Pack Materials-Page 2
MECHANICAL DATA
YZR0025xxx
0.600±0.075
D
E
TLA25XXX (Rev D)
D: Max = 2.532 mm, Min =2.472 mm
E: Max = 2.532 mm, Min =2.472 mm
4215055/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
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