LM5010A_14 [TI]
High-Voltage 1-A Step-Down Switching Regulator;
| 型号： | LM5010A_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Voltage 1-A Step-Down Switching Regulator |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5010A
LM5010A-Q1
www.ti.com
SNVS376E –OCTOBER 2005–REVISED FEBRUARY 2013
High-Voltage 1-A Step-Down Switching Regulator
Check for Samples: LM5010A, LM5010A-Q1
1
FEATURES
APPLICATIONS
2
•
•
•
Wide 6V to 75V Input Voltage Range
•
•
•
Non-Isolated Telecommunications Regulator
Valley Current Limiting At 1.25A
Secondary Side Post Regulator
Automotive Electronics
Programmable Switching Frequency Up To 1
MHz
DESCRIPTION
•
•
•
•
•
Integrated 80V N-Channel Buck Switch
Integrated High Voltage Bias Regulator
No Loop Compensation Required
Ultra-Fast Transient Response
The LM5010A Step-Down Switching Regulator is an
enhanced version of the LM5010 with the input
operating range extended to 6V minimum. The
LM5010A features all the functions needed to
implement
a low cost, efficient, buck regulator
Nearly Constant Operating Frequency With
Line and Load Variations
capable of supplying in excess of 1A load current.
This high voltage regulator integrates an N-Channel
Buck Switch, and is available in thermally enhanced
WSON-10 and HTSSOP-14 packages. The constant
on-time regulation scheme requires no loop
compensation resulting in fast load transient
response and simplified circuit implementation. The
operating frequency remains constant with line and
load variations due to the inverse relationship
between the input voltage and the on-time. The valley
current limit detection is set at 1.25A. Additional
features include: VCC under-voltage lock-out, thermal
shutdown, gate drive under-voltage lock-out, and
maximum duty cycle limiter.
•
•
•
•
•
Adjustable Output Voltage
2.5V, ±2% Feedback Reference
Programmable Soft-Start
Thermal Shutdown
LM5010AQ is AEC-Q100 Grade 1 and 0
qualified
•
Packages
–
–
–
WSON-10 (4 mm x 4 mm)
HTSSOP-14
Both Packages Have Exposed Thermal Pad
For Improved Heat Dissipation
Basic Step-Down Regulator
6V - 75V
Input
VCC
VIN
C3
C1
R
ON
LM5010A
BST
SW
C4
L1
RON/SD
V
OUT
SHUTDOWN
D1
R1
R2
R3
SS
ISEN
FB
C2
C6
RTN
SGND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM5010A
LM5010A-Q1
SNVS376E –OCTOBER 2005–REVISED FEBRUARY 2013
www.ti.com
Connection Diagram
14
1
2
3
4
5
6
7
1
2
3
4
5
10
9
SW
NC
NC
VIN
VCC
13
12
11
10
9
VIN
BST
SW
8
BST
ISEN
SGND
RTN
NC
VCC
ISEN
SGND
RTN
RON/SD
7
RON/SD
SS
SS
FB
6
FB
8
NC
Table 1. PIN DESCRIPTIONS
Pin Number
Name
Description
Application Information
WSON-10 HTSSOP-
14
1
2
SW
Switching Node
Internally connected to the buck switch source. Connect to the
inductor, free-wheeling diode, and bootstrap capacitor.
2
3
BST
Boost pin for bootstrap
capacitor
Connect a capacitor from SW to the BST pin. The capacitor is
charged from VCC via an internal diode during the buck switch
off-time.
3
4
ISEN
Current sense
During the buck switch off-time, the inductor current flows
through the internal sense resistor, and out of the ISEN pin to
the free-wheeling diode. The current limit comparator keeps the
buck switch off if the ISEN current exceeds 1.25A (typical).
4
5
6
7
5
6
SGND
RTN
FB
Current Sense Ground
Circuit Ground
Recirculating current flows into this pin to the current sense
resistor.
Ground return for all internal circuitry other than the current
sense resistor.
9
Voltage feedback input from
the regulated output
Input to both the regulation and over-voltage comparators. The
FB pin regulation level is 2.5V.
10
SS
Softstart
An internal 11.5 µA current source charges the SS pin capacitor
to 2.5V to soft-start the reference input of the regulation
comparator.
8
9
11
12
RON/SD
VCC
On-time control and shutdown An external resistor from VIN to the RON/SD pin sets the buck
switch on-time. Grounding this pin shuts down the regulator.
Output of the bias regulator
The voltage at VCC is nominally equal to VIN for VIN < 8.9V,
and regulated at 7V for VIN > 8.9V. Connect a 0.47 µF, or larger
capacitor from VCC to ground, as close as possible to the pins.
An external voltage can be applied to this pin to reduce internal
dissipation if VIN is greater than 8.9V. MOSFET body diodes
clamp VCC to VIN if VCC > VIN
.
10
13
VIN
Input supply voltage
Nominal input range is 6V to 75V. Input bypass capacitors
should be located as close as possible to the VIN pin and RTN
pins.
1,7,8,14
NC
EP
No connection
Exposed Pad
No internal connection. Can be connected to ground plane to
improve heat dissipation.
Exposed metal pad on the underside of the device. It is
recommended to connect this pad to the PC board ground
plane to aid in heat dissipation.
2
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SNVS376E –OCTOBER 2005–REVISED FEBRUARY 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
VIN to RTN
-0.3V to 76V
-0.3V to 90V
-1.5V
BST to RTN
SW to RTN (Steady State)
BST to VCC
76V
BST to SW
14V
VCC to RTN
-0.3V to 14V
-0.3V to +0.3V
-0.3V to 4V
76V
SGND to RTN
SS to RTN
VIN to SW
All Other Inputs to RTN
ESD Rating, Human Body Model(2)
Storage Temperature Range
Lead Temperature (Soldering 4 sec)(3)
-0.3V to 7V
2kV
-65°C to +150°C
260°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
(2) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
(3) For detailed information on soldering plastic HTSSOP and WSON packages, refer to the Packaging Data Book.
(1)
Operating Ratings
VIN Voltage
6.0V to 75V
Junction Temperature
LM5010A, LM5010AQ1
LM5010AQ0
−40°C to + 125°C
−40°C to + 150°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
Electrical Characteristics
Specifications with standard type are for TJ = 25°C only; limits in boldface type apply over the full Operating Junction
Temperature (TJ) range. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical
values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
(1)
otherwise stated the following conditions apply: VIN = 48V, RON = 200kΩ. See
.
Symbol
VCC Regulator
VCCReg
Parameter
Conditions
Min
6.6
Typ
Max
7.4
Unit
VCC regulated output
VIN - VCC
7
Volts
mV
V
ICC = 0 mA, FS < 200 kHz, 6.0V ≤ VIN ≤ 8.5V
VIN Increasing
100
8.9
260
55
VCC Bypass Threshold
VCC Bypass Hysteresis
VIN Decreasing
mV
Ω
VCC output impedance
VIN = 6.0V
(0 mA ≤ ICC ≤ 5 mA)
VIN = 8.0V
50
VIN = 48V
0.21
15
VCC current limit(2)
VIN = 48V, VCC = 0V
VCC Increasing
mA
V
UVLOVcc
VCC under-voltage lock-out
threshold
5.25
UVLOVCC hysteresis
UVLOVCC filter delay
IIN operating current
IIN shutdown current
VCC Decreasing
180
3
mV
µs
100 mV overdrive
Non-switching, FB = 3V
RON/SD = 0V
675
100
950
200
µA
µA
(1) Typical specifications represent the most likely parametric norm at 25°C operation.
(2) VCC provides bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.
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Electrical Characteristics (continued)
Specifications with standard type are for TJ = 25°C only; limits in boldface type apply over the full Operating Junction
Temperature (TJ) range. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical
values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 48V, RON = 200kΩ. See (1)
.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Switch Characteristics
RDS(on)
Buck Switch RDS(on) at ISW = 200 TJ ≤ 125°C
0.35
0.80
0.85
4.0
Ω
mA
TJ ≤ 150°C
UVLOGD
Gate Drive UVLO
VBST - VSW Increasing
1.7
3.0
V
UVLOGD hysteresis
400
mV
SOFT-START Pin
ISS
Internal current source
8.0
1
11.5
15
µA
Current Limit
ILIM
Threshold
Current out of ISEN
1.25
130
150
1.5
A
Resistance from ISEN to SGND
Response time
mΩ
ns
On Timer, RON/SD Pin
tON - 1
tON - 2
On-time
VIN = 10V, RON = 200 kΩ
VIN = 75V, RON = 200 kΩ
Voltage at RON/SD rising
2.1
290
0.30
2.75
390
0.7
40
3.4
496
1.05
µs
ns
V
On-time
Shutdown threshold
Threshold hysteresis
mV
Off Timer
tOFF
Minimum Off-time
260
ns
V
Regulation and Over-Voltage Comparators (FB Pin)
VREF
FB regulation threshold
TJ ≤ 125°C
TJ ≤ 150°C
2.445
2.435
2.50
2.550
FB over-voltage threshold
FB bias current
2.9
1
V
nA
Thermal Shutdown
TSD Thermal shutdown temperature
Thermal shutdown hysteresis
Thermal Resistance
175
20
°C
°C
θJA
Junction to Ambient, 0 LFPM Air WSON-10 Package
40
40
°C/W
°C/W
Flow
HTSSOP-14 Package
θJC
Junction to Case
WSON-10 Package
5.2
5.2
HTSSOP-14 Package
4
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Typical Performance Characteristics
VCC vs VIN
VCC vs ICC
10
8.0
6.0
4.0
2.0
0
8
7
6
5
4
3
2
1
0
V
= 8V
IN
V
= 48V
IN
V
= 9V
= 6V
IN
V
IN
V
UVLO
CC
I
= 0 mA
CC
7
V
Externally Loaded
= 400 kHz
CC
F
S
0
1
2
3
4
5
6
8
9
10
0
3
6
9
12
15
I
(mA)
CC
V
(V)
IN
Figure 1.
Figure 2.
On-Time vs VIN and RON
ICC vs Externally Applied VCC
10
9
8
7
6
5
4
3
2
1
0
100
10
F
S
= 700 kHz
F
S
= 400 kHz
R
ON
= 500k
300k
100k
1.0
0.1
F
S
= 80 kHz
V
= 48V
IN
0
6
20
40
(V)
60
80
7
8
9
10
11
12
13
14
V
IN
EXTERNALLY APPLIED V
(V)
CC
Figure 3.
Figure 4.
Voltage at RON/SD Pin
IIN vs VIN
1000
900
800
700
600
500
4.0
3.0
2.0
1.0
R
ON
= 50k
FB = 3V
115k
301k
400
300
200
100
0
511k
R
/SD = 0V
ON
0
0
6
20
40
(V)
60
80
0
6
20
40
(V)
60
80
V
IN
V
IN
Figure 5.
Figure 6.
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BLOCK DIAGRAM
7V BIAS
REGULATOR
LM5010A
Input
VIN
6V-75V
C5
VCC
BST
V
SENSE
IN
V
THERMAL
SHUTDOWN
CC
C3
C1
UVL
Q2
BYPASS
SWITCH
SD
Gate Drive
UVLO
V
GND
IN
C4
R
260 ns
OFF TIMER
START
ON
ON TIMER
START
ON
COMPLETE
Q1
0.7V
LEVEL
SHIFT
R
L1
COMPLETE
RON/SD
DRIVER
SW
Shutdown
Input
D1
CURRENT LIMIT
COMPARATOR
Driver
V
OUT
ISEN
LOGIC
R
CL
R
SENSE
2.5V
11.5 mA
-
62.5 mV
+
(optional)
50 mW
SGND
FB
SS
R1
R2
R3
C2
2.9V
C6
OVER-VOLTAGE
COMPARATOR
RTN
REGULATION
COMPARATOR
GND
6
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FUNCTIONAL DESCRIPTION
VIN
7.0V
UVLO
VCC
SW Pin
Inductor
Current
2.5V
SS Pin
V
OUT
t1
t2
Figure 7. Startup Sequence
The LM5010A Step Down Switching Regulator features all the functions needed to implement a low cost,
efficient buck DC-DC converter capable of supplying in excess of 1A to the load. This high voltage regulator
integrates an 80V N-Channel buck switch, with an easy to implement constant on-time controller. It is available in
the thermally enhanced WSON-10 and HTSSOP-14 packages. The regulator compares the feedback voltage to
a 2.5V reference to control the buck switch, and provides a switch on-time which varies inversely with VIN. This
feature results in the operating frequency remaining relatively constant with load and input voltage variations.
The switching frequency can range from less than 100 kHz to 1.0 MHz. The regulator requires no loop
compensation resulting in very fast load transient response. The valley current limit circuit holds the buck switch
off until the free-wheeling inductor current falls below the current limit threshold, nominally set at 1.25A.
The LM5010A can be applied in numerous applications to efficiently step down higher DC voltages. This
regulator is well suited for 48V telecom applications, as well as the 42V automotive power bus. Features include:
Thermal shutdown, VCC under-voltage lock-out, gate drive under-voltage lock-out, and maximum duty cycle limit.
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Control Circuit Overview
The LM5010A employs a control scheme based on a comparator and a one-shot on-timer, with the output
voltage feedback (FB) compared to an internal reference (2.5V). If the FB voltage is below the reference the
buck switch is turned on for a time period determined by the input voltage and a programming resistor (RON).
Following the on-time the switch remains off for a fixed 260 ns off-time, or until the FB voltage falls below the
reference, whichever is longer. The buck switch then turns on for another on-time period. Referring to the Block
Diagram, the output voltage is set by R1 and R2. The regulated output voltage is calculated as follows:
VOUT = 2.5V x (R1 + R2) / R2
(1)
The LM5010A requires a minimum of 25 mV of ripple voltage at the FB pin for stable fixed-frequency operation. If
the output capacitor’s ESR is insufficient additional series resistance may be required (R3 in the Block Diagram).
The LM5010A operates in continuous conduction mode at heavy load currents, and discontinuous conduction
mode at light load currents. In continuous conduction mode current always flows through the inductor, never
decaying to zero during the off-time. In this mode the operating frequency remains relatively constant with load
and line variations. The minimum load current for continuous conduction mode is one-half the inductor’s ripple
current amplitude. The operating frequency in the continuous conduction mode is calculated as follows:
VOUT x (VIN œ 1.4V)
FS =
1.18 x 10-10 x (RON + 1.4 kW) x VIN
(2)
The buck switch duty cycle is equal to:
VOUT
VIN
tON
DC =
= tON x FS =
tON + tOFF
(3)
Under light load conditions, the LM5010A operates in discontinuous conduction mode, with zero current flowing
through the inductor for a portion of the off-time. The operating frequency is always lower than that of the
continuous conduction mode, and the switching frequency varies with load current. Conversion efficiency is
maintained at a relatively high level at light loads since the switching losses diminish as the power delivered to
the load is reduced. The discontinuous mode operating frequency is approximately:
VOUT2 x L1 x 1.4 x 1020
FS =
2
RL x RON
(4)
where RL = the load resistance.
Start-Up Bias Regulator (VCC)
A high voltage bias regulator is integrated within the LM5010A. The input pin (VIN) can be connected directly to
line voltages between 6V and 75V. Referring to the block diagram and the graph of VCC vs. VIN, when VIN is
between 6V and the bypass threshold (nominally 8.9V), the bypass switch (Q2) is on, and VCC tracks VIN within
100 mV to 150 mV. The bypass switch on-resistance is approximately 50Ω, with inherent current limiting at
approximately 100 mA. When VIN is above the bypass threshold, Q2 is turned off, and VCC is regulated at 7V.
The VCC regulator output current is limited at approximately 15 mA. When the LM5010A is shutdown using the
RON/SD pin, the VCC bypass switch is shut off, regardless of the voltage at VIN.
When VIN exceeds the bypass threshold, the time required for Q2 to shut off is approximately 2 - 3 µs. The
capacitor at VCC (C3) must be a minimum of 0.47 µF to prevent the voltage at VCC from rising above its
absolute maximum rating in response to a step input applied at VIN. C3 must be located as close as possible to
the LM5010A pins.
In applications with a relatively high input voltage, power dissipation in the bias regulator is a concern. An
auxiliary voltage of between 7.5V and 14V can be diode connected to the VCC pin (D2 in Figure 8) to shut off the
VCC regulator, reducing internal power dissipation. The current required into the VCC pin is shown in the Typical
Performance Characteristics. Internally a diode connects VCC to VIN requiring that the auxiliary voltage be less
than VIN.
8
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The turn-on sequence is shown in Figure 7. When VCC exceeds the under-voltage lock-out threshold (UVLO) of
5.25V (t1 in Figure 7), the buck switch is enabled, and the SS pin is released to allow the soft-start capacitor (C6)
to charge up. The output voltage VOUT is regulated at a reduced level which increases to the desired value as the
soft-start voltage increases (t2 in Figure 7).
VCC
C3
BST
C4
L1
LM5010A
D2
SW
VOUT
D1
R1
R2
R3
C2
ISEN
SGND
FB
Figure 8. Self Biased Configuration
Regulation Comparator
The feedback voltage at the FB pin is compared to the voltage at the SS pin (2.5V, ±2%). In normal operation an
on-time period is initiated when the voltage at FB falls below 2.5V. The buck switch conducts for the on-time
programmed by RON, causing the FB voltage to rise above 2.5V. After the on-time period the buck switch
remains off until the FB voltage falls below 2.5V. Input bias current at the FB pin is less than 5 nA over
temperature.
Over-Voltage Comparator
The feedback voltage at FB is compared to an internal 2.9V reference. If the voltage at FB rises above 2.9V the
on-time is immediately terminated. This condition can occur if the input voltage, or the output load, changes
suddenly. The buck switch remains off until the voltage at FB falls below 2.5V.
ON-Time Control
The on-time of the internal buck switch is determined by the RON resistor and the input voltage (VIN), and is
calculated as follows:
1.18 x 10-10 x (RON + 1.4k)
+ 67 ns
tON
=
(VIN - 1.4V)
(5)
The RON resistor can be determined from the desired on-time by re-arranging Equation 5 to the following:
(tON - 67 ns) x (VIN - 1.4V)
- 1.4 kW
RON
=
1.18 x 10-10
(6)
To set a specific continuous conduction mode switching frequency (fS), the RON resistor is determined from the
following:
VOUT x (VIN - 1.4V)
VIN x FS x 1.18 x 10-10
- 1.4 kW
RON
=
(7)
In high frequency applications the minimum value for tON is limited by the maximum duty cycle required for
regulation and the minimum off-time of the LM5010A (260 ns, ±15%). The fixed off-time limits the maximum duty
cycle achievable with a low voltage at VIN. The minimum allowed on-time to regulate the desired VOUT at the
minimum VIN is determined from the following:
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VOUT x 300 ns
tON(min)
=
(VIN(min) œ VOUT
)
(8)
Shutdown
The LM5010A can be remotely shut down by forcing the RON/SD pin below 0.7V with a switch or open drain
device. See Figure 9. In the shutdown mode the SS pin is internally grounded, the on-time one-shot is disabled,
the input current at VIN is reduced, and the VCC bypass switch is turned off. The VCC regulator is not disabled in
the shutdown mode. Releasing the RON/SD pin allows normal operation to resume. The nominal voltage at
RON/SD is shown in the Typical Performance Characteristics. When switching the RON/SD pin, the transition
time should be faster than one to two cycles of the regulator’s nominal switching frequency.
VIN
Input
Voltage
LM5010A
R
ON
RON/SD
STOP
RUN
Figure 9. Shutdown Implementation
Current Limit
Current limit detection occurs during the off-time by monitoring the recirculating current through the internal
current sense resistor (RSENSE). The detection threshold is 1.25A, ±0.25A. Referring to the Block Diagram, if the
current into SGND during the off-time exceeds the threshold level the current limit comparator delays the start of
the next on-time period. The next on-time starts when the current into SGND is below the threshold and the
voltage at FB is below 2.5V. Figure 10 illustrates the inductor current waveform during normal operation and
during current limit. The output current IO is the average of the inductor ripple current waveform. The Low Load
Current waveform illustrates continuous conduction mode operation with peak and valley inductor currents below
the current limit threshold. When the load current is increased (High Load Current), the ripple waveform
maintains the same amplitude and frequency since the current falls below the current limit threshold at the valley
of the ripple waveform. Note the average current in the High Load Current portion of Figure 10 is above the
current limit threshold. Since the current reduces below the threshold in the normal off-time each cycle, the start
of each on-time is not delayed, and the circuit’s output voltage is regulated at the correct value. When the load
current is further increased such that the lower peak would be above the threshold, the off-time is lengthened to
allow the current to decrease to the threshold before the next on-time begins (Current Limited portion of
Figure 10). Both VOUT and the switching frequency are reduced as the circuit operates in a constant current
mode. The load current (IOCL) is equal to the current limit threshold plus half the ripple current (ΔI/2). The ripple
amplitude (ΔI) is calculated from:
(VIN - VOUT) x tON
DI =
L1
(9)
The current limit threshold can be increased by connecting an external resistor (RCL) between SGND and ISEN.
RCL typically is less than 1Ω, and the calculation of its value is explained in Applications Information. If the
current limit threshold is increased by adding RCL, the maximum continuous load current should not exceed 1.5A,
and the peak current out of the SW pin should not exceed 2A.
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I
PK
I
OCL
Current Limit
Threshold
Io
DI
High Load Current
Current Limited
Low Load Current
Normal Operation
Figure 10. Inductor Current - Current Limit Operation
N-Channel Buck Switch and Driver
The LM5010A integrates an N-Channel buck switch and associated floating high voltage gate driver. The peak
current through the buck switch should not exceed 2A, and the load current should not exceed 1.5A. The gate
driver circuit is powered by the external bootstrap capacitor between BST and SW (C4), which is recharged each
off-time from VCC through the internal high voltage diode. The minimum off-time, nominally 260 ns, ensures
sufficient time during each cycle to recharge the bootstrap capacitor. A 0.022 µF ceramic capacitor is
recommended for C4.
Soft-start
The soft-start feature allows the regulator to gradually reach a steady state operating point, thereby reducing
startup stresses and current surges. At turn-on, while VCC is below the under-voltage threshold (t1 in Figure 7),
the SS pin is internally grounded, and VOUT is held at 0V. When VCC exceeds the under-voltage threshold
(UVLO) an internal 11.5 µA current source charges the external capacitor (C6) at the SS pin to 2.5V (t2 in
Figure 7). The increasing SS voltage at the non-inverting input of the regulation comparator gradually increases
the output voltage from zero to the desired value. The soft-start feature keeps the load inductor current from
reaching the current limit threshold during start-up, thereby reducing inrush currents.
An internal switch grounds the SS pin if VCC is below the under-voltage lock-out threshold, or if the circuit is
shutdown using the RON/SD pin.
Thermal Shutdown
The LM5010A should be operated below the Maximum Operating Junction Temperature rating. If the junction
temperature increases during a fault or abnormal operating condition, the internal Thermal Shutdown circuit
activates typically at 175°C. The Thermal Shutdown circuit reduces power dissipation by disabling the buck
switch and the on-timer. This feature helps prevent catastrophic failures from accidental device overheating.
When the junction temperature reduces below approximately 155°C (20°C typical hysteresis), normal operation
resumes.
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APPLICATIONS INFORMATION
EXTERNAL COMPONENTS
The procedure for calculating the external components is illustrated with a design example. Referring to the
Block Diagram, the circuit is to be configured for the following specifications:
•
•
•
•
•
•
VOUT = 5V
VIN = 6V to 60V
FS = 175 kHz
Minimum load current = 200 mA
Maximum load current = 1.0A
Softstart time = 5 ms
R1 and R2: These resistors set the output voltage, and their ratio is calculated from:
R1/R2 = (VOUT/2.5V) - 1
(10)
R1/R2 calculates to 1.0. The resistors should be chosen from standard value resistors in the range of 1.0 kΩ - 10
kΩ. A value of 1.0 kΩ will be used for R1 and for R2.
RON, FS: RON can be chosen using Equation 7 to set the nominal frequency, or from Equation 6 if the on-time at
a particular VIN is important. A higher frequency generally means a smaller inductor and capacitors (value, size
and cost), but higher switching losses. A lower frequency means a higher efficiency, but with larger components.
Generally, if PC board space is tight, a higher frequency is better. The resulting on-time and frequency have a
±25% tolerance. Using Equation 7 at a nominal VIN of 8V,
5V x (8V - 1.4V)
8V x 175 kHz x 1.18 x 10-10
- 1.4 kW = 198 kW
RON
=
(11)
A value of 200 kΩ will be used for RON, yielding a nominal frequency of 161 kHz at VIN = 6V, and 205 kHz at VIN
= 60V.
L1: The guideline for choosing the inductor value in this example is that it must keep the circuit’s operation in
continuous conduction mode at minimum load current. This is not a strict requirement since the LM5010A
regulates correctly when in discontinuous conduction mode, although at a lower frequency. However, to provide
an initial value for L1 the above guideline will be used.
IPK+
IO
IOR
IPK-
0 mA
1/Fs
Figure 11. Inductor Current
To keep the circuit in continuous conduction mode, the maximum allowed ripple current is twice the minimum
load current, or 400 mAp-p. Using this value of ripple current, the inductor (L1) is calculated using the following:
VOUT x (VIN(max) - VOUT
)
L1 =
IOR x FS(min) x VIN(max)
(12)
where FS(min) is the minimum frequency of 154 kHz (205 kHz - 25%) at VIN(max)
.
5V x (60V - 5V)
= 74.4 mH
L1 =
0.40A x 154 kHz x 60V
(13)
12
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This provides a minimum value for L1 - the next higher standard value (100 µH) will be used. To prevent
saturation, and possible destructive current levels, L1 must be rated for the peak current which occurs if the
current limit and maximum ripple current are reached simultaneously (IPK in Figure 10). The maximum ripple
amplitude is calculated by re-arranging Equation 12 using VIN(max), FS(min), and the minimum inductor value,
based on the manufacturer’s tolerance. Assume, for this exercise, the inductor’s tolerance is ±20%.
VOUT x (VIN(max) - VOUT
)
IOR(max)
=
L1min x FS(min) x VIN(max)
(14)
5V x (60V - 5V)
IOR(max)
=
= 372 mAp-p
80 mH x 154 kHz x 60V
(15)
(16)
IPK = ILIM + IOR(max) = 1.5A + 0.372A = 1.872A
where ILIM is the maximum current limit threshold. At the nominal maximum load current of 1.0A, the peak
inductor current is 1.186A.
RCL: Since it is obvious that the lower peak of the inductor current waveform does not exceed 1.0A at maximum
load current (see Figure 11), it is not necessary to increase the current limit threshold. Therefore RCL is not
needed for this exercise. For applications where the lower peak exceeds 1.0A, see INCREASING THE
CURRENT LIMIT THRESHOLD.
C1: This capacitor limits the ripple voltage at VIN resulting from the source impedance of the supply feeding this
circuit, and the on/off nature of the switch current into VIN. At maximum load current, when the buck switch turns
on, the current into VIN steps up from zero to the lower peak of the inductor current waveform (IPK-in Figure 11),
ramps up to the peak value (IPK+), then drops to zero at turn-off. The average current into VIN during this on-time
is the load current. For a worst case calculation, C1 must supply this average current during the maximum on-
time. The maximum on-time is calculated at VIN = 6V using Equation 5, with a 25% tolerance added:
1.18 x 10-10 x (200k + 1.4k)
x 1.25 = 6.5 ms
+ 67 ns
tON(max)
=
6V - 1.4V
(17)
The voltage at VIN should not be allowed to drop below 5.5V in order to maintain VCC above its UVLO.
IO x tON
1.0A x 6.5 ms
C1 =
=
= 13 mF
DV
0.5V
(18)
Normally a lower value can be used for C1 since the above calculation is a worst case calculation which
assumes the power source has a high source impedance. A quality ceramic capacitor with a low ESR should be
used for C1.
C2 and R3: Since the LM5010A requires a minimum of 25 mVp-p of ripple at the FB pin for proper operation, the
required ripple at VOUT is increased by R1 and R2, and is equal to:
VRIPPLE = 25 mVp-p x (R1 + R2)/R2 = 50 mVp-p
(19)
This necessary ripple voltage is created by the inductor ripple current acting on C2’s ESR + R3. First, the
minimum ripple current, which occurs at minimum VIN, maximum inductor value, and maximum frequency, is
determined.
VOUT x (VIN(min) - VOUT
)
IOR(min)
=
L1max x FS(max) x VIN(min)
5V x (6V - 5V)
= 34.5 mAp-p
=
120 mH x 201 kHz x 6V
(20)
The minimum ESR for C2 is then equal to:
50 mV
ESR(min)
=
= 1.45W
34.5 mA
(21)
13
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If the capacitor used for C2 does not have sufficient ESR, R3 is added in series as shown in the Block Diagram.
The value chosen for C2 is application dependent, and it is recommended that it be no smaller than 3.3 µF. C2
affects the ripple at VOUT, and transient response. Experimentation is usually necessary to determine the
optimum value for C2.
C3: The capacitor at the VCC pin provides noise filtering and stability, prevents false triggering of the VCC UVLO
at the buck switch on/off transitions, and limits the peak voltage at VCC when a high voltage with a short rise time
is initially applied at VIN. C3 should be no smaller than 0.47 µF, and should be a good quality, low ESR, ceramic
capacitor, physically close to the IC pins.
C4: The recommended value for C4 is 0.022 µF. A high quality ceramic capacitor with low ESR is recommended
as C4 supplies the surge current to charge the buck switch gate at each turn-on. A low ESR also ensures a
complete recharge during each off-time.
C5: This capacitor suppresses transients and ringing due to lead inductance at VIN. A low ESR, 0.1 µF ceramic
chip capacitor is recommended, located physically close to the LM5010A.
C6: The capacitor at the SS pin determines the soft-start time, i.e. the time for the reference voltage at the
regulation comparator, and the output voltage, to reach their final value. The capacitor value is determined from
the following:
tSS x 11.5 mA
C6 =
2.5V
(22)
For a 5 ms softstart time, C6 calculates to 0.022 µF.
D1: A Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high speed
transitions at the SW pin may inadvertently affect the IC’s operation through external or internal EMI. The diode
should be rated for the maximum VIN (60V), the maximum load current (1A), and the peak current which occurs
when current limit and maximum ripple current are reached simultaneously (IPK in Figure 10), previously
calculated to be 1.87A. The diode’s forward voltage drop affects efficiency due to the power dissipated during the
off-time. The average power dissipation in D1 is calculated from:
PD1 = VF x IO x (1 - D)
(23)
where IO is the load current, and D is the duty cycle.
FINAL CIRCUIT
The final circuit is shown in Figure 12, and its performance is shown in Figure 13 and Figure 14. Current limit
measured approximately 1.3A.
6 - 60V
Input
VIN
VCC
13
C5
0.1 mF
12
C3
0.47 mF
C1
4.4 mF
LM5010A
R
ON
BST
3
200k
0.022 mF
C4
L1 100 mH
RON/SD
11
SW
2
5V
V
OUT
D1
SS
10
ISEN
4
R1
1.0k
R3
1.5
C6
0.022 mF
FB
9
SGND
5
C2
22 mF
R2
1.0k
6
RTN
GND
Figure 12. Example Circuit
14
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Table 2. Bill of Materials
Item
C1
Description
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Schottky Diode
Inductor
Value
(2) 2.2 µF, 100V
22 µF, 16V
0.47 µF, 16V
0.022 µF, 16V
0.1 µF, 100V
100V, 6A
100 µH
C2
C3
C4, C6
C5
D1
L1
R1
Resistor
1.0 kΩ
R2
Resistor
1.0 kΩ
R3
Resistor
1.5 Ω
RON
U1
Resistor
200 kΩ
LM5010A
100
80
250
200
150
100
50
V
= 6V
IN
12V
60V
60
40
20
Load Curent = 500 mA
0
200
400
600
800
1000
0
6
20
60
40
LOAD CURRENT (mA)
V
(V)
IN
Figure 13. Efficiency vs Load Current and VIN
Circuit of Figure 12
Figure 14. Frequency vs VIN
Circuit of Figure 12
MINIMUM LOAD CURRENT
The LM5010A requires a minimum load current of 500 µA. If the load current falls below that level, the bootstrap
capacitor (C4) may discharge during the long off-time, and the circuit will either shutdown, or cycle on and off at
a low frequency. If the load current is expected to drop below 500 µA in the application, R1 and R2 should be
chosen low enough in value so they provide the minimum required current at nominal VOUT
.
LOW OUTPUT RIPPLE CONFIGURATIONS
For applications where low output voltage ripple is required the output can be taken directly from the low ESR
output capacitor (C2) as shown in Figure 15. However, R3 slightly degrades the load regulation. The specific
component values, and the application determine if this is suitable.
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L1
SW
FB
LM5010A
R3
C2
R1
R2
V
OUT
Figure 15. Low Ripple Output
Where the circuit of Figure 15 is not suitable, the circuits of Figure 16 or Figure 17 can be used.
L1
SW
V
OUT
LM5010A
Cff
R1
R2
R3
FB
C2
Figure 16. Low Output Ripple Using a Feed-Forward Capacitor
In Figure 16, Cff is added across R1 to AC-couple the ripple at VOUT directly to the FB pin. This allows the ripple
at VOUT to be reduced, in some cases considerably, by reducing R3. In the circuit of Figure 12, the ripple at VOUT
ranged from 50 mVp-p at VIN = 6V to 320 mVp-p at VIN = 60V. By adding a 1000 pF capacitor at Cff and
reducing R3 to 0.75Ω, the VOUT ripple was reduced by 50%, ranging from 25 mVp-p to 160 mVp-p.
L1
SW
V
OUT
C2
LM5010A
RA
CB
CA
R1
R2
FB
Figure 17. Low Output Ripple Using Ripple Injection
To reduce VOUT ripple further, the circuit of Figure 17 can be used. R3 has been removed, and the output ripple
amplitude is determined by C2’s ESR and the inductor ripple current. RA and CA are chosen to generate a 40-50
mVp-p sawtooth at their junction, and that voltage is AC-coupled to the FB pin via CB. In selecting RA and CA,
VOUT is considered a virtual ground as the SW pin switches between VIN and -1V. Since the on-time at SW varies
inversely with VIN, the waveform amplitude at the RA/CA junction is relatively constant. R1 and R2 must typically
be increased to more than 10k each to not significantly attenuate the signal provided to FB through CB. Typical
values for the additional components are RA = 200k, CA = 680 pF, and CB = 0.01 µF.
INCREASING THE CURRENT LIMIT THRESHOLD
The current limit threshold is nominally 1.25A, with a minimum value of 1.0A. If, at maximum load current, the
lower peak of the inductor current (IPK-in Figure 11) exceeds 1.0A, resistor RCL must be added between SGND and
ISEN to increase the current limit threshold to equal or exceed that lower peak current. This resistor diverts some
of the recirculating current from the internal sense resistor so that a higher current level is needed to switch the
internal current limit comparator. IPK-is calculated from:
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IOR(min)
IPK- = IO(max)
-
2
(24)
where IO(max) is the maximum load current, and IOR(min) is the minimum ripple current calculated using
Equation 20. RCL is calculated from:
1.0A x 0.11W
RCL
=
IPK- - 1.0A
(25)
where 0.11Ω is the minimum value of the internal resistance from SGND to ISEN. The next smaller standard
value resistor should be used for RCL. With the addition of RCL, and when the circuit is in current limit, the upper
peak current out of the SW pin (IPK in Figure 10) can be as high as:
1.5A x (150 mW + RCL
)
+ IOR(MAX)
IPK
=
RCL
(26)
where IOR(max) is calculated using Equation 14. The inductor L1 and diode D1 must be rated for this current. If IPK
exceeds 2A , the inductor value must be increased to reduce the ripple amplitude. This will necessitate
recalculation of IOR(min), IPK-, and RCL
.
Increasing the circuit’s current limit will increase power dissipation and the junction temperature within the
LM5010A. See PC BOARD LAYOUT AND THERMAL CONSIDERATIONS for guidelines on this issue.
PC BOARD LAYOUT AND THERMAL CONSIDERATIONS
The LM5010A regulation, over-voltage, and current limit comparators are very fast, and will respond to short
duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout must be
as neat and compact as possible, and all the components must be as close as possible to their associated pins.
The two major current loops have currents which switch very fast, and so the loops should be as small as
possible to minimize conducted and radiated EMI. The first loop is that formed by C1, through the VIN to SW
pins, L1, C2, and back to C1. The second loop is that formed by D1, L1, C2, and the SGND and ISEN pins. The
ground connection from C2 to C1 should be as short and direct as possible, preferably without going through
vias. Directly connect the SGND and RTN pin to each other, and they should be connected as directly as
possible to the C1/C2 ground line without going through vias. The power dissipation within the IC can be
approximated by determining the total conversion loss (PIN - POUT), and then subtracting the power losses in the
free-wheeling diode and the inductor. The power loss in the diode is approximately:
PD1 = IO x VF x (1-D)
(27)
where IO is the load current, VF is the diode’s forward voltage drop, and D is the duty cycle. The power loss in the
inductor is approximately:
PL1 = IO2 x RL x 1.1
(28)
where RL is the inductor’s DC resistance, and the 1.1 factor is an approximation for the AC losses. If it is
expected that the internal dissipation of the LM5010A will produce high junction temperatures during normal
operation, good use of the PC board’s ground plane can help considerably to dissipate heat. The exposed pad
on the IC package bottom should be soldered to a ground plane, and that plane should both extend from
beneath the IC, and be connected to exposed ground plane on the board’s other side using as many vias as
possible. The exposed pad is internally connected to the IC substrate. The use of wide PC board traces at the
pins, where possible, can help conduct heat away from the IC. The four No Connect pins on the HTSSOP
package are not electrically connected to any part of the IC, and may be connected to ground plane to help
dissipate heat from the package. Judicious positioning of the PC board within the end product, along with the use
of any available air flow (forced or natural convection) can help reduce the junction temperature.
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REVISION HISTORY
Changes from Revision D (February 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
18
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
LM5010AMH/NOPB
LM5010AMHE/NOPB
LM5010AMHX
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
14
14
14
14
14
14
14
14
94
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Call TI
CU SN
CU SN
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
L5010
AMH
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PWP
PWP
PWP
PWP
PWP
PWP
PWP
250
2500
2500
94
Green (RoHS
& no Sb/Br)
L5010
AMH
TBD
L5010
AMH
LM5010AMHX/NOPB
LM5010AQ0MH/NOPB
LM5010AQ0MHX/NOPB
LM5010AQ1MH/NOPB
LM5010AQ1MHX/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
L5010
AMH
Green (RoHS
& no Sb/Br)
L5010A
Q0MH
2500
94
Green (RoHS
& no Sb/Br)
L5010A
Q0MH
Green (RoHS
& no Sb/Br)
L5010A
Q1MH
2500
Green (RoHS
& no Sb/Br)
L5010A
Q1MH
LM5010ASD
ACTIVE
ACTIVE
WSON
WSON
DPR
DPR
10
10
1000
1000
TBD
Call TI
SN
Call TI
-40 to 150
-40 to 150
L00065B
LM5010ASD/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
L00065B
LM5010ASDX
ACTIVE
ACTIVE
WSON
WSON
DPR
DPR
10
10
4500
4500
TBD
Call TI
SN
Call TI
-40 to 150
-40 to 150
L00065B
L00065B
LM5010ASDX/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM5010A, LM5010A-Q1 :
Catalog: LM5010A
•
Automotive: LM5010A-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5010AMHE/NOPB HTSSOP PWP
LM5010AMHX HTSSOP PWP
14
14
14
14
14
10
10
10
10
250
178.0
330.0
330.0
330.0
330.0
178.0
178.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
6.95
6.95
6.95
6.95
6.95
4.3
8.3
8.3
8.3
8.3
8.3
4.3
4.3
4.3
4.3
1.6
1.6
1.6
1.6
1.6
1.3
1.3
1.3
1.3
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
2500
2500
2500
2500
1000
1000
4500
4500
LM5010AMHX/NOPB HTSSOP PWP
LM5010AQ0MHX/NOPB HTSSOP PWP
LM5010AQ1MHX/NOPB HTSSOP PWP
LM5010ASD
LM5010ASD/NOPB
LM5010ASDX
WSON
WSON
WSON
WSON
DPR
DPR
DPR
DPR
4.3
4.3
LM5010ASDX/NOPB
4.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5010AMHE/NOPB
LM5010AMHX
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
WSON
PWP
PWP
PWP
PWP
PWP
DPR
DPR
DPR
DPR
14
14
14
14
14
10
10
10
10
250
203.0
367.0
367.0
367.0
367.0
203.0
203.0
367.0
367.0
190.0
367.0
367.0
367.0
367.0
190.0
190.0
367.0
367.0
41.0
35.0
35.0
35.0
35.0
41.0
41.0
35.0
35.0
2500
2500
2500
2500
1000
1000
4500
4500
LM5010AMHX/NOPB
LM5010AQ0MHX/NOPB
LM5010AQ1MHX/NOPB
LM5010ASD
LM5010ASD/NOPB
LM5010ASDX
WSON
WSON
LM5010ASDX/NOPB
WSON
Pack Materials-Page 2
MECHANICAL DATA
PWP0014A
MXA14A (Rev A)
www.ti.com
MECHANICAL DATA
DPR0010A
SDC10A (Rev A)
www.ti.com
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相关型号：
LM5010SD/NOPB
IC 1.5 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, DSO10, 4 X 4 MM, LEAD FREE, LLP-10, Switching Regulator or Controller
NSC
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