LM5013QDDARQ1 [TI]
具有超低静态电流 (IQ) 的 6V 至 100V 输入、3.5A 非同步直流/直流降压转换器 | DDA | 8 | -40 to 150;
| 型号： | LM5013QDDARQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有超低静态电流 (IQ) 的 6V 至 100V 输入、3.5A 非同步直流/直流降压转换器 | DDA | 8 | -40 to 150 转换器 |
| 文件： | 总37页 (文件大小：3250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5013-Q1
ZHCSQD0 –APRIL 2022
LM5013-Q1 具有超低IQ 的汽车类100V 输入、3.5A 非同步降压直流/直流转换器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
LM5013-Q1 非同步降压转换器用于在宽输入电压范围
内进行调节，从而最大限度地减少对外部浪涌抑制元件
的需求。50 ns 的最短可控导通时间有助于实现较大的
降压转换比，支持从 48V 标称输入到低电压轨的直接
降压转换，从而降低系统的复杂性并减少解决方案成
本。LM5013-Q1 能够在输入电压突降至 6V 时根据需
要以接近 100% 的占空比继续工作，因而是高性能
48V 电池汽车应用和MHEV/EV 系统的理想选择。
– 器件温度等级1：–40°C 至+125°C 的环境温
度范围
• 提供功能安全
– 有助于进行功能安全系统设计的文档
• 专为可靠耐用的应用而设计
– 6V 至100V 的宽输入电压范围
– 具有–40°C 至+150°C 的结温范围
– 固定3.5 ms 内部软启动计时器
– 峰值电流限制保护
LM5013-Q1 具有集成式高侧功率MOSFET，可提供高
达3.5A 的输出电流。恒定导通时间 (COT) 控制架构可
提供几乎恒定的开关频率，具有出色的负载和线路瞬态
响应。LM5013-Q1 的其他特性包括超低 IQ 运行（可实
现较高的轻负载效率）、创新的峰值过流保护、集成式
VCC 偏置电源和自举二极管、精密使能和输入 UVLO
以及具有自动恢复功能的热关断保护。开漏 PGOOD
指示器可提供进行定序、故障报告和输出电压监视功
能。
– 输入UVLO 和热关断保护
• 针对超低EMI 要求进行了优化
– 符合CISPR 25 5 类标准
• 适用于可扩展的汽车电源
– 与LM5163-Q1 和LM5164-Q1（100V，0.5A 或
1A）引脚对引脚兼容
– 最短导通时间和关闭时间低至50 ns
– 10 µA 空载睡眠电流
– 3.1 µA 关断静态电流
• 通过集成技术减小解决方案尺寸，降低成本
LM5013-Q1 符合汽车 AEC-Q100 1 级标准并采用 8 引
脚 SO PowerPAD™ 封装。1.27mm 引脚间距可以为高
电压应用提供足够的间距。
– COT 模式控制架构
器件信息
封装(1)
– 集成100V、0.25Ω功率MOSFET
– 1.2V 内部电压基准
– 无环路补偿组件
封装尺寸（标称值）
器件型号
LM5013-Q1
SO PowerPAD (8)
4.89mm × 3.90mm
– 内部VCC 偏置稳压器和自举二极管
• 使用WEBENCH® Power Designer 并借助
LM5013-Q1 创建定制稳压器设计
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 混合动力、电动和动力总成系统
• 逆变器和电机控制
• 工业运输
VOUT = 12 V
IOUT = 3.5 A
LO
U1
VIN = 15 V...100 V
33 mH
VIN
SW
CBST
2.2 nF
CIN
LM5013-Q1
COUT
27 mF
2.2 mF
RFB1
EN/UVLO
RON
BST
FB
453 kΩ
RRON
RFB2
100 kΩ
49.9 kΩ
PGOOD
GND
典型应用效率，VOUT = 12V
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBP5
LM5013-Q1
ZHCSQD0 –APRIL 2022
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Table of Contents
8 Application and Implementation..................................16
8.1 Application Information............................................. 16
8.2 Typical Application.................................................... 16
9 Power Supply Recommendations................................23
10 Layout...........................................................................24
10.1 Layout Guidelines................................................... 24
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................29
11.1 Device Support........................................................29
11.2 Documentation Support.......................................... 29
11.3 接收文档更新通知................................................... 30
11.4 支持资源..................................................................30
11.5 Trademarks............................................................. 30
11.6 Electrostatic Discharge Caution..............................30
11.7 术语表..................................................................... 30
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram.........................................10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................15
Information.................................................................... 30
4 Revision History
DATE
REVISION
NOTES
April 2022
*
Initial release
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5 Pin Configuration and Functions
GND
SW
VIN
BST
EP
EN/UVLO
PGOOD
RON
FB
图5-1. 8-Pin SO PowerPAD DDA Package (Top View)
表5-1. Pin Functions
Pin
Type(1)
Description
Name
NO.
GND
1
G
Ground connection for internal circuits
Regulator supply input pin to high-side power MOSFET and internal bias regulator. Connect directly
to the input supply of the buck converter with short, low impedance paths.
VIN
2
3
P/I
Precision enable and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is
below 1.1 V, the converter is in shutdown mode with all functions disabled. If the UVLO voltage is
greater than 1.1 V and below 1.5 V, the converter is in standby mode with the internal VCC
regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up
sequence begins.
EN/UVLO
I
RON
FB
4
5
I
I
On-time programming pin. A resistor between this pin and GND sets the buck switch on time.
Feedback input of voltage regulation comparator
Power-good indicator. This pin is an open-drain output pin. Connect to a source voltage through an
external pullup resistor between 10 kΩto 100 kΩ.
PGOOD
BST
6
7
O
P/I
P
Bootstrap gate-drive supply. Required to connect a high-quality 2.2-nF, 50-V X7R ceramic capacitor
between BST and SW to bias the internal high-side gate driver.
Switching node that is internally connected to the source of the high-side NMOS buck switch.
Connect to the switching node of the power inductor and schottky diode.
SW
8
Exposed pad of the package. No internal electrical connection. Connect the EP to the GND pin and
connect to a large copper plane to reduce thermal resistance.
EP
—
—
(1) G = Ground, I = Input, O = Output, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range (unless otherwise noted) (1)
MIN
–0.3
–1.5
–3
MAX
100
UNIT
VIN to GND
SW to GND
100
SW to GND, <20-ns transient
BST to GND
Pin voltage
105.5
5.5
–3
V
BST to SW
–0.3
–0.3
–0.3
–0.3
EN/UVLO to GND
FB, RON to GND
PGOOD to GND
100
5.5
14
Boostrap
External BST to SW capacitor
capacitor
1.5
2.5
nF
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
–40
–65
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings do not
imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operation
Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be
fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC-Q100-002 (1)
HBM ESD Classification Level 2
±2000
V
V(ESD)
Electrostatic discharge
All pins
±500
±750
V
V
Charge device model (CDM), per AEC-Q100-011,
CDM ESD Classification Level C4B
Corner pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
6.3 Recommended Operating Conditions
Over the operating junction temperature range (unless otherwise noted)
MIN
6
NOM
MAX
100
100
105.5
5.5
UNIT
V
VIN
Input voltage voltage range
Pin voltage
SW to GND
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
Pin voltage
BST to GND
V
Pin voltage
BST to SW
V
Pin voltage
FB, RON to GND
EN/UVLO to GND
5.5
V
Pin voltage
100
14
V
PGOOD to GND
Output current range
FSW
V
IOUT
3.0
3.5
A
1000
1000
2.2
kHz
ns
nF
°C
tON
CBST
TJ
Programmable on time
External BST to SW capacitance
Operating junction temperature
50
150
–40
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6.4 Thermal Information
DDA (SOIC)
8 PINS
29.0
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance (LM5013-Q1 EVM)
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
34.8
RθJC(top)
RθJB
RθJC(bot)
ΨJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
22.8
9.5
Junction-to-case (bottom) thermal resistance
Junction-to-board characterization parameter
Junction-to-top characterization parameter
1.3
9.4
0.3
ΨJT
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TJ = –40°C to +150°C, VIN = 24 V. Typical values are at TJ = 25°C and VEN/UVLO = 2 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IQ-SHUTDOWN
VIN shutdown current
VIN sleep current
VEN = 0 V
3.1
10
9.9
20
40
µA
µA
VEN = 2.5 V, VFB = 1.5 V, VBST –SW = 5 V,
non-switching
IQ-SLEEP
IQ-STANDBY
IQ-ACTIVE
EN/UVLO
VSD-RISING
VSD-FALLING
VEN-RISING
VEN-FALLING
FEEDBACK VOLTAGE
VREF
VIN standby current
VEN = 1.2 V
VEN = 2.5 V
25
µA
µA
VIN active current
450
Shutdown threshold
Shutdown threshold
EN threshold
1.1
V
V
V
V
0.45
1.43
1.35
1.5
1.4
1.6
EN threshold
1.47
FB regulation voltage
1.181
1.2
1.218
V
TIMING
tON1
On time1
On time2
On time3
On time4
On time5
On time6
2550
830
625
245
330
128
ns
ns
ns
ns
ns
ns
VVIN = 12 V, RRON = 75 kΩ
VVIN = 12 V, RRON = 25 kΩ
VVIN = 48 V, RRON = 75 kΩ
VVIN = 48 V, RRON = 25 kΩ
VVIN = 100 V, RRON = 75 kΩ
VVIN = 100 V, RRON = 25 kΩ
tON2
tON3
tON4
tON5
tON6
PGOOD
VPG-UTH
VPG-LTH
FB upper threshold for PGOOD high to low VFB rising
1.1
1.14
1.08
1.2
V
V
FB lower threshold for PGOOD high to low
VFB falling
VFB falling
VFB = 1 V
1.05
1.12
PGOOD upper and lower threshold
hysteresis
VPG-HYS
60
8
mV
RPG
PGOOD pulldown resistance
Ω
BOOTSTRAP
VBST-UV
Gate drive UVLO
VBST falling
2.4
0.25
3.5
3.4
V
POWER SWITCHES
RDSON-HS
High-side MOSFET RDSON
Internal soft start
ISW = –100 mA
Ω
ms
A
SOFT START
tSS
1.75
3.7
4.75
5
CURRENT LIMIT
IPEAK
Peak current limit threshold
4.2
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +150°C, VIN = 24 V. Typical values are at TJ = 25°C and VEN/UVLO = 2 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL SHUTDOWN
TJ-SD
Thermal shutdown threshold (1)
Thermal shutdown hysteresis (1)
Temperature rising
175
10
°C
°C
TJ-HYS
(1) Specified by design, not product tested
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6.6 Typical Characteristics
At TA = 25°C, VOUT = 12 V, LO = 33 µH, RRON = 105 kΩ, unless otherwise specified
图6-2. Load and Line Regulation
图6-1. Conversion Efficiency (Linear Scale)
图6-3. Shutdown, Sleep, and Supply Current Versus
Temperature
图6-4. VIN Active Current Versus Temperature
1.21
1.205
1.2
425
400
375
350
325
300
275
250
225
200
175
150
1.195
1.19
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
D009
-40 -20
0
20
40
60
80 100 120 140 160
Junction Temperature (C)
图6-5. Feedback Comparator Threshold Versus Temperature
图6-6. MOSFETs On-State Resistance Versus Temperature
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6.6 Typical Characteristics (continued)
At TA = 25°C, VOUT = 12 V, LO = 33 µH, RRON = 105 kΩ, unless otherwise specified
图6-8. COT On Time Versus VIN
图6-7. Peak Current Limit Versus Temperature
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7 Detailed Description
7.1 Overview
The LM5013-Q1 is an easy-to-use, ultra-low IQ constant on-time (COT) non-synchronous step-down buck
regulator. With an integrated high-side power MOSFET, the LM5013-Q1 is a low-cost, highly efficient buck
converter that operates from a wide input voltage of 6 V to 100 V, delivering up to 3.5-A DC load current. The
LM5013-Q1 is available in an 8-pin SO PowerPAD package with 1.27-mm pin pitch for adequate spacing in high-
voltage applications. This constant on-time (COT) converter is ideal for low-noise, high-current, and fast load
transient requirements, operating with a predictive on-time switching pulse. Over the input voltage range, input
voltage feedforward is employed to achieve a quasi-fixed switching frequency. A controllable on time as low as
50 ns permits high step-down ratios and a minimum forced off time of 50 ns provides extremely high duty cycles,
allowing VIN to drop close to VOUT before frequency foldback occurs. At light loads, the device transitions into an
ultra-low IQ mode to maintain high efficiency and prevent draining battery cells connected to the input when the
system is in standby. The LM5013-Q1 implements a peak current limit detection circuit to ensure robust
protection during output short circuit conditions. Control loop compensation is not required for this regulator,
reducing design time and external component count.
The LM5013-Q1 incorporates additional features for comprehensive system requirements:
• Power-rail sequencing and fault reporting
• Internally-fixed soft start
• Open-drain power good
• Monotonic start-up into prebiased loads
• Precision enable for programmable line undervoltage lockout (UVLO)
• Smart cycle-by-cycle current limit for optimal inductor sizing
• Thermal shutdown with automatic recovery
These features enable a flexible and easy-to-use platform for a wide range of applications. The LM5013-Q1
supports a wide range of end-equipment systems requiring a regulated output from a high input supply where
the transient voltage deviates from the DC level. The following are examples of such end equipment systems:
• 48-V automotive systems
• High cell-count battery-pack systems
• Hybrid, electric, and powertrain systems
• Inverter and motor control
The pin arrangement is designed for a simple layout requiring only a few external components.
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7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Control Architecture
The LM5013-Q1 step-down switching converter employs a constant on-time (COT) control scheme. The COT
control scheme sets a fixed on time, tON, of the high-side FET using a timing resistor (RON). tON is adjusted as
VIN changes and is inversely proportional to the input voltage to maintain a fixed frequency when in continuous
conduction mode (CCM). After tON expires, the high-side FET remains off until the feedback pin is equal or below
the 1.2-V reference voltage. To maintain stability, the feedback comparator requires a minimal ripple voltage that
is in-phase with the inductor current during the off time. Furthermore, this change in feedback voltage during the
off time must be large enough to dominate any noise present at the feedback node. The minimum recommended
ripple voltage is 20 mV. See 表7-1 for different types of ripple injection schemes that ensure stability over the full
input voltage range.
During a rapid start-up or a positive load step, the regulator operates with minimum off times until regulation is
achieved. This feature enables extremely fast load transient response with minimum output voltage undershoot.
When regulating the output in steady-state operation, the off time automatically adjusts itself to produce the SW-
pin duty cycle required for output voltage regulation to maintain a fixed switching frequency. In CCM, the
switching frequency, FSW, is programmed by the RRON resistor. Use 方程式 1 to calculate the switching
frequency.
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VOUT (V)∂ 2500
RRON(kW)
FSW (kHz) =
(1)
表7-1. Ripple Generation Methods
Type 1
Type 2
Type 3
Lowest Cost
Reduced Ripple
Minimum Ripple
10
CA
í
20mV
RESR
í
FSW ∂(RFB1 || RFB2 )
DIL(nom)
20mV ∂ VOUT
VFB1 ∂ DIL(nom)
RESR
í
RACA
Ç
VOUT
RESR
í
V
- VOUT ∂ t
)
20mV
(
IN-nom
ON @V
(
)
IN-nom
2∂ VIN ∂FSW ∂COUT
VOUT
RESR
í
2∂ VIN ∂FSW ∂COUT
1
CFF
í
tTR-settling
2p ∂FSW ∂(RFB1 || RFB2
)
CB
í
3∂RFB1
表 7-1 presents three different methods for generating appropriate voltage ripple at the feedback node. Type-1
ripple generation method uses a single resistor, RESR, in series with the output capacitor. The generated voltage
ripple has two components: capacitive ripple caused by the inductor ripple current charging and discharging the
output capacitor and resistive ripple caused by the inductor ripple current flowing into the output capacitor and
through series resistance, RESR. The capacitive ripple component is out-of-phase with the inductor current and
does not decrease monotonically during the off time. The resistive ripple component is in-phase with the inductor
current and decreases monotonically during the off time. The resistive ripple must exceed the capacitive ripple at
VOUT for stable operation. If this condition is not satisfied, unstable switching behavior is observed in COT
converters with multiple on-time bursts in close succession followed by a long off time. The lowest cost
equations define the value of the series resistance RESR to ensure sufficient in-phase ripple at the feedback
node.
Type-2 ripple generation uses a CFF capacitor in addition to the series resistor. As the output voltage ripple is
directly AC-coupled by CFF to the feedback node, the RESR and ultimately the output voltage ripple, are reduced
by a factor of VOUT / VFB1
.
Type-3 ripple generation uses an RC network consisting of RA and CA, and the switch node voltage to generate
a triangular ramp that is in-phase with the inductor current. This triangular wave is the AC-coupled into the
feedback node with capacitor CB. Because this circuit does not use output voltage ripple, it is suited for
applications where low output voltage ripple is critical. The AN-1481 Controlling Output Ripple and Achieving
ESR Independence in Constant On-time (COT) Regulator Designs Application Note provides additional details
on this topic.
备注
For all methods specified, 12 mV is the minimum FB ripple voltage. 20 mV is calculated as a
conservative figure. For wide-VIN ranges, calculating for 20 mV can be insufficient to achieve 12-mV
FB ripple at minimum input voltage. Careful evaluation should be done to ensure the minimum ripple
requirement is fulfilled, or the design can be faced with large output ripple/irregular switching at the
application minimum output voltage.
7.3.2 Internal VCC Regulator and Bootstrap Capacitor
The LM5013-Q1 contains an internal linear regulator that is powered from VIN with a nominal output of 5 V,
eliminating the need for an external capacitor to stabilize the linear regulator. The internal VCC regulator
supplies current to internal circuit blocks including the asynchronous FET driver and logic circuits. The input pin
(VIN) can be connected directly to line voltages up to 100 V. As the power MOSFET has a low total gate charge,
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use a low bootstrap capacitor value to reduce the stress on the internal regulator. It is required to select a high-
quality ceramic bootstrap capacitor with an effective value of 2.2-nF, 50-V X7R as specified in the Absolute
Maximum Ratings. VCC does not have current limit protection, so selecting a higher value capacitance stresses
the internal VCC regulator and can damage the device. A lower capacitance than required is not sufficient to
drive the internal gate of the power MOSFET. An internal diode connects from the VCC regulator to the BST pin
to replenish the charge in the high-side gate drive bootstrap capacitor when the SW voltage is low.
7.3.3 Regulation Comparator
The feedback voltage at FB is compared to an internal 1.2-V reference. The LM5013-Q1 voltage regulation loop
regulates the output voltage by maintaining the FB voltage equal to the internal reference voltage, VREF. A
resistor divider programs the ratio from output voltage, VOUT, to FB.
For a target VOUT setpoint, use 方程式2 to calculate RFB2 based on the selected RFB1
.
1.2V
RFB2
=
∂RFB1
VOUT -1.2V
(2)
TI recommends selecting RFB1 in the range of 100 kΩ to 1 MΩ for most applications. A larger RFB1 consumes
less DC current, which is mandatory if light-load efficiency is critical. RFB1 larger than 1 MΩis not recommended
as the feedback path becomes more susceptible to noise. It is important to route the feedback trace away from
the noisy area of the PCB and minimize the feedback node size. It is important to route the feedback trace away
from the noisy areas of the PCB and minimize the feedback node size. FB resistors, type 3 ripple injection
resistors, or both should be kept close to the device pin.
7.3.4 Internal Soft Start
The LM5013-Q1 employs an internal soft-start control ramp that allows the output voltage to gradually reach a
steady-state operating point, thereby reducing start-up stresses and current surges. The soft-start feature
produces a controlled, monotonic output voltage start-up. The soft-start time is internally set to 3.5 ms.
7.3.5 On-Time Generator
The on time of the LM5013-Q1 high-side FET is determined by the RRON resistor and is inversely proportional to
the input voltage, VIN. The inverse relationship with VIN results in a nearly constant frequency as VIN is varied.
Use 方程式3 to calculate the on time.
RRON kW
(
)
tON ꢀs =
(
)
V
V ∂ 2.5
)
(
IN
(3)
(4)
Use 方程式4 to determine the RRON resistor to set a specific switching frequency in CCM.
VOUT (V)∂2500
RRON(kW) =
FSW (kHz)
Select RRON for a minimum on time (at maximum VIN) greater than 50 ns for proper operation. In addition to this
minimum on time, the maximum frequency for this device is limited to 1 MHz.
7.3.6 Current Limit
The LM5013-Q1 manages overcurrent conditions with cycle-by-cycle current limiting of the peak inductor
current. The current sensed in the high-side MOSFET is compared every switching cycle to the current limit
threshold (4.5 A). There is a 100-ns leading-edge blanking time following the high-side MOSFET turn-on
transition to eliminate false tripping off the current limit comparator. To protect the converter from potential
current runaway conditions, the LM5013-Q1 includes a tOFF timer that is proportional to VIN and VOUT that is
enabled if a 4.5-A peak current limit is detected. As shown in 图7-1, if the peak current in the high-side MOSFET
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exceeds 4.5 A (typical), the present cycle is immediately terminated regardless of the programmed on time (tON),
the high-side MOSFET is turned off and the tOFF timer is activated. This allows the peak inductor current to fall
from 4.5-A peak to an acceptable value to ensure no excessive current in the power stage. This method folds
back the switching frequency to prevent overheating and limits the average output current to less than 4.5 A to
ensure proper short-circuit and heavy-load protection of the LM5013-Q1. This innovative current limit scheme
enables ultra-low duty-cycle operation, permitting large step-down voltage conversions while ensuring robust
protection of the converter.
vFB
VREF
iL
Peak ILIM
IAVG(ILIM)
IAVG1
tOFF
< tON
t
tON
tSW
> tSW
图7-1. Current Limit Timing Diagram
7.3.7 N-Channel Buck Switch and Driver
The LM5013-Q1 integrates an N-channel buck switch and an associated floating high-side gate driver. The gate-
driver circuit works in conjunction with an external bootstrap capacitor and an internal high-voltage bootstrap
diode. A high-quality 2.2-nF, 50-V X7R ceramic capacitor connected between the BST and SW pins provides the
voltage to the high-side driver during the buck switch on time. During the off time, the SW pin is pulled down to
approximately 0 V, and the bootstrap capacitor charges from the internal VCC through the internal bootstrap
diode. The minimum off timer, set to 50 ns (typical), ensures a minimum time each cycle to recharge the
bootstrap capacitor. When the on time is less than 300 ns, the minimum off timer is forced to 250 ns to ensure
that the BST capacitor is charged in a single cycle. This is vital during wake-up from sleep mode when the BST
capacitor is most likely discharged.
7.3.8 Schottky Diode Selection
A Schottky diode is required for all LM5013-Q1 applications to re-circulate the energy in the output inductor
when the high-side MOSFET is off. The reverse breakdown rating of the diode should be greater than the
maximum VIN plus a 25% safety margin, as specified in 节 8. The current rating of the diode should exceed the
maximum DC output current and support the peak current limit (IPEAK current limit) for the best reliability. In this
case, the diode will carry the maximum load current.
7.3.9 Enable/Undervoltage Lockout (EN/UVLO)
The LM5013-Q1 contains a dual-level EN/UVLO circuit. When the EN/UVLO voltage is below 1.1 V (typical), the
converter is in a low-current shutdown mode and the input quiescent current (IQ) is dropped down to 3 µA. When
the voltage is greater than 1.1 V but less than 1.5 V (typical), the converter is in standby mode. In standby mode,
the internal bias regulator is active while the control circuit is disabled. When the voltage exceeds the rising
threshold of 1.5 V (typical), normal operation begins. Install a resistor divider from VIN to GND to set the
minimum operating voltage of the regulator. Use 方程式 5 and 方程式 6 to calculate the input UVLO turn-on and
turn-off voltages, respectively.
≈
’
÷
◊
RUV1
RUV2
V
= 1.5V ∂ 1+
∆
IN(on)
«
(5)
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≈
’
÷
◊
RUV1
RUV2
V
= 1.4V ∂ 1+
∆
IN(off)
«
(6)
TI recommends selecting RUV1 in the range of no more than 1 MΩ for most applications. A larger RUV1
consumes less DC current, which is mandatory if light-load efficiency is critical. If input UVLO is not required, the
power-supply designer can either drive EN/UVLO as an enable input driven by a logic signal or connect it directly
to VIN. If EN/UVLO is directly connected to VIN, the regulator begins switching as soon as the internal bias rails
are active.
7.3.10 Power Good (PGOOD)
The LM5013-Q1 provides a PGOOD flag pin to indicate when the output voltage is within the regulation level.
Use the PGOOD signal for start-up sequencing of downstream converters or for fault protection and output
monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 14 V.
The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the
voltage from a higher voltage pullup rail. When the FB voltage exceeds 95% of the internal reference, VREF, the
internal PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls
below 90% of VREF, an internal 8-Ω PGOOD switch turns on and PGOOD is pulled low to indicate that the
output voltage is out of regulation. The rising edge of PGOOD has a built-in deglitch delay of 5 µs.
7.3.11 Thermal Protection
The LM5013-Q1 includes an internal junction temperature monitor to protect the device in the event of a higher
than normal junction temperature. If the junction temperature exceeds 175°C (typical), thermal shutdown occurs
to prevent further power dissipation and temperature rise. The LM5013-Q1 initiates a restart sequence when the
junction temperature falls to 165°C, based on a typical thermal shutdown hysteresis of 10°C. This is a non-
latching protection, so the device cycles into and out of thermal shutdown if the fault persists.
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
EN/UVLO provides ON and OFF control for the LM5013-Q1. When VEN/UVLO is below approximately 1.1 V, the
device is in shutdown mode. Both the internal linear regulator and the switching regulator are off. The quiescent
current in shutdown mode drops to 3 µA at VIN = 24 V. The LM5013-Q1 also employs internal bias rail
undervoltage protection. If the internal bias supply voltage is below the UV threshold, the regulator remains off.
7.4.2 Standby Mode
The LM5013-Q1 enters standby mode during light or no-load on the output. The LM5013-Q1 enters standby
mode to prevent draining the input power supply. All internal controller circuits are turned off to reduce the
current consumption. The quiescent current in standby mode is 25 μA (typical).
7.4.3 Active Mode
The LM5013-Q1 is in active mode when VEN/UVLO is above the precision enable threshold and the internal bias
rail is above its UV threshold. In COT active mode, the LM5013-Q1 is in one of three modes depending on the
load current:
• CCM with fixed switching frequency when load current is above half of the peak-to-peak inductor current
ripple
• The LM5013-Q1 will enter discontinuous conduction mode when the load current is less than half of the peak-
to-peak inductor current ripple in CCM operation.
• Current limit CCM with peak current limit protection when an overcurrent condition is applied at the output
7.4.4 Sleep Mode
During discontinuous conduction mode, the load current is lower than half of the peak-to-peak inductor current
ripple and the switching frequency decreases when the load is further decreased in pulse skipping mode. A
switching pulse is set when VFB drops below 1.2 V.
As the frequency of operation decreases and VFB remains above 1.2 V (VREF) with the output capacitor sourcing
the load current for greater than 15 µs, the converter enters an ultra-low IQ sleep mode to prevent draining the
input power supply. The input quiescent current (IQ) required by the LM5013-Q1 decreases to 10 µA in sleep
mode, improving the light-load efficiency of the regulator. In this mode, all internal controller circuits are turned
off to ensure very low current consumption by the device. Such low IQ renders the LM5013-Q1 as the best option
to extend operating lifetime for off-battery applications. The FB comparator and internal bias rail are active to
detect when the FB voltage drops below the internal reference, VREF, and the converter transitions out of sleep
mode into active mode. There is a 9-µs wake-up delay from sleep to active states.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The LM5013-Q1 requires only a few external components to step down from a wide range of supply voltages to
a fixed output voltage. Several features are integrated to meet system design requirements, including the
following:
• Precision enable
• Input voltage UVLO
• Internal soft start
• Programmable switching frequency
• A PGOOD indicator
To expedite the process of designing with LM5013-Q1, a LM5013-Q1 design calculator is available on the
product folder under the Design tools & simulation section. This calculator is complemented by an evaluation
module for order, PSPICE models, as well as TI's WEBENCH® Power Designer.
8.2 Typical Application
图8-1 shows the schematic for 48-V to 12-V conversion.
图8-1. Typical Application, VIN(nom) = 48 V, VOUT = 12 V, IOUT(max) = 3.5 A, FSW(nom) = 300 kHz
备注
This and subsequent design examples are provided herein to showcase the LM5013-Q1 converter in
several different applications. Depending on the source impedance of the input supply bus, an
electrolytic capacitor can be required at the input to ensure stability, particularly at low input voltage
and high output current operating conditions. See the Power Supply Recommendations for more
details.
8.2.1 Design Requirements
The target full-load efficiency is 92% based on a nominal input voltage of 48 V and an output voltage of 12 V.
The required input voltage range is 15 V to 100 V. The switching frequency is set by resistor RON at 300 kHz.
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The output voltage soft-start time is 3.5 ms. Refer to LM5013-Q1 EVM User's Guide for more details on
component selection.
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5013-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Switching Frequency (RRON
)
The switching frequency of the LM5013-Q1 is set by the on-time programming resistor placed at RRON. As
shown by 方程式7, a standard 100-kΩ, 1% resistor sets the switching frequency at 300 kHz.
VOUT (V)∂2500
RRON(kW) =
FSW (kHz)
(7)
Note that at very low duty cycles, the 50-ns minimum controllable on time of the high-side MOSFET, tON(min)
,
limits the maximum switching frequency. In CCM, tON(min) limits the voltage conversion step-down ratio for a
given switching frequency. Use 方程式8 to calculate the minimum controllable duty cycle.
DMIN = tON(min) ∂FSW
(8)
Ultimately, the choice of switching frequency for a given output voltage affects the available input voltage range,
solution size, and efficiency. Use 方程式 9 to calculate the maximum supply voltage for a given tON(min) before
switching frequency reduction occurs.
VOUT
V
=
IN(max)
tON(min) ∂FSW
(9)
8.2.2.3 Buck Inductor (LO)
Use 方程式 10 and 方程式 11 to calculate the inductor ripple current (assuming CCM operation) and peak
inductor current, respectively.
≈
’
÷
◊
VOUT
VOUT
DIL =
∂ 1-
∆
FSW ∂LO
V
IN
«
(10)
(11)
DIL
2
IL(peak) = IOUT(max)
+
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For most applications, choose an inductance such that the inductor ripple current, ΔIL, is between 30% and 50%
of the rated load current at nominal input voltage. Use 方程式12 to calculate the inductance.
≈
∆
«
’
VOUT
VOUT
LO
=
∂ 1-
∆
÷
÷
◊
FSW ∂ DIL
V
IN(nom)
(12)
For applications in which the device must support input transients exceeding 72 V, it is advised to select the
inductor to be at least 22 μH. This ensures that excessive current rise does not occur in the power stage due to
the potential large inductor current slew that could occur in an output short-circuit condition.
Choosing a 22-μH inductor in this design results in 1.36-A peak-to-peak ripple current at a nominal input voltage
of 48 V, equivalent to 39% of the 3.5-A rated load current. For designs that must operate up to the maximum
input voltage at the full-rated load current of 3.5 A, the inductance will need to increase to ensure current limit
(IPEAK current limit) is not hit.
Check the inductor data sheet to make sure the saturation current of the inductor is well above the current limit
setting of the LM5013-Q1. It is recommended that the saturation current be greater than 7 A. Ferrite-core
inductors have relatively lower core losses and are preferred at high switching frequencies, but exhibit a hard
saturation characteristic — the inductance collapses abruptly when the saturation current is exceeded. This
results in an abrupt increase in inductor ripple current, higher output voltage ripple, and reduced efficiency, in
turn compromising reliability. Note that inductor saturation current levels generally decrease as the core
temperature increases.
8.2.2.4 Schottky Diode (DSW
)
The breakdown voltage rating of the diode is preferred to be 25% higher than the maximum input voltage. In the
target application, the power rating for the diode should exceed the maximum DC output current and support the
peak current limit (IPEAK current limit) for best reliability in most applications.
For example, the LM5013-Q1EVM uses the V8P12-M3/86A Schottky diode. The 120-V breakdown voltage rating
and 8-A current rating make sure that the design can support a 100-V input and a short-circuit condition without
any reliability concern. Furthermore, being that it is a Schottky diode with a low forward voltage and has small
switching losses due to its low junction capacitance, the efficiency figure of the design can be optimized. With
what loss does occur in the device, the package of the diode should be selected so it can have good heat
conduction out of it into the copper ground plane.
8.2.2.5 Output Capacitor (COUT
)
Select a ceramic output capacitor to limit the capacitive voltage ripple at the converter output. This is the
sinusoidal ripple voltage that is generated from the triangular inductor current ripple flowing into and out of the
capacitor. Select an output capacitance using 方程式 13 to limit the voltage ripple component to 0.5% of the
output voltage.
DIL
COUT
í
8 ∂FSW ∂ VOUT(ripple)
(13)
Substituting ΔIL(nom) of 1.36 A gives COUT greater than 10 μF. Considering the voltage coefficients of ceramic
capacitors, a 22-µF, 25-V rated capacitor with X7R dielectric is selected.
8.2.2.6 Input Capacitor (CIN)
An input capacitor is necessary to limit the input ripple voltage while providing AC current to the buck power
stage at every switching cycle. To minimize the parasitic inductance in the switching loop, position the input
capacitors as close as possible to the VIN and GND pins of the LM5013-Q1. The input capacitors conduct a
square-wave current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive
component of AC ripple voltage is a triangular waveform.
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Along with the ESR-related ripple component, use 方程式 14 to calculate the peak-to-peak ripple voltage
amplitude.
IOUT ∂D ∂ 1-D
(
)
+ IOUT ∂RESR
V
=
IN(ripple)
FSW ∂CIN
(14)
Use 方程式 15 to calculate the input capacitance required for a load current, based on an input voltage ripple
specification (ΔVIN).
IOUT ∂D∂ 1- D
(
)
CIN
í
FSW ∂ V
-IOUT ∂RESR
IN(ripple)
(15)
The recommended high-frequency input capacitance is 4.4 µF or higher. Ensure the input capacitor is a high-
quality X7S or X7R ceramic capacitor with sufficient voltage rating for CIN. Based on the voltage coefficient of
ceramic capacitors, choose a voltage rating preferably twice the maximum input voltage. Additionally, some bulk
capacitance can required for large input loop inductance or long wire harnesses used in the system. This
capacitor provides parallel damping to the resonance associated with parasitic inductance of the supply lines
and high-Q ceramics. See the Power Supply Recommendations for more detail.
8.2.2.7 Type 3 Ripple Network
A Type 3 ripple generation network uses an RC filter consisting of RA and CA across SW and VOUT to generate a
triangular ramp that is in-phase with the inductor current. This triangular ramp is then AC-coupled into the
feedback node using capacitor CB as shown in 图8-1. Type 3 ripple injection is suited for applications where low
output voltage ripple is crucial.
Use 方程式16 and 方程式17 to calculate RA and CA to provide the required ripple amplitude at the FB pin.
10
CA
í
FSW ∂ R
RFB2
FB1
(16)
For the feedback resistors RFBT = 453 kΩ and RFBB = 49.9 kΩ values shown in 图 8-1, 方程式 16 dictates a
minimum CA of 742 pF. In this design, a 3300-pF capacitance is chosen. This is done to keep RA within practical
limits between 100 kΩ and 1 MΩ when using 方程式17.
V
- VOUT ∂ t
(
)
IN(nom)
ON(nom)
RACA
í
20mV
(17)
Based on CA set at 3.3 nF, RA is calculated to be 453 kΩ to provide a 20-mV ripple voltage at FB. The general
recommendation for a Type 3 network is to calculate RA and CA to get 20 mV of ripple at typical operating
conditions. A smaller RA can be required to operate below nominal 48-V input.
备注
12 mV of FB ripple or more should be ensured at the minimum input voltage of the design to ensure
stability.
While the amplitude of the generated ripple does not affect the output voltage ripple, it impacts the output
regulation as it reflects as a DC error of approximately half the amplitude of the generated ripple. For example, a
converter circuit with Type 3 network that generates a 40-mV ripple voltage at the feedback node has
approximately 10-mV worse load regulation scaled up through the FB divider to VOUT than the same circuit that
generates a 20-mV ripple at FB. Use 方程式18 to calculate the coupling capacitance, CB.
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tTR-settling
CB í
3∂RFB1
(18)
where
• tTR-settling is the desired load transient response settling time.
CB calculates to 56 pF based on a 75-µs settling time. This value avoids excessive coupling capacitor discharge
by the feedback resistors during sleep intervals when operating at light loads. To avoid capacitance fall-off with
DC bias, use a C0G or NP0 dielectric capacitor for CB.
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8.2.3 Application Curves
VOUT = 12 V
VOUT = 12 V
RON = 102 kΩ
LO = 22 μH
RON = 102 kΩ
LO = 22 μH
图8-2. Conversion Efficiency (Log Scale)
图8-3. Conversion Efficiency (Linear Scale)
VOUT = 12 V
RON = 102 kΩ
LO = 22 μH
VIN = 48 V
VOUT = 12 V
IOUT = 1.75 A to 3.5 A
(Rise/fall time = 1A/μS)
图8-4. Load and Line Regulation Performance
图8-5. Load Step Response
VIN = 48 V
VOUT = 12 V
IOUT = 0 A
VIN = 48 V
VOUT 12 V
Load = 0 A to Short
图8-6. No-Load Start-Up with EN/UVLO
图8-7. Short Circuit Applied
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VIN = 48 V
VOUT 12 V
IOUT = 200 mA
VIN = 48 V
VOUT 12 V
Load = 0 A to Short
图8-9. Light-Load Switching
图8-8. Short Circuit Recovery
Filter used for EMC scan. Additionally, the regulator was
housed in an enclosed shield.
VIN = 48 V
VOUT = 12 V
IOUT = 3.5 A
图8-11. Suggested EMC Filter for CISPR 25 Class 5
Compliance
图8-10. Full-Load Switching
VIN = 48 V
VOUT = 12 V
IOUT = 3.5 A
图8-12. CISPR 25 Class 5 Conducted Emissions Plot, 150 kHz to 110 MHz
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9 Power Supply Recommendations
The LM5013-Q1 buck converter is designed to operate from a wide input voltage range between 6 V and 100 V.
In addition, the input supply must be capable of delivering the required input current to the fully loaded regulator.
Use 方程式19 to estimate the average input current.
VOUT ∂IOUT
IIN
=
V ∂ h
IN
(19)
where
• ηis the efficiency.
If the converter is connected to an input supply through long wires or PCB traces with a large impedance, take
special care to achieve stable performance. The parasitic inductance and resistance of the input cables can
have an adverse effect on converter operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at
VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip
during a load transient. If the converter is operating close to the minimum input voltage, this dip can cause false
UVLO fault triggering and a system reset, in addition to potential stability issues. The circuit can be damped with
a "parallel damping network." For example, a 22-μF damping capacitor in series with a 1.4-Ω resistor
connected to the VIN node creates a parallel damped network, providing sufficient damping for a 8.2-μH input
filter inductor and 4.4-μF ceramic input capacitance. Damping is not only needed for an input EMC filter, but
also when the application utilizes a power harness which can present a large input loop inductance. For
example, two cables (one for VIN and one for GND), each one meter (approximately three feet) long with
approximately 1-mm diameter (18 AWG), placed 1 cm (approximately 0.4 inch) apart, forms a rectangular loop
resulting in about 1.2 µH of inductance. The Input Filter Design for Switching Power Supplies Application Report
provides more detail on this topic.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as
well as some of the effects mentioned above. The Simple Success with Conducted EMI for DC-DC Converters
Application Report provides helpful suggestions when designing an input filter for any switching regulator.
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10 Layout
10.1 Layout Guidelines
PCB layout is a critical portion of good power supply design. There are several paths that conduct high slew-rate
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or
degrade the power supply performance.
• To help eliminate these problems, bypass the VIN pin to GND with a low-ESR ceramic bypass capacitor with
a high-quality dielectric. Place CIN as close as possible to the LM5013-Q1 VIN and GND pins. Grounding for
both the input and output capacitors must consist of localized top-side planes that connect to the GND pin
and GND PAD.
• Minimize the loop area formed by the input capacitor connections to the VIN and GND pins.
• Locate the inductor and Schottky diode close to the SW pin. Minimize the area of the SW trace or plane to
prevent excessive capacitive coupling.
• Place the Schottky diode anode terminal in close proximity to the input capacitor ground/return.
• Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
• Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
• Place a single-point ground connection to the plane. Route the ground connections for the feedback, soft
start, and enable components to the ground plane. This prevents any switched or load currents from flowing
in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic
output voltage ripple behavior.
• Make VIN, VOUT, and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
• Minimize trace length to the FB pin. Place both feedback resistors, RFB1 and RFB2, close to the FB pin. Place
CFF (if needed) directly in parallel with RFB1. If output setpoint accuracy at the load is important, connect the
VOUT sense at the load. Route the VOUT sense path away from noisy nodes and preferably through a layer on
the other side of a grounded shielding layer.
• The RON pin is sensitive to noise. Thus, locate the RRON resistor as close as possible to the device and route
with minimal lengths of trace. The parasitic capacitance from RON to GND must not exceed 20 pF.
• Provide adequate heat sinking for the LM5013-Q1 to keep the junction temperature below 150°C. For
operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of
heat-sinking vias to connect the exposed pad to the PCB ground plane. If the PCB has multiple copper
layers, these thermal vias must also be connected to inner layer heat-spreading ground planes.
• Reference 节10.2.
10.1.1 Compact PCB Layout for EMI Reduction
Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to
minimizing radiated EMI is to identify the pulsing current path and minimize the area of that path.
图 10-1 denotes the critical switching loop of the buck converter power stage in terms of EMI. The topological
architecture of a buck converter means that a particularly high di/dt current path exists in the loop comprising the
input capacitor, the integrated MOSFET of the LM5013-Q1, and Schottky diode. It becomes mandatory to reduce
the parasitic inductance of this loop by minimizing the effective loop area.
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VIN
CIN
2
LM5013-Q1
High
di/dt
loop
BST
High-side
NMOS
gate driver
Q1
LO
SW
VOUT
8
CO
D1
GND
GND
1
图10-1. DC/DC Buck Converter With Power Stage Circuit Switching Loop
The input capacitor provides the primary path for the high di/dt components of the current of the high-side
MOSFET. Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction.
In addition, the cathode of the Schottky diode should be placed closely to the SW pin of the device, while its
anode is kept closely to the GND pin.
Keep the trace connecting SW to the inductor as short as possible and just wide enough to carry the load current
without excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to
minimize parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect the
return terminal of the capacitor to the GND pin and exposed PAD of the LM5013-Q1.
10.1.2 Feedback Resistors
Reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin,
rather than close to the load. This reduces the trace length of FB signal and noise coupling. The FB pin is the
input to the feedback comparator, and as such, is a high impedance node sensitive to noise. The output node is
a low impedance node, so the trace from VOUT to the resistor divider can be long if a short path is not available.
Route the voltage sense trace from the load to the feedback resistor divider, keeping away from the SW node,
the inductor, and VIN to avoid contaminating the feedback signal with switch noise, while also minimizing the
trace length. This is most important when high feedback resistances greater than 100 kΩ are used to set the
output voltage. Also, route the voltage sense trace on a different layer from the inductor, SW node, and VIN so
there is a ground plane that separates the feedback trace from the inductor and SW node copper polygon. This
provides further shielding for the voltage feedback path from switching noise sources.
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10.2 Layout Example
图 10-2 shows an example layout for the PCB top layer of a 2-layer board with essential components placed on
the top side.
图10-2. LM5013-Q1 Layout Example
10.2.1 Thermal Considerations
As with any power conversion device, the LM5013-Q1 dissipates internal power while operating. The effect of
this power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the following:
• Ambient temperature
• Power loss
• Effective thermal resistance, RθJA, of the device
• PCB combination
The maximum internal die temperature for the LM5013-Q1 must be limited to 150°C. This establishes a limit on
the maximum device power dissipation and, therefore, the load current. 方程式 20 shows the relationships
between the important parameters. It is easy to see that larger ambient temperatures (TA) and larger values of
RθJA reduce the maximum available output current. The converter efficiency can be estimated by using the
curves provided in this data sheet. Note that these curves include the power loss in the inductor. If the desired
operating conditions cannot be found in one of the curves, then interpolation can be used to estimate the
efficiency. Alternatively, the EVM can be adjusted to match the desired application requirements and the
efficiency can be measured directly. The correct value of RθJA is more difficult to estimate. As stated in the
Semiconductor and IC Package Thermal Metrics Application Report, the value of RθJA given in the Thermal
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Information is not valid for design purposes and must not be used to estimate the thermal performance of the
application. The values reported in that table were measured under a specific set of conditions that are rarely
obtained in an actual application. The data given for RθJC(bott) and ΨJT can be useful when determining thermal
performance. See the Semiconductor and IC Package Thermal Metrics Application Report for more information
and the resources given at the end of this section.
(
TJ - TA
RqJA
)
∂
h
1- h
1
IOUT
=
∂
MAX
VOUT
(20)
where
• ηis the efficiency.
The effective RθJA is a critical parameter and depends on many factors such as the following:
• Power dissipation
• Air temperature/flow
• PCB area
• Copper heat-sink area
• Number of thermal vias under the package
• Adjacent component placement
The LM5013-Q1 features a die attach paddle, or "thermal pad" (EP), to provide a place to solder down to the
PCB heat-sinking copper. This provides a good heat conduction path from the regulator junction to the heat sink
and must be properly soldered to the PCB heat sink copper. Typical examples of RΘJA can be found in 图 10-3.
The copper area given in the graph is for each layer. The top and bottom layers are 2-oz copper each, while the
inner layers are 1 oz. Remember that the data given in this graph is for illustration purposes only, and the actual
performance in any given application depends on all of the previously mentioned factors.
65
2L
4L
60
55
50
45
40
35
30
25
20
15
0
10
20
30
40
50
60
70
80
90
100
110
Copper Area (cm2)
图10-3. Typical RΘJA Versus Copper Area
To continue with the design example, assume that the user has an ambient temperature of 70ºC and wishes to
estimate the required copper area to keep the device junction temperature below 125ºC, at full load. From the
curves in 节 8.2.3, an efficiency of about 92% was found at an input voltage of 48 V with output of 12 V with
1.75-A load. The efficiency will be somewhat less at high junction temperatures, so an efficiency of
approximately 90% is assumed. This gives a total loss of about 2.3 W. Subtracting out the conduction loss alone
for the inductor and catch diode, the user arrives at a device dissipation of about 1.54 W. With this information,
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the user can calculate the required RθJA of about 30ºC/W. Based on 图 10-3, the required copper area is about
40 cm2 for a two-layer PCB.
The engineer's best judgment is to be used if using a lossy inductor, diode, or both in the application, as their
large losses can contribute to localized heating of the component, as well, the nearby regulator. As an example,
biasing the Schottky diode (DSW) with 1.3-A continuous current (average current for 1.75-A load current) results
in approximately 10°C rise in the case temperature of the regulator. This should be "buffered" for in the ambient
temperature used in the previous calculation. For more details on these calculations, please see the PCB
Thermal Design Tips for Automotive DC/DC Converters Application Note.
The following resources can be used as a guide to optimal thermal PCB design and estimating RθJA for a given
application environment:
• LM5013 Thermal Optimization and Example PCB design
• Semiconductor and IC Package Thermal Metrics Application Report
• AN-2020 Thermal Design By Insight, Not Hindsight Application Report
• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report
• Using New Thermal Metrics Application Report
• PCB Thermal Design Tips for Automotive DC/DC Converters Application Report
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.1.2 Development Support
• LM5013-Q1 Quickstart Calculator
• LM5013-Q1 Simulation Models
• TI Reference Design Library
• Technical Articles:
– Use a Low-quiescent-current Switcher for High-voltage Conversion
– How a DC/DC Converter Package and Pinout Design Can Enhance Automotive EMI Performance
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5013-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, LM5012/3/4/3/4-Q1EVM-041 EVM User's Guide
• Texas Instruments, Selecting an Ideal Ripple Generation Network for Your COT Buck Converter Application
Report
• Texas Instruments, Valuing Wide VIN, Low-EMI Synchronous Buck Circuits for Cost-Effective, Demanding
Applications White Paper
• Texas Instruments, An Overview of Conducted EMI Specifications for Power Supplies White Paper
• Texas Instruments, An Overview of Radiated EMI Specifications for Power Supplies White Paper
• Texas Instruments, 24-V AC Power Stage with Wide VIN Converter and Battery Gauge for Smart Thermostat
Design Guide
• Texas Instruments, Accurate Gauging and 50-μA Standby Current, 13S, 48-V Li-ion Battery Pack Reference
Design Guide
• Texas Instruments, AN-2162: Simple Success with Conducted EMI from DC/DC Converters Application
Report
• Texas Instruments, Automotive Cranking Simulator User's Guide
• Texas Instruments, Powering Drones with a Wide VIN DC/DC Converter Application Report
• Texas Instruments, Using New Thermal Metrics Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
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11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5013QDDARQ1
ACTIVE SO PowerPAD
DDA
8
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 150
LM5013
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5013QDDARQ1
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Apr-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO PowerPAD DDA
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
LM5013QDDARQ1
8
2500
Pack Materials-Page 2
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相关型号：
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