LM5019MR/NOPB [TI]
100-V, 100-mA Constant On-Time Synchronous Buck Regulator;
| 型号： | LM5019MR/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 100-V, 100-mA Constant On-Time Synchronous Buck Regulator 开关 光电二极管 输出元件 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM5019
SNVS788F –JANUARY 2012–REVISED DECEMBER 2014
LM5019 100-V, 100-mA Constant On-Time Synchronous Buck Regulator
1 Features
3 Description
The LM5019 is a 100-V, 100-mA synchronous step-
down regulator with integrated high-side and low-side
MOSFETs. The constant-on-time (COT) control
scheme employed in the LM5019 requires no loop
compensation, provides excellent transient response,
and enables very low step-down ratios. The on-time
varies inversely with the input voltage resulting in
nearly constant frequency over the input voltage
range. A high-voltage startup regulator provides bias
power for internal operation of the IC and for
integrated gate drivers.
1
•
Wide 7.5-V to 100-V Input Range
•
Integrated 100-mA High-Side and Low-Side
Switches
•
•
•
•
•
•
•
•
•
•
•
•
•
No Schottky Required
Constant On-Time Control
No Loop Compensation Required
Ultra-Fast Transient Response
Nearly Constant Operating Frequency
Intelligent Peak Current Limit
Adjustable Output Voltage from 1.225 V
Precision 2% Feedback Reference
Frequency Adjustable to 1 MHz
Adjustable Undervoltage Lockout
Remote Shutdown
A peak current limit circuit protects against overload
conditions. The undervoltage lockout (UVLO) circuit
allows the input undervoltage threshold and
hysteresis to be independently programmed. Other
protection features include thermal shutdown and
bias supply undervoltage lockout.
The LM5019 device is available in WSON-8 and SO
PowerPAD-8 plastic packages.
Thermal Shutdown
Packages:
Device Information(1)
–
–
8-Pin WSON
8-Pin SO PowerPAD
PART NUMBER
LM5019
PACKAGE
SO PowerPAD (8)
WSON (8)
BODY SIZE (NOM)
4.89 mm x 3.90 mm
4.00 mm x 4.00 mm
2 Applications
•
•
•
•
Smart Power Meters
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Telecommunication Systems
Automotive Electronics
Isolated Bias Supply
Typical Application
LM5019
7.5V-100V
VIN
7
BST
2
4
+
V
L1
IN
VOUT
C
BST
8
+
SW
C
IN
RON
R
UV2
C
VCC
R
ON
R
VCC
FB
3
FB2
R
C
6
5
UVLO
SD
+
R
UV1
RTN
C
OU
T
R
FB1
1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5019
SNVS788F –JANUARY 2012–REVISED DECEMBER 2014
www.ti.com
Table of Contents
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
Power Supply Recommendations...................... 22
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions ...................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
8
9
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1 Documentation Support ........................................ 23
11.2 Trademarks........................................................... 23
11.3 Electrostatic Discharge Caution............................ 23
11.4 Glossary................................................................ 23
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
Changes from Revision E (December 2013) to Revision F
Page
•
Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
•
•
•
•
•
•
Added package designators to pin out drawings. ................................................................................................................. 3
Changed Thermal Information table. ..................................................................................................................................... 4
Added Timing Requirements table. ........................................................................................................................................ 6
Changed Control Overview section........................................................................................................................................ 9
Changed Soft-Start Circuit graphic....................................................................................................................................... 13
Changed Series Ripple Resistor RC section to Type III Ripple Circuit ................................................................................ 15
Changed Isolated Fly-Buck Converter graphic..................................................................................................................... 17
Changes from Revision D (December 2013) to Revision E
Page
•
Added Thermal Parameters. .................................................................................................................................................. 4
Changes from Revision C (September 2013) to Revision D
Page
•
•
•
•
•
•
Changed Formatting throughout document to the TI standard .............................................................................................. 1
Changed minimum operating input voltage from 9 V to 7.5 V in Features ........................................................................... 1
Changed minimum operating input voltage from 9 V to 7.5 V in Typical Application ........................................................... 1
Changed minimum operating input voltage from 9 V to 7.5 V in Pin Descriptions ............................................................... 3
Added Maximum Junction Temperature................................................................................................................................. 4
Changed minimum operating input voltage from 9 V to 7.5 V in Recommended Operating Conditions. ............................. 4
Changes from Revision B (February 2012) to Revision C
Page
•
Added SW to RTN (100 ns transient) in Absolute Maximum Ratings. .................................................................................. 4
2
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SNVS788F –JANUARY 2012–REVISED DECEMBER 2014
5 Pin Configuration and Functions
8-Pin SO PowerPAD
DDA Package
Top View
8-Pin WSON
NGU Package
Top View
SW
BST
VCC
FB
1
2
3
4
8
RTN
VIN
RTN
VIN
1
2
3
4
8
7
6
5
SW
BST
VCC
FB
7
Power
PAD-8
Exp Pad
WSON-8
UVLO
RON
UVLO
RON
6
5
Exp Pad
Connect Exposed Pad to RTN
Connect Exposed Pad to RTN
Pin Functions
PIN
I/O
DESCRIPTION
APPLICATION INFORMATION
NO.
1
NAME
RTN
VIN
—
I
Ground
Ground connection of the integrated circuit.
Operating input range is 7.5 V to 100 V.
2
Input Voltage
Resistor divider from VIN to UVLO to GND programs the
undervoltage detection threshold. An internal current source is
enabled when UVLO is above 1.225 V to provide hysteresis. When
UVLO pin is pulled below 0.66 V externally, the parts goes in
shutdown mode.
Input Pin of Undervoltage
Comparator
3
UVLO
I
A resistor between this pin and VIN sets the switch on-time as a
function of VIN. Minimum recommended on-time is 100 ns at max
input voltage.
4
5
6
RON
FB
I
I
On-Time Control
This pin is connected to the inverting input of the internal regulation
comparator. The regulation level is 1.225 V.
Feedback
Output From the Internal High
The internal VCC regulator provides bias supply for the gate drivers
Voltage Series Pass Regulator. and other internal circuitry. A 1.0-μF decoupling capacitor is
VCC
O
Regulated at 7.6 V
recommended.
An external capacitor is required between the BST and SW pins
(0.01-μF ceramic). The BST pin capacitor is charged by the VCC
regulator through an internal diode when the SW pin is low.
7
BST
I
Bootstrap Capacitor
Power switching node. Connect to the output inductor and bootstrap
capacitor.
8
SW
EP
O
Switching Node
Exposed Pad
Exposed pad must be connected to RTN pin. Connect to system
ground plane on application board for reduced thermal resistance.
—
—
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6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.3
–1.5
–5
MAX
100
UNIT
V
VIN, UVLO to RTN
SW to RTN
VIN + 0.3
VIN + 0.3
100
V
SW to RTN (100 ns transient)
BST to VCC
V
V
BST to SW
13
V
RON to RTN
–0.3
–0.3
–0.3
100
V
VCC to RTN
13
V
FB to RTN
5
V
Lead Temperature(2)
Maximum Junction Temperature(3)
Storage temperature, Tstg
200
°C
°C
°C
150
–55
150
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Conditions are
conditions under which operation of the device is intended to be functional. For verified specifications and test conditions, see Electrical
Characteristics . The RTN pin is the GND reference electrically connected to the substrate.
(2) For detailed information on soldering plastic PowerPAD package, refer to PowerPAD™ Layout Guidelines (SLOA120). Maximum solder
time not to exceed 4 seconds.
(3) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
100
UNIT
V
VIN Voltage
7.5
Operating Junction Temperature(2)
–40
125
°C
(1) Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test conditions,
see Electrical Characteristics .
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.4 Thermal Information
LM5019
THERMAL METRIC(1)
WSON NGU
SO PowerPAD DDA
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
41.3
3.2
41.1
2.4
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCbot
ΨJB
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal characteristic parameter
Junction-to-board thermal resistance
19.2
19.1
34.7
0.3
24.4
30.6
37.3
6.7
RθJB
RθJCtop
ΨJT
Junction-to-case (top) thermal resistance
Junction-to-top thermal characteristic parameter
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range
unless otherwise stated. VIN = 48 V unless stated otherwise. See(1)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC SUPPLY
VCC Reg VCC Regulator Output
VCC Current Limit
VIN = 48 V, ICC = 20 mA
VIN = 48 V(2)
6.25
26
7.6
8.55
V
mA
VCC Undervoltage Lockout Voltage
(VCC Increasing)
4.15
4.5
4.9
V
VCC Undervoltage Hysteresis
VCC Drop Out Voltage
IIN Operating Current
IIN Shutdown Current
300
2.3
mV
V
VIN = 9 V, ICC = 20 mA
Non-Switching, FB = 3 V
UVLO = 0 V
1.75
50
mA
µA
225
SWITCH CHARACTERISTICS
Buck Switch RDS(ON)
Synchronous RDS(ON)
Gate Drive UVLO
ITEST = 200 mA, BST-SW = 7 V
ITEST = 200 mA
0.8
0.45
3
1.8
1
Ω
Ω
VBST − VSW Rising
2.4
3.6
V
Gate Drive UVLO Hysteresis
260
mV
CURRENT LIMIT
Current Limit Threshold
–40°C ≤ TJ ≤ 125°C
Time to Switch Off
150
240
150
12
300
mA
ns
Current Limit Response Time
Off-Time Generator (Test 1)
Off-Time Generator (Test 2)
FB = 0.1 V, VIN = 48 V
FB = 1 V, VIN = 48 V
µs
µs
2.5
REGULATION AND OVERVOLTAGE COMPARATORS
Internal Reference Trip Point for
Switch ON
FB Regulation Level
1.2
1.225
1.25
V
FB Overvoltage Threshold
FB Bias Current
Trip Point for Switch OFF
1.62
60
V
nA
UNDERVOLTAGE SENSING FUNCTION
UV Threshold
UV Rising
1.19
–10
1.225
–20
1.26
–29
V
µA
V
UV Hysteresis Input Current
Remote Shutdown Threshold
Remote Shutdown Hysteresis
THERMAL SHUTDOWN
UV = 2.5 V
Voltage at UVLO Falling
0.32
0.66
110
mV
Tsd
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
165
20
°C
°C
(1) All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
(2) VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.
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6.6 Switching Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range
unless otherwise stated. VIN = 48 V unless stated otherwise. See(1)
.
MIN
TYP
MAX
UNIT
ON-TIME GENERATOR
TON Test 1
TON Test 2
VIN = 32 V, RON = 100 kΩ
270
188
350
250
460
336
ns
ns
ns
ns
VIN = 48 V, RON = 100 kΩ
VIN = 75 V, RON = 100 kΩ
VIN = 10 V, RON = 250 kΩ
TON Test 3
250
370
500
TON Test 4
1880
3200
4425
MINIMUM OFF-TIME
Minimum Off-Timer
FB = 0 V
144
ns
(1) All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
6.7 Typical Characteristics
Figure 2. VCC vs VIN
Figure 1. Efficiency at 240 kHz, 10 V
Figure 4. ICC vs External VCC
Figure 3. VCC vs ICC
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Typical Characteristics (continued)
Figure 5. TON vs VIN and RON
Figure 6. TOFF (ILIM) vs VFB and VIN
Figure 8. IIN vs VIN (Shutdown)
Figure 7. IIN vs VIN (Operating, Non-Switching)
Figure 9. Switching Frequency vs VIN
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7 Detailed Description
7.1 Overview
The LM5019 step-down switching regulator features all the functions needed to implement a low cost, efficient,
buck converter capable of supplying up to 100 mA to the load. This high-voltage regulator contains 100 V, N-
channel buck and synchronous switches, is easy to implement, and is provided in thermally enhanced SO
PowerPAD-8 and WSON-8 packages. The regulator operation is based on a constant on-time control scheme
using an on-time inversely proportional to VIN. This control scheme does not require loop compensation. The
current limit is implemented with a forced off-time inversely proportional to VOUT. This scheme ensures short
circuit protection while providing minimum foldback.
The LM5019 can be applied in numerous applications to efficiently regulate down higher voltages. This regulator
is well suited for 48 V telecom and automotive power bus ranges. Protection features include: thermal shutdown,
undervoltage lockout, minimum forced off-time, and an intelligent current limit.
7.2 Functional Block Diagram
LM5019
START-UP
V
CC
V
IN
REGULATOR
V UVLO
4.5V
20 µA
UVLO
THERMAL
SHUTDOWN
UVLO
1.225V
SD
VDD REG
BST
0.66V
SHUTDOWN
BG REF
V
IN
DISABLE
ON/OFF
TIMERS
R
ON
SW
COT CONTROL
LOGIC
1.225V
FEEDBACK
FB
ILIM
COMPARATOR
OVER-VOLTAGE
1.62V
+
-
CURRENT
LIMIT
ONE-SHOT
VILIM
RTN
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7.3 Feature Description
7.3.1 Control Overview
The LM5019 buck regulator employs a control principle based on a comparator and a one-shot on-timer, with the
output voltage feedback (FB) compared to an internal reference (1.225 V). If the FB voltage is below the
reference the internal buck switch is turned on for the one-shot timer period, which is a function of the input
voltage and the programming resistor (RON). Following the on-time the switch remains off until the FB voltage
falls below the reference, but never before the minimum off-time forced by the minimum off-time one-shot timer.
When the FB pin voltage falls below the reference and the minimum off-time one-shot period expires, the buck
switch is turned on for another on-time one-shot period. This will continue until regulation is achieved and the FB
voltage is approximately equal to 1.225 V (typ).
In a synchronous buck converter, the low side (sync) FET is ‘on’ when the high side (buck) FET is ‘off’. The
inductor current ramps up when the high side switch is ‘on’ and ramps down when the high side switch is ‘off’.
There is no diode emulation feature in this IC, and therefore, the inductor current may ramp in the negative
direction at light load. This causes the converter to operate in continuous conduction mode (CCM) regardless of
the output loading. The operating frequency remains relatively constant with load and line variations. The
operating frequency can be calculated as shown in Equation 1.
VOUT1
.ꢀx RON
f
=
ꢀ
SW
(1)
Where K = 9 × 10–11
The output voltage (VOUT) is set by two external resistors (RFB1, RFB2). The regulated output voltage is calculated
as shown in Equation 2.
VOUT - 1.225V
1.225V
RFB2
RFB1
=
(2)
This regulator regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum
amount of ESR for the output capacitor (COUT). A minimum of 25 mV of ripple voltage at the feedback pin (FB) is
required for the LM5019. In cases where the capacitor ESR is too small, additional series resistance may be
required (RC in Figure 10).
For applications where lower output voltage ripple is required the output can be taken directly from a low ESR
output capacitor, as shown in Figure 10. However, RC slightly degrades the load regulation.
L1
VOUT
SW
LM5019
R
R
FB2
C
VOUT
(low ripple)
FB
+
C
OUT
R
FB1
Figure 10. Low Ripple Output Configuration
7.3.2 VCC Regulator
The LM5019 contains an internal high-voltage linear regulator with a nominal output of 7.6 V. The input pin (VIN)
can be connected directly to the line voltages up to 100 V. The VCC regulator is internally current limited to
30 mA. The regulator sources current into the external capacitor at VCC. This regulator supplies current to
internal circuit blocks including the synchronous MOSFET driver and the logic circuits. When the voltage on the
VCC pin reaches the undervoltage lockout threshold of 4.5 V, the IC is enabled.
The VCC regulator contains an internal diode connection to the BST pin to replenish the charge in the gate drive
boot capacitor when SW pin is low.
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Feature Description (continued)
At high input voltages, the power dissipated in the high voltage regulator is significant and can limit the overall
achievable output power. As an example, with the input at 48 V and switching at high frequency, the VCC
regulator may supply up to 7 mA of current resulting in 48 V × 7 mA = 336 mW of power dissipation. If the VCC
voltage is driven externally by an alternate voltage source, between 8.55 V and 14 V, the internal regulator is
disabled. This reduces the power dissipation in the IC.
7.3.3 Regulation Comparator
The feedback voltage at FB is compared to an internal 1.225 V reference. In normal operation, when the output
voltage is in regulation, an on-time period is initiated when the voltage at FB falls below 1.225 V. The high side
switch will stay on for the on-time, causing the FB voltage to rise above 1.225 V. After the on-time period, the
high side switch will stay off until the FB voltage again falls below 1.225 V. During start-up, the FB voltage will be
below 1.225 V at the end of each on-time, causing the high side switch to turn on immediately after the minimum
forced off-time of 144 ns. The high side switch can be turned off before the on-time is over if the peak current in
the inductor reaches the current limit threshold.
7.3.4 Overvoltage Comparator
The feedback voltage at FB is compared to an internal 1.62 V reference. If the voltage at FB rises above 1.62 V
the on-time pulse is immediately terminated. This condition can occur if the input voltage and/or the output load
changes suddenly. The high side switch will not turn on again until the voltage at FB falls below 1.225 V.
7.3.5 On-Time Generator
The on-time for the LM5019 is determined by the RON resistor, and is inversely proportional to the input voltage
(VIN), resulting in a nearly constant frequency as VIN is varied over its range. The on-time equation for the
LM5019 is shown in Equation 3.
10-10 x RON
TON
=
VIN
(3)
See Figure 5. RON should be selected for a minimum on-time (at maximum VIN) greater than 100 ns, for proper
operation. This requirement limits the maximum switching frequency for high VIN.
7.3.6 Current Limit
The LM5019 contains an intelligent current limit off-timer. If the current in the buck switch exceeds 240 mA, the
present cycle is immediately terminated, and a non-resetable off-timer is initiated. The length of off-time is
controlled by the FB voltage and the input voltage VIN. As an example, when FB = 0 V and VIN = 48 V, the
maximum off-time is set to 16 μs. This condition occurs when the output is shorted, and during the initial part of
start-up. This amount of time ensures safe short circuit operation up to the maximum input voltage of 100 V.
In cases of overload where the FB voltage is above zero volts (not a short circuit) the current limit off-time is
reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time, and
start-up time. The off-time is calculated from the following equation:
0.07 x VIN
Ps
TOFF(ILIM)
=
VFB + 0.2V
(4)
The current limit protection feature is peak limited. The maximum average output will be less than the peak.
7.3.7 N-Channel Buck Switch and Driver
The LM5019 integrates an N-Channel Buck switch and associated floating high voltage gate driver. The gate
driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A
0.01-uF ceramic capacitor connected between the BST pin and the SW pin provides the voltage to the driver
during the on-time. During each off-time, the SW pin is at approximately 0 V, and the bootstrap capacitor charges
from VCC through the internal diode. The minimum off-timer, set to 144 ns, ensures a minimum time each cycle to
recharge the bootstrap capacitor.
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Feature Description (continued)
7.3.8 Synchronous Rectifier
The LM5019 provides an internal synchronous N-Channel MOSFET rectifier. This MOSFET provides a path for
the inductor current to flow when the high-side MOSFET is turned off.
The synchronous rectifier has no diode emulation mode, and is designed to keep the regulator in continuous
conduction mode even during light loads which would otherwise result in discontinuous operation.
7.3.9 Undervoltage Detector
The LM5019 contains a dual level Undervoltage Lockout (UVLO) circuit. When the UVLO pin voltage is below
0.66 V, the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.66 V but
less than 1.225 V, the controller is in standby mode. In standby mode the VCC bias regulator is active while the
regulator output is disabled. When the VCC pin exceeds the VCC undervoltage threshold and the UVLO pin
voltage is greater than 1.225 V, normal operation begins. An external set-point voltage divider from VIN to GND
can be used to set the minimum operating voltage of the regulator.
UVLO hysteresis is accomplished with an internal 20-μA current source that is switched on or off into the
impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to
quickly raise the voltage at the UVLO pin. The hysteresis is equal to the value of this current times the resistance
RUV2
.
If the UVLO pin is wired directly to the VIN pin, the regulator will begin operation once the VCC undervoltage is
satisfied.
VIN
2
V
IN
+
C
IN
R
R
UV2
UV1
LM5019
3
UVLO
Figure 11. UVLO Resistor Setting
7.3.10 Thermal Protection
The LM5019 should be operated so the junction temperature does not exceed 150°C during normal operation.
An internal Thermal Shutdown circuit is provided to protect the LM5019 in the event of a higher than normal
junction temperature. When activated, typically at 165°C, the controller is forced into a low power reset state,
disabling the buck switch and the VCC regulator. This feature prevents catastrophic failures from accidental
device overheating. When the junction temperature reduces below 145°C (typical hysteresis = 20°C), the VCC
regulator is enabled, and normal operation is resumed.
7.3.11 Ripple Configuration
LM5019 uses Constant-On-Time (COT) control scheme, in which the on-time is terminated by an on-timer, and
the off-time is terminated by the feedback voltage (VFB) falling below the reference voltage (VREF). Therefore, for
stable operation, the feedback voltage must decrease monotonically, in phase with the inductor current during
the off-time. Furthermore, this change in feedback voltage (VFB) during off-time must be large enough to
suppress any noise component present at the feedback node.
Table 1 shows three different methods for generating appropriate voltage ripple at the feedback node. Type 1
and Type 2 ripple circuits couple the ripple at the output of the converter to the feedback node (FB). The output
voltage ripple has two components:
1. Capacitive ripple caused by the inductor current ripple charging/discharging the output capacitor.
2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor.
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Feature Description (continued)
The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not
decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and
decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at the output
node (VOUT) for stable operation. If this condition is not satisfied unstable switching behavior is observed in COT
converters, with multiple on-time bursts in close succession followed by a long off-time.
Type 3 ripple method uses Rr and Cr and the switch node (SW) voltage to generate a triangular ramp. This
triangular ramp is ac coupled using Cac to the feedback node (FB). Since this circuit does not use the output
voltage ripple, it is ideally suited for applications where low output voltage ripple is required. See AN-1481
Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator Designs
(SNVA166) for more details for each ripple generation method.
Table 1. Ripple Configuration
TYPE 1
TYPE 2
TYPE 3
LOWEST COST CONFIGURATION
REDUCED RIPPLE CONFIGURATION
MINIMUM RIPPLE CONFIGURATION
VOUT
VOUT
VOUT
L1
L1
L1
C
ac
R
C
OUT
r
C
R
R
FB2
r
FB2
R
C
R
C
R
FB2
C
ac
To FB
To FB
GND
C
C
OUT
To FB
OUT
R
R
FB1
FB1
R
FB1
GND
GND
5
VOUT
VREF
Cr = 3300 pF
Cac = 100 nF
25 mV
ûIL(MIN)
C >
>
x
RC
g
swꢀ(RFB2||RFB1
)
(VIN(MIN) - VOUT) x TON
25 mV
25 mV
ûIL(MIN)
<
>
RrCr
RC
7.3.12 Soft-Start
A soft-start feature can be implemented with the LM5019 using an external circuit. As shown in Figure 12, the
soft-start circuit consists of one capacitor, C1, two resistors, R1 and R2, and a diode, D. During the initial start-up,
the VCC voltage is established prior to the VOUT voltage. Capacitor C1 is discharged and D is thereby forward
biased. The FB voltage exceeds the reference voltage (1.225 V) and switching is therefore disabled. As capacitor
C1 charges, the voltage at node B gradually decreases and switching commences. VOUT will gradually rise to
maintain the FB voltage at the reference voltage. Once the voltage at node B is less than a diode drop above the
FB voltage, the soft-start sequence is finished and D is reverse biased.
During the initial part of the start-up, the FB voltage can be approximated as follows. Please note that the effect
of R1 has been ignored to simplify the calculation shown in .
RFB1 x RFB2
R2 x (RFB1 + RFB2) + RFB1 x RFB2
VFB = (VCC - VD) x
C1 is charged after the first start up. Diode D1 is optional and can be added to discharge C1 and initialize the
soft-start sequence when the input voltage experiences a momentary drop.
To achieve the desired soft-start, the following design guidance is recommended:
(1) R2 is selected so that VFB is higher than 1.225 V for a VCC of 4.5 V, but is lower than 5 V when VCC is 8.55 V.
If an external VCC is used, VFB should not exceed 5 V at maximum VCC
.
(2) C1 is selected to achieve the desired start-up time that can be determined as shown in .
RFB1 x RFB2
RFB1 + RFB2
)
tS = C1 x (R2 +
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(3) R1 is used to maintain the node B voltage at zero after the soft-start is finished. A value larger than the
feedback resistor divider is preferred.
With component values from the applications from the schematic shown in Figure 13, selecting C1 = 1 µF, R2 = 1
kΩ, R1 = 30 kΩ results in a soft-start time of about 2 ms.
VOUT
VCC
C
1
R
FB2
R
2
To FB
D
D
1
B
R
FB1
R
1
Figure 12. Soft-Start Circuit
7.4 Device Functional Modes
The UVLO pin controls the operating mode of the LM5019 device (see Table 2 for the detailed functional states).
Table 2. UVLO Mode
UVLO
VCC
MODE
DESCRIPTION
VCC regulator disabled.
Switching disabled.
< 0.66 V
Disabled
Shutdown
VCC regulator enabled
Switching disabled.
0.66 V to 1.225 V
> 1.225 V
Enabled
Standby
Standby
Operating
VCC regulator enabled.
Switching disabled.
VCC < 4.5 V
VCC > 4.5 V
VCC enabled.
Switching enabled.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5019 device is step-down dc-dc converter. The device is typically used to convert a higher dc voltage to a
lower dc voltage with a maximum available output current of 100 mA. Use the following design procedure to
select component values for the LM5019 device. Alternately, use the WEBENCH® software to generate a
complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive
database of components when generating a design. This section presents a simplified discussion of the design
process.
8.2 Typical Application
8.2.1 Application Circuit: 12.5 V to 95 V Input and 10 V, 100-mA Output Buck Converter
The application schematic of a buck supply is shown in Figure 13. For output voltage (VOUT) more than one diode
drop higher than the maximum regulation threshold of VCC (8.55 V, see Electrical Characteristics ), the VCC pin
can be connected to VOUT through a diode (D2), to improve efficiency and reduce power dissipation in the IC.
The design example uses equations from the Feature Description section with component names provided in the
Typical Application schematic. Corresponding component designators from Figure 13 are also provided for each
selected value.
SW
12V - 95V
LM5019
VIN
(TP1)
0.01 ꢀF
7
8
BST
SW
2
4
+
V
IN
L1
VOUT
(TP3)
C1
R3
+
+
C4
1 ꢀF
C5
0.1 ꢀF
R5
RON
220 ꢀH
127 N
237 N
R2
3
GND
UVLO
1.5ꢀ
C8
0.1 ꢀF
R1
6.98 N
(TP2)
6
5
UVLO/SD
VCC
FB
R7
14 N
+
C9
4.7 ꢀF
D2
EXP
RTN
1
+
1 N
R6
C7
1 ꢀF
GND
(TP5)
U1
Figure 13. 12.5 V to 95 V Input and 10 V, 100 mA Output Buck Converter
8.2.1.1 Design Requirements
DESIGN PARAMETERS
VALUE
Input Range
Output Voltage
12.5 V to 95 V, transients up to 100 V
10 V
Maximum Output Current
Nominal Switching Frequency
100 mA
≈ 440 kHz
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 RFB1, RFB2
VOUT = VFB × (RFB2 / RFB1 + 1), and since VFB = 1.225 V, the ratio of RFB2 to RFB1 calculates to be 7:1. Standard
values are chosen with RFB2 = R1 = 6.98 kΩ and RFB1 = R6 = 1.00 kΩ are chosen. Other values could be used
as long as the 7:1 ratio is maintained.
8.2.1.2.2 Frequency Selection
At the minimum input voltage, the maximum switching frequency of LM5019 is restricted by the forced minimum
off-time (TOFF(MIN)) as given by Equation 5.
1 - DMAX
TOFF(MIN)
1 - 10/12.5
200 ns
=
= 1 MHz
gSW(MAX)
=
(5)
Similarly, at maximum input voltage, the maximum switching frequency of LM5019 is restricted by the minimum
TON as given by Equation 6.
DMIN
10/48
100 ns
gSW(MAX)
=
=
= 2.1 MHz
TON(MIN)
(6)
Resistor RON sets the nominal switching frequency based on Equation 7.
VOUT
K x RON
gSW
=
(7)
Where:
K = 9 × 10–11
Operation at high switching frequency results in lower efficiency while providing the smallest solution. For this
example 440 kHz was selected, resulting in RON = 253 kΩ. A standard value for RON = R3 = 237 kΩ is selected.
8.2.1.2.3 Inductor Selection
The inductance selection is a compromise between solution size, output ripple, and efficiency. The peak inductor
current at maximum load current should be smaller than the minimum current limit threshold of 150 mA. The
maximum permissible peak to peak inductor ripple is determined by Equation 8.
ΔIL = 2 × (ILIM(min) – IOUT(max)) = 2 × 50 = 100 mA
(8)
The minimum inductance is determined by Equation 9.
VIN - VOUT VOUT
x
ûIL =
L1 x gSW
VIN
(9)
Using maximum VIN of 95 V, the calculation from Equation 9 results in L = 203 μH. A standard value of 220 μH is
selected. With this value of inductance, peak-to-peak minimum and miaximum inductor current ripple of 27 mA
and 92 mA occur at the minimum and maximum input voltages, respectively. For robust short circuit protection,
the inductor saturation current should be higher than the maximum current limit threshold of 300 mA.
8.2.1.2.4 Output Capacitor
The output capacitor is selected to minimize the capacitive ripple across it. The maximum ripple is observed at
maximum input voltage and is given by Equation 10.
ûIL
COUT
=
8 x gsw x ûVripple
(10)
Where:
ΔVripple is the voltage ripple across the capacitor and ΔIL is the inductor ripple current.
Assuming VIN = 95 V and substituting ΔVripple = 10 mV gives COUT = 2.6 μF. A 4.7-μF standard value is selected
for COUT = C9. An X5R or X7R type capacitor with a voltage rating 16 V or higher should be selected.
8.2.1.2.5 Type II Ripple Circuit
Type II ripple circuit as described in Ripple Configuration is chosen for this example. For a constant on time
converter to be stable, the injected in-phase ripple should be larger than the capacitive ripple on COUT
.
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Using type II ripple circuit equations with minimum FB pin ripple of 25 mV, the values of the series resistor RC
and ac coupling capacitor Cac can calculated.
5
C >
g
swꢀ(RFB2||RFB1
)
25 mV
ûIL(MIN)
>
RC
(11)
Assuming RFB2 = 6.98 kΩ and RFB1 = 1 kΩ, the calculated minimum value of Cac is 0.013 µF. A standard value of
0.1 µF is selected for Cac = C8. The value of the series output resistor RC is calculated for the minimum input
voltage condition when the inductor ripple current as at a minimum. Using Equation 9 and assuming VIN = 12.5
V, the minimum inductor ripple current is 27 mA. The calculated minimum value of RC is 0.93 Ω. A standard
value of 1.5 Ω is selected for RC = R2 to provide additional ripple for stable switching at low VIN.
8.2.1.2.6 VCC and Bootstrap Capacitor
The VCC capacitor provides charge to bootstrap capacitor as well as internal circuitry and low side gate driver.
The bootstrap capacitor provides charge to high side gate driver. The recommended value for CVCC = C7 is 1 μF.
A good value for CBST = C1 is 0.01 μF.
8.2.1.2.7 Input Capacitor
Input capacitor should be large enough to limit the input voltage ripple shown in Equation 12.
IOUT(MAX)
8 x gSW x ûVIN
>
CIN
(12)
Choosing a ΔVIN = 0.5 V gives a minimum CIN = 0.06 μF. A standard value of 1.0 μF is selected for CIN = C4.
The input capacitor should be rated for the maximum input voltage under all conditions. A 50-V, X7R dielectric
should be selected for this design.
Input capacitor should be placed directly across VIN and RTN (pin 2 and 1) of the IC. If it is not possible to place
all of the input capacitor close to the IC, a 0.1-μF capacitor should be placed near the IC to provide a bypass
path for the high frequency component of the switching current. This helps limit the switching noise.
8.2.1.2.8 UVLO
The UVLO resistors RUV1 and RUV2 set the UVLO threshold and hysteresis according to Equation 13 and
Equation 14.
V (HYS)
IN
IHYS x RUV2
=
(13)
RUV2
RUV1
VIN (UVLO,rising) = 1.225V x
+ 1
(
)
(14)
Where IHYS = 20 µA. For UVLO hysteresis of 2.5 Vand UVLO rising threshold of 12 V the calculated values of the
UVLO resistors are RUV2 = 127 kΩ and RUV1 = 14.5 kΩ. Selecting standard values for RUV1 = R7 = 14 kΩ and
RUV2 = R5 = 127 kΩ results in UVLO rising threshold of 12.5 V and hysteresis of 2.5 V.
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8.2.1.3 Application Curves
Figure 15. Frequency vs Input Voltage
Figure 14. Efficiency vs Load Current
Figure 16. Typical Switching Waveform (VIN = 48 V, IOUT = 100 mA)
8.2.2 Application Circuit: 20 V to 95 V Input and 10 V, 100 mA Output Isolated Fly-Buck™ Converter
D1
VOUT2
+
C
OUT2
N2
1 µF
X1
N1 150 µH
LM5019
0.01 µF
+
BST
VOUT1
C
BST
VIN
SW
20V-95V
46.4 kΩ
R
1 nF
C
V
IN
r
r
+
+
+
C
OUT1
C
BYP
0.1 µF
RON
R
UV2
C
IN
C
ac
0.1 µF
D2
1 µF
R
ON
130 kΩ
1 µF
127 kΩ
R
FB2
VCC
FB
UVLO
7.32 kΩ
R
UV1
RTN
+
8.25 kΩ
C
VCC
R
FB1
1 µF
1 kΩ
Figure 17. Isolated Fly-Buck Converter Using LM5019
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8.2.2.1 Design Requirements
Selection of external components is illustrated through a design example. The design example specifications are
shown in Table 3.
Table 3. Buck Converter Design Specifications
DESIGN PARAMETERS
VALUE
20 V to 95 V
10 V
Input Voltage Range
Primary Output Voltage
Secondary (Isolated) Output Voltage
Maximum Output Current (Primary + Secondary)
Maximum Power Output
9.5 V
100 mA
1 W
Nominal Switching Frequency
750 kHz
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Transformer Turns Ratio
The transformer turns ratio is selected based on the ratio of the primary output voltage to the secondary
(isolated) output voltage. In this design example, the two outputs are nearly equal and a 1:1 turns ratio
transformer is selected. Therefore, N2 / N1 = 1.
If the secondary (isolated) output voltage is significantly higher or lower than the primary output voltage, a turns
ratio less than or greater than 1 is recommended. The primary output voltage is normally selected based on the
input voltage range such that the duty cycle of the converter does not exceed 50% at the minimum input voltage.
This condition is satisfied if VOUT1 < VIN_MIN / 2.
8.2.2.2.2 Total IOUT
The total primary referred load current is calculated by multiplying the isolated output load(s) by the turns ratio of
the transformer as shown in Equation 15.
N2
I
OUT(MAX) = IOUT1 + IOUT2
´
= 0.1 A
N1
(15)
8.2.2.2.3 RFB1, RFB2
The feedback resistors are selected to set the primary output voltage. The selected value for RFB1 is 1 kΩ. RFB2
can be calculated using the following equations to set VOUT1 to the specified value of 10 V. A standard resistor
value of 7.32 kΩ is selected for RFB2
.
RFB2
RFB1
1+
ꢀ
VOUT1 = 1.225V x (
)
(16)
(17)
:ꢀRFB2 = (1V.225
OUT1
x RFB1 = 7.16 k:
-1
)
8.2.2.2.4 Frequency Selection
Equation 18 is used to calculate the value of RON required to achieve the desired switching frequency.
VOUT1
.ꢀx RON
f
=
ꢀ
SW
(18)
Where K = 9 × 10–11
For VOUT1 of 10 V and fSW of 750 kHz, the calculated value of RON is 148 kΩ. A lower value of 130 kΩ is selected
for this design to allow for second order effects at high switching frequency that are not included in Equation 1.
8.2.2.2.5 Transformer Selection
A coupled inductor or a flyback-type transformer is required for this topology. Energy is transferred from primary
to secondary when the low-side synchronous switch of the buck converter is conducting.
The maximum inductor primary ripple current that can be tolerated without exceeding the buck switch peak
current limit threshold (0.15 A minimum) is given by Equation 19.
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N2
N1
æ
ö
DIL1 = 0.15 - IOUT1 - IOUT2
´
´ 2 = 0.1 A
ç
÷
è
ø
(19)
Using the maximum peak-to-peak inductor ripple current ΔIL1 from Equation 19, the minimum inductor value is
given by Equation 20.
V
IN(MAX) - VOUT
VOUT
L1=
´
= 119.3mH
DI L1´fSW
V
IN(MAX)
(20)
A higher value of 150 µH is selected to insure the high-side switch current does not exceed the minimum peak
current limit threshold.
8.2.2.2.6 Primary Output Capacitor
In a conventional buck converter the output ripple voltage is calculated as shown in Equation 21.
'IL1
x f x COUT1
'VOUT
=
(21)
To limit the primary output ripple voltage ΔVOUT1 to approximately 50 mV, an output capcitor COUT1 of 0.33 µF is
required.
Figure 18 shows the primary winding current waveform (IL1) of a Fly-Buck converter. The reflected secondary
winding current adds to the primary winding current during the buck switch off-time. Because of this increased
current, the output voltage ripple is not the same as in conventional buck converter. The output capacitor value
calculated in Equation 21 should be used as the starting point. Optimization of output capacitance over the entire
line and load range must be done experimentally. If the majority of the load current is drawn from the secondary
isolated output, a better approximation of the primary output voltage ripple is given by Equation 22.
N2
N1
æ
ö
I
´
´TON(MAX)
ç OUT2
÷
è
ø
DVOUT1
=
» 67mV
COUT1
(22)
T
x I
OUT2
x N2/N1
ON(MAX)
IL1
IL2
IOUT2
T
x I
OUT2
ON(MAX)
Figure 18. Current Waveforms for COUT1 Ripple Calculation
A standard 1-µF, 25 V capacitor is selected for this design. If lower output voltage ripple is required, a higher
value should be selected for COUT1 and/or COUT2
.
8.2.2.2.7 Secondary Output Capacitor
A simplified waveform for secondary output current (IOUT2) is shown in Figure 19.
I
OUT2
I
L2
T
x I
OUT2
ON(MAX)
Figure 19. Secondary Current Waveforms for COUT2 Ripple Calculation
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The secondary output current (IOUT2) is sourced by COUT2 during on-time of the buck switch, TON. Ignoring the
current transition times in the secondary winding, the secondary output capacitor ripple voltage can be calculated
using Equation 23.
IOUT2 x TON (MAX)
'VOUT2
=
COUT2
(23)
For a 1:1 transformer turns ratio, the primary and secondary voltage ripple equations are identical. Therefore,
COUT2 is chosen to be equal to COUT1 (1 µF) to achieve comparable ripple voltages on primary and secondary
outputs.
If lower output voltage ripple is required, a higher value should be selected for COUT1 and/or COUT2
.
8.2.2.2.8 Type III Feedback Ripple Circuit
Type III ripple circuit as described in Ripple Configuration is required for the Fly-Buck topology. Type I and Type
II ripple circuits use series resistance and the triangular inductor ripple current to generate ripple at VOUT and the
FB pin. The primary ripple current of a Fly-Buck is the combination or primary and reflected secondary currents
as illustrated in Figure 18. In the Fly-Buck topology, Type I and Type II ripple circuits suffer from large jitter as the
reflected load current affects the feedback ripple.
V
OUT
L1
C
R
r
OUT
C
r
R
FB2
C
ac
GND
To FB
R
FB1
Figure 20. Type III Ripple Circuit
Selecting the Type III ripple components using the equations from Ripple Configuration will guarantee that the FB
pin ripple is be greater than the capacitive ripple from the primary output capacitor COUT1. The feedback ripple
component values are chosen as shown in Equation 24.
C = 1000 pF
r
C
= 0.1 PF
ac
x T
)
R C d (VIN (MIN) - VOUT
50 mV
ON
r
r
(24)
The calculated value for Rr is 66 kΩ. This value provides the minimum ripple for stable operation. A smaller
resistance should be selected to allow for variations in TON, COUT1 and other components. For this design, Rr
value of 46.4 kΩ is selected.
8.2.2.2.9 Secondary Diode
The reverse voltage across secondary-rectifier diode D1 when the high-side buck switch is off can be calculated
using Equation 25.
N2
N1
VD1
=
VIN
(25)
For a VIN_MAX of 95 V and the 1:1 turns ratio of this design, a 100 V Schottky is selected.
8.2.2.2.10 VCC and Bootstrap Capacitor
A 1-µF capacitor of 16 V or higher rating is recommended for the VCC regulator bypass capacitor.
A good value for the BST pin bootstrap capacitor is 0.01-µF with a 16 V or higher rating.
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8.2.2.2.11 Input Capacitor
The input capacitor is typically a combination of a smaller bypass capacitor located near the regulator IC and a
larger bulk capacitor. The total input capacitance should be large enough to limit the input voltage ripple to a
desired amplitude. For input ripple voltage ΔVIN, CIN can be calculated using Equation 26.
IOUT(MAX)
CIN
³
4 ´ f ´ DV
IN
(26)
Choosing a ΔVIN of 0.5 V gives a minimum CIN of 0.067 μF. A standard value of 0.1 μF is selected for for CBYP in
this design. A bulk capacitor of higher value reduces voltage spikes due to parasitic inductance between the
power source to the converter. A standard value of 1 μF is selected for for CIN in this design. The voltage ratings
of the two input capacitors should be greater than the maximum input voltage under all conditions.
8.2.2.2.12 UVLO Resistors
UVLO resistors RUV1 and RUV2 set the undervoltage lockout threshold and hysteresis according to Equation 27
and Equation 28.
VIN (HYS) = IHYS x RUV2
(27)
VIN(UVLO, rising) = 1.225V x (R
UV2
+1
)
RUV1
(28)
Where IHYS = 20 μA, typical.
For a UVLO hysteresis of 2.5 V and UVLO rising threshold of 20 V, Equation 27 and Equation 28 require RUV1 of
8.25 kΩ and RUV2 of 127 kΩ and these values are selected for this design example.
8.2.2.2.13 VCC Diode
Diode D2 is an optional diode connected between VOUT1 and the VCC regulator output pin. When VOUT1 is more
than one diode drop greater than the VCC voltage, the VCC bias current is supplied from VOUT1. This results in
reduced power losses in the internal VCC regulator which improves converter efficiency. VOUT1 must be set to a
voltage at least one diode drop higher than 8.55 V (the maximum VCC voltage) if D2 is used to supply bias
current.
8.2.2.3 Application Curves
VIN = 48 V
IOUT1 = 0 mA
IOUT2 = 100 mA
Figure 22. Steady State Waveform
Figure 21. Efficiency at 750 kHz, VOUT1 = 10 V
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9 Power Supply Recommendations
LM5019 is a power management device. The power supply for the device is any DC voltage source within the
specified input range.
10 Layout
10.1 Layout Guidelines
A proper layout is essential for optimum performance of the circuit. In particular, the following guidelines should
be observed:
1. CIN: The loop consisting of input capacitor (CIN), VIN pin, and RTN pin carries switching currents. Therefore,
the input capacitor should be placed close to the IC, directly across VIN and RTN pins and the connections to
these two pins should be direct to minimize the loop area. In general it is not possible to accommodate all of
input capacitance near the IC. A good practice is to use a 0.1-μF or 0.47-μF capacitor directly across the VIN
and RTN pins close to the IC, and the remaining bulk capacitor as close as possible (see Figure 23).
2. CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high and
low side gate drivers. These two capacitors should also be placed as close to the IC as possible, and the
connecting trace length and loop area should be minimized (see Figure 23).
3. The Feedback trace carries the output voltage information and a small ripple component that is necessary for
proper operation of LM5019. Therefore, care should be taken while routing the feedback trace to avoid
coupling any noise to this pin. In particular, feedback trace should not run close to magnetic components, or
parallel to any other switching trace.
4. SW trace: The SW node switches rapidly between VIN and GND every cycle and is therefore a possible
source of noise. The SW node area should be minimized. In particular, the SW node should not be
inadvertently connected to a copper plane or pour.
10.2 Layout Example
SW
BST
VCC
FB
1
2
3
4
8
RTN
VIN
C
IN
7
Power
PAD-8
UVLO
RON
6
5
C
VCC
Figure 23. Placement of Bypass Capacitors
22
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Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LM5019
LM5019
www.ti.com
SNVS788F –JANUARY 2012–REVISED DECEMBER 2014
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
•
•
•
AN-2240 LM5019 Isolated Evaluation Board (SNOU100)
PowerPAD ™ Layout Guidelines (SLOA120)
AN-1481 Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator
Designs (SNVA166)
•
AN-2238 LM5019 Buck Evaluation Board (SNVA647)
11.2 Trademarks
Fly-Buck is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: LM5019
PACKAGE OPTION ADDENDUM
www.ti.com
10-Sep-2014
PACKAGING INFORMATION
Orderable Device
LM5019MR/NOPB
LM5019MRX/NOPB
LM5019SD/NOPB
LM5019SDX/NOPB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE SO PowerPAD
DDA
8
8
8
8
95
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
L5019
MR
ACTIVE SO PowerPAD
DDA
NGU
NGU
2500
1000
4500
Green (RoHS
& no Sb/Br)
L5019
MR
ACTIVE
ACTIVE
WSON
WSON
Green (RoHS
& no Sb/Br)
L5019
Green (RoHS
& no Sb/Br)
L5019
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Sep-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Sep-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5019MRX/NOPB
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM5019SD/NOPB
LM5019SDX/NOPB
WSON
WSON
NGU
NGU
8
8
1000
4500
178.0
330.0
12.4
12.4
4.3
4.3
4.3
4.3
1.3
1.3
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Sep-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5019MRX/NOPB
LM5019SD/NOPB
LM5019SDX/NOPB
SO PowerPAD
WSON
DDA
NGU
NGU
8
8
8
2500
1000
4500
367.0
210.0
367.0
367.0
185.0
367.0
35.0
35.0
35.0
WSON
Pack Materials-Page 2
MECHANICAL DATA
DDA0008B
MRA08B (Rev B)
www.ti.com
MECHANICAL DATA
NGU0008B
SDC08B (Rev A)
www.ti.com
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