LM5025BMTCX/NOPB [TI]
具有 P 或 N 沟道钳位 FET 和 75% 最大占空比的 90V 有源钳位电压模式 PWM 控制器 | PW | 16 | -40 to 125;
| 型号： | LM5025BMTCX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 P 或 N 沟道钳位 FET 和 75% 最大占空比的 90V 有源钳位电压模式 PWM 控制器 | PW | 16 | -40 to 125 控制器 开关 光电二极管 |
| 文件： | 总26页 (文件大小：746K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5025B
www.ti.com
SNVS354B –JULY 2005–REVISED MARCH 2013
LM5025B Active Clamp Voltage Mode PWM Controller
Check for Samples: LM5025B
1
FEATURES
DESCRIPTION
The LM5025B is a functional variant of the LM5025
active clamp PWM controller. The functional
differences of the LM5025B are as follows:
2
•
•
•
Internal Start-Up Bias Regulator
3A Compound Main Gate Driver
Programmable Line Under-Voltage Lockout
(UVLO) with Adjustable Hysteresis
•
The maximum PWM duty cycle is limited to less
than 75% to reduce voltage stress on the power
MOSFETs.
•
•
•
Voltage Mode Control with Feed-Forward
•
The CS2 hiccup mode threshold is increased to
0.5V
Adjustable Dual Mode Over-Current Protection
Programmable Overlap or Deadtime between
the Main and Active Clamp Outputs
•
•
The CS2 filter discharge device is disabled
The VCC regulator continues to operate when the
line UVLO is below the threshold of normal
operation
•
•
•
•
•
•
•
Volt x Second Maximum Duty Cycle Clamp
Programmable Soft-Start
Current Sense Leading Edge Blanking
Single Resistor Programmable Oscillator
Oscillator Up / Down Sync Capability
Precision 5V Reference
•
•
The VREF regulator is switched off when the line
UVLO input falls below the operating threshold
The internal 5kΩ COMP pin pull-up resistor is
removed
The LM5025B PWM controller contains all of the
features necessary to implement power converters
utilizing the Active Clamp / Reset technique. With the
active clamp technique, higher efficiencies and
greater power densities can be realized compared to
conventional catch winding or RDC clamp / reset
techniques. Two control outputs are provided, the
main power switch control (OUT_A) and the active
clamp switch control (OUT_B). The two internal
compound gate drivers parallel both MOS and Bipolar
devices, providing superior gate drive characteristics.
This controller is designed for high-speed operation
including an oscillator frequency range up to 1MHz
and total PWM and current sense propagation delays
less than 100ns.
Thermal Shutdown
PACKAGES
•
•
TSSOP-16
WSON-16 (5x5 mm) Thermally Enhanced
The LM5025B includes
a high-voltage start-up
regulator that operates over a wide input range of
13V to 100V. Additional features include: Line Under
Voltage Lockout (UVLO), softstart, oscillator
UP/DOWN sync capability, precision reference and
thermal shutdown.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM5025B
SNVS354B –JULY 2005–REVISED MARCH 2013
www.ti.com
Typical Application Circuit
V
OUT
3.3V
V
IN
35 - 78V
LM5025B
CS1
ERROR
AMP &
ISOLATION
V
V
CC
IN
UVLO
OUT_A
OUT_B
RAMP
REF
COMP
CS2
Rt
TIME
PGND
SYNC
SS
AGND
UP/DOWN
SYNC
Figure 1. Simplified Active Clamp Forward Power Converter
Connection Diagram
VIN
RAMP
CS1
16
15
14
13
12
11
10
9
UVLO
SYNC
RT
1
2
3
4
5
6
7
8
CS2
COMP
SS
TIME
REF
AGND
PGND
OUT_B
VCC
OUT_A
Figure 2. 16-Lead TSSOP (See Package Number PW0016A)
16-Lead WSON (See Package Number NHQ0016A)
2
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5025B
LM5025B
www.ti.com
SNVS354B –JULY 2005–REVISED MARCH 2013
PIN DESCRIPTIONS
Pin
Name
Description
Application Information
1
VIN
Source Input Voltage
Input to start-up regulator. Input range 13V to 100V, with
transient capability to 105V.
2
RAMP
Modulator ramp signal
An external RC circuit from Vin sets the ramp slope. This
pin is discharged at the conclusion of every cycle by an
internal FET, initiated by either the internal clock or the
V*Sec Clamp comparator.
3
4
CS1
CS2
Current sense input for cycle-by-cycle limiting
Current sense input for soft restart
If CS1 exceeds 0.25V the outputs will go into Cycle-by-
Cycle current limit. CS1 is held low for 50ns after OUT_A
switches high providing leading edge blanking.
If CS2 exceeds 0.5V the outputs will be disabled and a
softstart commenced. The soft-start capacitor will be fully
discharged and then released with a pull-up current of
1µA. After the first output pulse (when SS =1V), the SS
charge current will revert back to 20µA.
5
TIME
Output overlap/Deadtime control
An external resistor (RSET) sets either the overlap time or
dead time for the active clamp output. An RSET resistor
connected between TIME and GND produces in-phase
OUT_A and OUT_B pulses with overlap. An RSET resistor
connected between TIME and REF produces out-of-phase
OUT_A and OUT_B pulses with deadtime.
6
7
REF
VCC
Precision 5 volt reference output
Maximum output current: 10mA Locally decouple with a
0.1µF capacitor. Reference stays low until the VCC UV
comparator and line UVLO comparator are satisfied.
Output from the internal high voltage start-up
regulator. The VCC voltage is regulated to 7.6V.
If an auxiliary winding raises the voltage on this pin above
the regulation setpoint, the internal start-up regulator will
shutdown, reducing the IC power dissipation.
8
9
OUT_A
OUT_B
Main output driver
Output of the main switch PWM output gate driver. Output
capability of 3A peak sink current.
Active Clamp output driver
Output of the Active Clamp switch gate driver. Capable of
1.25A peak sink current..
10
11
12
PGND
AGND
SS
Power ground
Analog ground
Soft-start control
Connect directly to analog ground.
Connect directly to power ground.
An external capacitor and an internal 20µA current source
set the soft-start ramp. The SS current source is reduced
to 1uA following a CS2 over-current event or an over
temperature event.
13
COMP
Input to the Pulse Width Modulator
PWM duty cycle is controlled by the voltage applied to the
COMP pin. The COMP pin voltage is reduced by a fixed
1V offset and compared with the RAMP pin signal.
14
15
RT
Oscillator timing resistor pin
An external resistor connected from RT to ground sets the
internal oscillator frequency.
SYNC
Oscillator UP/DOWN synchronization input
The internal oscillator can be synchronized to an external
clock with a frequency 20% lower than the internal
oscillator’s free running frequency. There is no constraint
on the maximum sync frequency.
16
UVLO
EP
Line Under-Voltage shutdown
An external voltage divider from the power source sets the
shutdown comparator levels. The comparator threshold is
2.5V. Hysteresis is set by an internal current source (20µA)
that is switched on or off as the UVLO pin potential
crosses the 2.5V threshold.
-
Exposed PAD, underside of the WSON package
option
Internally bonded to the die substrate. Connect to GND
potential with low thermal impedance.
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LM5025B
LM5025B
SNVS354B –JULY 2005–REVISED MARCH 2013
www.ti.com
Block Diagram
7.6V SERIES
REGULATOR
V
V
IN
CC
REF
5V
V
CC
REFERENCE
UVLO
UVLO
HYSTERESIS
UVLO
(20 mA)
ENABLE OUTPUTS
and REF
+
-
2.5V
V
CC
OUT_A
CLK
RT
DRIVER
OSCILLATOR
SYNC
SLOPE a V
IN
DEADTIME
OR
TIME
OVERLAP
CONTROL
FF RAMP
RAMP
COMP
V
CC
OUT_B
PWM
+
-
DRIVER
Q
Q
S
R
1V
SS Amp
(Sink Only)
LOGIC
SS
+
-
2.5V
MAX V*S
CLAMP
CS1
CS2
PGND
+
-
0.25V
0.5V
+
-
AGND
CLK + LEB
SS
20 mA
SS
19 mA
Figure 3. Simplified Block Diagram
4
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5025B
LM5025B
www.ti.com
SNVS354B –JULY 2005–REVISED MARCH 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
VIN to GND
-0.3V to 105V
-0.3V to 16V
-0.3 to 1.00V
-0.3 to 7V
VCC to GND
CS1, CS2 to GND
All other inputs to GND
(3)
ESD Rating
Human Body Model
Storage Temperature Range
Junction Temperature
2kV
-55°C to 150°C
150°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) For detailed information on soldering plastic TSSOP and WSON packages, refer to the Packaging Data Book visit
www.ti.com/packaging.
(1)
Operating Ratings
VIN Voltage
13 to 100V
8 to 15V
External Voltage Applied to VCC
Operating Junction Temperature
-40°C to +125°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
Electrical Characteristics(1)
Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 26.7kΩ, RSET = 27.4kΩ) unless otherwise stated
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Startup Regulator
VCC Reg
VCC Regulation
No Load
(2)
7.3
20
7.6
25
7.9
V
VCC Current Limit
mA
µA
I-VIN
Startup Regulator
Leakage (external Vcc
Supply)
VIN = 100V
165
500
VCC Supply
VCC Under-voltage
Lockout Voltage (positive
VCC Reg -
220mV
VCC Reg -
120mV
V
going Vcc
)
VCC Under-voltage
Hysteresis
1.0
1.5
2.0
4.2
V
VCC Supply Current (ICC
)
Cgate = 0
mA
Reference Supply
VREF Ref Voltage
IREF = 0 mA
4.85
10
5
5.15
50
V
Ref Voltage Regulation
Ref Current Limit
IREF = 0 to 10mA
25
20
mV
mA
(1) All electrical characteristics having room temperature limits are tested during production with TA = TJ = 25°C. All hot and cold limits are
specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) Device thermal limitations may limit usable range.
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LM5025B
LM5025B
SNVS354B –JULY 2005–REVISED MARCH 2013
www.ti.com
Electrical Characteristics(1) (continued)
Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 26.7kΩ, RSET = 27.4kΩ) unless otherwise stated
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Current Limit
CS1 Prop
CS1 Delay to Output
CS1 Step from 0 to 0.4V
Time to onset of OUT
Transition (90%)
Cgate = 0
40
ns
CS2 Prop
CS2 Delay to Output
CS2 Step from 0 to 0.6V
Time to onset of OUT
Transition (90%)
Cgate = 0
50
ns
Cycle by Cycle Threshold
Voltage (CS1)
0.22
0.45
0.25
0.5
50
0.28
0.55
V
V
Cycle Skip Threshold
Voltage (CS2)
Resets SS capacitor; auto
restart
Leading Edge Blanking
Time (CS1)
ns
Ω
CS1 Sink Impedance
(clocked)
CS1 = 0.2V
30
50
95
95
1
CS1 Sink Impedance
(Post Fault Discharge)
CS1 = 0.3V
55
Ω
CS2 Sink Impedance
(Post Fault Discharge)
CS2 = 0.6V
55
Ω
CS1 and CS2 Leakage
Current
CS = CS Threshold - 100mV
µA
Soft-Start
Oscillator
Soft-start Current Source
Normal
17
22
1
27
µA
µA
Soft-start Current Source
following a CS2 event
0.5
1.5
Frequency1
Frequency2
TA = 25°C
TJ = Tlow to Thigh
180
175
220
225
200
kHz
kHz
RT = 13.3 kΩ
TJ = Tlow to Thigh
TJ = 0°C to 125°C
360
364
400
2
440
436
Sync threshold
V
Min Sync Pulse Width
Sync Frequency Range
100
ns
160
kHz
PWM Comparator
Delay to Output
COMP step 5V to 0V
Time to onset of OUT_A
transition low
40
ns
%
Maximum Duty Cycle 1
Maximum Duty Cycle 2
Measured at OUT_A
73
71
Measured at OUT_A;
RT = 13.3K
66
75
COMP to PWM Offset
COMP Input Current
0.75
1
1.15
80
V
COMP = 4V, SS open
50
µA
Volt x Second Clamp
Ramp Clamp Level
Delta RAMP measured from
onset of OUT_A to Ramp peak.
COMP = 5V
2.4
2.5
2.6
V
6
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5025B
LM5025B
www.ti.com
SNVS354B –JULY 2005–REVISED MARCH 2013
Electrical Characteristics(1) (continued)
Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 26.7kΩ, RSET = 27.4kΩ) unless otherwise stated
Symbol
Parameter
Conditions
Min
Typ
Max
Units
UVLO Shutdown
Undervoltage Shutdown
Threshold
2.44
16
2.5
20
2.56
24
V
Undervoltage Shutdown
Hysteresis
µA
Output Section
OUT_A High Saturation
MOS Device @ Iout = -10mA,
5
3
10
9
Ω
OUTPUT_A Peak Current Bipolar Device @ Vcc/2
Sink
A
OUT_A Low Saturation
OUTPUT_A Rise Time
OUTPUT_A Fall Time
OUT_B High Saturation
MOS Device @ Iout = 10mA,
Cgate = 2.2nF
6
Ω
ns
ns
Ω
20
15
10
1
Cgate = 2.2nF
MOS Device @ Iout = -10mA,
20
18
OUTPUT_B Peak Current Bipolar Device @ Vcc/2
Sink
A
OUT_B Low Saturation
OUTPUT_B Rise Time
OUTPUT_B Fall Time
MOS Device @ Iout = 10mA,
Cgate = 1nF
12
20
15
Ω
ns
ns
Cgate = 1nF
Output Timing Control
Overlap Time
RSET = 38 kΩ connected to
GND, 50% to 50% transitions
75
75
105
105
135
135
ns
ns
Deadtime
RSET = 29.5 kΩ connected to
REF, 50% to 50% transitions
Thermal Shutdown
TSD
Thermal Shutdown
Threshold
165
25
°C
°C
Thermal Shutdown
Hysteresis
Thermal Resistance
θJA Junction to Ambient
PW Package
NHQ Package
PW Package
NHQ Package
125
32
30
5
°C/W
°C/W
°C/W
°C/W
θJC
Junction to Case
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LM5025B
LM5025B
SNVS354B –JULY 2005–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics
VCC Regulator Start-up Characteristics, VCC vs Vin
VCC vs ICC
16
14
12
10
8
10
VIN
8
6
VCC
4
2
0
6
4
2
0
0
2
4
6
8
10 12 14 16
0
5
10
15
20
25
VIN (V)
ICC (mA)
Figure 4.
Figure 5.
VREF vs IREF
Oscillator Frequency vs RT
6
1000
5
4
3
2
1
0
100
1
10
100
0
5
10
15
20
25
RT (kW)
IREF (mA)
Figure 6.
Figure 7.
Overlap Time vs Temperature
RSET = 38K
Overlap Time vs RSET
140
130
120
110
100
90
400
350
300
250
200
150
100
50
0
80
-40
25
_
75
_
125
0
20
40
80
100 120
60
RSET (kW)
TEMPERATURE (oC)
Figure 8.
Figure 9.
8
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5025B
LM5025B
www.ti.com
SNVS354B –JULY 2005–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Dead Time vs Temperature
RSET = 29.5K
Dead Time vs RSET
140
130
120
110
100
90
400
350
300
250
200
150
100
50
0
80
-40
25
75
125
0
20
40
60
80
100 120
RSET (kW)
TEMPERATURE (oC)
Figure 10.
Figure 11.
SS Pin Current vs Temperature
26
24
22
20
18
16
14
-40
25
75
125
TEMPERATURE (oC)
Figure 12.
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LM5025B
LM5025B
SNVS354B –JULY 2005–REVISED MARCH 2013
www.ti.com
DETAILED OPERATING DESCRIPTION
The LM5025B is a functional variant of the LM5025 active clamp PWM controller. The functional differences of
the LM5025B are as follows:
•
•
•
•
•
•
The maximum PWM duty cycle is limited to less than 75% to reduce voltage stress on the power MOSFETs
The CS2 hiccup mode threshold is increased to 0.5V
The CS2 filter discharge device is disabled
The VCC regulator continues to operate when the line UVLO is below the threshold of normal operation
The VREF regulator is switched off when the line UVLO input falls below the operating threshold
The internal 5kΩ COMP pin pull-up resistor is removed
The LM5025B PWM controller contains all of the features necessary to implement power converters utilizing the
Active Clamp Reset technique. The device can be configured to control either a P-Channel clamp switch or an N-
Channel clamp switch. With the active clamp technique higher efficiencies and greater power densities can be
realized compared to conventional catch winding or RDC clamp / reset techniques. Two control outputs are
provided, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The active clamp
output can be configured for either a spefified overlap time (for P-Channel switch applications) or a spefified dead
time (for N_Channel applications). The two internal compound gate drivers parallel both MOS and Bipolar
devices, providing superior gate drive characteristics. This controller is designed for high-speed operation
including an oscillator frequency range up to 1MHz and total PWM and current sense propagation delays less
than 100ns. The LM5025B includes a high-voltage start-up regulator that operates over a wide input range of
13V to 100V. Additional features include: Line Under Voltage Lockout (UVLO), softstart, oscillator UP/DOWN
sync capability, precision reference and thermal shutdown.
High Voltage Start-Up Regulator
The LM5025B contains an internal high voltage start-up regulator that allows the input pin (VIN) to be connected
directly to the line voltage. The regulator output is internally current limited to 20mA. When power is applied, the
regulator is enabled and sources current into an external capacitor connected to the VCC pin. The recommended
capacitance range for the VCC regulator is 0.1µF to 100µF. When the voltage on the VCC pin reaches the
regulation point of 7.6V and the internal voltage reference (REF) reaches its regulation point of 5V, the controller
outputs are enabled. The outputs will remain enabled until VCC falls below 6.2V or the line Under Voltage Lock
Out detector indicates that VIN is out of range. In typical applications, an auxiliary transformer winding is
connected through a diode to the VCC pin. This winding must raise the VCC voltage above 8V to shut off the
internal start-up regulator. Powering VCC from an auxiliary winding improves efficiency while reducing the
controller power dissipation.
When the converter auxiliary winding is inactive, external current draw on the VCC line should be limited so the
power dissipated in the start-up regulator does not exceed the maximum power dissipation of the controller.
An external start-up regulator or other bias rail can be used instead of the internal start-up regulator by
connecting the VCC and the VIN pins together and feeding the external bias voltage into the two pins.
Line Under-Voltage Detector
The LM5025B contains a line Under Voltage Lock Out (UVLO) circuit. An external set-point voltage divider from
Vin to GND, sets the operational range of the converter. The divider must be designed such that the voltage at
the UVLO pin will be greater than 2.5V when Vin is in the desired operating range. If the undervoltage threshold
is not met, both outputs and the VREF regulator are disabled. The VCC regulator is not disabled by UVLO.
UVLO hysteresis is accomplished with an internal 20uA current source that is switched on or off into the
impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to
instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.5V threshold, the
current source is turned off causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to
implement a remote enable / disable function. Pulling the UVLO pin below the 2.5V threshold disables the PWM
outputs.
10
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5025B
LM5025B
www.ti.com
SNVS354B –JULY 2005–REVISED MARCH 2013
PWM Outputs
The relative phase of the main (OUT_A) and active clamp outputs (OUT_B) can be configured for the specific
application. For active clamp configurations utilizing a ground referenced P-Channel clamp switch, the two
outputs should be in phase with the active clamp output overlapping the main output. For active clamp
configurations utilizing a high side N-Channel switch, the active clamp output should be out of phase with main
output and there should be a dead time between the two gate drive pulses. A distinguishing feature of the
LM5025B is the ability to accurately configure either dead time (both off) or overlap time (both on) of the gate
driver outputs. The overlap / deadtime magnitude is controlled by the resistor value connected to the TIME pin of
the controller. The opposite end of the resistor can be connected to either REF for deadtime control or GND for
overlap control. The internal configuration detector senses the connection and configures the phase relationship
of the main and active clamp outputs. The magnitude of the overlap/dead time can be calculated as follows:
Overlap Time (ns) = 2.8 x RSET - 1.2
Dead Time (ns) = 2.9 x RSET +20
RSET in kΩ, Time in ns
OUT_A
K1 * R
K1 * R
SET
P-Channel Active Clamp
(R to GND)
SET
SET
OUT_B
OUT_A
K2 * R
N-Channel Active Clamp
(R to REF)
K2 * R
SET
SET
SET
OUT_B
Figure 13.
Compound Gate Drivers
The LM5025B contains two unique compound gate drivers, which parallel both MOS and Bipolar devices to
provide high drive current throughout the entire switching event. The Bipolar device provides most of the drive
current capability and provides a relatively constant sink current which is ideal for driving large power MOSFETs.
As the switching event nears conclusion and the Bipolar device saturates, the internal MOS device continues to
provide a low impedance to compete the switching event.
During turn-off at the Miller plateau region, typically around 2V - 3V, is where gate driver current capability is
needed most. The resistive characteristics of all MOS gate drivers are adequate for turn-on since the supply to
output voltage differential is fairly large at the Miller region. During turn-off however, the voltage differential is
small and the current source characteristic of the Bipolar gate driver is beneficial to provide fast drive capability.
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LM5025B
LM5025B
SNVS354B –JULY 2005–REVISED MARCH 2013
www.ti.com
VCC
OUT
CNTRL
PGND
PWM Comparator
The PWM comparator compares the ramp signal (RAMP) to the loop error signal (COMP). This comparator is
optimized for speed in order to achieve minimum controllable duty cycles. The COMP pin is a high impedance
comparator input. If the opto coupler is connected between the COMP pin and ground, then a pull-up resistor
must be added between COMP and REF to bias the opto coupler transistor. The comparator polarity is such that
0V on the COMP pin will produce a zero duty cycle on both gate driver outputs.
Volt x Second Clamp
The Volt x Second Clamp comparator compares the ramp signal (RAMP) to a fixed 2.5V reference. By proper
selection of RFF and CFF, the maximum ON time of the main switch can be set to the desired duration. The ON
time set by Volt x Second Clamp varies inversely with the line voltage because the RAMP capacitor is charged
by a resistor connected to Vin while the threshold of the clamp is a fixed voltage (2.5V). An example will illustrate
the use of the Volt x Second Clamp comparator to achieve a 50% duty cycle limit, at 200KHz, at a 48V line input:
A 50% duty cycle at a 200KHz requires a 2.5µs of ON time. At 48V input the Volt x Second product is 120V-µs
(48V x 2.5µs). To achieve this clamp level choose RFF and CFF using the following equation:
RFF x CFF = VIN x TON / 2.5V =
48V x 2.5µs / 2.5V = 48µs
(1)
(2)
Select CFF = 470pF. RFF = 102kΩ. The recommended capacitor value range for CFF is 100pF to 1000pF.
The CFF ramp capacitor is discharged at the conclusion of every cycle by an internal discharge switch controlled
by either the internal clock or by the Volt x Second Clamp comparator, whichever event occurs first.
Maximum Duty Cycle
At low line input voltages, the Volt x Second clamp will not limit the maximum PWM duty cycle because the
RAMP signal does not charge to the 2.5V threshold voltage within the period of the PWM clock. In this case, the
maximum duty cycle is determined by the internal PWM clock and the output overlap or deadtime programmed
by the resistor RSET connected to the TIME pin. Referring to Figure 13, the initial transition of OUT_B
corresponds to the leading edge of the PWM clock. The leading edge of OUT_A is delayed with respect to
OUT_B by the overlap time which is determined by the TIME pin resistor (K1 x RSET) When operating at
maximum duty cycle, the trailing edge of OUT_A corresponds to the trailing edge of the PWM clock. The duty
cycle at OUT_A is therefore always less than the duty cycle of the clock. The internal clock of the LM5025B
operates at a nominal duty cycle of 75%. If the clock frequency is 400KHz and the overlap time is set to 100ns,
then the maximum PWM duty cycle will be:
Max Duty Cycle = 75% - 100ns x 400KHz = 71%
(3)
12
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5025B
LM5025B
www.ti.com
SNVS354B –JULY 2005–REVISED MARCH 2013
Current Limit
The LM5025B contains two modes of over-current protection. If the sense voltage at the CS1 input exceeds
0.25V the present power cycle is terminated (cycle-by-cycle current limit). If the sense voltage at the CS2 input
exceeds 0.5V, the controller will terminate the present cycle, discharge the softstart capacitor and reduce the
softstart current source to 1µA. The softstart (SS) capacitor is released after being fully discharged and slowly
charges with a 1µA current source. When the voltage at the SS pin reaches approximately 1V, the PWM
comparator will produce the first output pulse at OUT_A. After the first pulse occurs, the softstart current source
will revert to the normal 20µA level. Fully discharging and then slowly charging the SS capacitor protects a
continuously over-loaded converter with a low duty cycle hiccup mode.
These two modes of over-current protection allow the user great flexibility to configure the system behavior in
over-load conditions. If it is desired for the system to act as a current source during an over-load, then the CS1
cycle-by-cycle current limiting should be used. In this case the current sense signal should be applied to the CS1
input and the CS2 input should be grounded. If during an overload condition it is desired for the system to briefly
shutdown, followed by softstart retry, then the CS2 hiccup current limiting mode should be used. In this case the
current sense signal should be applied to the CS2 input and the CS1 input should be grounded. This shutdown /
soft-start retry will repeat indefinitely while the over-load condition remains. The hiccup mode will greatly reduce
the thermal stresses to the system during heavy overloads. The cycle-by-cycle mode will have higher system
thermal dissipations during heavy overloads, but provides the advantage of continuous operation for short
duration overload conditions.
It is possible to utilize both over-current modes concurrently, whereby momentary overload conditions activate
the CS1 cycle-by-cycle mode while prolonged overloading activates the CS2 hiccup mode. Generally the CS1
input will always be configured to monitor the main switch FET current each cycle. The CS2 input can be
configured in several different ways depending upon the system requirements.
a) The CS2 input can also be set to monitor the main switch FET current except scaled to a higher threshold
than CS1
b) An external over-current timer can be configured which trips after a pre-determined over-current time, driving
the CS2 input high, initiating a hiccup event.
c) In a closed loop voltage regulaton system, the COMP input will rise to saturation when the cycle-by-cycle
current limit is active. An external filter/delay timer and voltage divider can be configured between the COMP pin
and the CS2 pin to scale and delay the COMP voltage. If the CS2 pin voltage reaches 0.5V a hiccup event will
initiate.
A small RC filter, located near the controller, is recommended for each of the CS pins. The CS1 input has an
internal FET which discharges the current sense filter capacitor at the conclusion of every cycle, to improve
dynamic performance. This same FET remains on an additional 50ns at the start of each main switch cycle to
attenuate the leading edge spike in the current sense signal. The CS2 discharge FET only operates following a
CS2 event, UVLO and thermal shutdown.
The LM5025B CS comparators are very fast and may respond to short duration noise pulses. Layout
considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS
filter must be placed very close to the device and connected directly to the pins of the IC (CS and GND). If a
current sense transformer is used, both leads of the transformer secondary should be routed to the filter
network , which should be located close to the IC. If a sense resistor in the source of the main switch MOSFET is
used for current sensing, a low inductance type of resistor is required. When designing with a current sense
resistor, all of the noise sensitive low power ground connections should be connected together near the IC GND
and a single connection should be made to the power ground (sense resistor ground point).
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LM5025B
LM5025B
SNVS354B –JULY 2005–REVISED MARCH 2013
www.ti.com
OUT_A
0.5V
CS2
20 mA
SS
1 mA
Overload
Cool Down
Restart
Oscillator and Sync Capability
The LM5025B oscillator is set by a single external resistor connected between the RT pin and GND. To set a
desired oscillator frequency (F), the necessary RT resistor can be calculated from:
RT = (4960/F)1.02
where
•
F is in kHz and RT in kΩ.
(4)
The RT resistor should be located very close to the device and connected directly to the pins of the IC (RT and
GND).
A unique feature of LM5025B is the ability to synchronize the oscillator to an external clock with a frequency that
is either higher or lower than the frequency of the internal oscillator. The lower frequency sync frequency range is
80% of the free running internal oscillator frequency. There is no constraint on the maximum sync frequency. A
minimum pulse width of 100ns is required for the synchronization clock. If the synchronization feature is not
required, the SYNC pin should be connected to GND to prevent any abnormal interference. The internal
oscillator can be completely disabled by connecting the RT pin to REF. Once disabled, the sync signal will act
directly as the master clock for the controller. Both the frequency and the maximum duty cycle of the PWM
controller can be controlled by the sync signal (within the limitations of the Volt x Second Clamp). The maximum
duty cycle (D) will be (1-D) of the sync signal.
Feed-Forward Ramp
An external resistor (RFF) and capacitor (CFF) connected to VIN and GND are required to create the PWM ramp
signal. The slope of the signal at the RAMP pin will vary in proportion to the input line voltage. This varying slope
provides line feedforward information necessary to improve line transient response with voltage mode control.
The RAMP signal is compared to the error signal at the COMP pin by the pulse width modulator comparator to
control the duty cycle of the main switch output. The Volt x Second Clamp comparator also monitors the RAMP
pin and if the ramp amplitude exceeds 2.5V, the present cycle is terminated. The ramp signal is reset to GND at
the end of each cycle by either the internal clock or the Volt x Second comparator, which ever occurs first.
Soft-start
The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus
reducing start-up stresses and surges. At power on, a 20µA current is sourced out of the soft-start pin (SS) into
an external capacitor. The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and therefore
the PWM duty cycle. In the event of a fault as determined by VCC undervoltage, line undervoltage (UVLO) or
second level current limit, the output gate drivers are disabled and the soft-start capacitor is fully discharged.
When the fault condition is no longer present a soft-start sequence will be initiated. Following a second level
current limit detection (CS2), the soft-start current source is reduced to 1µA until the first output pulse is
generated by the PWM comparator. The current source returns to the nominal 20µA level after the first output
pulse (~1V at the SS pin).
14
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5025B
LM5025B
www.ti.com
SNVS354B –JULY 2005–REVISED MARCH 2013
The soft-start circuit controls the COMP pin voltage through a unity gain amplifier with an open drain (sink only)
output. If the SS pin voltage is less than the PWM control signal applied to the COMP pin, this amplifier will sink
current from the external pull-up connected to the COMP pin to force the COMP voltage to follow the soft-start
capacitor ramp. When the soft-start capacitor charges to a voltage that is greater than the control voltage applied
to the COMP pin, the soft-start amplifier automatically disengages, allowing closed loop control of the PWM duty
cycle. The soft-start amplifier output stage is capable of sinking up to 5mA. External pull-up circuits connected to
the COMP pin must limit the current into the pin to a value less than 5mA.
Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction
temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power standby
state with the output drivers and the bias regulator disabled. The device will restart after the thermal hysteresis
(typically 25°C). During a restart after thermal shutdown, the soft-start capacitor will be fully discharged and then
charged in the low current mode (1µA) similar to a second level current limit event. The thermal protection
feature is provided to prevent catastrophic failures from accidental device overheating.
Application Circuit: Input 36-78V, Output 3.3V, 30A
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LM5025B
LM5025B
SNVS354B –JULY 2005–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
16
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5025B
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5025BMTC/NOPB
LM5025BMTCX/NOPB
LM5025BSD/NOPB
ACTIVE
TSSOP
TSSOP
WSON
PW
16
16
16
92
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
L5025B
MTC
ACTIVE
ACTIVE
PW
2500 RoHS & Green
1000 RoHS & Green
NIPDAU | SN
SN
L5025B
MTC
NHQ
5025BSD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5025BMTCX/NOPB
LM5025BSD/NOPB
TSSOP
WSON
PW
16
16
2500
1000
330.0
178.0
12.4
12.4
6.95
5.3
5.6
5.3
1.6
1.3
8.0
8.0
12.0
12.0
Q1
Q1
NHQ
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5025BMTCX/NOPB
LM5025BSD/NOPB
TSSOP
WSON
PW
16
16
2500
1000
367.0
208.0
367.0
191.0
35.0
35.0
NHQ
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM5025BMTC/NOPB
LM5025BMTC/NOPB
LM5025BMTC/NOPB
PW
PW
PW
TSSOP
TSSOP
TSSOP
16
16
16
92
92
92
530
495
495
10.2
8
3600
3.5
2514.6
2514.6
4.06
4.06
8
Pack Materials-Page 3
MECHANICAL DATA
NHQ0016A
SDA16A (Rev A)
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明