LM5030 [TI]
100V 推挽电流模式 PWM 控制器;
| 型号： | LM5030 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 100V 推挽电流模式 PWM 控制器 控制器 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM5030
SNVS215D –APRIL 2003–REVISED NOVEMBER 2015
LM5030 100-V Push-Pull Current Mode PWM Controller
1 Features
3 Description
The LM5030 high-voltage PWM controller contains all
1
•
•
•
•
•
•
•
•
•
•
•
Internal High-Voltage Start-Up Regulator
Single Resistor Oscillator Setting
Synchronizable
of the features needed to implement push-pull and
bridge topologies, using current-mode control in a
small 10-pin package. This device provides two
alternating gate driver outputs. The LM5030 includes
a high-voltage start-up regulator that operates over a
wide input range of 14 V to 100 V. Additional features
include: error amplifier, precision reference, dual
mode current limit, slope compensation, softstart,
sync capability, and thermal shutdown. This high
speed IC has total propagation delays less than
Error Amplifier
Precision Reference
Adjustable Softstart
Dual Mode Overcurrent Protection
Slope Compensation
Direct Optocoupler Interface
1.5-A Peak Gate Drivers
Thermal Shutdown
100 ns and
a
1-MHz capable single-resistor
adjustable oscillator.
Device Information(1)
PART NUMBER
LM5030
PACKAGE
VSSOP (10)
WSON (10)
BODY SIZE (NOM)
2 Applications
3.00 mm × 3.00 mm
4.00 mm × 4.00 mm
•
•
•
Telecommunication Power Converters
Industrial Power Converters
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
+42-V Automotive Systems
Typical Application Diagram
VIN
VOUT
LM5030
OUT1
VIN
OUT2
VCC
CS
COMP
VFB
RT
SS
ISOLATED
FEEDBACK
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5030
SNVS215D –APRIL 2003–REVISED NOVEMBER 2015
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
Power Supply Recommendations...................... 20
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
8
9
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1 Device Support...................................................... 21
11.2 Documentation Support ....................................... 21
11.3 Community Resources.......................................... 21
11.4 Trademarks........................................................... 21
11.5 Electrostatic Discharge Caution............................ 21
11.6 Glossary................................................................ 21
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2013) to Revision D
Page
•
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 16
2
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SNVS215D –APRIL 2003–REVISED NOVEMBER 2015
5 Pin Configuration and Functions
DGS, DPR Package
10-Pin VSSOP, WSON
Top View
10
1
2
3
4
5
VIN
SS
9
8
7
6
VFB
RT
CS
COMP
VCC
GND
OUT2
OUT1
Pin Functions
PIN
I/O
DESCRIPTION
APPLICATION INFORMATION
NAME
NO.
There is an internal 5-kΩ pullup resistor on this pin. The
error amplifier provides an active sink.
COMP
3
O
Output to the error amplifier
Current sense input for current mode control and current
limit sensing. Using separate dedicated comparators, if CS
exceeds 0.5 V, the outputs will go into cycle-by-cycle
current limit. If CS exceeds 0.625 V the outputs will be
disabled and a softstart commenced.
CS
8
I
Current sense input
GND
7
5
6
—
O
O
Return
Ground
OUT1
OUT2
Output of the PWM controller
Output of the PWM controller
Alternating PWM output gate driver
Alternating PWM output gate driver
An external resistor sets the oscillator frequency. This pin
will also accept synchronization pulses from an external
oscillator.
Oscillator timing resistor pin and
synchronization input
RT
9
I
A 10-µA current source and an external capacitor set the
softstart timing length. The controller will enter a low power
state if the SS pin is pulled below the typical shutdown
threshold of 0.45 V.
SS
10
I
Dual purpose soft start and shutdown pin
VIN
1
2
I
I
Source input voltage
Input to start-up regulator. Input range 14 to 100 V.
The non-inverting input is internally connected to a 1.25-V
reference.
VFB
Inverting input to the error amplifier
Output from the internal high-voltage series
pass regulator. The regulation setpoint is
7.7 V.
If an auxiliary winding raises the voltage on this pin above
the regulation setpoint, the internal series pass regulator
will shutdown, reducing the IC power dissipation.
VCC
4
I/O
—
The exposed die attach pad on the WSON package should
be connected to a PCB thermal pad at ground potential.
For additional information on using TI's No Pull Back
WSON package, refer to WSON Application Note AN-1187
(SNOA401).
WSON
DAP
SUB
Die substrate
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SNVS215D –APRIL 2003–REVISED NOVEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
100
16
UNIT
VIN to GND (Survival)
V
V
V
V
VCC to GND (Survival)
RT to GND (Survival)
5.5
7
All other pins to GND (Survival)
Power dissipation
Internally Limited
Lead temperature (soldering 4 seconds)
Operating junction temperature
Storage temperature, Tstg
260
150
°C
°C
°C
–55
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±200
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Machine model (MM)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
14
NOM
MAX
90
UNIT
V
VIN
TJ Operating junction temperature
–40
105
°C
6.4 Thermal Information
LM5030
THERMAL METRIC(1)
DGS (VSSOP)
10 PINS
158.8
53.6
DPR (WSON)
UNIT
10 PINS
38.1
137.1
15.2
0.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
74.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.3
ψJB
77.6
15.4
4.6
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SNVS215D –APRIL 2003–REVISED NOVEMBER 2015
6.5 Electrical Characteristics
Specifications are for TJ = 25°C. Unless otherwise specified: VIN = 48 V, VCC = 10 V, and RT = 26.7 kΩ
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1) UNIT
START-UP REGULATOR
TJ = 25°C
7.7
VCCReg VCC Regulation
VCC Current limit
Open ckt
V
full operating junction
temperature range
7.4
10
8.0
TJ = 25°C
17
150
250
See Figure 2
VIN = 90 V
mA
full operating junction
temperature range
TJ = 25°C
Start-up regulator leakage
(external VCC supply)
I-VIN
µA
full operating junction
temperature range
500
TJ = 25°C
SS = 0 V, VCC
open
=
IIN
VCC SUPPLY
VCC Undervoltage lockout
Shutdown current
µA
full operating junction
temperature range
350
VCCReg –
100 mV
TJ = 25°C
V
voltage
VCCReg –
300 mV
full operating junction temperature range
TJ = 25°C
1.6
2
Undervoltage hysteresis
Supply current
V
full operating junction temperature range
TJ = 25°C
1.2
2.1
ICC
Cload = 0
mA
3
full operating junction
temperature range
ERROR AMPLIFIER
GBW Gain bandwidth
4
75
MHz
dB
DC gain
TJ = 25°C
1.245
Input voltage
VFB = COMP
V
full operating junction
temperature range
1.220
5
1.270
TJ = 25°C
13
VFB = 1.5 V COMP
= 1 V
COMP sink capability
mA
full operating junction
temperature range
CURRENT LIMIT
TJ = 25°C
0.5
Cycle-by-cyble CS threshold
voltage
CS1
V
full operating junction temperature range
0.45
0.55
TJ = 25°C
0.625
Resets SS
capacitor; auto
restart
CS2
Restart CS threshold voltage
V
full operating junction
temperature range
0.575
0.675
CS step from 0-V to 0.6-V time-to-onset of OUT
ILIM delay to output
transition (90%)
Cload = 0
30
6
ns
TJ = 25°C
CS sink current (clocked)
CS = 0.3 V
mA
full operating junction
temperature range
3
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).
(2) Typical numbers represent the most likely parametric norm for 25°C operation.
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Electrical Characteristics (continued)
Specifications are for TJ = 25°C. Unless otherwise specified: VIN = 48 V, VCC = 10 V, and RT = 26.7 kΩ
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1) UNIT
SOFT START AND SHUTDOWN
TJ = 25°C
10
Softstart current source
Softstart to COMP offset
µA
13
full operating junction temperature range
TJ = 25°C
7
0.25
0.2
0.5
V
full operating junction temperature range
TJ = 25°C
0.75
0.45
Shutdown threshold
OSCILLATOR
V
full operating junction temperature range
0.7
TJ = 25°C
200
600
3.2
Frequency1 (RT = 26.7K)
kHz
225
full operating junction temperature range
TJ = 25°C
175
510
Frequency2 (RT = 8.2K)
Sync threshold
kHz
690
full operating junction temperature range
TJ = 25°C
V
full operating junction temperature range
3.8
PWM COMPARATOR
COMP set to 2-V CS stepped 0 to 0.4 V, time-to-
onset of OUT transition low
Delay to output
30
ns
TJ = 25°C
49%
Inferred from
Max duty cycle
Min duty cycle
full operating junction
deadtime
47.5%
50%
0%
temperature range
full operating junction
COMP = 0 V
temperature range
COMP to PWM comparator
gain
0.34
5.2
V / V
TJ = 25°C
COMP open circuit voltage
VFB = 0 V
V
full operating junction
temperature range
4.3
0.6
6.1
TJ = 25°C
1.1
VFB = 0 V, COMP =
0 V
COMP short circuit current
SLOPE COMPENSATION
Slope comp amplitude
OUTPUT SECTION
mA
1.5
full operating junction
temperature range
TJ = 25°C
105
Delta increase at
PWM Comparator to
CS
mV
full operating junction
temperature range
80
85
130
TJ = 25°C
135
0.25
0.25
Cload = 0, 10% to
10%
Deadtime
ns
full operating junction
temperature range
185
TJ = 25°C
Iout = 50 mA, VCC
VOUT
–
Output high saturation
Output low saturation
V
full operating junction
temperature range
0.75
TJ = 25°C
IOUT = 100 mA
V
full operating junction
temperature range
0.75
Rise time
Fall time
Cload = 1 nF
Cload = 1 nF
16
16
ns
ns
6
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Electrical Characteristics (continued)
Specifications are for TJ = 25°C. Unless otherwise specified: VIN = 48 V, VCC = 10 V, and RT = 26.7 kΩ
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX(1) UNIT
THERMAL SHUTDOWN
Thermal shutdown
temperature
Tsd
165
15
°C
°C
Thermal shutdown hysteresis
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6.6 Typical Characteristics
at TJ = 25°C (unless otherwise noted)
16
14
12
10
8
10
9
8
7
6
5
4
3
2
1
0
6
4
2
0
0
2
4
6
8
10 12 14 16
0
2
4
6
8
10 12 14 16 18 20
VIN (V)
ICC (mA)
Figure 2. VCC vs ICC (VIN = 48 V)
Figure 1. VCC vs VIN
1000
203.0
202.5
202.0
201.5
201.0
200.5
200.0
199.5
199.0
100
1
10
100
-50
0
50
100
150
RT (KW)
TEMPERATURE (oC)
Figure 3. Oscillator Frequency vs RT
Figure 4. Oscillator Frequency vs Temperature RT = 26.7 kΩ
160
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10.0
9.9
155
150
145
140
135
130
9.8
9.7
50
100
-50
0
150
50
100
-50
0
150
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 5. Softstart Current vs Temperature
Figure 6. Deadtime vs Temperature
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Typical Characteristics (continued)
at TJ = 25°C (unless otherwise noted)
Figure 7. Feedback Amplifier Gainphase
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7 Detailed Description
7.1 Overview
The LM5030 high-voltage PWM controller contains all of the features needed to implement push-pull and bridge
topologies, using current-mode control in a small 10-pin package. Features included are, start-up regulator, dual
mode current limit, dual alternating gate drivers, thermal shutdown, softstart, and slope compensation. This high
speed IC has total propagation delays < 100 ns. The functional block diagram of the LM5030 is shown in
Functional Block Diagram.
The LM5030 is designed for current-mode control converters that require alternating outputs, such as push-pull
and half- and full-bridge topologies. The features included in the LM5030 enable all of the advantages of current-
mode control, line feed-forward, cycle-by-cycle current limit, and simplified loop compensation. The oscillator
ramp is internally buffered and added to the PWM comparator input to provide the necessary slope
compensation for current-mode control at higher duty cycles.
7.2 Functional Block Diagram
7.7V SERIES
REGULATOR
VIN
VCC
5V
1.25V
GENERATOR
REFERENCE
ENABLE
LOGIC
CLK
Rt / SYNC
OSC
SLOPECOMP RAMP
VCC
SET
GENERATOR
J
Q
Q
45mA
K
OUT1
CLR
SET
0
5V
S
Q
Q
COMP
1.25V
DRIVER
R
5k
100k
PWM
CLR
+
-
VFB
1.4V
LOGIC
50k
VCC
SS
OUT2
CS
+
-
DRIVER
GND
0.5V
2k
+
-
0.625V
CLK
ERROR AMP
SOFT START
10mA
SS
SHUTDOWN
COMPARATOR
+
-
ENABLE
0.45V
10
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7.3 Feature Description
7.3.1 High-Voltage Start-Up Regulator
The LM5030 contains an internal high-voltage start-up regulator. The input pin (VIN) can be connected directly to
line voltages as high as 100 V. The regulator output is internally current limited to 10 mA. Upon power up, the
regulator is enabled and sources current into an external capacitor connected to the VCC pin. The recommended
capacitance range for the VCC regulator is 0.1 µF to 50 µF. When the voltage on the VCC pin reaches the
regulation point of 7.7 V, the controller outputs are enabled. The outputs will remain enabled unless, VCC falls
below 6.1 V or if the SS/SHUTDOWN pin is pulled to ground or an over temperature condition occurs. In typical
applications, an auxiliary transformer winding is diode connected to the VCC pin. This winding raises the VCC
voltage greater than 8 V, effectively shutting off the internal start-up regulator and saving power while reducing
the controller dissipation. The external VCC capacitor must be sized such that the self-bias will maintain a VCC
voltage greater than 6.1 V during the initial start-up. During a fault mode when the converter self bias winding is
inactive, external current draw on the VCC line should be limited as to not exceed the maximum power dissipation
of the controller. An external start-up or other bias rail can be used instead of the internal start-up regulator by
connecting the VCC and the Vin pins and feeding the external bias voltage (8 V to 15 V) to that node.
7.3.2 Error Amplifier
An internal high gain error amplifier is provided within the LM5030. The noninverting reference of the amplifier is
tied to 1.25 V. In nonisolated applications the power converter output is connected to the VFB pin via the voltage
setting resistors and loop compensation is connected between the COMP and VFB pins.
For most isolated applications the error amplifier function is implemented on the secondary side ground. Because
the internal error amplifier is configured as an open drain output it can be disabled by connecting VFB to ground.
The internal 5-kΩ pullup resistor, connected between the 5-V reference and COMP, can be used as the pullup
for an optocoupler or other isolation device.
7.3.3 PWM Comparator
The PWM comparator compares the compensated current ramp signal to the loop error voltage from the internal
error amplifier (COMP pin). This comparator is optimized for speed in order to achieve minimum discernable duty
cycles. The comparator polarity is such that 0 V on the COMP pin will cause a zero duty cycle.
7.3.4 Current Limit and Current Sense
The LM5030 contains two levels of over-current protection. If the voltage on the current sense comparator
exceeds 0.5 V the present cycle is terminated (cycle-by-cycle current limit). If the voltage on the current sense
comparator exceeds 0.625 V, the controller will terminate the present cycle and discharge the softstart capacitor.
A small RC filter, located near the controller, is recommended for the CS pin. An internal MOSFET discharges
the current sense filter capacitor at the conclusion of every cycle, to improve dynamic performance.
The LM5030 CS and PWM comparators are very fast, and as such will respond to short duration noise pulses.
Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the
CS filter must be placed very close to the device and connected directly to the pins of the IC (CS and RTN). Also
if a current sense transformer is used, both leads of the transformer secondary should be routed to the sense
resistor, which should also be located close to the IC. If a current sense resistor located in the drive transistor
sources is used, for current sense, a low inductance resistor should be chosen. In this case all of the noise
sensitive low power grounds should be commoned together around the IC and then a single connection should
be made to the power ground (sense resistor ground point).
The second level threshold is intended to protect the power converter by initiating a low duty cycle hiccup mode
when abnormally high, fast rising currents occur. During excessive loading, the first level threshold will always be
reached and the output characteristic of the converter will be that of a current source but this sustained current
level can cause excessive temperatures in the power train especially the output rectifiers. If the second level
threshold is reached, the softstart capacitor will be fully discharged, a retry will commence following the
discharge detection. The second level threshold will only be reached when a high dV/dt is present at the current
sense pin. The signal must be fast enough to reach the second level threshold before the first threshold detector
turns off the driver. This can usually happen for a saturated power inductor or shorted load. Excessive filtering on
the CS pin, extremely low value current sense resistor or an inductor that does not saturate with excessive
loading may prevent the second level threshold from ever being reached.
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Feature Description (continued)
7.3.5 Oscillator, Shutdown and Sync Capability
The LM5030 oscillator is set by a single external resistor connected between the RT pin and return. To set a
desired oscillator frequency, the necessary RT resistor can be calculated in Equation 1:
(1/F) - 172 x 10-9
wÇ =
182 x 10-12
(1)
Each output switches at half the oscillator frequency in a push-pull configuration. The LM5030 can also be
synchronized to an external clock. The external clock must be of higher frequency than the free running
frequency set by the RT resistor. The clock signal should be capacitively coupled into the RT pin with a 100-pF
capacitor. A peak voltage level greater than 3 V with respect to ground is required for detection of the sync pulse.
The sync pulse width should be set in the 15- to 150-ns range by the external components. The RT resistor is
always required, whether the oscillator is free running or externally synchronized. The voltage at the RT pin is
internally regulated to a nominal 2 V.
Locate the RT resistor close to the device and connected directly to the pins of the IC (RT and GND).
7.3.6 Slope Compensation
The PWM comparator compares the current sense signal to the voltage derived from the COMP pin. The COMP
voltage is set by either the internal error amplifier or an external error amplifier through an optocoupler. At duty
cycles greater than 50% (composite of alternating outputs) current mode control circuits are prone to
subharmonic oscillation. By adding an additional ramp signal to the current sense ramp signal this condition can
be avoided. The LM5030 integrates this slope compensation by buffering the internal oscillator ramp and
summing it internally to the current sense (CS) signal. Additional slope compensation may be added by
increasing the source impedance of the current sense signal.
7.3.7 Soft Start and Shutdown
The soft-start feature allows the converter to gradually reach the initial steady state operating point, thus reducing
start-up stresses and surges. An internal 10-μA current source and an external capacitor generate a ramping
voltage signal that limits the error amplifier output during start-up. In the event of a second level current limit fault,
the soft-start capacitor will be fully discharged which disables the output drivers. When the fault condition is no
longer present, the soft-start capacitor is released to ramp and gradually restart the converter. The SS pin can
also be used to disable the controller. If the SS pin voltage is pulled down below 0.45 V (nominal) the controller
will disable the outputs and enter a low power state.
7.3.8 OUT1, OUT2, and Time Delay
The LM5030 provides two alternating outputs, OUT1 and OUT2. The internal gate drivers can each sink 1.5-A
peak each. The maximum duty cycle for each output is inherently limited to less than 50%. The typical deadtime
between the falling edge of one gate driver output and the rising edge of the other gate driver output is 135 ns.
7.3.9 Thermal Protection
Internal thermal-shutdown circuitry is provided to protect the integrated circuit in the event the excessive junction
temperature. When activated, typically at 165°C, the controller is forced into a low-power reset state, disabling
the output drivers and the bias regulator. This feature is provided to prevent catastrophic failures from accidental
device overheating.
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7.4 Device Functional Modes
The LM5030 is a versatile PWM controller that can be used in the following functional modes:
•
•
The LM5030 provides a complete push-pull current mode current mode controller.
The LM5030 driver outputs can be configured to drive high side MOSFETs through a gate driver chip to
implement half and full bridge topologies.
•
•
The LM5030 can be configured in single ended outputs such as a flyback converter or boost.
The LM5030 can also operate in conjunction with a high side driver chip to implement a synchronous buck
converter.
Details of these circuits can be found in Versatility of the LM5030 PWM Push-Pull Controller, SNVA548.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5030 is a highly integrated PWM controller that contains all of the features necessary for implementing
push-pull topology power converters. The device targets DC-DC converter applications with input voltages of up
to 100 VDC and output power in the range 15 W to 150 W.
8.2 Typical Application
The schematic in Figure 8 shows an example of a 33-W push-pull converter controlled by a LM5030. The
operating input range is 36 V to 75 V, and the output voltage is 3.3 V. The output current capability is 10 A. The
converter is configured for input current protection with cycle-by-cycle current limit. An auxiliary winding is used
to raise the VCC voltage to reduce the controller power dissipation.
Figure 8. Typical Application Circuit, 36-V to 75-V IN and 3.3-V, 10-A OUT
14
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the input parameters listed in Table 1.
Table 1. Design Parameters
PARAMETER
MIN
NOM
MAX
UNIT
Input Voltage
36
75
V
V
A
Output Voltage
3.3
Output Current
0
10
Efficiency (Full Load)
Efficiency (Half Load)
Load Regulation
Line Regulation
82.5%
84.5%
1%
0.15%
11
Output Current Limit
A
8.2.2 Detailed Design Procedure
8.2.2.1 VCC
While the LM5030 internally generates a voltage at VCC (7.7 V), the internal regulator is used mainly during the
start-up sequence. Once the load current begins flowing through L2, which is both an inductor for the output filter
and a transformer, a voltage is generated at the secondary of L2, which powers the VCC pin. When the
externally applied voltage exceeds the internal value (7.7 V), the internal regulator shuts off, thereby reducing
internal power dissipation in the LM5030. L2 is constructed such that the voltage supplied to VCC ranges from
approximately 10.6 V to approximately 11.3 V, depending on the load current (see Figure 9).
11.3
11.2
11.1
11.0
10.9
10.8
10.7
10.6
10.5
0.0
2.0
4.0
6.0
8.0
10.0
LOAD CURRENT (A)
Figure 9. VCC Voltage vs Load Current
8.2.2.2 Current Sense
Monitoring the input current provides a good indication of the operation of the circuit. If an overload condition
should exist at the output (a partial overload or a short circuit), the input current would rise above the nominal
value shown in Figure 12. Transformer T2, in conjunction with D3, R9, R12 and C10, provides a voltage to pin 8
on the LM5030 (CS) which is representative of the input current flowing through its primary. The average voltage
seen at pin 8 is plotted in Figure 10. If the voltage at the first current sense comparator exceeds 0.5 V, the
LM5030 disables its outputs, and the circuit enters a cycle-by-cycle current limit mode. If the second level
threshold (0.625 V) is exceeded due to a severe overload and transformer saturation, the LM5030 will disable its
outputs and initiate a softstart sequence. However, the very short propagation delay of the cycle-by-cycle current
limiter (CS1), the design of the CS filter (R9, R12, and C10), and the conservative design of the output inductor
(L2), may prevent the second level current threshold from being realized on this evaluation board.
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0.25
0.20
0.15
0.10
0.05
0.00
0.0
0.2
0.4
0.6
0.8
1.0
INPUT CURRENT (A)
Figure 10. Average Voltage at the CS Pin vs Input Current
8.2.2.3 Shutdown
The Shutdown pad (SD) on the board connects to the SoftStart pin on the LM5030 (pin 10), and permits on/off
control of the converter by an external switch. SD should be pulled below 0.45 V, with an open collector or open
drain device, to shut down the LM5030 outputs and the VCC regulator. If the voltage at the SD pad is between
1.0 and 1.5 V, a partial-on condition results, which could be disruptive to the system. Therefore, the voltage at
the SD pad should transition quickly between its open circuit voltage (4.9 V) and ground.
8.2.2.4 External Sync
Although the LM5030 includes an internal oscillator, its operating frequency can be synchronized to an external
signal if desired. The external source frequency must be higher than the internal frequency set with the RT
resistor (262 kHz with RT = 20 kΩ). The sync input pulse width must be between 15 and 150 ns, and have an
amplitude of 1.5 to 3.0 V at the Sync pad on the board. The pulses are coupled to the LM5030 through a 100-pF
capacitor (C16) as specified in the data sheet.
Table 2. Bill of Materials
ITEM
PART NUMBER
C0805C472K5RAC
DESCRIPTION
Capacitor, CER, KEMET
VALUE
4700 p, 50 V
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
1
2
3
4
5
6
7
8
9
C0805C103K5RAC
C4532X7S0G686M
T520D337M006AS4350
T520D337M006AS4350
C4532X7R3A103K
C3216X7R2A104K
C4532X7R2A105M
C4532X7R2A105M
C0805C102K1RAC
C1206C223K5RAC
C3216X7R1E105M
C3216COG2J221J
C3216COG2J221J
C1206C104K5RAC
C0805C101J1GAC
C0805C101J1GAC
C3216X7R1H334K
Capacitor, CER, KEMET
Capacitor, CER, TDK
Capacitor, TANT, KEMET
Capacitor, TANT, KEMET
Capacitor, CER, TDK
Capacitor, CER, TDK
Capacitor, CER, TDK
Capacitor, CER, TDK
Capacitor, CER, KEMET
Capacitor, CER, KEMET
Capacitor, CER, TDK
Capacitor, CER, TDK
Capacitor, CER, TDK
Capacitor, CER, KEMET
Capacitor, CER, KEMET
Capacitor, CER, KEMET
Capacitor, CER, TDK
0.01 µ, 50 V
68 µ, 4 V
330 µ, 6.3 V
330 µ, 6.3 V
0.01 µ, 1000 V
0.1 µ, 100 V
1 µ, 100 V
1 µ, 100 V
10
11
12
13
14
15
16
17
18
1000 p, 100 V
0.022 µ, 50 V
1 µ, 25 V
220 p, 630 V
220 p, 630 V
0.1 µ, 50 V
100 p, 100 V
100 p, 100 V
0.33 µ, 50 µ
16
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ITEM
SNVS215D –APRIL 2003–REVISED NOVEMBER 2015
Table 2. Bill of Materials (continued)
PART NUMBER
MBRB3030CTL
DESCRIPTION
VALUE
D
D
1
2
Diode, Schottky, ON
CMPD2838-NSA
CMPD2838-NSA
CMPD2838-NSA
CMPD2838-NSA
MSS6132-103
Diode, Signal, Central
Diode, Signal, Central
Diode, Signal, Central
Diode, Signal, Central
Input Choke, Coilcraft
Output Choke, Coilcraft
Resistor
D
3
D
4
D
5
L
1
10 µH, 1.5 A
L
2
A9785-B
7 µH
1
R
1
CRCW12061R00F
CRCW12064990F
CRCW2512101J
CRCW2512101J
CRCW12064022F
CRCW120610R0F
CRCW120610R0F
CRCW12061002F
CRCW120623R7F
CRCW12062002F
CRCW120610R0F
CRCW12063010F
CRCW120610R0F
CRCW12061001F
A9784-B
R
2
Resistor
499
R
3
Resistor
100, 1 W
100, 1 W
40.2K
10
R
4
Resistor
R
5
Resistor
R
6
Resistor
R
7
Resistor
10
R
8
Resistor
10K
23.7
20K
10
R
9
Resistor
R
10
11
12
13
14
1
Resistor
R
Resistor
R
Resistor
301
R
Resistor
10
R
Resistor
1K
TX
TX
U1
U2
U3
POWER XFR, COILCRAFT
CURRENT XFR, Pulse
REGULATOR, TI
OPTO-COUPLER, QT OPTOELECTRONICS
REFERENCE, TI
DUAL TERMINALS, MOUSER
FET, N, 200 V, SILICONIX
FET, N, 200 V, SILICONIX
2
P8208T
100:1
1
LM5030
2
MOCD207M
3
LM3411AM5-3.3
651-1727010
3 per ASSY
X
X
1
2
SUD19N20-90
SUD19N20-90
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V1
Q2 Gate
0V
t1
t2
V1
V4
Q1 Gate
0V
V3
V2
0V
Q2 Drain
tR = 150 ns
V5
V6
T1 (Pin 4)
0V
V8
V7
V9
V10
D1 Output
L2 Output
0V
3.3V
100 mVp-p
Figure 11. Representative Waveforms
Table 3. Test Data
VIN
IOUT
1.0 A
10 A
1.0 A
t1
t2
Fs
V1
V2
V3
V4
V5
V6
6 V
V7
V8
V9
V10
6 V
36 V
48 V
75 V
2.2 µS 5.3 µS 266.7 10.5 V
1.9 µS 5.5 µS 270.3 11.5 V
1.2 µS 6.2 µS 270.3 10.5 V
36 V
48 V
75 V
72 V
96 V
150 V
90 V
10 V
18 V
20 V
–10 V
–18 V
–20 V
–6 V
–8 V
–13 V
10 V
13 V
20 V
130 V
200 V
8 V
8 V
13 V
13 V
18
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8.2.3 Application Curves
100
90
80
70
60
50
40
30
20
1.2
1.0
0.8
0.6
0.4
0.2
VIN = 36 V
VIN = 75 V
VIN = 36 V
VIN = 75 V
0.0
0
0
2
4
6
8
10
5
LOAD CURRENT (A)
10
LOAD CURRENT (A)
Figure 13. Efficiency vs Load Current and VIN
Figure 12. Input Current vs Load Current and VIN
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9 Power Supply Recommendations
The LM5030 can be used as a controller for push-pull, full bridge or half bridge power supplies. Typical
applications are for input voltages up to 100 V and output power around 30 W with switching frequency up to
1 MHz.
Care should be taken that components with the correct current rating are chosen. This includes magnetic
components, power MOSFETs and diodes, connectors and wire sizes. Input and output capacitors should have
the correct ripple current rating.
The VCC pin requires a local decoupling capacitor that is connected to GND. This capacitor ensures stability of
the internal regulator from the VIN pin. The decoupling capacitor also provides the current pulses to drive the
gates of the external MOSFETs through the driver output pins.
Place the decoupling capacitor close to the VCC and GND pins and track it directly to these pins.
10 Layout
10.1 Layout Guidelines
As in all high frequency switching power supplies, it is important to separate the high current return trace from
the low level GND signal of the controller. These signals should be connected together at a single point, usually
the negative side of the DC input filter capacitor.
Layout considerations are critical for the current sense filter. If a current sense transformer is used, both leads of
the transformer secondary should be routed to the sense filter components and to the device pins. If the current
sense circuit employs a sense resistor in the power MOSFET source, a low inductance resistor should be used
and all the low current traces should be connected in common near the device with a single connection made to
the GND pin.
The gate drive outputs of the device should have short, direct paths to the power MOSFETs in order to minimize
inductance in the gate path.
If the internal dissipation of the device produces a high junction temperature during normal operation, the use of
multiple vias under the device to a ground plane can help conduct heat away from the device.
10.2 Layout Example
VIN
SS
RT
CS
VFB
From VIN
COMP
To Current Sense
Resistor
VCC
GND
To Gate Drive 2
OUT1
OUT2
To Isolated Feedback
To Gate Drive 1
Figure 14. LM5030 Board Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
SNOA401: AN-1187 Leadless Leadframe Package (LLP)
SNVA548: Versatility of the LM5030 PWM Push-Pull Controller
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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25-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5030MM
NRND
VSSOP
DGS
10
1000
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
-40 to 125
S73B
LM5030MM/NOPB
LM5030MMX/NOPB
LM5030SD/NOPB
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
WSON
DGS
DGS
DPR
10
10
10
1000 RoHS & Green
3500 RoHS & Green
1000 RoHS & Green
SN
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
S73B
S73B
Samples
Samples
Samples
5030SD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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25-Jan-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5030MM/NOPB
LM5030MMX/NOPB
LM5030SD/NOPB
VSSOP
VSSOP
WSON
DGS
DGS
DPR
10
10
10
1000
3500
1000
178.0
330.0
178.0
12.4
12.4
12.4
5.3
5.3
4.3
3.4
3.4
4.3
1.4
1.4
1.3
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5030MM/NOPB
LM5030MMX/NOPB
LM5030SD/NOPB
VSSOP
VSSOP
WSON
DGS
DGS
DPR
10
10
10
1000
3500
1000
208.0
367.0
208.0
191.0
367.0
191.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
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EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
DPR0010A
WSON - 0.8 mm max height
SCALE 3.000
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
A
B
(0.2)
4.1
3.9
PIN 1 INDEX AREA
FULL R
BOTTOM VIEW
SIDE VIEW
20.000
ALTERNATIVE LEAD
DETAIL
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
2.6 0.1
(0.1) TYP
SEE ALTERNATIVE
LEAD DETAIL
5
6
2X
3.2
11
3
0.1
8X 0.8
1
10
0.35
0.25
0.1
10X
0.5
0.3
PIN 1 ID
10X
C A B
C
0.05
4218856/B 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.6)
10X (0.6)
SYMM
10
1
10X (0.3)
(1.25)
SYMM
11
(3)
8X (0.8)
6
5
(
0.2) VIA
TYP
(1.05)
(R0.05) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EDGE
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218856/B 01/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
10X (0.6)
METAL
TYP
(0.68)
10
1
10X (0.3)
(0.76)
11
SYMM
8X (0.8)
4X
(1.31)
5
6
(R0.05) TYP
4X (1.15)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4218856/B 01/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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