LM5036RJBR [TI]
具有集成辅助偏置电源和稳压预偏置启动的半桥 PWM 控制器 | RJB | 28 | -40 to 125;型号: | LM5036RJBR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有集成辅助偏置电源和稳压预偏置启动的半桥 PWM 控制器 | RJB | 28 | -40 to 125 控制器 |
文件: | 总69页 (文件大小:3648K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LM5036
ZHCSI27C –APRIL 2018 –REVISED OCTOBER 2021
具有集成辅助偏置电源的LM5036 半桥PWM 控制器
1 特性
3 说明
• 适用于小外形尺寸、高密度直流/直流电源转换器的
高集成度控制器
• 集成100V、100mA 辅助偏置电源
• 全稳压预偏置启动
• 适用于低侧和高侧初级FET 的具有脉冲匹配的增强
型逐周期电流限制
LM5036 PWM 控制器,集成了辅助偏置电源,可为工
业隔离式电源应用提供高功率密度。它包含使用带有输
入电压前馈的电压模式控制来实现半桥功率转换器所需
的所有功能。此控制器适合在直流输入电压高达 100V
的隔离式转换器的初级侧运行。此控制器包含的功能可
提高功率密度和可靠性,同时降低系统成本:
• 针对初级侧FET 优化了最大占空比
• 带有输入电压前馈的电压模式控制
• 100V 高压启动稳压器
• 可配置锁存器,支持OVP
• 用于初级侧FET 的集成式100V、2A MOSFET 驱
动器
• 作为辅助偏置电源的集成Fly-Buck 转换器。为一级
和二级电路提供偏置电源,具有极少的外部组件。
• 全稳压预偏置启动。即使启动到预充电输出电容器
时,也可消除输出电压过冲或突降。
• 具有脉冲匹配的增强型逐周期峰值电流限制。此控
制器可限制正负电流。脉冲匹配可确保低侧和高侧
器件具有相等的脉宽,以避免变压器饱和。输出电
流限制在整个输入电压范围内保持大致恒定。
• 初级侧和同步整流器(SR) FET 之间的死区时间可
编程
• 使用LM5036 并借助Excel 计算器工具或
WEBENCH® Power Designer 创建定制设计方案
器件信息
封装(1)
封装尺寸(标称值)
器件型号
LM5036
2 应用
WQFN (28)
5.00mm × 5.00mm
• 电信和数据通信隔离式电源
• 工业电源和工厂自动化
• 测试和测量设备
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
13 VIN
BST_AUX 15
SW_AUX 14
VIN
VAUX2
28 UVLO
VAUX1
VCC 17
24 RAMP
FB_AUX 12
BST 21
1
6
7
RES
VCC
VIN
RON
SR1
ON_OFF
VIN
VO
HSG 22
8
SS
SW 23
LSG 18
11 RD2
RD1
10
2
SR2
VCS+
VCSœ
SGND
AGND
VAUX2
16 PGND
REF
SR1 20
SR2 19
SR1
SR2
VO
5
RT
Isolated
Driver
VIN
VFB
VAUX2
REF
4
25 CS_POS
VCS+
26 CS_NEG
27 CS_SET
VCSœ
+
COMP
SSSR
3
9
VREF
VAUX2
VAUX2
TH
+
简化版应用
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNVSB14
LM5036
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ZHCSI27C –APRIL 2018 –REVISED OCTOBER 2021
Table of Contents
7.4 Device Functional Modes..........................................41
8 Application and Implementation..................................42
8.1 Application Information............................................. 42
8.2 Typical Application.................................................... 42
9 Power Supply Recommendations................................57
10 Layout...........................................................................58
10.1 Layout Guidelines................................................... 58
10.2 Layout Example...................................................... 58
11 Device and Documentation Support..........................60
11.1 Device Support........................................................60
11.2 Documentation Support.......................................... 60
11.3 支持资源..................................................................60
11.4 Trademarks............................................................. 60
11.5 Electrostatic Discharge Caution..............................60
11.6 术语表..................................................................... 60
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics.............................................7
6.6 Switching Characteristics..........................................10
6.7 Typical Characteristics.............................................. 11
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................15
Information.................................................................... 61
4 Revision History
Changes from Revision B (April 2019) to Revision C (October 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Updated footnote to standard language............................................................................................................. 7
• Deleted minimum and maximum peak value of current source for slope compensation (ISLOPE) specifications.
Updated typical from 54 µA to 36 µA. Removed table note (1) from this parameter.......................................... 7
• Changed typical peak current (ISO_PRI) specification from 1.5 A to 1 A .............................................................7
• Changed minimum BST_AUX undervoltage threshold (VBST_AUX(UVLO) ) specification from 2.1 V to 3.5 V ......7
• Changed typical BST_AUX undervoltage threshold (VBST_AUX(UVLO) ) specification from 2.8 V to 5.0 V .......... 7
• Changed maximum BST_AUX undervoltage threshold (VBST_AUX(UVLO) ) specification from 3.6 V to 6.5 V .....7
• Changed typical peak current source value references from "1.5 A" to "1 A" in 节7.3.6 ................................ 17
Changes from Revision A (June 2018) to Revision B (April 2019)
Page
• Added minimum recommended values for RD1 and RD2 ..................................................................................6
• Changed minimum recommended input voltage from 18V to 16V. ....................................................................6
• Added current limit parameters KCBC1, VCSOFFSET and IBiasOffset .......................................................................7
• Changed typical value of ISLOPE from 50-µA to 54-µA........................................................................................7
• Added parameter names for some items that had none: IOVL, VSSSecEn, VSSREn, tCSLSG, tCSBLK, VRESTh2
,
VRESTh3 VRTReg, VRTSync,ICOSsrEn, IAUX(LIM) ........................................................................................................ 7
• Changed parameter name VRES to VRESTh1 ...................................................................................................... 7
• Changed parameter name VPWM-OS to IPWM-OS .................................................................................................7
• Changed parameter VAUX_UVLO maximum value from 16.6V to 16V. ................................................................ 7
• Changed parameter name HC_BLK_TH to VHC_BLK_TH ....................................................................................7
• Added new parameters AUX SUPPLY CURRENT LIMIT: tCSBLKA, tAUX(LIM), τAuxSns .......................................7
• Added new conditions in Switching Characteristics for tON ............................................................................. 10
• Added Reference to the Calculator tool............................................................................................................13
• Changed Positive and negative current limit shown to be affected by LEB signal. ......................................... 14
• Added reference to operation from voltages above 100V. Values replaced with parameter names. ...............15
• Added reference to table of device functional modes.......................................................................................15
• Changed Parameter name VREF to VREFSec to avoid confusion with primary reference voltage......................16
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• Changed Implied minimum value of tD from 0-ns to 30-ns............................................................................... 18
• Added note that minimum value of RD1/RD2 resistors should not be less that 5-kΩ.....................................18
• Added pre-biased start-up process is handled automatically by LM5036 ....................................................... 21
• Changed values to parameter names. VREF changed to VREFSec, TH changed to VTHSec .............................. 21
• Changed values to parameter names. ICOMP is graphed instead of VCOMP. ....................................................21
• Changed VCOMP to ICOMP. ................................................................................................................................21
• Changed and expanded Section: 'Enhanced Cycle-by-Cycle Current Limiting with Pulse Matching'.............. 24
• Changed and expanded Section: 'Reverse Current Protection'. ..................................................................... 28
• Added Section: 'CBC Threshold Accuracy'.......................................................................................................29
• Changed values to parameter names. .............................................................................................................31
• Changed Section: 'ON_OFF Pin' to 'Over-Voltage / Latch (ON_OFF Pin)'. Values replaced by parameter
names. .............................................................................................................................................................33
• Changed Section: 'Constant On-Time Control' to 'Auxiliary Constant On-Time Control'.................................. 34
• Changed Section: 'On-Time Generator' to 'Auxiliary On-Time Generator'........................................................35
• Added method to calculate peak Auxiliary transformer current. External schottky recommended to improve
Auxiliary efficiency during ASYNCH mode. ..................................................................................................... 36
• Deleted Section: 'Ripple Configuration Types'..................................................................................................38
• Added Section: 'Auxiliary Ripple Configuration and Control'. .......................................................................... 39
• Changed values to parameter names. .............................................................................................................41
• Changed C26 from 330-pF to 47-pF, R29 from 165-kΩto 220-kΩ. Added D11............................................. 42
• Changed voltage targets for auxiliary output voltage from 12.6 V / 9 V to 11.9 V / 8.5 V. ............................... 43
• Added reference to Excel Calculator Tool. .......................................................................................................43
• Added restriction on use of TL431 to implement secondary side error amplifier..............................................44
• Added reference to Power Stage Designer Tool. .............................................................................................44
• Changed values to parameter names. RUV1 andRUV2 replace R1 and R2. .......................................................45
• Changed Section: 'ON_OFF Pin Voltage Divider Selection' to 'Over Voltage / Latch (ON_OFF Pin) Voltage
Divider Selection'. ............................................................................................................................................ 46
• Added new Section: 'Half-Bridge Power Stage Design' ...................................................................................47
• Changed and expanded Section:'Current Limit' .............................................................................................. 48
• Changed calculation of Auxiliary transformer inductance. ...............................................................................53
• Changed calculated value for RON resistor. .....................................................................................................54
• Changed calculated value of Auxiliary primary output capacitor value. ...........................................................54
• Changed calculation of secondary output capacitor. Now uses ripple peak amplitude not peak-to-peak
amplitude. ........................................................................................................................................................ 54
• Changed calculation of Auxiliary Feedback component values. ......................................................................55
• Changed expression for ICOMP to fix error. .......................................................................................................55
• Changed layout diagram to include external schottky diode connected between PGND and SW_AUX pins. ....
58
Changes from Revision * (April 2018) to Revision A (June 2018)
Page
• 将销售状态从“预告信息”更改为“初始发行版”。.........................................................................................1
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5 Pin Configuration and Functions
28 27 26 25 24 23 22
RES
AGND
COMP
REF
BST
1
2
3
4
5
6
7
21
20
19
18
17
16
15
SR1
SR2
29
Thermal Pad
LSG
RT
VCC
RON
PGND
BST_AUX
ON_OFF
8
9
10 11 12 13 14
图5-1. RJB Package, 28-Pin WQFN (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
AGND
BST
NO.
2
G
I
Analog ground
21
15
3
Half-bridge high-side gate drive bootstrap
Auxiliary supply high-side gate drive bootstrap
Control current input to half-bridge PWM comparator
Current sense amplifier negative input terminal
Current sense amplifier positive input terminal
Current limit setting
BST_AUX
COMP
CS_NEG
CS_POS
CS_SET
FB_AUX
HSG
I
I
26
25
27
12
22
18
7
I
I
I
I
Auxiliary supply output voltage feedback
Half-bridge high-side MOSFET output driver
Half-bridge low-side MOSFET output driver
Configurable for over voltage protection (OVP) or latch mode
Power ground
O
O
I
LSG
ON_OFF
PGND
RAMP
RD1
16
24
10
11
4
G
I
RAMP signal input to half-bridge PWM comparator
Synchronous rectifier trailing-edge delay
Synchronous rectifier leading-edge delay
5-V reference regulator output
I
RD2
I
REF
O
I
RES
1
Hiccup mode restart timer
RON
6
I
Auxiliary supply on-time control
RT/SYNC
SR1
5
I
Oscillator frequency control or external clock synchronization
Synchronous rectifier PWM control output
Synchronous rectifier PWM control output
Soft-start input
20
19
8
O
O
I
SR2
SS
SSSR
9
I
Synchronous rectifier soft-start input
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表5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
SW
NO.
23
14
28
17
13
29
I
I
Half-bridge switch node
SW_AUX
UVLO
VCC
Auxiliary supply switch node
Input undervoltage lockout
Bias supply
I
I
VIN
I
Input voltage
Pad
G
Exposed thermal pad
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
-5
MAX
UNIT
V
VIN to GND
105
105
16
SW/SW_AUX to GND
V
BST TO SW, BST_AUX TO SW_AUX
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
V
HSG to SW
16
V
LSG to GND
16
V
SR1/SR2 to GND
5
V
VCC to GND
16
V
RT, UVLO, ON/OFF, RON, RAMP, RES, FB_AUX, CS_POS, CS_NEG, CS_SET to GND
5
V
COMP to GND
-0.3
10
V
COMP Input Current
Junction Temperature
Storage Temperature, Tstg
mA
°C
°C
150
150
-55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
±2000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specificationJESD22-
C101, all pins(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
16
8.5
5
NOM
MAX
100
14
UNIT
V
VIN
Input voltage
External VCC
Supply Voltage
V
RDx
TJ
RD1, RD2 Resistor value
Junction Temperature
kΩ
°C
125
–40
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6.4 Thermal Information
LM5036
THERMAL METRIC (1)
RJB (WQFN)
28 PINS
29.9
UNIT
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
18.2
Junction-to-board thermal resistance
10.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ΨJT
10.3
ΨJB
RΘJC(bot)
1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
MIN and MAX limits apply the junction temperature range of –40°C ≤TJ ≤125°C. Unless otherwise specified, the following
conditions apply: VIN = 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ, RON = 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5
V, ON_OFF = 0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
START-UP REGULATOR
VCC
VCC voltage
ICC = 10 mA
7.5
69
7.8
81
8.1
94
V
ICC (Lim)
Vcc current limit
VCC = 6 V, VIN = 20 V
mA
Supply current into Vcc from an
externally applied source. VCC = 9 V,
FB_AUX = 0 V
ICC(ext)
Vcc supply current
6.6
9
11
mA
VCC(reg)
VCC(UV)
Vcc load regulation
ICC from 0 to 50 mA
31
7.4
6.1
276
49
7.7
73
8.0
6.7
670
mV
V
Vcc undervoltage threshold
Positive going Vcc
Negative going Vcc
6.3
V
VIN shutdown current
580
µA
VIN = 20 V, VUVLO = 0 V, RON = 100 kΩ
VIN = 100 V, VUVLO = 0 V, RON = 100
kΩ
299
180
600
234
717
304
µA
µA
VCC = 9 V, applied externally, FB_AUX
> 2 V, SS = 0 V, RON = 100 kΩ
VIN start-up regulator leakage
VOLTAGE REFERENCE REGULATOR (REF PIN)
VREF
REF voltage
IREF = 0 mA
4.85
24
5
37
5.15
57
V
mV
mA
V
VREF(REG)
IREF(LIM)
VREF(UV)
REF load regulation
REF current limit
REF undervoltage threshold
Hysteresis
IREF = 0 to 25 mA
VREF = 4.5 V, VIN = 20 V
Positive going VREF
28
39
47
4.3
0.16
4.5
0.26
4.7
0.37
V
UNDERVOLTAGE LOCK OUT AND SHUTDOWN (UVLO PIN)
VUVLO
IUVLO
UVLO threshold
1.205
15
1.25
20
1.305
24
V
UVLO Hysteresis current
µA
Internal startup regulator enable
threshold
VSD
SS = 0 V, FB_AUX = 2.5 V
0.34
90
0.38
135
0.41
175
V
Hysteresis
mV
OVER-VOLTAGE/LATCH (ON_OFF PIN)
VON_OFF
IOVL
ON_OFF threshold
1.18
40
1.25
50
1.32
60
V
ON_OFF hysteresis current
µA
SOFT-START (SS PIN, SSSR PIN)
ISS SS charge current
SS = 0 V
17
20
24
µA
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MIN and MAX limits apply the junction temperature range of –40°C ≤TJ ≤125°C. Unless otherwise specified, the following
conditions apply: VIN = 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ, RON = 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5
V, ON_OFF = 0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SS threshold to enable SSSR
charge current
VSSSecEn
ICOMP < 800 µA
1.93
2.06
2.2
V
SS output low voltage
Sinking 100 µA
30
865
17
48
1000
20
57
1198
24
mV
mV
µA
SS threshold to disable switching
SSSR charge current
ISSSR
SS > 2 V, ICOMP < 800 µA
Sinking 100 µA
SSSR output low voltage
30
38.7
49
mV
SSSR threshold to enable SR
freewheeling pulse
VSSREn
0.65
1.17
1.67
V
CURRENT SENSE (CS_POS, CS_NEG, and CS_SET PIN)
VLIM
Current limit setting voltage
0.72
0.3
0.75
0.58
0.77
0.9
V
Ratio of internal negative to
positive current limit threshold
tCSLSG
tCSBLK
KCBC1
CS to gate driver output delay
CS leading-edge blanking
60
33
85
53
122
76
ns
ns
V
(1)
VLIM x (K2a X K10b - K10a
VCS_POS - VCS_NEG
IBiasPOS - IBiasNEG
)
At CBC trip threshold
At CBC trip threshold
At CBC trip threshold
7.28
-0.63
-0.67
7.51
-0.02
0.02
7.81
0.32
0.29
(1)
(1)
VCSOffset
IBiasOffset
mV
µA
Peak value of current source for
slope compensation
ISLOPE
36
µA
REVERSE CURRENT PROTECTION
Number of switching periods to
N
reset negative over-current event
counter
4
SSSR threshold to reset SSSR
cap clamp event counter
SR_CTR_TH
4.8
4.94
5.1
V
HICCUP MODE (RES PIN)
RRES
RES pulldown resistance
Termination of hiccup timer
24
0.90
3.91
1.95
12
36
1
55
1.04
4.07
2.04
18
Ω
V
VRESTh1
VRESTh3
VRESTh2
IRES-SRC1
IRES-SRC2
IRES-DIS1
IRES-DIS2
RES hiccup threshold
RES upper counter threshold
RES lower counter threshold
Charge current source1
Charge current source2
Discharge current source1
Discharge current source2
4
V
2
V
VRES < 1 V, CBC active
1 V < VRES< 4 V
CBC not active
15
30
5
µA
µA
µA
µA
25
36
3.2
5.5
2 V < VRES < 4 V
2.5
5
7.5
HICCUP MODE BLANKING
SSSR threshold to disable the
hiccup blanking
VHC_BLK_TH
5.26
3.9
5.5
6.0
5.66
9.1
V
VOLTAGE FEED-FORWARD (RAMP PIN)
RAMP sink impednace (clocked)
OSCILLATOR (RT PIN)
Ω
Frequency (half oscillator
frequency)
fSW1
185
420
200
480
215
540
kHz
kHz
RT = 25 kΩ
RT = 10 kΩ
Frequency (half oscillator
frequency)
fSW2
VRTReg
VRTSync
DC level
1.85
2.8
2
3
2.06
3.3
V
V
RT sync threshold
SYNCHRONOUS RECTIFIER TIMING CONTROL (RD1 and RD2 PINS)
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MIN and MAX limits apply the junction temperature range of –40°C ≤TJ ≤125°C. Unless otherwise specified, the following
conditions apply: VIN = 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ, RON = 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5
V, ON_OFF = 0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
123
278
79
MAX
157
350
102
UNIT
SR trailing edge delay SR turn-off
to primary switch turn-on
t1
94
ns
RD1 = 20 kΩ
213
60
ns
RD1 = 100 kΩ
RD2 = 20 kΩ
RD2 = 100 kΩ
SR leading edge delay primary
switch turn-off to SR turn-on
t2
ns
188
47
250
65
315
87
ns
ns
tclk
Pulse width of the clock
COMP PIN
IPWM-OS
VSS-OS
COMP current to RAMP offset
SS to RAMP offset
RAMP = 0 V
596
0.86
800
1
1063
1.15
2936
0.74
µA
V
RAMP = 0 V
COMP current to RAMP gain
SS to RAMP gain
delta RAMP/delta ICOMP
delta SS/delta RAMP
1895
0.574
2400
0.646
Ω
COMP current for SSSR charge
curent enable
ICOSsrEn
SS > 2 V
600
100
750
120
900
µA
COMP to gate driver output delay
Minimum duty cycle
150
0
ns
%
ICOMP = 1 mA
BOOST (BST PIN)
VBST(UV) BST under-voltage threshold
Hysteresis
LSG, HSG GATE DRIVERS
VOL_PRI Low-state output voltage
VBST - VSW rising
3.2
4.137
0.481
5.6
V
V
0.37
0.65
IHSG/LSG = 100 mA
0.1
0
0.3
0.41
1
V
V
IHSG/LSG = 100 mA, VOHL_PRI = VCC
VLSG, VOHH_PRI = VBST - VHSG
-
VOH_PRI
High-state output voltage
0.38
Rise Time
C-load =1000 pF
C-load =1000 pF
VHSG/LSG = 0V
2
2
8
10
1
12
14
ns
ns
A
Fall Time
ISO_PRI
ISI_PRI
Peak Source Current
Peak Sink Current
VHSG/LSG = VCC
2
A
SR1, SR2 GATE DRIVERS
VOL_SR Low-state output voltage
VOH_SR
ISR1/SR2 = 10 mA
0.12
0.313
65
V
V
High-state output voltage
Rise Time
ISR1/SR2 = 10 mA, VOH_SR = VREF - VSR
C-load = 1000 pF
C-load = 1000 pF
VSR = 0 V
25
4
45
10
ns
ns
A
Fall Time
16
ISO_SR
ISI_SR
Peak Source Current
Peak Sink Current
0.05
0.1
0.09
0.2
0.14
0.4
VSR = VREF
A
HALF BRIDGE THERMAL SHUTDOWN
TSD
Thermal Shutdown Temp
150
25
°C
°C
Thermal Shutdown Hysteresis
AUX SUPPLY SWITCH CHARACTERISTICS
Buck Switch RDS(ON)
ITEST= 60 mA
ITEST= 60 mA
3.0
1.2
5.2
2.8
7.5
4.5
Ω
Ω
Synchronous Switch RDS(ON)
AUX SUPPLY UNDERVOLTAGE LOCKOUT
VBST_AUX(UV)
VAUX_UVLO
BST_AUX undervoltage threshold VBST_AUX - VSW_AUX rising
3.5
5.0
15
6.5
V
V
AUX supply UVLO input voltage
rising threshold
12.2
16.0
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MIN and MAX limits apply the junction temperature range of –40°C ≤TJ ≤125°C. Unless otherwise specified, the following
conditions apply: VIN = 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ, RON = 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5
V, ON_OFF = 0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUX supply UVLO input voltage
falling threshold
7.9
11.2
12.7
V
AUX SUPPLY REGULATION
OFF-State AUX Voltage
Regulation Level
VAUX-OFF
VAUX-ON
1.26
0.95
1.4
1
1.53
1.04
V
V
ON-State AUX Voltage
Regulation Level
AUX SUPPLY CURRENT LIMIT
AUX Supply Current Limit
IAUX(LIM)
150
200
50
250
mA
ns
Threshold
Current limit comparator blanking
period measured from start of tON
period (1)
tCSBLKA
Delay from Comparator
Threshold to upper MOSFET
turn-OFF (1)
tAUX(LIM)
116
41
ns
ns
Aux Current Limit Parasitic Filter
time constant (1)
τAuxSns
AUX SUPPLY THERMAL SHUTDOWN
AUX Supply Thermal Shutdown
TSD_AUX
160
28
°C
°C
Temp
AUX Supply Thermal Shutdown
Hysteresis
(1) Specified by design. Not production tested.
6.6 Switching Characteristics
MIN and MAX limits apply the junction temperature range –40°C ≤TJ ≤125°C. Unless otherwise specified, the following
conditions apply: VIN = 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ, RON =100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5
V, ON_OFF = 0 V.
PARAMETER
TEST CONDITIONS
VIN = 32 V, RON = 100 kΩ
VIN=54 V, RON = 250 kΩ
VIN=75V, RON = 250 kΩ
MIN
TYP
330
493
370
MAX
UNIT
tON
tON
tON
AUX SUPPLY ON-TIME
AUX SUPPLY ON-TIME(1)
AUX SUPPLY ON-TIME(1)
240
440
ns
ns
ns
AUX SUPPLY MINIMUM OFF-
TIME
tOFF(MIN)
FB_AUX = 0 V
69
103
136
ns
(1) Specified by design. Not production tested.
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6.7 Typical Characteristics
100%
95%
90%
85%
80%
75%
70%
65%
60%
55%
50%
8
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
VIN = 36 V
VIN = 48 V
VIN = 75 V
1.5
1
0.5
0
0
1
2
3
4
5
Load Current (A)
6
7
8
0
10
20
30
40
50
60
VCC Supply Current (mV)
70
80
90 100
D001
D002
fSW = 200 kHz
VO = 12 V
图6-2. VCC Load Regulation
图6-1. Application Board Efficiency vs Load
Current
325
300
275
250
225
200
175
150
125
100
75
8
7
6
5
4
3
2
1
0
50
25
VCC
REF
0
9
19
29
39
49 59
Input Voltage (V)
69
79
89
99
2
4
6
8
10 12
Input Voltage (V)
14
16
18
20
D003
D004
图6-3. Input Leakage Current of Start-up Regulator
图6-4. VCC and REF Voltage vs Input Voltage
vs Input Voltage
2100
1800
1500
1200
900
600
300
0
300
275
250
225
RD1 = 20 kW, T1
RD1 = 100 kW, T1
RD2 = 20 kW, T2
RD2 = 100 kW, T2
200
175
150
125
100
75
50
0
5
10
15
20
25
30
35
40
45
50
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
RT Timing Resistance (kW)
D001
D006
图6-5. Oscillator Frequency vs RT Timing
图6-6. Dead Time vs Temperature
Resistance
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300
275
250
225
200
175
150
125
100
75
775
770
765
760
755
750
745
740
735
730
725
50
T1
T2
25
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
10
20
30
40
50
60
70
80
90 100
RD1 = RD2 Dead-Time Programming Resistance (kW)
D001
D007
图6-8. CS_SET Pin Voltage vs Temperature
图6-7. Dead Time vs Programming Resistance
1000
210
205
200
195
190
185
180
900
800
700
600
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D009
D010
图6-9. COMP Pin to 1-V RAMP Offset vs
图6-10. Auxiliary Supply Current Limit vs
Temperature
Temperature
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10
15
20
25
30
REF Current (mA)
35
40
45
50
D011
图6-11. REF Load Regulation
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7 Detailed Description
7.1 Overview
The LM5036 device is a highly-integrated, half-bridge PWM controller with integrated auxiliary bias supply. It
provides a high power-density solution for telecom, datacom and industrial power converters. The device has all
of the features necessary to implement a power converter that uses half-bridge topology. The device employs
voltage-mode control and includes input voltage feed-forward to improve performance. This device operates on
the primary side of an isolated DC-DC power converter with input voltage up to 100-V.
The soft-start function provides a fully regulated and monotonic rise of output voltage, even when the converter
energizes into a pre-biased load. The device uses an enhanced cycle-by-cycle (CBC) current limit. This function
matches the pulse to maintain the voltage balance of the half-bridge capacitor divider. This method ensures flux
balance of the transformer during CBC operation. The input voltage compensation function helps to minimize the
variation of the current limit level across the entire input voltage range.
The LM5036 device has these other features:
• configurable latch protection
• configurable overvoltage protection (OVP)
• optimized maximum duty cycle operation for the primary MOSFETs
• integrated half-bridge MOSFET gate drivers
• programmable dead-time between the primary MOSFETs and synchronous rectifiers
• auxiliary supply synchronous and asynchronous mode transition
• 5-V synchronous rectifier PWM outputs
• programmable line undervoltage lockout (UVLO)
• hiccup mode overcurrent protection (OCP)
• reverse current protection
• a 2-MHz capable oscillator with synchronization capability
• two-level thermal shutdown protection
An Excel Calculator Tool is provided to ease the process of creating custom designs using this controller. This
tool calculates values for all the external components required by the controller to meet a given specification. It
also generates many key parameters of the power stage including, for example, the turns ratio of the half-bridge
transformer. The tool generates graphs predicting, for a given set of current limit components, how the output
current limit will vary with input voltage. Maximum flexibility is offered by calculating suggested values for most
components, but allowing the user to input values of their own choice.
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7.2 Functional Block Diagram
VCC
IAUX
+
VCC
REF
REF
Regulator
ILIM
One-Shot
VIN 13
IAUX_LIM
AUX
OCP
RES
RON
1
6
RES
RON
15 BST_AUX
Start-Up Regulator
VIN
+
VAUX_UVLO
VIN
œ
UVLO 28
+
AUX
OFF
350 mV
VCC UV
REF UV
VCC UV
REF UV
AGND
SS
2
8
IAUX
HB OFF
AUX
TEMP
160°C
+
+
1.25 V
1.25 V
14 SW_AUX
Supply
Control
Logic,
Driver
Logic,
Dead
Time,
Protection
Logic
20 µA
AUX OTP
RON
VIN
COT
Timers
+
ON_OFF
7
50 µA
Hiccup Mode
150°C OTP
AUX
ASYNC
Mode
HB OFF
UVLO<1.25 V
(LATCH RESET)
VCC
17 VCC
AUX OCP
11
10
RD2
RD1
FB_AUX
12 FB_AUX
OFF STATE
ON STATE
0
FB_AUX
REG
+
Analog
MUX
1
REF_AUX
21 BST
22 HSG
23 SW
RAMP 24
+
SS
CLK
2 V
T
Q
MAIN CLK
DELAYED CLK
Prog.
Delay
RT
5
3
OSC
Q
REF
VCC
REF
S
R
Q
Q
COMP
RAMP
+
PWM
R
Main
Supply
Soft-Start,
Driver
Logic,
Dead-
Time
Control,
and
Pulse
18 LSG
20 SR1
19 SR2
R
MAIN CLK
VCOMP
+
1 V
+
TH
SSSR
HICCUP
BLANK
+
SS
ISLOPE
SS
CS_POS 25
Matching
REF
SSSR Cap
Clamp Event
Counter
IOFFSET
Hiccup
Mode
Timer
and
+
Amp
ISENSE
POS_OCP
LEB
K
1/K
+
CBC
CS_NEG
26
RES
Clamp
SSSR Cap
Logic
IPOS_LIM
2
ICS_SET
4
REF
REF
NEG OC
Event Counter
CS_SET 27
NEG
+
INEG_LIM
1/2
NEG_OCP
+
16 PGND
VLIM
œ
Clamp
SSSR Cap
0
+
AGND
9
SSSR
Duty
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7.3 Feature Description
7.3.1 High-Voltage Start-Up Regulator
The LM5036 device contains a high-voltage VCC start-up regulator that allows the input pin (VIN) to be
connected directly to an input voltage up to 100-V. Higher input voltages can be accommodated by adding some
additional external parts, as described in 节 8.2.2.4. When the UVLO pin voltage is greater than VSD (0.38-V
typical), the start-up regulator is enabled to charge an external capacitor connected to the VCC pin. The output
voltage of the VCC regulator is regulated at VCC (7.8-V typical). The VCC regulator provides power to the
reference (REF) regulator. The regulator output at VCC is internally current limited to ICC(Lim) (81-mA typical) .
The value of the VCC capacitor depends on the total system design, and its start-up characteristics. The
recommended range of values for the VCC capacitor is 0.47-µF to 10-µF.
LM5036 can power itself using its internal high-voltage start-up linear regulator, but internal power dissipation
can be reduced by powering VCC from an auxiliary switched mode supply. LM5036 device integrates all of the
functions needed to implement a low-cost and easy-to-design isolated fly-buck auxiliary supply based on the
constant-on-time (COT) control scheme. The primary output VAUX1 of the auxiliary supply must be connected
through a diode to the VCC pin, as shown in 图 7-1. The auxiliary supply must raise the VCC voltage above the
internally generated VCC voltage in order to shut off the internal start-up regulator. Powering VCC from an
auxiliary switched mode supply improves efficiency while reducing the power dissipation of the controller IC. The
VCC under-voltage (UV) circuit will still function in this mode, requiring that VCC never falls below its UV
threshold during the start-up sequence. The VCC regulator series pass transistor includes a diode between VCC
and VIN that should not be forward biased in normal operation. Therefore, the auxiliary VCC voltage should
never exceed the VIN voltage.
VIN
VAUX1
VCC
VIN
PGND
图7-1. External VCC Bias Supply Connection
7.3.2 Undervoltage Lockout (UVLO)
The LM5036 controller contains a three-level under-voltage lockout circuit. When the UVLO pin voltage is below
VSD (0.38-V typical), the controller is in a low current shutdown mode where the functional circuit blocks are not
enabled including VCC startup regulator, auxiliary supply and the main half-bridge control logic and gate drive
circuitry, etc.
When UVLO pin voltage is above VSD, the VCC and REF regulators become active.
When the VCC and REF outputs exceed their respective UV thresholds and the input voltage VIN rises above
VAUX_UVLO (15-V typical), the auxiliary supply is enabled.
When UVLO pin voltage rises above VUVLO (1.25-V typical) and VCC and REF voltage are above their
respective UV thresholds, the control logic of the main half-bridge converter is enabled. The soft-start capacitor
is released and normal operation begins. An external set-point voltage divider from VIN to GND can be used to
set the minimum operating voltage of the half-bridge converter. The divider must be designed such that the
voltage at the UVLO pin is greater than VUVLO when VIN enters the desired operating range. UVLO hysteresis is
accomplished with an internal current sink IUVLO (20-µA typical) that is switched on or off into the impedance of
the external set-point divider. When the UVLO pin voltage threshold of VUVLO is exceeded, the current sink is
deactivated to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the VUVLO
threshold, the current sink is enabled causing the voltage at the UVLO pin to quickly fall. See 表 7-1 for more
detail on functional modes of LM5036.
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7.3.3 Reference Regulator
The REF pin is the output of a 5-V linear regulator that can be used to bias an opto-coupler transistor, primary
side of an isolated gate driver or digital isolator, among other housekeeping circuits. The regulator output is
internally current limited to IREF(LIM) (39-mA typical). The REF pin must be locally decoupled with a ceramic
capacitor, the recommended range of values is from 0.1-µF to 10-µF.
7.3.4 Oscillator, Synchronized Input
The oscillator frequency of LM5036 device is set by a resistor connected between the RT pin and AGND. The RT
resistor should be located close to the device. To set a desired oscillator frequency (fOSC), the value of RT
resistor can be calculated from 方程式1.
1
RT =
fOSC × 1 × 10F10
(1)
For example, if the desired oscillator frequency is 400-kHz, that is, each phase (LSG and HSG) switches at 200-
kHz, the value of RT is calculated to be 25-kΩ. If the LM5036 device is to be synchronized to an external clock,
that signal must be coupled into the RT pin through a 100-pF capacitor. The RT pin voltage is nominally
regulated at VRTReg (2-V typical) and the external pulse amplitude should lift the pin to between 3.5-V and 5.0-V
on the low-to-high transition. The synchronization pulse width should be between 15-ns and 200-ns. The RT
resistor is always required, whether the oscillator is free running or externally synchronized and SYNC frequency
must be equal to or greater than the frequency set by the RT resistor.
7.3.5 Voltage-Mode Control
The LM5036 device employs voltage-mode control with input voltage feed-forward for the main half-bridge
converter. A simplified block diagram of the voltage-mode feedback control loop is shown in 图7-2.
RAMP
COMP
REF
VAUX2
VO
REF
RAMP
5 kΩ
VCOMP
+
PWM
VSS-OS
+
VFB
COMP
R
E/A
+
R
+
VREFSec
SS
SS
SS
图7-2. Voltage-Mode Feedback Control Loop for Half-Bridge Converter
The output voltage (VO) is sensed and compared against a reference voltage (VREFSec) on the secondary side
which produces an error voltage which is then processed by the error amplifier. The compensated error signal is
transmitted across the isolation boundary through an opto-coupler and then gets injected into the COMP pin in
the form of a control current. The COMP pin current is internally mirrored by a matching pair of NPN transistors
which sink current through a 5-kΩ resistor connected to the 5-V internal reference. The resulting control voltage
VCOMP is compared with the soft-start capacitor voltage (SS) and the smaller of the two passes through an offset
VSS-OS (1-V typical), followed by a 2:1 resistor divider before being applied to the PWM comparator to determine
the duty cycle of the half-bridge converter. The PWM comparator polarity is configured such that with no current
flowing into the COMP pin, the controller produces maximum duty cycle for the primary FETs.
An opto-coupler detector can be connected between the REF pin and the COMP pin. Because the COMP pin is
controlled by a current input, the voltage across the opto-coupler detector is nearly constant. The bandwidth
limiting phase delay which is normally introduced by the significant capacitance of the opto-coupler is thereby
greatly reduced. Higher loop bandwidths can be realized because the bandwidth limiting pole associated with
the opto-coupler is now at a much higher frequency.
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The voltage at the RAMP pin provides the modulation ramp for the PWM comparator. The PWM comparator
compares the modulation ramp signal at the RAMP pin to the COMP voltage to control the duty cycle. The
modulation ramp signal can be implemented as a ramp proportional to the input voltage, known as feed-forward
voltage mode control, as shown in 图 7-3. The RAMP pin is reset by an internal MOSFET when RAMP voltage
passes COMP voltage, current limit event, or at the conclusion of each PWM cycle, whichever comes earlier.
REF
5 kΩ
Slope proportional to VIN
COMP
1 V
R
VIN
R
PWM
+
RFF
RAMP
(1)
CFF
Time
AGND
图7-4. Modulation Ramp Slope
A. Slope proportional to input voltage (see 图7-4)
图7-3. Feed-Forward Voltage-Mode Control
Configuration
An external resistor (RFF) and capacitor (CFF) connected to VIN, AGND, and the RAMP pins are required to
create a saw-tooth modulation ramp signal. The slope of the signal at RAMP will vary in proportion to the input
voltage. The varying slope provides line feed-forward information necessary to improve line transient response
with voltage-mode control. With a constant control signal, the on-time (tON) varies inversely with the input voltage
(VIN) to stabilize the volt-second product of the transformer. Using a line feed-forward ramp for PWM control
requires very little change in the voltage regulation loop to compensate for changes in input voltage, as
compared to a ramp with fixed slope. In addition, voltage-mode control is less susceptible to noise. Therefore, it
is a good choice for wide input range power converter applications. However, voltage-mode control requires a
Type-III compensation network due to the complex-conjugate poles of the L-C output filter.
Assistance with half-bridge voltage control loop design may be obtained using the Power Stage Designer™ tool.
The recommended capacitor value range for CFF is from 100-pF to 1800-pF. 图 7-3, shows that the CFF value
must be small enough to be discharged within the clock pulse-width (tCLK). The value of RFF required can be
calculated from 方程式2
F1
RFF
=
VRAMP
fOSC × CFF × lnl1 F
p
V
:
;
IN min
(2)
For example, assuming a VRAMP voltage of 1.5-V (a good compromise of signal range and noise immunity),
IN(min) of 36-V, oscillator frequency of 400-kHz and CFF = 560-pF results in RFF = 105-kΩ.
V
7.3.6 Primary-Side Gate Driver Outputs (LSG and HSG)
The LM5036 device provides two gate driver outputs for the primary FETs of the main half-bridge converter: one
floating high-side gate driver output HSG and one ground referenced low-side gate driver output LSG. Each
internal gate driver is capable of sourcing 1-A peak and sinking 2-A peak (typical). Initially, the LSG output is
turned on during the power transfer phase, followed by a freewheeling period during which both LSG and HSG
outputs are turned off. In the subsequent power transfer phase, the HSG output is turned on followed by another
freewheeling period.
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The low-side LSG gate driver is powered directly by the VCC bias supply. The HSG gate driver is powered from
a bootstrap capacitor connected between BST and SW. An external diode connected between VCC and BST
provides the high-side gate driver power by charging the bootstrap capacitor from VCC when the switching node
SW is low. When the high side FET is turned on, BST rises to a peak voltage equal to VCC + VIN.
The BST and VCC capacitors should be placed close to the pins of the LM5036 device to minimize voltage
transients due to parasitic inductance because the peak current source to the MOSFET gates can exceed 1 A
(typical). The recommended value of the BST capacitor is 0.1-µF or greater. A low ESR/ESL capacitor, such as a
surface mount ceramic, should be used to prevent voltage drop during the HSG transitions.
7.3.7 Half-Bridge PWM Scheme
Synchronous rectification on the secondary side of the transformer provides higher efficiency, especially for low
output voltage and high output current converter, compared to the diode rectification. The reduction of the diode
forward voltage drop (0.5-V to 1.5-V) to 10-mV to 200-mV VDS voltage for a MOSFET significantly reduces
rectification losses. In a typical application, the secondary windings of the transformer can be center tapped, with
the output power inductor in series with the center tap, as shown in 图 7-5. The synchronous rectifiers (SRs)
provide the ground path for the energized secondary winding and the inductor current.
VIN
SR1
VO
HSG
LSG
SR2
SGND
PGND
图7-5. Half-bridge Topology with Center-Tap Rectification
The internal SR drivers are powered by the REF regulator and each SR output is capable of sourcing 0.1-A and
sinking 0.2-A peak (typical). The amplitude of the SR drivers is limited to 5-V. The 5-V SR signals enable the
transfer of SR control signals across the isolation barrier either through a digital isolator or isolated gate driver. It
should be noted that the actual gate sourcing and sinking currents for the SRs are provided by the secondary-
side gate drivers.
The timing diagram of the four PMW signals (LSG, HSG, SR1, and SR2) with dead-times is illustrated in 图 7-6.
The main clock is generated by the internal oscillator. A delayed clock is derived by adding a delay of tD to the
main clock. tD can be calculated from 方程式 3, where RD1 is the value of the resistor connected between RD1
pin and AGND.
tD = RD1 × 2 pF + 20 ns
(3)
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tCLK
tD
Main
CLK
tOSC .
Delayed
CLK
tSW .
LSG
HSG
t .
2
t .
2
t
1
t
1
SR1
SR2
Time
图7-6. PWM Signal Timing Diagram
As illustrated in 图 7-6, the rising edge of the main clock is used to turn off the SRs. Primary FET drive signal
LSG/HSG is turned on at the falling edge of the delayed clock. Therefore, the dead-time between the falling
edge of SR and the rising edge of the respective primary FET can be calculated from 方程式4
t1 = tD + tCLK
(4)
where
• tCLK is the pulse width of the clock which is 65 ns (typical).
The minimum achievable t1 is dominated by the pulse width of the clock when tD is set to minimum (30 ns).
After SR1 is turned off, the body diode of SR1 continues to carry about half the inductor current until the primary
power raises the drain voltage of the SR1 and reverse biases its body diode. Ideally, dead-time t1 would be set
to the minimum time that allows the SR to turn off before the body diode starts conducting.
Power is transferred from the primary to the secondary side when the LSG is turned on. During this power
transfer period, the SR2 is still turned on while the SR1 is turned off. The drain voltage of SR1 is twice the
voltage of the center tap at this time. Under the normal operation, the LSG is turned off either when the RAMP
signal exceeds the COMP signal or at the rising edge of the next delayed clock signal (maximum duty cycle
condition), whichever comes earlier. A dead-time t2 is inserted between the falling edge of LSG and rising edge
of SR1. t2 can be calculated from 方程式 5, where RD2 is the value of the resistor connected between RD2 pin
and AGND.
t2 = RD2 × 2 pF + 30 ns
(5)
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During the dead-time t2, the inductor current continues to flow through the body diode of SR1. Because the body
diode causes more conduction loss than the SR, efficiency can be improved by minimizing the t2 period while
maintaining sufficient margin across the entire operating conditions (component tolerances, input voltages, etc.)
to prevent the cross conduction between the primary FET and SR.
During the freewheeling period where both of the primary FETs are turned off while both of the SRs are turned
on, the inductor current is almost equally shared between SR1 and SR2 which effectively shorts the secondary
winding of the transformer. SR2 is then turned off before HSG is turned on. The power is transferred from the
primary to secondary side again when HSG is turned on. After HSG is disabled and the dead-time t2 expires,
SR1 and SR2 both conduct again during the freewheeling period.
Resistor values of no less than 5-kΩshould be connected between the RD1/RD2 pins and AGND
7.3.8 Maximum Duty Cycle Operation
The LSG and HSG will operate at maximum duty cycle when they are turned off at the rising edge of the delayed
clock, instead of by the event where RAMP voltage passes COMP voltage, as shown in 图 7-7. In LM5036
device, it is intended to achieve optimized maximum duty cycle for the primary FETs in order to accommodate
wider range of operation.
tCLK
tD
Main
CLK
Delayed
CLK
LSG
HSG
t
1
t .
2
t
1
SR1
SR2
t .
2
Time
图7-7. PWM Signals at Maximum Duty Cycle Condition
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Use 方程式6 to calculate the maximum duty cycle for the primary FETs
1
F tCLK
fOSC
DMAX
=
2
fOSC
(6)
where
• fOSC is the oscillator frequency which is twice the switching frequency
The pulse width of the clock is used in this case to prevent cross-conduction between the two primary FETs
during the maximum duty cycle operation.
7.3.9 Pre-Biased Start-Up Process
The soft-start functionality limits the inrush current and voltage stress of the power converter. A common
requirement for the power converters used in the telecom/datacom applications is to have a monotonic output
voltage start-up into pre-biased load conditions where the output capacitor is pre-charged prior to start-up. In a
pre-biased load condition, if the synchronous rectifiers are engaged prematurely they will sink current from the
pre-charged output capacitors resulting in undesired output voltage dip or even power converter damage. The
LM5036 device implements unique circuitry to ensure intelligent turn-on of the synchronous rectifiers such that
the output voltage has monotonic start-up.
The start-up process can be divided into two phases:
• soft-start of the primary FETs
• soft-start of the SRs
The pre-biased start-up process is handled automatically by LM5036. The user need only select values for CSS
,
CSSSR, and the ramp rate of the secondary reference (VREFSec) soft-start 图 7-8. The circuit of 图 7-8 uses a
comparator to, detect the voltage change of VAUX2 and, release the FET shorting across the secondary soft-start
capacitor (CSSSec). This comparator circuit may also be replaced by the transistor based circuit of 图8-3.
7.3.9.1 Primary FETs Soft-Start Process
图7-8 shows a simplified block diagram of the soft-start function.
FB_AUX
VAUX2
VO
0
REF
VAUX-OFF
FB_AUX
AUX PWM
Analog
MUX
+
REF_AUX
1
VAUX-ON
AUX Regulation
Comparator
VFB
COMP
E/A
+
SS
+
VSSSecEn
RSSSec
VREFSec
CSSSec
VAUX2
SS
VAUX2
+
VTHSec
图7-8. Soft-Start Function
The auxiliary supply has two reference output voltage levels of VAUX-OFF (1.4 -V typical, off state) and VAUX-ON
(1-V typical, on state) which facilitates easy voltage level shift detection on the secondary side. The auxiliary
supply starts to operate as soon as VIN > VAUX_UVLO (15-V typical) and VCC and REF are above the respective
UV thresholds. When the soft-start capacitor is below VSSSecEn (2.06-V typical), the auxiliary supply will produce
the off-state voltage on the primary (VAUX1-OFF) and secondary side (VAUX2-OFF), as shown in 图7-9.
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The off-state auxiliary output voltage level present on the secondary side VAUX2-OFF is above the threshold
VTHSec, which activates a reset circuit that discharges the output voltage reference VREFSec. This ensures that
the opto-coupler is producing a 0% duty-cycle command. When UVLO exceeds VUVLO (1.25-V typical) and VCC
and REF are above the respective UV thresholds, the soft-start capacitor starts to charge. The auxiliary supply
will produce the on-state voltage level when the soft-start capacitor reaches VSSSecEn
.
VAUX_UVLO
VIN
VUVLO
VSD
UVLO
VAUX2-OFF
VAUX2-ON
VTHSec
VAUX2
VSSSecEn
VSS-OS
SS
Prebias
Voltage
VO
VREFSec
ICOSsrEn
Soft-Start of SR
Freewheeling
SYNC Mode
Pulse
SR
ICOMP
VSSREn
SSSR
t1
t2
t3
图7-9. Pre-biased Start-Up Waveform
The secondary side reset circuit will now be disabled because VAUX2-ON < VTHSec, and the output voltage
reference is released. The reference capacitor soft-starts the output voltage under full regulation. By modulation
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of the auxiliary output voltage, the communication between the primary and secondary side is established
without the need of any additional opto-coupler.
Due to the introduced programmable soft-start delay (before SS capacitor reaches VSSSecEn), the duty cycle is
controlled by the feedback control loop at all times without being interfered by the SS capacitor voltage (because
VCOMP < VSS). When the reference voltage exceeds the pre-bias voltage at the output, the ICOMP starts to fall as
the secondary side error amplifier demands increased power. As ICOMP falls the internal VCOMP voltage will rise
and when it exceeds VSS-OS, which corresponds to zero duty cycle, the duty cycle of the primary FETs starts to
increase. Once the ICOMP current falls below ICOSsrEn the device starts to charge SSSR capacitor with current
ISSSR (20-µA typical).
Main
Clk
Delayed
Clk
LSG
HSG
SR1
SR2
VSSREn
SSSR
图7-10. PWM Timing During Startup Process
7.3.9.2 Synchronous Rectifier (SR) Soft-Start Process
Until SSSR capacitor reaches VSSREn (1-V typical), the controller operates at SR synchronization (SYNC) mode
where the SR pulses are synchronized to the respective primary FET pulses, as shown in 图 7-10. This helps to
reduce the conduction loss of the SRs. In addition, due to the fact that the SRs only conduct during power
transfer phase, there is no risk of reverse current in SYNC mode. Since the pulse width of SRs gradually
increases, the output voltage disturbance due to the difference in the voltage drop between the body diode and
the on resistance of the SRs is prevented.
Once the SSSR capacitor crosses the VSSREn, the LM5036 device begins the soft-start of the SRs freewheeling
period (highlighted in gray in 图 7-10) where the SRs may sink current from the output if they are engaged
prematurely. The VSSREn offset on the SSSR pin is intended to provide additional delay which ensures that the
primary duty cycle ramps up to a point where the output voltage is in-regulation, thereby avoiding reverse current
when the SRs are engaged. The SR soft-start follows a leading-edge modulation technique such that the
leading-edge of the SR pulse is soft-started as opposed to the trailing-edge modulation of the primary FETs. As
shown in 图 7-10, SR1 and SR2 are turned on simultaneously with a narrow pulse-width during the freewheeling
period. At the end of the freewheel period, that is, at the rising edge of the main CLK, the SR in phase with the
next power transfer cycle remains on while the SR out of phase with it is turned off. The in-phase SR remains on
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throughout the power transfer cycle and at the end of it, both the primary FET and the in-phase SR are turned off
simultaneously. At the end of the soft-start, the SR pulses will become complementary to the respective primary
FETs, as shown in 图7-6.
7.3.10 Zero Duty Cycle Operation
The zero duty cycle detection ensures that there is no excessive reverse current when the primary duty cycle is
zero. In that case, the SSSR capacitor would be clamped to ground and therefore SRs will be turned off (SR
SYNC mode). Normal operation will resume (SSSR capacitor start to charge) as soon as the load is applied. It
should be noted about a special application scenario where there is a low output capacitance value. During the
start-up under no load condition, the output capacitor acts like a load. With small output capacitor the converter
might get stuck in zero duty until load is applied.
7.3.11 Enhanced Cycle-by-Cycle Current Limiting with Pulse Matching
图7-11 illustrates the half-bridge converter with low-side current sensing using a sense resistor.
VIN
SR1
VO
HSG
SW
LSG
SR2
VCS+
VCSœ
SGND
PGND
PGND
图7-11. Half-Bridge Converter with Low-Side Current Sensing
In LM5036 device, current limiting for the half-bridge converter is accomplished with three pins, including
CS_SET, CS_POS and CS_ NEG pins, as shown in 图 7-12. The current sense circuit limits positive current
flowing from input to output and also negative current flowing from output to input. An input voltage
compensation function helps to minimize the variation of effective output current limit across the range of input
voltage. A pulse matching function is automatically implemented when the peak current limit circuit is active. This
function matches the pulse width on the high and low primary FETs to maintain voltage balance of the half-
bridge capacitor divider. This method ensures flux balance of the transformer during peak current limit operation.
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VIN
IPRI
R2
ISLOPE
K10a
R1
CS_POS
+
Amp
CF
R3
RCS
VCS
1/K10b
K2a
+
CBC
CS_NEG
CS_SET
POS_OCP
NEG_OCP
PGND
ICS_SET
RLIM
1/K2b
NEG
+
+
AGND
VLIM
œ
AGND
图7-12. Block Diagram of the Current Limiting Function
CS_SET pin is used to set the internal current limit threshold with an external resistor RLIM according to 方程式
7.
V
LIM
ICS_SET
=
RLIM
(7)
where
• VLIM (0.75-V typical) is the internal current limit setting voltage.
The CS_POS pin is driven by a signal representative of the current flowing through the low-side FET of the half-
bridge converter. The current sense voltage at CS_POS pin (equal to CS_NEG pin voltage) is converted to a
current sense signal through R3 which is then sensed, scaled and compared against the internal current limit
thresholds. In order to blank the leading-edge transient noise seen when the low-side FET is turned on, the
current sense signal is blanked for tCSBLK after LSG is turned on. If the magnitude of the noise spike is
excessive, an additional filter capacitor CF may be added to form an RC filter with R1 to reduce the high-
frequency noise spike. Both the leading-edge blanking and RC filter help to prevent false triggering of CBC
current limiting operation.
In order to achieve bi-directional current sensing, an internal offset current (K10a x ICS_SET), is injected to the
CS_POS pin. This offset allows positive internal thresholds on the CBC and NEG comparators that correspond
to effective ICS_SET and -ICS_SET / 2 thresholds at the input.
When the current sense signal (IR3 x 1 / K10b) reaches the positive threshold (K2a x ICS_SET), CBC current limiting
operation is activated. The controller essentially operates in peak current mode control, with the voltage loop
open, during the CBC operation. A common issue with peak current mode control is sub-harmonic oscillation.
This occurs when the effective duty cycle is greater than 50%. A common solution for sub-harmonic oscillation is
to add slope compensation. The slope of the compensation ramp must be set to at least one half the downslope
of the output inductor current transformed to the primary side across the current sense resistor. To eliminate sub-
harmonic oscillation after one switching cycle, the slope compensation must be equal to the downslope of the
output inductor current. This is known as deadbeat control. In LM5036, the slope compensation signal is a saw-
tooth current signal ramping up from 0 to ISLOPE at the oscillator frequency (twice the switching frequency of
each primary FET).
However, another issue will arise after slope compensation is added. The current limit level varies with the input
voltage, as illustrated in 图 7-13. Because the slope compensation magnitude is different at different input
voltages, the actual current limit level varies with input voltage for a given internal current limit threshold.
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ICS_SET x 20
ISLOPE x Dmax
ICS_SET x 20
ISLOPE x Dmin
VCS / R1
IO / NPS
IO / NPS
VCS / R1
VIN(min) / R2
VIN(max) / R2
ICS_SET x 10
ICS_SET x 10
ICS_SET x 5
ICS_SET x 5
time
time
图7-13. Current Sense and Current Limit Waveforms
A new feature, input voltage compensation, is provided by LM5036. By adding an extra signal, which is a
function of input voltage, on top of the current sense signal and the slope compensation signal, variation of the
current limit level can be minimized over the entire input voltage range. The CS_POS pin voltage at time t, after
the rising edge of LSG, is expressed by 方程式8:
≈
V
IN - vCS _POS
t
( )
’
vCS _POS t = v
( )
t + R ì ICS _ SET ìK10a
+
+ISLOPE ì t ì fOSC
CS ( )
∆
÷
÷
1
∆
R2
«
◊
(8)
(9)
≈
’
V
IN
vCS t + R ì ICS _ SET ìK10a
+
+ISLOPE ì t ì fOSC
( )
∆
÷
◊
1
R2
«
vCS _POS t =
( )
R1
1+
R2
At the trip threshold, of the CBC comparator, both its inputs are at the same potential. In this case the voltage on
the CS_NEG pin is expressed by 方程式10.
vCS_NEG = ICS_ SET ìK2a ìK10b ìR3
(10)
vCS _POS t = v
CS _NEG
(11)
For a given duty cycle (D) the current sense threshold voltage that will just trigger the CBC comparator can be
determined by combining 方程式9, 方程式10 and 方程式11.
≈
’
≈
∆
«
’
≈
∆
«
’
÷
V
1
1
IN
vCS_ CBCTh = R ì I
ì K2a ìK10b ìR3
+
-K
-
-ISLOPE ìD
∆
÷
÷
◊
∆
÷
÷
1
CS_ SET
10a
∆
R1 R2 ◊
R2
◊
«
(12)
Now if we assume:
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1
1
1
=
+
R3 R1 R2
K10a = K10b = 10
K2a = 2
2ì VO
D = tON ì fOSC
=
ìNPS
V
IN
NP
NPS
=
NS
(13)
方程式12 simplifies to 方程式14.
≈
∆
«
’
÷
◊
KCBC1
V
2ì VO
IN
vCS _ CBCTh = R ì
-
-ISLOPE
ì
ìNPS
1
RLIM
R2
V
IN
Where
KCBC1 = VLIM ì K2a ìK10b -K10a
(
)
(14)
节 8.2.2.11 gives an example design process for calculating the CBC external resistor values. The Excel
Calculator Tool can also be used to assist in the process of selecting these resistor values.
LM5036 ensures flux balance of the main transformer during CBC operation. The duty cycles of the two primary
FETs are always matched. If the low-side FET is terminated due to a current limit event, a matched duty cycle
will be applied to the high-side FET during the next half switching period, regardless of the current condition. The
matched duty cycles ensure voltage-second balance of the transformer which prevents transformer saturation.
The pulse matching operation is illustrated in 图 7-14. When the current limit is reached during the low-side
phase, a FLAG signal goes high. The RAMP signal is sampled at the rising edge of the FLAG signal and then
held through the next half switching period for the high-side phase. When the high-side phase RAMP signal rises
above the sampled value, the high-side PWM pulse is turned off so that the duty cycle are matched for both
phases. In the meantime, the hiccup restart capacitor is charged with a current source IRES-SRC1 (15-µA typical)
during CBC operation. The pulse matching feature is handled automatically by the LM5036 controller and
requires no action from the designer.
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Delayed
CLK
Current Limit
Sensed
Current
S&H
Ramp
Flag
LSG
HSG
图7-14. Pulse Matching Operation
7.3.12 Reverse Current Protection
In addition to the CBC current limit, a negative current limit, which is set to be half of the positive current limit as
shown in 图 7-15. This is used to prevent excessive reverse current which could cause significant output voltage
dip and potentially damage the power converter. When the negative current limit is exceeded twice, the SSSR
capacitor will be clamped to ground so the controller enters the SR SYNC mode where the SR pulses are
synchronized to the respective primary FET pulses. Therefore, the SR freewheeling pulses are turned off. The
negative current limit event counter will be reset if the number of negative current limit events detected within
four switching periods is less than two.
1/K2b
Negative
Current Limit
Event Counter Clamping
SSSR cap
SSSR Cap
Clamp Event
Counter
+
Hiccup Mode ON
When Counter = 8
CS_SET
RLIM
INEG_LIM
NEG_OCP
+
VLIM
œ
AGND
AGND
图7-15. Reverse Current Protection Circuit
At the trip threshold of the NEG comparator both inputs are at the same potential. In this case the voltage on the
CS_NEG pin is expressed by 方程式15.
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1
vCS_NEG = ICS_ SET
ì
ìK10b ìR3
K2b
(15)
The voltage across the CS resistor at the trip threshold of the NEG comparator can therefore be determined by
combining 方程式9, 方程式11 and 方程式15.
≈
∆
«
’
÷
◊
KCBC2
V
IN
vCS _ NEGTh = R ì
-
-ISLOPE ì tCSBLK ì fosc
1
RLIM
R2
Where :
K2b = 2
≈
’
1
KCBC2 = VLIM
ì
ìK10b -K10a
∆
«
÷
◊
K2b
(16)
Notice that the inductor current has its most negative value at the start of the LSG on period. The NEG
comparator trip will occur immediately after the blanking period (tCSBLK) has expired.
The Excel Calculator Tool predicts both the positive and negative output current limit levels as a function of input
voltage for a given set of resistor values.
7.3.13 CBC Threshold Accuracy
The CBC current limit amplifier deployed within LM5036 is a precise component. In common with all such
devices the input bias currents and input offset voltage will lead to small variations in the current trip threshold
between parts and across temperature.
VIN
R2
IPRI
ISLOPE
VCSOffset
K10a
R1
IBiasPOS
IBiasNEG
CS_POS
+
Amp
CF
R3
RCS
VCS
1/K10b
K2a
+
CBC
CS_NEG
CS_SET
POS_OCP
NEG_OCP
PGND
ICS_SET
RLIM
1/K2b
NEG
+
+
AGND
VLIM
œ
AGND
图7-16. Diagram of Current Limiting Function with Error Terms Shown in Red
At its trip threshold the two inputs of the CBC comparator must be equal. At this condition the voltage on the
CS_NEG pin is given by 方程式17.
≈
∆
«
’
VLIM
RLIM
vCS _NEG
=
ìK2a ìK10b + IBiasNEG ìR
÷
3
◊
(17)
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The voltage drop across the ideal amplifier input must be zero. The voltage of the CS_POS pin, at the trip
threshold can be expressed as follows:
vCS_POS = vCS_NEG + vCSOffset
(18)
V - vCS_POS
≈
∆
«
’
÷
◊
VLIM
RLIM
IN
vCS_POS = vCS_ CBCTh
+
ìK10a +IBiasPOS +DìISLOPE
+
ìR
1
R2
(19)
Combining 方程式 17, 方程式 18 and 方程式 19 and re-arranging gives an expression for the voltage across the
current sense resistor at the trip threshold 方程式20.
≈
’
÷
K
vCSOffset
V
IN
vCS _ CBCTh = R ì CBC1 -IBiasOffset
+
-DìISLOPE -
∆
1
RLIM
R3
R2 ◊
«
Where :
IBiasOffset = IBiasPOS -IBiasNEG
(20)
Hence, for a given set of external component values, the variation in current trip threshold across parts and
temperature can be found using data supplied in the Electrical Tables.
A short delay will exist (tCSLSG), after the CBC comparator inputs reach their trip threshold, before the LSG falling
edge. During this delay the primary current will continue to ramp, giving rise to a further error in the apparent trip
threshold. The peak primary current flowing when the low side MOSFET switches OFF (IPriCBC), is expressed by
方程式21.
≈
’
≈
’
VCS _ CBCTh
V
V
VO
1
2
IN
IN
∆
∆
«
÷
÷
◊
IPriCBC
=
+ tCSLSG
ì
ì
+
-
∆
∆
«
÷
÷
◊
2
RCS
LMag
LO ìNPS
LO ìNPS
(21)
The output current at which the primary peak current threshold is reached is expressed by 方程式22.
»
ÿ
LMagŸ
⁄
DILO
NPS
ILIM = NPS ì I
-
- DI
…
PriCBC
(22)
(23)
ΔILO is the amplitude of ripple current in the output inductor and is expressed in 方程式23.
VO ì(1-D)
DILO
=
2ìLO ì fOSC
ΔILMag is the amplitude of ripple current in the magnetising inductor and is expressed in 方程式24.
V
NPS ì VO
2ìLMag ì fOSC 2ìLMag ì fOSC
D
IN
DILMag
=
ì
=
2
(24)
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Combining 方程式 22, 方程式 23 and 方程式 24 gives an expression for output current limit as a function of
primary current limit threshold 方程式25.
»
ÿ
Ÿ
V ì 1-D
(
)
VO ìNPS
O
ILIM = NPS ì I
-
-
…
PriCBC
2ìLO ì fOSC ìNPS 2ìLMag ì fOSC Ÿ
…
⁄
(25)
The Excel Calculator Tool can be used to evaluate the tolerance of output current limit.
7.3.14 Hiccup Mode Protection
A block diagram of the hiccup mode function is shown in 图 7-17. Both the repetitive CBC and negative current
limit events will trigger hiccup mode operation in LM5036 device.
Continuous
CBC
Hiccup
Mode
Timer
and
RES
SSSR Cap
Clamp Event
Counter
Logic
Reset
SSSR
Hiccup
Blank
VRES
1 V
TH
SSSR
+
+
图7-17. Hiccup Mode Circuitry
The device charges the hiccup restart capacitor with a current source IRES-SRC1 (15-µA typical) during CBC
operation. The hiccup mode is activated when VRES exceeds 1 V. During hiccup mode operation, the SS and
SSSR capacitors are fully discharged and the half-bridge converter remains off for a period of time (tHIC) before a
new soft-start sequence is initiated.
4 V
2 V
1 V
tCBC
SS
tHIC
图7-18. Hiccup Mode Activated By Continuous CBC Operation
Use 方程式26 to calculate the duration of CBC operation before entering the hiccup mode.
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CRES ì1V
IRES-SRC1
tCBC
=
(26)
where
• CRES is the value of the hiccup capacitor
After the RES pin reaches 1.0-V, current source IRES-SRC1 (15-μA typical) is turned off and current source
RES-SRC2 (30-μA typical) is turned on which charges the RES capacitor to 4-V. Then current source IRES-DIS2 (5-
I
μA typical) is enabled which discharges the RES capacitor to 2-V.
Use 方程式27 to calculate the hiccup mode off-time.
CRES ì 2 V ì8 +1V
CRES ì 2 V ì8
(
)
tHIC
=
+
IRES-DIS2
IRES-SRC2
(27)
In addition to the repetitive CBC current limit condition, the device also enters hiccup mode if the SSSR capacitor
is clamped for eight times due to repetitive negative current limit condition. The operating pattern of the hiccup
mode activated by the negative current limit is similar to that activated by CBC current limit. The only difference
is that at the beginning of the hiccup mode operation the RES capacitor is charged with current source IRES-SRC2
when activated by negative current limit as illustrated in 图 7-19 whereas the RES capacitor is charged with
current source IRES-SRC1 when activated by CBC current limit condition.
4 V
2 V
0 V
Counter (1)
tHIC
(1) SSSR capacitor clamp event counter
图7-19. Hiccup Mode Activated By Repetitive Negative OCP Condition
Once the hiccup off-timer expires, the SSSR capacitor clamp event counter will be reset. If SSSR capacitor gets
clamped for less than eight times before the SSSR capacitor voltage is fully ramped up to its maximum value,
the SSSR capacitor clamp event counter will also be reset. This is because the fact that SSSR capacitor voltage
is able to fully ramp up to its maximum value indicates that repetitive negative current limit condition no longer
exists.
7.3.15 Hiccup Mode Blanking
In some application scenarios such as high output capacitance and/or heavy load, there can be excessive inrush
current during the start-up process. This would trigger CBC current limit which in turn activates the hiccup mode
operation, thereby causing the converter to keep attempting to restart. In LM5036 device, a hiccup mode
blanking circuitry is implemented to disable the hiccup mode operation during the start-up. The hiccup capacitor
is clamped to ground until the SSSR capacitor voltage rises above the hiccup blank threshold VHC_BLK_TH (5.5-V
typical).
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7.3.16 Over-Temperature Protection (OTP)
Two-level internal thermal shutdown circuitry is implemented in LM5036 device to protect the integrated circuit
should its maximum rated junction temperature be exceeded. When the internal temperature is above the lower-
level threshold of 150°C, the half-bridge converter is turned off and thereby the SS and SSSR capacitors are
fully discharged.
Typically, the internal temperature should drop after the main half-bridge converter is turned off. However, if the
temperature continues to rise above the higher-level threshold of 160°C, the auxiliary supply will be disabled in
order to prevent the device from catastrophic failure due to accidental device overheating . Note that the internal
VCC and REF bias regulators still remain active during thermal shutdown to provide the bias power for the
external house-keeping circuitry.
7.3.17 Over-Voltage / Latch (ON_OFF Pin)
The ON_OFF pin can be configured as a latch pin or OVP pin. In the latch configuration, the half-bridge
converter remains off even after the faults are cleared. A new soft-start sequence will not be initiated until the
latch is reset. One latch configuration is illustrated in 图7-20 where a large latch resistor RL (for example, 50 kΩ)
and a diode are tied to the ON_OFF pin.
REF
IOVL
VIN
ON_OFF
VON_OFF
ROV1
REF UV
+
ROV2
RL
Hiccup Mode
150°C OTP
VCC UV
HB OFF
UVLO < 1.25 V
(LATCH RESET)
UVLO < 1.25 V
图7-20. ON/OFF Pin Latch Function
When any of the faults is detected including OVP, hiccup mode OCP and 150 °C OTP, the ON_OFF pin current
source, IOVL (50-µA typical), is activated, that raises the ON_OFF pin voltage quickly. As a result, the latch diode
is reverse biased. The current source IOVL remains active even if the fault is cleared because the ON_OFF pin
voltage is latched above VON_OFF (1.25-V typical). To reset the latch operation, simply pulling down the UVLO pin
voltage below VON_OFF disables the current source and thus the ON_OFF pin voltage falls quickly. A new soft-
start sequence will be initiated as soon as the latch is reset and the faults are cleared.
Use 方程式28 to design the external voltage divider in latch mode.
V
ON_ OFF + VF VON_ OFF
≈
∆
«
’
÷
◊
V
=
+
ìROV1 + VON_ OFF + VF
IN_L
ROV2
RL
(28)
where
• VF is the forward voltage drop of the latch diode
• VIN_L is the desired input voltage latch threshold, and RL is the latch resistor.
Note that the current source IOVL does not provide any hysteresis when ON_OFF pin is configured in latch mode.
The ON_OFF pin can also be configured as an OVP pin as shown in 图 7-21. In this configuration, the external
voltage divider should be designed such that the ON_OFF pin voltage is greater than VON_OFF when an over-
voltage condition occurs.
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REF
IOVL
VIN
ON_OFF
VON_OFF
ROV1
REF UV
+
ROV2
Hiccup Mode
150°C OTP
VCC UV
HB_OFF
UVLO < 1.25 V
UVLO < 1.25 V
AGND
图7-21. ON/OFF Pin Configured as OVP Pin
The OVP hysteresis is accomplished with the IOVL current source. When the ON_OFF pin voltage exceeds
VON_OFF, the IOVL current source is activated which quickly raises the voltage at the pin. The half-bridge
converter is turned off and the SS and SSSR capacitors are fully discharged. When the ON_OFF pin voltage
falls below VON_OFF, the current source is deactivated causing the voltage at the pin to quickly fall followed by a
new soft-start sequence. In addition to the OVP fault, hiccup mode and internal 150-°C thermal shutdown faults
will also cause the half-bridge converter to turn off. Once the faults are cleared, a new soft-start sequence
automatically begins. Because the hiccup mode or 150-°C thermal shutdown fault also activates the current
source, it is important to make sure that the ON_OFF pin voltage doesn't rise above VON_OFF when the input
voltage is high, which otherwise would lead to latch operation. Avoid this scenario by selecting a proper voltage
divider.
Use 方程式29 and 方程式30 to select the voltage divider for the OVP configuration.
VHYS(OVP)
ROV1
=
IOVL
(29)
where
• VHYS(OVP) is the OVP hysteresis
VON_ OFF ìROV1
ROV2
=
VIN(OFF) - VON_ OFF
(30)
where
• VIN(OFF) is the OVP rising threshold
7.3.18 Auxiliary Constant On-Time Control
图 7-22 shows a block diagram of the constant on-time (COT) controlled fly-buck converter. The LM5036 device
integrates an N-channel high-side MOSFET and associated high-voltage gate driver. The gate driver circuit
works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A 0.01-µF ceramic
capacitor connected between the BST_AUX pin and SW_AUX pin provides the voltage to the driver during the
on-time. During each off-time, the SW_AUX pin is at approximately 0-V, and the bootstrap capacitor charges
from VCC through the internal diode. The minimum off-timer ensures a minimum time in each cycle to recharge
the bootstrap capacitor. The LM5036 device also provides an internal N-channel SR MOSFET and associated
driver. This MOSFET provides a path for the inductor current to flow when the high-side MOSFET is turned off.
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The integrated auxiliary supply employs constant on-time (COT) hysteretic control which provides excellent
transient response and ease of use. The control principle is based on a comparator and a one-shot on-timer,
with the output voltage feedback (FB_AUX) compared to an internal reference. If the feedback voltage is below
the reference the internal buck switch is switched on for the one-shot timer period, which is a function of the
input voltage and the on-time resistor (RON). Following the on-time the switch remains off until the FB_AUX
voltage falls below the reference, and the forced minimum off-time has expired. When the feedback voltage falls
below the reference and the minimum off-time one-shot period expires, the high-side buck switch is then turned
on for another on-time one-shot period. This will continue until regulation is achieved.
VCC
VCC
BST_AUX
VIN
PWMA
SW_AUX
VAUX2
Constant
On-Time
(COT)
VCC
VAUX1
PWMB
Control
Logic
FB_AUX
+
REF_AUX
图7-22. COT Controlled Fly-Buck Auxiliary Supply Circuitry
In a fly-buck converter, the low-side SR MOSFET is on when the high-side switch is off. The inductor current
ramps up when the high-side switch is on and ramps down when the low-side switch is on.
The switching frequency remains relatively constant with load and line variations. Use 方程式 31 to calculate the
switching frequency of the auxiliary supply.
VAUX1
9 × 10F11 × RON
fSW_AUX
=
(31)
where
• VAUX1 is the primary output voltage of the auxiliary supply.
Two external resistor values set the value of VAUX1. This regulation of the output voltage depends on ripple
voltage at the feedback input, requiring a minimum amount of ESR for the output capacitor (CAUX1). A minimum
of 25-mV of ripple voltage at the feedback pin is required for stable operation of the auxiliary supply. The 节
7.3.22 section describes auxiliary ripple circuit configuration.
7.3.19 Auxiliary On-Time Generator
The on-time for the auxiliary supply is determined by the resistor RON, and is inversely proportional to the input
voltage, resulting in a nearly constant switching frequency as the input voltage is varied over its entire range. 图
7-23 shows the block diagram for the on-time generator.
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VIN
AUX RAMP
t
ON
AUX RAMP
RESET
RON
PWMA
RON
PWMB
图7-23. On-Time Generator
Time
图7-24. Constant On-Time Control Waveform
A current source, which is a function of the input voltage and the RON resistor value, charges a capacitor. The
capacitor voltage ramps up linearly and gets reset when it reaches the threshold.
Use 方程式32 to calculate the on time tON of the high-side switch.
9 × 10F11 × RON
tON
=
V
IN
(32)
7.3.20 Auxiliary Supply Current Limiting
The LM5036 controller contains an intelligent current limit off-timer for the auxiliary supply. If the current in the
high-side switch exceeds IAUX(LIM) (200-mA typical), both the high-side MOSFET and the low-side SR are
immediately turned off, and a non-resetable off-timer is initiated. The length of the off-time is a function of the
FB_AUX pin voltage and the input voltage VIN. As an example, when VFB_AUX = 0 V and VIN = 48 V, a maximum
off-time is set to 16 µs. This condition occurs when the output is shorted, and during the initial phase of start-up.
This amount of time ensures safe short-circuit operation up to the maximum input voltage of 100 V.
In cases of overload where the FB_AUX voltage is above zero volts (not a short circuit) the current limit off-time
is reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time,
and start-up time. The current limit off-time is calculated from 方程式33.
(0.07 × V )
IN
tOFF (ILIM )
=
Js
VFB_AUX + 0.2 V
(33)
Because the current limit protection feature of the auxiliary supply is peak limited, the maximum average output
is less than the peak.
To prevent excessive reverse current during the off-time of the current limit, the auxiliary supply operates in
asynchronous (ASYNC) mode where the low-side SR is turned off during current limit operation. The body diode
of the internal low-side MOSFET (QB) incurs significant power loss during asynchronous operation. TI
recommends adding an external schottky diode (DFW) between the PGND and SW_AUX pins to ensure robust
and efficient current limit operation. This schottky diode is particularly important when operating from high input
voltage. Use an external schottky diode (DFW) that is rated to carry the maximum auxiliary current and block the
maximum input voltage (VIN(max)).
For high density designs it is desirable to use an auxiliary transformer with low magnetising inductance and
saturation current. The peak magnetising current flowing in the auxiliary transformer can exceed IAUX(LIM) due to
delays in the peak current detection and comparator circuit. The actual peak magnetising current reached is a
function of the maximum slope of the transformer magnetising current. This behavior depends upon both
maximum input voltage VIN(max) and magnetising inductance value. The method outlined below allows designers
to estimate the peak magnetising current that will flow in the Aux transformer (ILPk).
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As illustrated in 图7-25, it is convenient to model the internal current sense circuit as a simple RC time constant,
τAuxSns (41-ns typical), that delays the sensed current signal presented to the OCP comparator input. There is a
further delay tAUX(LIM) (116-ns typical), after the comparator input reaches its trip threshold before the OCPb fault
flag is set. The controller applies this extended off time, tOFF(ILIM), only if the OCPb fault flag is set before the
COT (tON) period ends. 方程式 34 is an expression for the sensed and delayed magnetising current inductor
signal applied to the non-inverting input of the OCP comparator.
V
IN
QA
t
AuxSns
PWMA
I
I
(t)
AuxSns
LPk
I (t)
QA
t
AUX(LIM)
I
(t)
LAux
+
OCPb
I
I (t)
QA
AUX(LIM)
œ
I
V
AUX2
LInit
SW_AUX
I
AUX(LIM)
I
(t)
AuxSns
QB
t
PWMB
AUX(LIM)
D
FW
t
ON
V
PGND
AUX1
PGND
PGND
图7-25. Aux Current Limit Circuit Model
-t
tAuxSns
≈
∆
’
÷
IAuxSns(t) = I
-mAux ì tAuxSns ì 1- e
+ mAux ì t
(
)
LInit
∆
∆
÷
÷
«
◊
(34)
where
• mAux is the slope of Aux transformer magnetising inductor current during QA on period
• τAuxSns is the time constant of the internal current sensing circuit feeding the OCP comparator
Maximum peak current occurs when the magnetising inductor current slope has its highest value. This peak
occurs at start-up, or when a short circuit is applied across the VAUX1 output, while operating from maximum
input voltage (VIN(max)). The maximum inductor current slope is given by 方程式35.
V
IN(max)
mAux
=
LAUX
(35)
where
• LAUX is the magnetising inductance of the Aux transformer
For a use case where the inductor current slope is fixed at its maximum value (mAux), the highest peak current
occurs when the inductor current at the start of the pulse (ILInit) is just high enough to trip the OCPb flag before
the COT period (tON) expires. After this trip occurrs, the controller applies the extended OFF period (tOFF(ILIM)) to
reduce the inductor current for subsequent pulses. This condition is given in 方程式 36 and is shown graphically
in 图7-25
IAuxSns
t
ON - tAUX(LIM) = I
AUX(LIM)
(36)
where
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• tAUX(LIM) is the time delay between comparator input threshold being achieved and the OCPb flag set
Combining 方程式 34 and 方程式 36 determines the initial inductor current for a pulse containing the highest
peak current 方程式37.
IAUX(LIM) - mAux ì tON - tAUX(LIM)
(
)
ILInit
=
+ mAux ì tAuxSns
- tON -tAUX(LIM)
(
)
tAuxSns
1- e
(37)
(38)
方程式38 uses the COT period in 方程式37 for the maximum input voltage.
KON ìRON
tON
=
V
IN(max)
where
• KON (9 × 10–11 typical) is an internal constant that defines the COT period for a given VIN and RON
Having calculated ILInit the estimated peak inductor current is given by 方程式39.
ILPk = ILInit + mAux ì tON
(39)
Use this method to ensure that the operation does not exceed the Aux transformer saturation current under
transient or fault conditions. This method assumes fixed transformer magnetising inductance. The method
provides only a reasonable accuracy if the transformer magnetising inductance has not fallen significantly at the
predicted peak current.
To avoid excessive peak magnetising current during transient or fault events, ensure that the COT period (tON) is
longer than the response time of the peak current protection circuit. 方程式 40 expresses it as a minimum
required value for RON
.
t
AuxSns + tAUX(LIM) ì1.2
(
)
RON
í
ì V
= VIN(max) ì 2.09 kW
IN(max)
KON
(40)
7.3.21 Auxiliary Primary Output Capacitor Ripple
方程式 41 describes the output ripple voltage amplitude for a buck converter. This equation may be used if there
is no secondary winding or if the current supplied by VAUX2 is small compared with that supplied by VAUX1
(IAUX1>>IAUX2). 方程式 41 neglects capacitor ESR and therefore calculates only the capacitive component of
output voltage ripple.
DIL(AUX)
DVAUX1Cap
=
2ì fSW _ AUX ìCAUX1
(41)
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IL_PRI/I
L_SEC
I
+ N2/N1 × I
AUX2
AUX1
(1)
(2)
0 A
I
I
L_PRI
L_SEC
Time
图7-26. Auxiliary Transformer Current Waveform for CAUX1 Ripple Calculation
图 7-26 shows the flybuck primary and secondary winding current waveforms IL_PRI and IL_SEC. The reflected
secondary winding current adds to the primary winding current during the off-time of the high-side switch. Due to
this increased current, the output voltage ripple is not the same as in a conventional buck converter. In this case
the average current flowing into CAUX1 during the tON period is the reflected secondary current. Hence 方程式 42
can be used to calculate ΔVAUX1Cap, the voltage ripple across the primary side capacitor, for the more typical
case when the secondary current cannot be neglected. Notice that 方程式 42 neglects capacitor ESR and
therefore calculates only the capacitive component of ripple voltage amplitude.
N2
IAUX2
ì
ì tON(max)
N1
2ìCAUX1
DVAUX1Cap
=
(42)
7.3.22 Auxiliary Ripple Configuration and Control
The voltage ripple across the output capacitor CAUX1 is made up of two components:
• Resistive ripple appears across the equivalent series resistance (ESR) of the output capacitor. This
component of ripple is in phase with the inductor current and is 90° delayed compared with the applied PWM
signal.
• Capacitive ripple appears across the ideal capacitor. This component of ripple is 90° delayed compared with
the inductor current ripple and 180° delayed compared with the applied PWM signal.
With COT control, the on-time of the high-side FET is terminated by an on-timer, and the off-time is terminated
when the feedback voltage VFB_AUX falls below the reference voltage (VAUX-ON). For a buck topology this type of
hysteretic control provides stable operation if these two conditions are met:
• Output voltage ripple is dominated by the resistive ESR component. The resistive ripple amplitude must be
approximately five times the capacitive ripple amplitude to guarantee stable operation.
• Output voltage ripple amplitude present at the FB_AUX pin must be greater than noise coupled onto this pin
from other sources. For an output voltage ripple amplitude of 25 mV at the FB_AUX pin ensures that other
sources of noise coupled to the pin can be assumed small
Aux transformer magnetising inductor ripple current amplitude is expressed by 方程式43.
≈
’
≈
’
÷
◊
VAUX1
KON ìRON
2ìLAUX
VAUX1
1
DIL(AUX)
=
ì
- tON
=
ì 1-
∆
∆
«
÷
÷
◊
∆
2ìLAUX
fSW _ AUX
V
IN
«
(43)
For a buck converter the capacitive component of output voltage ripple amplitude is expressed by 方程式 41.
The resistive component of output ripple voltage amplitude is expressed by 方程式44.
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DVAUX1Res = DIL(AUX) ìREsr
(44)
Our condition for stable operation requires that 方程式45 and 方程式46 are both satisfied.
DVAUX1Res í 5 ì DVAUX1Cap
(45)
(46)
DVAUX1Res í 25 - mV
The method outlined above allows us to calculate the resistance (REsr) that must be present in series with the
output capacitor (CAUX1) to provide stable operation of a buck converter. This simple method has disadvantages
of high output voltage ripple amplitude and high dissipation in the series resistor REsr. The method is also not
ideal for a flybuck topology, especially if most of the load current is drawn from the secondary winding. In this
case much of the magnetising inductor current flows into the secondary output capacitor (CAUX2) and not the
primary output capacitor (CAUX1) during the low-side FET conduction period (tOFF). The circuit of 图 7-27
provides a better solution that is well suited to the flybuck topology. A series branch Rr –Cr is connected across
LAUX. The controller applies the same PWM voltage across this series branch as appears across LAUX
.
Assuming most of the PWM voltage is dropped across Rr, the voltage across Cr has the almost the same shape
and phase as the inductor current. The voltage ripple across Cr can be used to substitute the voltage across
RESR and thus provide stable operation without the need for high output ripple and dissipation. By coupling this
capacitor voltage signal directly to the FB_AUX pin we can achieve the same result as a large ESR resistor, but
without the penalty of dissipation and high output voltage ripple amplitude. The method is suitable for a flybuck
topology, since the down-slope of the magnetising current is synthesised, across Cr, and therefore available on
the primary side to couple onto the FB_AUX pin.
LAUX
SW_AUX
VAUX1
Rr
Cr
RFB1
Cac
CAUX1
FB_AUX
RFB2
PGND PGND
PGND
图7-27. Minimum Ripple Configuration
The impedance of the capacitor generating the synthesised inductor current ripple signal, at the Aux switching
frequency (fSW_AUX), must be low compared with the impedance of the RFBx divider network.
RFB1 + RFB2
2ì p ì fSW _ AUX RFB1 ìRFB2
3
Cr >
ì
(47)
The synthesised inductor ripple, generated across Cr, is added to the ripple across the output capacitor (CAUX1).
The resultant signal is coupled to the FB_AUX pin via capacitor Cac. The value of series resistor Rr is chosen to
ensure the synthesised resistive ripple amplitude satisfies 方程式45 giving 方程式48.
≈
∆
«
’
KON ìRON
10 ìCr ì DVAUX1Cap
VAUX1
Rr Ç
ì 1-
∆
÷
÷
◊
V
IN(min)
(48)
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Capacitor Cac couples the ripple signal directly onto the FB_AUX pin. Ensure that the value of this capacitor is at
least five times greater than the value of Cr. This ratio ensures minimum attenuation and phase shift of the
coupled ripple signal.
Cac í 5 ìCr
(49)
7.3.23 Asynchronous Mode Operation of Auxiliary Supply
In LM5036 device, there are two conditions where the auxiliary supply will enter asynchronous (ASYNC) mode
operation where the low-side SR is turned off and only its body diode is allowed to conduct. The first condition is
when the half-bridge converter is turned off (Refer to the 节 7.4 section). This helps to reduce the power
consumption of the auxiliary supply at light loads. As described in the 节 7.3.20 section, the auxiliary supply will
also be forced to operate at ASYNC mode during current limit operation to prevent excessive reverse current.
7.4 Device Functional Modes
The functional modes of the device are summarized in the following table. Faults include hiccup mode OCP,
OVP, and 150°C OTP.
表7-1. Device Functional Modes
VCC AND REF
REGULATORS
AUXILIARY
SUPPLY
HALF-BRIDGE
CONVERTER
CRITERIA
UVLO < VSD
OFF
ON
OFF
OFF
OFF
OFF
( VSD < UVLO < VUVLO) & (VIN
<
VAUX_UVLO
( VSD < UVLO < VUVLO) & (VCC & REF >
UV) & (VIN > VAUX_UVLO
)
ON at ASYNC
Mode
ON
ON
ON
ON
OFF
ON
)
(UVLO > VUVLO) & (VIN > VAUX_UVLO) &
(VCC & REF > UV) & No Faults
ON at SYNC Mode
(UVLO > VUVLO) & (VIN > VAUX_UVLO) &
(VCC & REF > UV) & Any Faults
ON at ASYNC
Mode
OFF
NA
(VCC & REF > UV) & (VIN > VAUX_UVLO
& AUX Current Limit
)
ON at ASYNC
Mode
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LM5036 device is a highly integrated half-bridge PWM controller that contains all the features necessary for
implementing the half-bridge topology power converters using voltage-mode control with input voltage feed-
forward. The device targets isolated DC-DC converter applications with input voltage of up to 100 VDC
.
8.2 Typical Application
The following schematic shows an example of an isolated half-bridge DC-DC converter controlled by LM5036
device. The operating input voltage range is 36-V to 75-V, and the output voltage is 12-V. The maximum load
current is 8-A and the output current limit is configured to be 10-A.
D10
TP4
VIN
TP1
L1
R39
VIN
VIN_PIN
Prebias source
1.21k
100V
J1
470nH
J7
Q1
6.8µF
6.8µF
R36
3.3
RM7/ILP
4:3:3
T1
1
HSG
R4
100k
C5
C6
3
5
6
TxOut
SW
131-5031-00
1
TP5
C2
220pF
C1
2.2µF
C3
2.2µF
C4
2.2µF
L2
C42
100µF
SGND
TxOut
TP9
J3
4.7µH
2
C14
470µF
C11
47µF
C12
47µF
C13
47µF
C15
0.1µF
12V/10A
R5
100k
Q2
R37
3.3
C7
C8
LSG
SGND
6.8µF
6.8µF
PGND
TP2
J2
TxOut
SGND
TP6
RCS
Q3
Q5
C9
470pF
Q4
Q6
C10
470pF
0.005
TP7
J5
PGND
R33
4.99
R38
4.99
R6
100
NT1
Add shunt on J5
TP8
Net-Tie
PGND
AGND
SGND
SGND
SGND
SGND
SGND
SGND
TP3
U1
VIN
D3
R13
511
RC
VIN_PIN
30V
D7
13
15
14
BST_AUX
SW_AUX
R7
25.5k
C19
100V
C16
0.1µF
C33
0.01µF
L3
SW_AUX
C34
16
28
1
2
4
PGND
UVLO
C17
1500pF
VIN
220pF
R14
150k
R24
46.4k
R21
2.2k
C31
1µF
C18
R30
100k
R31
D11
100V
PGND
D9
D4
SGND
VAUX1
VAUX1
R12
11.8k
17
12
3
VCC
C44
1000pF
C32
2.2µF
6800pF
150µH
VAUX2
1000pF
45V
100V
4.02k
R22
R16
240
24
R32
105k
C35
RAMP
FB_AUX
D2
7.50k
0.1µF
D8
C36
1µF
4.7V
VX
PGND
PGND
100V
AGND
C22
21
22
VAUX2
BST
D6
R23
1.00k
VX
C25
0.01µF
C43 0.068µF
VIN
Add shunt on J4
J4
1
C45
560pF
RES
HSG
R8
6.65k
HSG
SGND
30V
C46
0.1µF
0.01µF
U4
4
3
R28 24.9k
5
6
7
8
R27
RT
SGND
1
V+
V-
PGND
R10
5.11k
R9
10.0k
40.2k
R29
23
RON
ON/OFF
SS
SW
SW
LM8261M5
220k
U5
NC
LM4040BIM3-2.5/NOPB
AGND
Add shunt on J6
U2
VCCI
REF
C21
0.47µF
C20
1000pF
D1
C39 0.047µF
18
20
4
7
13
12
11
45V
LSG
SR1
VDDA
LSG
SGND
0.018uF
VCCI
C40
C38
R11
R25
R26
715
9
SSSR
VOUTA
VSSA
C28
1µF
J6
R34
6.81k
49.9k
2
5
1000pF
INA
20.0k
10
11
RD1
RD2
SGND
R35 40.2k
19
4
SR2
REF
DISABLE
VIN
SGND
REF
R2
25
26
27
C29 C30
0.1µF 0.1µF
AGND
CS_POS
CS_NEG
CS_SET
6
3
1
10
9
1.96M
DT
VDDB
VOUTB
VSSB
Q7B
3
COMP
R1 576
VCS+
INB
GND
C27
1µF
0.1µF
C41
MMDT3946-7-F
R3
RLIM
56.2k
A1
A2
A3
A4
8
C26
R20
10k
A1
A2
A3
A4
576
29
2
EP
47pF
R18
1.15k
UCC21225ANPL
PGND
SGND
R19
10k
VAUX2
AGND
R17
10k
PGND
PGND
AGND
LM5036RJBR
D5
9.1V
C37
AGND
2200pF
Q7A
MMDT3946-7-F
PGND
SGND
C24
C23
0.1µF
0.01µF
U3
4
3
1
2
R15
1.82k
SGND
PS2811-1-M-A
图8-1. Evaluation Board Schematic
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8.2.1 Design Requirements
PARAMETER
VALUE
36 V to 75 V
12 V
VIN
Input voltage
VO
Output voltage
IO (max)
ILIM
η
Maximum load current
Output current limit
Peak efficiency
8 A
10 A
94.4 %
93.5 %
11.9 V
8.5 V
Efficiency at VIN = 48 V and IO = 8 A
Off-state auxiliary output voltage
On-state auxiliary output voltage
Load regulation
VAUX1-OFF
VAUX1-ON
0.2%
Line regulation
0.1%
Line UVLO rising threshold
Line UVLO falling threshold
Line OVP rising threshold
Line OVP falling threshold
Latch threshold
34 V
32 V
80 V
78 V
80 V
IAUX(max)
Maximum load current for auxiliary supply
100 mA
8.2.2 Detailed Design Procedure
The Excel Calculator Tool can be used to assist with selecting both power stage and controller setup
components.
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5036 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Input Transient Protection
The voltage applied to the VIN pin of LM5036 device serves as the input voltage for the internal VCC startup
regulator and auxiliary supply. In typical applications, the VIN pin voltage is the same as the input voltage for the
main half-bridge converter. The recommended range of the VIN pin voltage is 18-V to 100-V. 图 8-2 shows the
recommended filter to suppress transients that may occur at the input supply. This suppression is particularly
important when the input voltage rises to a level near the maximum recommended operating rating (100-V) of
the LM5036 device.
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VIN
50 Ω
VIN
0.1 mF
PGND
图8-2. Input Transient Protection
8.2.2.3 Level-Shift Detection Circuit
An example implementation of the VAUX2 level-shift detection circuit is shown in 图 8-3. The zener voltage must
be between the off-state and on-state level of VAUX2. When VAUX2 is above the zener voltage, both Q1A and
Q1B are turned on and therefore the reference output voltage VREFSec is clamped to ground. Once VAUX2 falls
below the zener voltage, both Q1A and Q1B are turned off, and the reference is released.
Designers who wish to benefit from the fully regulated pre-biased startup feature of LM5036 must use separate
voltage reference and error amplifier devices. Popular combined error amplifier and voltage reference devices,
such as TL431, can be used only when the fully regulated pre-biased startup feature is not required.
Assistance with half-bridge voltage control loop design may be obtained using the Power Stage Designer™ tool.
V
REFSec
Q1B
MMDT3946-7-F
V
AUX2
10 kꢀ
10 kꢀ
Q1A
MMDT3946-7-F
0.01 …F
0.1 …F
GND
图8-3. Secondary Auxiliary Voltage Level-Shift Detection Circuit
8.2.2.4 Applications with VIN > 100-V
For applications where the input voltage exceeds 100-V, all of the 100V-rated internal circuit blocks, including
VCC start-up regulator, auxiliary supply and half-bridge gate drivers, need to be bypassed, or powered from a
reduced voltage. In this case, VIN pin can be powered from an external start-up regulator, as shown in 图 8-4. If
pre-biased start-up is required the integrated flybuck aux circuit should be used from the reduced VIN pin voltage
to supply the secondary control circuit. If pre-biased start-up is not required, the bias supply VAUX1, can be
derived from an external auxiliary supply. An external gate driver with higher voltage rating should be used to
drive the half bridge.
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VIN
VAUX1
VCC
VIN
PGND
PGND
图8-4. External Start-Up Regulator
8.2.2.5 Applications without Pre-Biased Start-Up Requirement
For applications where the pre-biased startup is not required, the level-shift detection circuit described in the 节
7.3.9 section is not necessary. Without the level-shift detection circuit, the reference voltage on the secondary
side would be released as soon as the secondary bias is established. The external VCC bias supply can be
derived from the integrated auxiliary supply or an auxiliary winding of the main transformer.
8.2.2.6 UVLO Voltage Divider Selection
As described in 节 7.3.2 , two external resistors can be used to program the minimum operating voltage for the
power converter, as shown 图 8-5. When the UVLO pin voltage falls below VUVLO (1.25-V typical), an internal
current sink IUVLO (20-µA typical) is enabled to lower the voltage at the UVLO pin, thus providing threshold
hysteresis. Resistance values for RUV1 and RUV2 can be determined from 方程式50 and 方程式51.
HHYS(UVLO)
RUV1
=
IUVLO
(50)
where
• VHYS(UVLO) is the UVLO hysteresis
VUVLO ìRUV1
IN(on) - VUVLO -IUVLO ìRUV1
RUV2
=
V
(51)
where
• VIN(on) is the input voltage above which the main converter will start to operate.
图 8-6 illustrates one way to configure a latch reset operation by pulling the UVLO pin voltage below VUVLO. The
diode voltage drop must be between 0.35 V and 1.25 V. The controller can be forced to enter shutdown mode by
pulling UVLO pin to GND.
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VIN
RUV1
VIN
VUVLO
+
UVLO
RUV1
VUVLO
UVLO
+
IUVLO
IUVLO
RUV2
RUV2
LATCH
RESET
AGND
VSD
+
图8-5. UVLO Configuration
图8-6. Latch Reset
8.2.2.7 Over Voltage, Latch (ON_OFF Pin) Voltage Divider Selection
As described in 节 7.3.17, the ON_OFF pin can be configured as a latch pin or an OVP pin. 图 7-20 shows the
latch configuration. The ON_OFF pin is latched when the pin voltage reaches IOVL × RL when any of the internal
faults is detected. The latch diode is reverse-biased during latch operation. Select the latch resistor RL value
such that IOVL × RL > VON_OFF. This design example uses an RL value of 49.9 kΩ. If the latch threshold is 80 V,
use an ROV1 value of 40 kΩ, and use an ROV2 value of 710 Ω.
If the ON_OFF pin is configured as an OVP pin, two resistors can be used to program the maximum operating
input voltage for the half-bridge converter, as illustrated in 图 7-21. When the ON_OFF pin voltage rises above
the VON_OFF threshold, an internal current source IOVL is enabled to raise the ON_OFF pin voltage, thus
providing the threshold hysteresis. Use 方程式 29 and 方程式 30 to determine resistance values for ROV1 and
ROV2. If the LM5036 controller is to be disabled when VIN rises above 80 V and enabled when it falls below 78 V.
Use an ROV1 value of 40-kΩ, and an ROV2 value of 635-Ω. The ON_OFF pin can also be used for external
thermal protection with a thermistor.
8.2.2.8 SS Capacitor
The soft-start delay tD(SS) , which is the time it takes for the soft-start capacitor to rise from 0 V to VSSSecEn (2.06-
V typical), can be programmed with the SS capacitor value according to 方程式52
ISS ì tD(SS)
CSS
=
VSSSecEn
(52)
where
• ISS (20-µA typical) is the current source of the soft-start pin
8.2.2.9 SSSR Capacitor
The SSSR capacitor value determines the rate at which the pulse width of the SRs of the half-bridge converter
increases. To achieve a monotonic start-up for the output voltage, the optimum SSSR capacitor value satisfies
the following two conditions:
• Ensure the SR soft-start sequence is completed before the controller reaches the regulation set-point of the
output voltage.
• With a lower control loop bandwidth, the primary-side duty cycle tends to increase at a slower rate. in order to
prevent excessive reverse current, reduce the ramp-up speed of the SSSR capacitor voltage accordingly.
A general rule is to maintain the control loop bandwidth of the half-bridge converter above 1 kHz. With a slow
control loop bandwidth, the output voltage needs to drop at least 25% from the regulation set-point during the
restart time period where the SS pin voltage rises from 0 V to VSSSecEn (2.06-V typical) and then the secondary-
side reference VREF rises to 75% of regulation set-point. To satisfy the first condition above, maintain the rise
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time of the SSSR capacitor voltage to less than 25% of the rise time of the output voltage, as described in 方程
式53.
ISSSR × 25% × tRAMP
CSSSR
<
5 V
(53)
where
• ISSSR (20-µA typical) is the current source of the SSSR pin. tRAMP is the ramp-up time of the output voltage.
Use the SSSR capacitor value calculated from 方程式 53 as a starting point. Fine-tuning may be needed based
on the actual control loop design and other specific design requirements such as pre-bias conditions and loading
profile.
8.2.2.10 Half-Bridge Power Stage Design
For a PWM operating frequency of 400kHz applied to the output inductor the oscillator frequency of LM5036
must also be set to 400kHz. The value of resistor RT is obtained using 方程式54.
1
RT
=
= 25 - kW
fOSC ì1ì10-10
(54)
(55)
Maximum effective duty cycle that can be applied to the output inductor is 方程式55.
DMAX = 1- tCLK ì fOSC = 0.974
Maximum transformer turns ratio that will deliver the required output voltage from minimum input voltage is given
by 方程式56.
DMAX ì V
IN(min)
NPS(max)
=
= 1.46
2ì VO
(56)
For our example design we will opt for a planar transformer with 4 primary turns and 3 secondary turns. The
turns are located in an un-gapped RM7/ILP ferrite core made of 3C95 material. This core has an inductance
factor AL = 4.4-µH/turn2. Hence the actual turns ratio (NPS) and magnetising inductance (LMag) are given by 方程
式57 and 方程式58.
NP
NS
4
3
NPS
=
=
(57)
(58)
LMag = NP2 ì AL = 70.4 - mH
Maximum inductor current ripple will occur at maximum input voltage. The output inductor value LO will be
selected to limit inductor current ripple amplitude to 20-% of the maximum output current ILIM
V ì 1-D
(
)
O
MIN
LO
=
= 4.3 - mH
20%ì 2ìILIM ì fOSC
(59)
Hence a catalog part with an inductance of 4.7-µH, capable of carrying the full output current, and with a
saturation current of more that 120-% of ILIM, is selected.
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LO = 4.7 - mH
(60)
8.2.2.11 Current Limit
节 7.3.11 describes the CBC current limiting functionality in detail. 图 8-7 illustrates the current limiting block
diagram of the LM5036 controller. These are the five resistors associated with the current limiting function of the
half-bridge converter:
• RCS
• R3
• R2
• RLIM
• R1
Because R3 is equal to the equivalent resistance of R1 and R2 as given by 方程式 13, there are four unknown
resistor values to be determined.
VIN
IPRI
R2
ISLOPE
K10a
R1
CS_POS
+
Amp
CF
RCS
VCS
1/K10b
R3
K2a
+
CBC
CS_NEG
CS_SET
POS_OCP
NEG_OCP
PGND
ICS_SET
RLIM
1/K2b
NEG
+
+
AGND
VLIM
œ
AGND
图8-7. Current Limiting Block
The value of current sense resistor RCS is determined based on the maximum power consumption requirement.
Typically, the current sense resistor should consume less than 0.5% of the input power of the converter at the
worst case scenario. The sense resistor conducts every alternate current pulse flowing in the primary winding.
The power dissipated in the sense resistor is determined by 方程式61.
2
IPri _ RMS
PCS
=
ìRCS
2
(61)
The RMS current flowing in the primary winding may be calculated using 方程式62.
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2
≈
’
÷
≈
∆
«
’
÷
◊
IO
DIPri
IO
1
3
∆
IPri _RMS
Where :
=
ì D ì 1+
ì
NPS
∆
«
÷
◊
≈
∆
’
÷
DILO
NPS
VO
2ìLO ìNPS
V
IN
1- D
D
DIPri
=
+ DILMag
=
ì
+
ì
f
4 ìLMag fOSC
« OSC ◊
(62)
Maximum loss in the current sense resistor will occur while maximum output current (ILIM) is delivered from
minimum input voltage (VIN(min)). Evaluating 方程式62 gives 方程式63.
IPri _RMS = 7.07A
(63)
To achieve our target of dissipating less than 0.5% of maximum output power the current sense resistor must
satisfy 方程式64.
2
RCS < 0.5%ì VO ìILIM
ì
= 0.024 W
2
IPri _RMS
(64)
(65)
In our example design the current sense resistor value selected is given in 方程式65.
RCS = 5 mW
HSG
t
t
t
OFF
ON
OFF
LSG
V
IN
V
SW
V /2
IN
t
I
ON
/N
LO ps
I /N
O
ps
4I
4I /N
LO PS
Pri
4I /N
LO PS
4I
Pri
I
LMag
0
4I
LMag
4I
LMag
Ipri
图8-8. Main Converter Operating Waveforms
The resistor R1 is used to set the slope compensation magnitude. In LM5036 device, the slope of the
compensation ramp is given by 方程式 66. To eliminate sub-harmonic oscillation, set mC to at least one-half the
down-slope of output inductor current transformed to the primary side across the current sense resistor, as given
by 方程式 67 and 方程式 68. To damp the sub-harmonic oscillation after one cycle, mC must be set equal to one
times the down-slope of the output inductor current. This configuration is known as deadbeat control. In LM5036
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controller, the slope compensation signal is a saw-tooth current waveform of magnitude ISLOPE at the oscillator
frequency (twice the switching frequency).
mC = ISLOPE ì fOSC ìR1
where
(66)
• mC is the slope of the compensation ramp
• ISLOPE is the amplitude of the saw-tooth current signal used for slope compensation
VO
1
mV
mL =
ì
ìRCS = 9.57
LO NPS
ms
(67)
where
• mL is the down-slope of the output inductor current transformed to the primary side
• NP is the number of turns for the primary winding of the main transformer
• NS is the number of turns for the secondary winding of the main transformer
• VO is the output voltage of the half-bridge converter
• LO is the output inductor value of the half-bridge converter
• RCS is the current sense resistor value
1
mC > × mL
(68)
Substituting 方程式66 and 方程式67 into 方程式68 gives an expression for the minimum value for resistor R1 to
avoid sub-harmonic oscillation.
VO
1
2
1
1
R1 >
ì
ì
ìRCS
ì
= 221- W
LO NPS
ISLOPE ì fOSC
(69)
Doubling this value ensures deadbeat control. For this example design, the value given in 方程式 70 are
selected
R1 = 576 W
(70)
Values have now been selected for both RCS and R1. Values for RLIM and R2 are yet to be determined. These
values define the peak current limit threshold and how this level varies with input voltage. 方程式 20, 方程式 21
and 方程式 25 define the relationship between peak primary current limit and maximum output current. For this
design example ignore IBiasOffset and VCSOffset, because these parameters have only a small effect on output
current limit. Setting these parameters to zero calculates 方程式71, 方程式72 and 方程式73.
»
ÿ
Ÿ
VO
VO ìNPS
2ìLMag ìfOSC Ÿ
IO V ,RLIM,R2 = N ì I
V ,RLIM,R2
-
ì 1-D -
(
)
(
)
(
)
…
…
IN
PS
PriCBC
IN
2ìLO ìfOSC ìNPS
⁄
(71)
(72)
≈
’
≈
’
VCS_ CBCTh(V ,RLIM,R2)
V
V
VO
1
2
IN
IN
IN
∆
∆
«
÷
÷
◊
IPriCBC V ,RLIM,R2
(
=
)
+ tCSLSG
ì
ì
+
-
∆
∆
«
÷
÷
◊
IN
2
RCS
LMag
LO ìNPS
LO ìNPS
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≈
’
÷
K
V
IN
VCS_ CBCTh(V ,RLIM,R ) = R ì CBC1 -ISLOPE ìD -
∆
IN
2
1
RLIM
R2 ◊
«
(73)
The output current limit varies with input voltage. This design example limits the output current to ILIM at the
extremes of input voltage giving 方程式 74 and 方程式 75. This value limits the spread of output current limit
across the range of input voltage.
IO
V
IN(min),RLIM,R2 = I
LIM
(74)
(75)
IO
VIN(max),RLIM,R2 = I
LIM
Solving 方程式74 and 方程式75 simultaneously yields values for resistors RLIM and R2.
1
R2 =
= 2.32 - MW
2
≈
’
≈
’
t
RCS
VO
RCS
1
1
1
CSLSG ì
ì
+
-
ì
-ISLOPE ì 2ì VO ìNPS
∆
∆
«
÷
÷
◊
∆
∆
«
÷
÷
◊
2
2
R1 ìNPS
LMag
V
IN(min) ì V
LO ìfOSC R1
LO ìNPS
IN(max)
(76)
(77)
KCBC1
RLIM
=
= 55.2 - kW
»
ÿ
Ÿ
≈
’
»
…
…
ÿ
Ÿ
V
V
V
IN(min)
RCS
R1
ILIM
VO
2ì VO ìNPS
VO ìNPS
2ìLMag ìfOSC
t
VO
2ì VO ìNPS
IN(min)
IN(min)
ì
+
ì 1-
+
-
CSLSG ì
+
-
+ISLOPE ì
+
…
…
∆
÷
÷
◊
2
∆
N
2ìLO ìNPS ìfOSC
V
NPS
2ìLMag
LO ìNPS Ÿ
V
R2
2ìLO ìNPS
Ÿ
⁄
PS
IN(min)
IN(min)
«
⁄
Having determined values for R1 and R2, the value of resistor R3 is fixed by 方程式13.
The selected values for R2 and RLIM are given in 方程式78. 图8-9 presents the measured output current limit vs
input voltage for the circuit presented in 图 8-1. 图 8-9 also presents the output current limit vs line for the same
circuit predicted by 方程式 71, 方程式 72 and 方程式 73. There is good agreement between measured and
predicted results.
R2 = 1.96 MW
RLIM = 56.2 kW
(78)
10.2
ILIM Calculated
ILIM Measured
10.1
10
9.9
9.8
9.7
9.6
9.5
9.4
9.3
36
41
46
51
56
61
Input Voltage (V)
66
71
76
D002
图8-9. Main Converter Measured vs Predicted Output Current Limit
If the magnitude of the leading-edge spike is excessive, add an additional filter capacitor CF to form an RC filter
with R1, to reduce the high-frequency noise spike. Both the leading-edge blanking (tCSBLK) and the RC filter help
to prevent false triggering of the CBC current limiting operation.
The circuit connected to the CS_POS pin may be approximated by the simplified circuit shown in 图8-10.
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I (t)
Pri
I (t) x R
Pri CS
R
1
V
CF
(t)
CS_POS
C
F
PGND
图8-10. CS_POS Filter Circuit Model and Waveform
The voltage across the current sense resistor during the conduction period of the low-side MOSFET is
represented by 方程式79.
IPri t ìR = I + mì t ìR
( )
(
)
CS
P0
CS
(79)
Where IP0 is the primary current at the start of the on period of the lower switch, and m is the slope of the
primary current during the on period.
IO
DILO
NPS
IP0
=
- DILMag
-
NPS
(80)
(81)
V
V
IN(max)
≈
∆
«
’
÷
◊
1
IN(max)
m =
- VO
ì
+
2ìNPS
LO ìNPS 2ìLMag
The voltage across capacitor CF for the circuit shown is expressed by 方程式82.
-t
CFìR1
»
…
…
…
ÿ
Ÿ
Ÿ
≈
∆
’
÷
VCF t = RCS ì
( )
I
P0 -mìCF ìR1 ì 1- e
+ mì t
(
)
∆
∆
÷
÷
Ÿ
⁄
«
◊
(82)
Let us assume that the on period of the lower switch is more than four times longer than the time constant made
up of CF and R1. In this case the exponential term of 方程式 82 tends to zero and the voltage across capacitor
CF at the end of the tON period may be expressed by 方程式83.
VCF
t
= R ì I - mìCF ìR1 + mì tON
(
)
[
]
ON
CS
P0
(83)
Comparing 方程式 79 and 方程式 83 shows that capacitor CF introduces an error in the sensed peak current
given by 方程式84.
»
…
…
IN(max) ÿ
V
V
≈
∆
«
’
÷
◊
1
IN(max)
- VO
ì
+
ìC ìR
Ÿ
F
1
2ìNPS
LO ìNPS 2ìLMag Ÿ
ILIM
VCS
t
- V
t
(
)
(
CF ON
)
mìCF ìR1
ILIM
ON
⁄
ErrCF =
=
=
ILIM
ìRCS
NPS
NPS
NPS
(84)
Hence, to ensure the error introduced by the filter capacitor is less than 2%, the value of capacitor CF should not
exceed the value given by 方程式85.
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0.02ìILIM
CF Ç
= 84 - pF
»
≈
IN(max) ÿ
V
V
’
÷
◊
1
IN(max)
- VO
ì
+
ìR ìN
Ÿ
1 PS
…
…
∆
«
2ìNPS
LO ìNPS 2ìLMag Ÿ
⁄
(85)
The Excel Calculator Tool can be used to facilitate the process of calculating all the external CBC component
values.
8.2.2.12 Auxiliary Transformer
A coupled inductor or a flyback-type transformer is required for this fly-buck topology auxiliary supply. Energy is
transferred from primary to secondary when the low-side SR MOSFET is conducting.
The transformer turns ratio is selected based on the ratio of the primary output voltage to the secondary output
voltage. In this design example, the two outputs are set to be equal and a 1:1 turns ratio transformer is selected,
i.e., N2/N1 = 1. The primary output voltage is normally selected based on the input voltage range such that the
duty cycle of the converter does not exceed 50% at the minimum input voltage. This condition is satisfied if
VAUX1 < VIN(min) / 2.
Use 方程式86 to calculate the maximum inductor current ripple amplitude ΔIL (AUX) that can be tolerated without
exceeding the peak current limit threshold IAUX(LIM) (200-mA typical) of the high-side switch,
≈
’
÷
N2
DIL(AUX) = IAUX(LIM) -IAUX1 -IAUX2
ì
∆
N1 ◊
«
(86)
where
• IAUX1 is the primary output current, and IAUX2 is the secondary output current of the auxiliary supply,
respectively.
In this design example, the maximum total output current IAUX(max) of the auxiliary supply referred to the primary
side is 100-mA, as given by 方程式87.
N2
IAUX (max ) = IAUX1 + IAUX2
×
= 0.1 A
N1
(87)
Therefore, ΔIL(AUX) = 0.1-A. Use 方程式88 to calculate the minimum inductor value for the auxiliary supply.
≈
∆
«
’
KON ìRON
2ì DIL(AUX)
VAUX1
LAUX
í
ì 1-
= 88 -mH
∆
÷
÷
◊
V
IN(max)
(88)
Select a higher value of 150-µH to ensure the high-side switch current doesn’t exceed the minimum peak
current limit threshold.
8.2.2.13 Auxiliary Feedback Resistors
The two feedback resistors are selected to set the primary output voltage VAUX1 of the auxiliary supply. The
internal reference for the off-state and on-state auxiliary output voltage levels are VAUX-OFF (1.4-V typical) and
VAUX-ON (1-V typical). The feedback resistors are calculated such that both of the off-state and on-state auxiliary
output voltage fall into the recommended operating range (8.5-V to 14-V). In this design example, the off-state
and on-state auxiliary output voltages are set to 11.9-V and 8.5-V, respectively. RFB2 is selected to be 1-kΩ and
RFB1 is calculated to be 7.5-kΩ according to 方程式 89. Note that it is the valley of the output voltage that is
regulated at the reference value. Therefore the average output voltage is greater than the reference value due to
the ripple injected to the feedback node.
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≈
’
÷
RFB1
VAUX1-ON = VAUX-ON ì 1+
∆
RFB2 ◊
«
(89)
8.2.2.14 RON Resistor
Use 方程式 31 to calculate the value of RON required to achieve the desired switching frequency for the auxiliary
supply. Make sure that the calculated RON value is greater than the minimum value required by 方程式 40. For
this design example where on-state VAUX1 is 8.5-V and target fSW_AUX is 500-kHz, the calculated value of RON is
189-kΩ. The minimum recommended value calculated using 方程式 40 is 209-kΩ. A standard value of 220-kΩ
is selected to satisfy this minimum RON requirement giving and actual switching frequency (fSW_AUX) of 430-kHz.
8.2.2.15 VIN Pin Capacitor
Place the required bypass capacitor close to the VIN pin of the LM5036 device. Ensure that the capacitance is
large enough to limit the ripple of the VIN pin voltage to a desired level. Use 方程式 90 to calculate the value of
CIN required to meet the ripple voltage ∆VIN requirement.
IAUX max
:
;
CIN
R
4 × fSW_AUX × ¿V
IN
(90)
Choosing a value of 0.5-V for ∆VIN yields a minimum CIN value of 0.12-µF. Select the standard value of 0.1-µF
for this design. Ensure that the voltage rating of the input capacitor is greater than the maximum input voltage
under all conditions.
8.2.2.16 Auxiliary Primary Output Capacitor
The output capacitor value (CAUX1), needed to achieve our target output ripple amplitude (ΔVAUX1Cap = 25-mV),
may be calculated using 方程式 94.Highest ripple voltage will be observed if all the Aux current is drawn from
VAUX2 (IAUX2=IAUX(max)). In this case a capacitor value of 1.1-µF is required to limit capacitive ripple voltage
amplitude to 25-mV. A standard 1-µF, 25-V capacitor is selected for this design.
8.2.2.17 Auxiliary Secondary Output Capacitor
A simplified waveform for the secondary winding current IL_SEC is shown in 图8-11.
I
L_SEC
I
AUX2
0 A
Time
图8-11. Auxiliary Transformer Secondary Winding Current Waveforms for CAUX2 Ripple Calculation
The secondary output current IAUX2 is sourced by CAUX2 during on-time of the high-side switch, tON. Ignoring the
current transition times in the secondary winding, the secondary output capacitor ripple voltage amplitude can be
calculated using 方程式91.
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IAUX2 ì tON(max)
DVAUX2Cap
=
2ìCAUX2
(91)
For a 1:1 auxiliary transformer turns ratio, the primary and secondary voltage ripple equations are identical.
Therefore, CAUX2 is chosen to be equal to CAUX1 (1 µF) to achieve comparable ripple voltages on the primary
and secondary outputs.
8.2.2.18 Auxiliary Feedback Ripple Circuit
The auxiliary feedback ripple circuit employed is presented in 图 7-27. Having selected appropriate values for
RON in 节 8.2.2.14 and RFBx in 节 8.2.2.13, the value of Cr required can be calculated using 方程式 47. For our
design we have opted to use a standard value Cr = 1-nF.
RFB1 + RFB2
2ì p ì fSW _ AUX RFB1 ìRFB2
3
Cr >
ì
= 1.3 - nF
(92)
Based on our target output ripple specification a value for the primary output capacitor (CAUX1 = 1-µF) was
chosen in 节 8.2.2.16. The primary output ripple voltage VAUX1Cap can be calculated using 方程式 94. Since the
value of VAUX1Cap is already greater than 25-mV there is no danger that we will fail to meet the requirement of 方
程式 46. Hence the value of Rr needed to ensure stable operation is calculated using 方程式 48. For our design
example a value of 46.4-kΩhas been selected.
≈
∆
«
’
KON ìRON
10 ìCr ì DVAUX1Cap
VAUX1
Rr Ç
ì 1-
= 55 - kW
∆
÷
÷
◊
V
IN(min)
(93)
The minimum value of Cac is determined using 方程式49. The precise value of this component is not very critical
and for our design example we selected a convenient value of Cac = 100-nF.
Cac í 5ìCr = 5 -nF
(94)
8.2.2.19 Auxiliary Secondary Diode
Use 方程式 95 to calculate the reverse voltage across secondary rectifier of the auxiliary supply when the high-
side switch is on.
N2
VD =
× V
IN(max )
N1
(95)
For a maximum input voltage of 75-V and the 1:1 turns ratio of this design, select a schottky diode with a rating
of 75-V or higher.
8.2.2.20 VCC Diode
A diode must be connected between the primary output VAUX1 and the VCC pin. When VAUX1 is more than one
diode voltage drop greater than the internal VCC voltage, the VCC bias current is supplied from VAUX1. This
results in reduced power losses in the internal VCC regulator, especially at high input voltage.
8.2.2.21 Opto-Coupler Interface
图 8-12 illustrates the opto-coupler interface for the main feedback control loop. The primary side of the opto-
coupler is biased with VREF voltage from LM5036 device. ROPTO should be selected such that with the minimum
error amplifier output, the comp current flowing into the COMP pin of the device is greater than IPWM-OS (800-µA
typical) which corresponds to zero duty cycle, as given by 方程式96.
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Vb
VREF
ROPTO
COMP
VO
Ve
+
VREFSec
SGND
图8-12. Opto-Coupler Interface
Vb - Vf - Ve
Ropto
ICOMP
=
ìCTR
(96)
where
• Vb is the bias supply for the error amplifier and opto-coupler on the secondary side
• Vf is the diode forward voltage drop of the opto-coupler LED
• Ve is the error amplifier output
• CTR is the current transfer ratio of the opto-coupler
• ICOMP is the comp current flowing into the COMP pin
• VREF (5-V typical) is the reference of LM5036 device
8.2.2.22 Full-Bridge Converter Applications
While LM5036 device is optimized for half-bridge applications, it can also be used for full-bridge applications.
External gate drivers are needed to support an additional pair of FETs in full-bridge configuration. In addition, a
DC-blocking capacitor is required to ensure voltage-second balance of the main transformer with the voltage-
mode control of LM5036 device. Only one phase current information is needed for current protection in the full-
bridge applications.
8.2.3 Application Curves
100%
95%
90%
85%
80%
75%
70%
65%
60%
VIN = 36 V
VIN = 48 V
VIN = 75 V
55%
50%
0
1
2
3
4
5
Load Current (A)
6
7
8
D001
fSW = 200-kHz
VO= 12 V
VIN = 48-V
IO = 8-A
VO = 12-V
图8-13. Efficiency
图8-14. Steady State Operation Waveform
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9 Power Supply Recommendations
The power converter controlled by LM5036 device can have considerable current level. Care should be taken
that components with the correct current rating are chosen. This includes magnetic components, power
MOSFETS and diodes, connectors and wire sizes. Input and output capacitors should have the correct ripple
current rating.
The recommended maximum input voltage for the VIN pin of LM5036 device is 100-V. The recommended
voltage for the VCC pin is between 8.5-V and 14-V. Both VCC pin and REF pin must be locally decoupled with a
ceramic capacitor. The recommended range of values is 0.47-µF to 10-µF for VCC pin, and 0.1-µF to 10-µF for
REF pin. To reduce the power consumption of the internal VCC regulator, an external bias supply can be
connected to VCC pin through a diode.
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10 Layout
10.1 Layout Guidelines
• The two ground planes (AGND and PGND) of LM5036 device should be tied together with a short and direct
connection to avoid jitter due to relative ground bounce. The connection point could be at the negative
terminal of the input power supply.
• The VIN, VCC, REF pin capacitors, and CS_NEG resistor should be tied to PGND plane. UVLO, ON_OFF,
RT, RON, RD1 and RD2 resistors, RAMP, RES, SS and SSSR capacitors, and the thermal pad should all be
tied to AGND plane.
• SW and SW_AUX are switching nodes which switch rapidly between VIN and GND every cycle which are
sources of high dv/dt noise. Therefore, large SW/SW_AUX node area should be avoided.
• The differential current sense signals at CS_POS and CS_NEG pins should be routed in parallel and close to
each other to minimize the common-mode noise.
• The area of the loop formed by the main feedback control signal traces (COMP and REF) should be
minimized in order to reduce the noise pick up. This can be accomplished by placing the COMP and REF
signal traces on top of each other in adjacent PCB layers. In addition, the main feedback control signal traces
should be routed away from the SW_AUX switching node to avoid high dv/dt noise coupling.
• The gate drive outputs (LSG and HSG) should have short and direct paths to the power MOSFETs to
minimize parasitic inductance in the gate driving loop.
• The VCC and REF decoupling capacitors should be placed close to their respective pins with short trace
inductance. Low ESR and ESL ceramic capacitors are recommended for the boot-strap, VCC and the REF
capacitors.
• A decoupling capacitor should be placed close to the IC, directly across VIN and PGND pins. The
connections to these two pins should be direct to minimize the loop area which carries switching currents.
• The boot-strap capacitors required for the high-side gate drivers of the half-bridge converter and auxiliary
supply should be located close to the IC and connected directly to the BST/BST_AUX and SW/SW_AUX
pins.
• The area of the switching loop of the power stage consisting of input capacitor, capacitive divider,
transformer, and the primary MOSFETs should be minimized.
10.2 Layout Example
See 图10-1 for an example layout that matches the schematic of 图8-1.
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图10-1. LM5036 PCB Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5036 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
11.2.1.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5036RJBR
LM5036RJBT
ACTIVE
ACTIVE
WQFN
WQFN
RJB
RJB
28
28
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
LM5036
LM5036
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5036RJBR
LM5036RJBT
WQFN
WQFN
RJB
RJB
28
28
3000
250
330.0
180.0
12.4
12.4
5.25
5.25
5.25
5.25
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5036RJBR
LM5036RJBT
WQFN
WQFN
RJB
RJB
28
28
3000
250
367.0
213.0
367.0
191.0
38.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RJB0028A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
0.65
0.45
5.1
4.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
3.4 0.1
2X 3
A3
SYMM
(0.2) TYP
4X ( 0.325)
A2
8
14
24X 0.5
7
15
(2.138) TYP
29
SYMM
2X
3
EXPOSED
THERMAL PAD
1
21
SEE TERMINAL
DETAIL
0.3
28X
0.2
A4
0.1
C A B
A1
28
22
0.05
0.65
0.45
PIN 1 ID
(OPTIONAL)
28X
(2.138) TYP
4223149/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RJB0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(2.138) TYP
22
28
4X ( 0.325)
28X (0.75)
28X (0.25)
1
21
(2.138)
TYP
24X (0.5)
29
SYMM
(4.65)
(1.45)
TYP
(R0.05)
TYP
7
15
(
0.2) TYP
VIA
8
14
(
3.4)
(4.65)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223149/A 08/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RJB0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(2.138) TYP
22
4X ( 1.47)
28
4X ( 0.325)
28X (0.75)
28X (0.25)
29
1
21
(2.138)
TYP
24X (0.5)
SYMM
(4.65)
(0.835)
TYP
(R0.05) TYP
15
7
METAL
TYP
8
14
(0.835) TYP
(4.65)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 29:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:18X
4223149/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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