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LM5045

SNVS699H –FEBRUARY 2011–REVISED JANUARY 2015

LM5045 Full-Bridge PWM Controller With Integrated MOSFET Drivers

1 Features

3 Description

The LM5045 PWM controller contains all of the

features necessary to implement full-bridge topology

power converters using either current mode or

voltage mode control. This device is intended to

operate on the primary side of an isolated DC-DC

converter with input voltage up to 100 V. This highly

integrated controller-driver provides dual 2-A high-

side and low-side gate drivers for the four external

bridge MOSFETs plus control signals for the

secondary-side synchronous rectifier MOSFETs.

External resistors program the leading and trailing

edge dead-time between the main and synchronous

rectifier control signals. Intelligent start-up of the

synchronous rectifiers allows monotonic turnon of the

power converter even with prebias load conditions.

Additional features include cycle-by-cycle current

limiting, hiccup mode restart, programmable soft-

start, synchronous rectifier soft-start, and a 2-MHz

capable oscillator with synchronization capability and

thermal shutdown.

1

•

Highest Integration Controller for Small Form

Factor, High-Density Power Converters

•

High-Voltage Start-Up Regulator

Intelligent Sync Rectifier Start-Up Allows Linear

Turnon Into Prebiased Loads

•

Synchronous Rectifiers Disabled in UVLO mode

and Hiccup Mode

Two Independent, Programmable Synchronous

Rectifier Dead-Time Adjustments

•

Four High-Current 2-A Bridge Gate Drivers

Wide-Bandwidth Optocoupler Interface

Configurable for Either Current Mode or Voltage

Mode Control

•

Dual-Mode Overcurrent Protection

Resistor Programmed 2-MHz Oscillator

Programmable Line UVLO and OVP

Device Information⁽¹⁾

2 Applications

PART NUMBER

LM5045

PACKAGE

HTSSOP (28)

WQFN (28)

BODY SIZE (NOM)

9.70 mm × 4.40 mm

5.00 mm × 5.00 mm

•

E-Bike

Military: Radar and Electronic Warfare

Power: Telecom DC-DC Module: Analog

Private Branch Exchange (PBX)

Solar Power Inverters

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Vector Signal Generators

Microwave Ovens

Point-to-Point Microwave Backhaul

Power: Telecom/Server AC/DC Supply: Dual

Controller: Analog

•

Solar Micro-Inverters

TETRA Base Stations

Washing Machine: Low-End

Simplified Full-Bridge Power Converter

Vin

Vout

T1

VCC

HO1 BST1 HS1 LO1 SLOPE RAMP CS LO2 HS2 BST2 HO2

VIN

GATE

DRIVE

ISOLATION

SR1

UVLO

OVP

SR2

LM5045 FULL-BRIDGE CONTROLLER

WITH INTEGRATED GATE DRIVERS

VCC

ISOLATED

FEEDBACK

COMP

SSOFF

RT

RES

SS

RD1 RD2 REF PGND AGND

SSSR

ISOLATION

BOUNDARY

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM5045

SNVS699H –FEBRUARY 2011–REVISED JANUARY 2015

www.ti.com

Table of Contents

7.3 Feature Description................................................. 14

7.4 Device Functional Modes........................................ 22

Application and Implementation ........................ 25

8.1 Application Information............................................ 25

8.2 Typical Application .................................................. 25

Power Supply Recommendations...................... 34

1

2

3

4

5

6

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ..................................... 6

6.2 ESD Ratings ............................................................ 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 7

6.6 Typical Characteristics............................................ 10

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7.2 Functional Block Diagram ....................................... 13

8

9

10 Layout................................................................... 34

10.1 Layout Guidelines ................................................. 34

10.2 Layout Example .................................................... 35

11 Device and Documentation Support ................. 37

11.1 Trademarks........................................................... 37

11.2 Electrostatic Discharge Caution............................ 37

11.3 Glossary................................................................ 37

7

12 Mechanical, Packaging, and Orderable

Information ........................................................... 37

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (March 2013) to Revision H

Page

•

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision F (March 2013) to Revision G

Page

•

Changed layout of National Data Sheet to TI format ........................................................................................................... 25

2

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SNVS699H –FEBRUARY 2011–REVISED JANUARY 2015

5 Pin Configuration and Functions

PWP Package

28-Pin HTSSOP With PowerPAD™

Top View

UVLO

1

VIN

28

OVP

RAMP

CS

HS1

2

3

27

HO1

BST1

SR1

26

25

4

24

23

22

SLOPE

5

6

LO1

COMP

REF

PowerPAD™

PGND

VCC

7

8

9

21

20

19

RT

LO2

SR2

AGND

RD1

10

BST2

18

17

16

RD2

11

12

13

HO2

HS2

RES

SS

SSSR

SS OFF

15

14

RSG Package

28-Pin WQFN, 5 mm × 5 mm

Top View

25

24

23

28

27

26

22

BST1

21

SLOPE

COMP

1

2

3

20

19

SR1

LO1

REF

RT

PGND

4

18

AGND

RD1

5

6

VCC

LO2

17

16

RD2

7

15

SR2

11

12

13

8

9

10

14

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Pin Functions

I/O

DESCRIPTION

Analog Ground

APPLICATION INFORMATION

NAME

AGND

BST1

HTSSOP

WQFN

9

5

O

I

Connect directly to the Power Ground.

25

21

Bootstrap capacitors connected between BST1, 2 and SW1,

2 provide bias supply for the high side HO1, 2 gate drivers.

External diodes are required between VCC and BST1, 2 to

charge the bootstrap capacitors when SW1, 2 are low.

Gate Drive Bootstrap

BST2

18

6

14

2

An external opto-coupler connected to the COMP pin

sources current into an internal NPN current mirror. The

PWM duty cycle is at maximum with zero input current, while

1 mA reduces the duty cycle to zero. The current mirror

improves the frequency response by reducing the AC voltage

across the opto-coupler.

Input to the Pulse Width

Modulator

COMP

I

If CS exceeds 750 mV the PWM output pulse will be

terminated, entering cycle-by-cycle current limit. An internal

switch holds CS low for 40 nS after either output switches

high to blank leading edge transients.

CS

4

28

I

Current Sense Input

HO1

HO2

26

17

22

13

High side PWM outputs capable of driving the upper

MOSFET of the bridge with 1.5-A peak source and 2-A peak

sink current.

O

High Side Output Driver

HS1

HS2

LO1

LO2

27

16

23

20

23

12

19

16

Common connection of the high side FET source, low side

FET drain and transformer primary winding.

I

Switch Node

Alternating output of the PWM gate driver. Capable of 1.5-A

peak source and 2-A peak sink current.

O

Low Side Output Driver

An external voltage divider from the input power supply sets

the shutdown level during an over-voltage condition.

Alternatively, an external NTC thermistor voltage divider can

be used to set the shutdown temperature. The threshold is

1.25 V. Hysteresis is set by an internal current that sources

20 µA of current into the external resistor divider.

OVP/OTP

2

26

I

Overvoltage Protection

PGND

RAMP

22

3

18

27

O

I

Power Ground

Connect directly to Analog Ground

Modulation ramp for the PWM comparator. This ramp can be

a signal representative of the primary current (current mode)

or proportional to the input voltage (feed-forward voltage

mode). This pin is reset to GND at the end of every cycle.

Input to PWM Comparator

The resistance connected between RD1 and AGND sets the

delay from the falling edge of SR1 or SR2 and the rising

edge of HO2/LO1 or HO1/LO2, respectively.

Synchronous Rectifier

Leading Edge Delay

RD1

10

6

I

The resistance connected between RD2 and AGND sets the

delay from the falling edge of HO1/LO2 or HO2/LO1 and the

rising edge of SR2 or SR1, respectively.

Synchronous Rectifier

Trailing Edge Delay

RD2

REF

11

7

3

I

Maximum output current is 15 mA. Locally decouple with a

0.1-µF capacitor.

O

Output of a 5V reference

Whenever the CS pin exceeds the 750-mV cycle-cycle

current limit threshold, 30-µA current is sourced into the RES

capacitor for the remainder of the PWM cycle. If the RES

capacitor voltage reaches 1.0 V, the SS capacitor is

discharged to disable the HO1, HO2, LO1, LO2 and SR1,

SR2 outputs. The SS pin is held low until the voltage on the

RES capacitor has been ramped between 2-V and 4-V eight

times by 10-µA charge and 5-µA discharge currents. After

the delay sequence, the SS capacitor is released to initiate a

normal start-up sequence.

RES

12

8

I

Restart Timer

The resistance connected between RT and AGND sets the

oscillator frequency. Synchronization is achieved by AC

coupling a pulse to the RT/SYNC pin that raises the voltage

at least 1.5 V above the 2-V nominal bias level.

Oscillator Frequency

Control and Frequency

Synchronization

RT/SYNC

SLOPE

8

5

4

1

O

A ramping current source from 0 to 100 µA is provided for

slope compensation in current mode control. This pin can be

connected through an appropriate resistor to the CS pin to

provide slope compensation. If slope compensation is not

required, SLOPE must be tied to ground.

Slope Compensation

Current

4

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Pin Functions (continued)

I/O

DESCRIPTION

APPLICATION INFORMATION

NAME

HTSSOP

WQFN

Synchronous Rectifier

Driver

Control output for synchronous rectifier gate. Capable of

peak sourcing 100 mA and sinking 400 mA.

SR1

24

19

20

O

Synchronous Rectifier

Driver

Control output for synchronous rectifier gate. Capable of

peak sourcing 100 mA and sinking 400 mA.

SR2

SS

15

9

An internal 20-µA current source charges the SS pin during

start-up. The input to the PWM comparator gradually rises as

the SS capacitor charges to steadily increase the PWM duty

cycle. Pulling the SS pin to a voltage below 20 0mV stops

PWM pulses at HO1, 2 and LO1, 2 and turns off the

synchronous rectifier FETs to a low state.

13

I

Soft-Start Input

When SS OFF pin is connected to the AGND, the LM5045

soft-stops in the event of a VIN UVLO and Hiccup mode

current limit condition. If the SSOFF pin is connected to REF

pin, the controller hard-stops on any fault condition. Refer to

Table 1 for more details.

SSOFF

SSSR

15

14

11

10

I

Soft-Stop Disable

An external capacitor and an internal 20-µA current source

set the soft-start ramp for the synchronous rectifiers. The

SSSR capacitor charge-up is enabled after the first output

pulse and SS > 2 V and Icomp < 800 µA

Secondary Side Soft-Start

An external voltage divider from the power source sets the

shutdown and standby comparator levels. When UVLO

reaches the 0.4-V threshold the VCC and REF regulators are

enabled. At the 1.25-V threshold, the SS pin is released and

the controller enters the active mode. Hysteresis is set by an

internal current sink that pulls 20 µA from the external

resistor divider.

Line Undervoltage

Lockout

UVLO

1

25

I

The output voltage of the start-up regulator is initially

regulated to 9.5 V. Once the secondary side soft-start (SSSR

pin) reaches 1 V, the VCC output is reduced to 7.7 V. If an

auxiliary winding raises the voltage on this pin above the

regulation set-point, the internal start-up regulator will

shutdown, thus reducing the IC power dissipation.

Output of Start-Up

Regulator

VCC

VIN

21

28

17

24

I

Input to the Start-up Regulator. Operating input range is 14 V

to 100 V. For power sources outside of this range, the

LM5045 can be biased directly at VCC by an external

regulator.

Input Power Source

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6 Specifications

(1)

6.1 Absolute Maximum Ratings

MIN

–0.3

–5

MAX

UNIT

V

VIN to GND

HS to GND⁽²⁾

105

V

BST1/BST2 to GND

BST1/BST2 to HS1/HS2

HO1/HO2 to HS1/HS2⁽³⁾

LO1/LO2/SR1/SR2⁽³⁾

V_CCto GND

–0.3

116

V

16

V

BST1/BST2 + 0.3

V

V_CC+ 0.3

V

16

V

REF,SSOFF,RT,OVP,UVLO to GND

RAMP

7

V

COMP

–0.3

10

V

COMP Input Current

All other inputs to GND⁽³⁾

Junction Temperature

Storage temperature, T_stg

mA

V

–0.3

–55

REF + 0.3

150

°C

150

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which

operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.

(2) The negative HS voltage must never be more negative than VCC–16 V. For example, if VCC = 12 V, the negative transients at HS must

not exceed –4 V.

(3) These pins are output pins and as such should not be connected to an external voltage source. The voltage range listed is the limits the

internal circuitry is designed to reliably tolerate in the application circuit.

6.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

14

NOM

MAX

100

14

UNIT

V

VIN Voltage

External Voltage Applied to VCC

Junction Temperature

SLOPE

10

V

–40

–0.3

125

2

°C

V

6.4 Thermal Information

LM5045

THERMAL METRIC⁽¹⁾

PWP

RSG

UNIT

28 PINS

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

40

4

40

4

°C/W

R_θJC(top)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6

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6.5 Electrical Characteristics

Limits in standard typeface are for T_J= 25°C only; MIN and MAX limits apply the junction temperature range of –40°C to

125°C. Unless otherwise specified, the following conditions apply: V_IN= 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ. No load on

HO1, HO2, LO1, LO2, SR1, SR2, COMP = 0 V, UVLO = 2.5 V, OVP = 0 V, SSOFF = 0 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

START-UP REGULATOR (V_CCPIN)

V_CC1

V_CCvoltage

I_CC= 10 mA (SSSR < 1 V)

I_CC= 10 mA (SSSR > 1 V)

V_CC= 6 V

9.3

7.5

60

9.6

7.8

80

9.9

8.1

V

V_CC2

V_CCvoltage

I_CC(Lim)

I_CC(ext)

V_CCcurrent limit

V_CCsupply current

mA

Supply current into VCC from an

4.6

externally applied source. V_CC= 10

V

V_CCload regulation

I_CCfrom 0 to 50 mA

Positive going VCC

Negative going VCC

35

V_CC1–0.1

6.3

mV

V

V_CC(UV)

V_CCundervoltage threshold

V_CC1–0.2

5.9

6.7

V

I_IN

V_INoperating current

V_INshutdown current

4

mA

µA

V_IN= 20 V, V_UVLO= 0 V

V_IN= 100 V, V_UVLO= 0 V

V_CC=10 V

300

520

550

350

V_INstart-up regulator leakage

160

VOLTAGE REFERENCE REGULATOR (REF PIN)

V_REF

REF voltage

I_REF= 0 mA

4.85

5

25

5.15

50

V

mV

mA

V

REF voltage regulation

REF current limit

V_REFundervoltage threshold

Hysteresis

I_REF= 0 to 10 mA

V_REF= 4.5 V

I_REF(Lim)

V_REFUV

15

20

Positive going V_REF

4.3

4.5

0.25

4.7

V

UNDERVOLTAGE LOCK OUT AND SHUTDOWN (UVLO PIN)

V_UVLO

I_UVLO

Under-voltage threshold

Hysteresis current

1.18

16

1.25

20

1.32

24

V

UVLO pin sinking current when

V_UVLO< 1.25 V

µA

Undervoltage standby enable

threshold

UVLO voltage rising

0.32

0.4

0.48

V

Hysteresis

0.05

1.25

20

V

V_OVP

OVP shutdown threshold

OVP hysteresis current

OVP rising

1.18

16

1.32

24

OVP sources current when OVP >

1.25 V

µA

SOFT-START (SS PIN)

I_SS

SS charge current

V_SS= 0 V

16

20

2

24

µA

V

SS threshold for SSSR charge current I_COMP< 800 µA

1.93

2.2

enable

SS output low voltage

Sinking 100 µA

40

200

20

mV

µA

mV

V

SS threshold to disable switching

SSSR charge current

I_SSSR

V_SS> 2 V, I_COMP< 800 µA

V_UVLO< 1.25 V

16

54

24

75

I_SSSR-DIS1

I_SSSR-DIS2

SSSR discharge current 1

SSSR discharge current 2

SSSR output low voltage

SSSR threshold to enable SR1/SR2

65

V_RES> 1 V

109

125

50

147

Sinking 100 µA

1.2

CURRENT SENSE INPUT (CS PIN)

V_CS

Current limit threshold

CS delay to output

0.71

0.75 0.785

V

ns

Ω

65

50

CS leading edge blanking

CS sink impedance (clocked)

R_CS

Internal FET sink impedance

18

45

SOFT-STOP DISABLE (SS OFF PIN)

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Electrical Characteristics (continued)

Limits in standard typeface are for T_J= 25°C only; MIN and MAX limits apply the junction temperature range of –40°C to

125°C. Unless otherwise specified, the following conditions apply: V_IN= 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ. No load on

HO1, HO2, LO1, LO2, SR1, SR2, COMP = 0 V, UVLO = 2.5 V, OVP = 0 V, SSOFF = 0 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

2.8

MAX UNIT

V_IH(min)

SSOFF Input-threshold

SSOFF pulldown resistance

V

200

kΩ

CURRENT LIMIT RESTART (RES Pin)

R_RES

V_RES

RES pulldown resistance

RES hiccup threshold

Termination of hiccup timer

37

1

Ω

V

RES upper counter threshold

RES lower counter threshold

Charge current source 1

Charge current source 2

Discharge current source 1

Discharge current source 2

4

V

2

V

I_RES-SRC1

I_RES-SRC2

I_RES-DIS2

V_RES< 1 V, V_CS> 750 mV

1 V < V_RES< 4 V

30

10

5

µA

V_CS< 750 mV

2 V < V_RES< 4 V

5

Ratio of time in hiccup mode to time

in current limit

V_RES> 1 V, Hiccup counter

147

VOLTAGE FEED-FORWARD (RAMP PIN)

RAMP sink impedance (Clocked)

OSCILLATOR (RT PIN)

5.5

20

Ω

F_SW1

Frequency (LO1, half oscillator

frequency)

R_T= 25 kΩ

R_T= 10 kΩ

185

420

200

480

215

540

kHz

F_SW2

Frequency (LO1, half oscillator

frequency)

DC level

2

3

V

RT sync threshold

2.8

3.3

8

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Electrical Characteristics (continued)

Limits in standard typeface are for T_J= 25°C only; MIN and MAX limits apply the junction temperature range of –40°C to

125°C. Unless otherwise specified, the following conditions apply: V_IN= 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ. No load on

HO1, HO2, LO1, LO2, SR1, SR2, COMP = 0 V, UVLO = 2.5 V, OVP = 0 V, SSOFF = 0 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SYNCHRONOUS RECTIFIER TIMING CONTROL (RD1 and RD2 PINS)

T1

T2

SR trailing edge delay

SR turnoff to HO&LO both on

R_D1= 20 kΩ

45

65

90

ns

R_D1= 100 kΩ

R_D2= 20 kΩ

232

43

300

65

388

90

ns

SR leading edge

HO or LO turnoff to SR turnon

R_D2= 100 kΩ

227

300

384

ns

COMP PIN

V_PWM-OS

V_SS-OS

COMP current to RAMP offset

SS to RAMP offset

V_RAMP= 0 V

ΔRAMP/ΔI_COMP

ΔSS/ΔRAMP

V_SS> 2 V

680

800

1.0

940

µA

V

0.78

1.22

COMP current to RAMP gain

SS to RAMP gain

2400

0.5

Ω

COMP current for SSSR charge

current enable

690

800

915

0%

µA

ns

COMP to output delay

Minimum duty cycle

120

100

I_COMP= 1 mA

SLOPE COMPENSATION (SLOPE PIN)

I_SLOPE

Slope compensation current ramp

Peak of RAMP current

V_BST– V_HSrising

µA

BOOST (BST PIN)

V_{Bst uv}

BST under-voltage threshold

Hysteresis

HO1, HO2, LO1, LO2 GATE DRIVERS

3.8

4.7

0.5

5.6

V

V_OL

V_OH

Low-state output voltage

High-state output voltage

I_HO/LO= 100 mA

0.16

0.32

V

I_HO/LO= 100 mA

V_OHL= V_CC– V_LO

V_OHH= V_BST– V_HO

0.27 0.495

Rise Time

C-load = 1000 pF

V_HO/LO= 0 V

16

11

1.5

2

ns

A

Fall Time

I_OHL

I_OLL

Peak Source Current

Peak Sink Current

V_HO/LO= V_CC

A

SR1, SR2 GATE DRIVERS

V_OL

V_OH

Low-state output voltage

I_SR1/SR2= 10 mA

0.05

0.17

0.1

V

High-state output voltage

I_SR1/SR2= 10 mA,

V_OH= V_REF– V_SR

0.28

Rise Time

C-load = 1000 pF

V_SR= 0 V

60

20

ns

A

Fall Time

I_OHL

I_OLL

Peak Source Current

Peak Sink Current

0.1

0.4

V_SR= V_REF

A

THERMAL SHUTDOWN

TSD Thermal Shutdown Temp

Thermal Shutdown Hysteresis

160

25

°C

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6.6 Typical Characteristics

100

90

36V

48V

72V

80

V

= 3.3V

OUT

70

60

50

5

10

15

20

25

30

LOAD CURRENT (A)

Figure 2. V_CCvs I_CC

Figure 1. Application Board Efficiency

Figure 3. V_CCand V_REFvs V_IN

Figure 5. V_REFvs I_REF

6

5

4

3

2

1

0

V

=3V

UVLO

=1V

=0V

UVLO

V

UVLO

0

20

40

60

(V)

80

100

V

IN

Figure 4. I_INvs V_IN

Figure 6. Oscillator Frequency vs R_T

10

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Typical Characteristics (continued)

75

70

T2

65

T1

60

55

-50

0

50

100

150

TEMPERATURE(°C)

Figure 7. Dead-Time T1, T2 vs R_D1, R_D2

Figure 8. Dead-Time T1, T2 vs. Temperature

Figure 9. CS Threshold vs Temperature

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7 Detailed Description

7.1 Overview

The LM5045 PWM controller contains all of the features necessary to implement a full-bridge topology power

converter using either current mode or voltage mode control. This device is intended to operate on the primary

side of an isolated DC-DC converter with input voltage up to 100 V. This highly integrated controller-driver

provides dual 2-A high-side and low-side gate drivers for the four external bridge MOSFETs plus control signals

for secondary side synchronous rectifiers. External resistors program the leading and trailing edge dead-time

between the main and synchronous rectifier control signals. Intelligent start-up of synchronous rectifier allows

turnon of the power converter into the prebias loads. Cycle-by-cycle current limit protects the power components

from load transients while hiccup mode protection limits average power dissipation during extended overload

conditions. Additional features include programmable soft-start, soft-start of the synchronous rectifiers, and a 2-

MHz capable oscillator with synchronization capability and thermal shutdown.

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7.2 Functional Block Diagram

VOLTAGE

REGULATOR

VIN

VCC

REF

1.25V

+

-

OVP

VCC

UVLO

5V

20 PA

5V

HYSTERESIS

REFERENCE

0.4V

+

-

SHUTDOWN

STANDBY

BST1

HO1

HS1

UVLO

LOGIC

THERMAL

LIMIT

(160°C)

1.25V

+

-

VCC

UVLO

LO1

HYSTERESIS

20 PA

BST2

HO2

CLK

RT

DELAY

OSCILLATOR

HS2

LO2

Q

TIMERS

AND

T

VCC

REF

Q

DRIVER

LOGIC

S

R

Q

100 PA

0 PA

SR1

SLOPE

SLOPECOMP

SR2

RD1

GENERATOR

RAMP

RD2

SSOFF

RAMP

COMP

20 PA

SSSR

5V

DRIVER

LOGIC

5k

+

1V

R

PWM

-

SS

20 PA

SS

R

1:1

SS

Buffer

0.75V

10 PA

-

CS

+

HICCUP

30 PA

MODE

TIMER and

LOGIC

CLK + LEB

RES

PGND

5 PA

+

-

AGND

1.0V

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7.3 Feature Description

7.3.1 High-Voltage Start-Up Regulator

The LM5045 contains an internal high-voltage start-up regulator that allows the input pin (VIN) to be connected

directly to the supply voltage over a wide range from 14 V to 100 V. The input can withstand transients up to

105 V. When the UVLO pin potential is greater than 0.4 V, the VCC regulator is enabled to charge an external

capacitor connected to the VCC pin. The VCC regulator provides power to the voltage reference (REF) and the

gate drivers (HO1/HO2 and LO1/LO2). When the voltage on the VCC pin exceeds its undervoltage (UV)

threshold, the internal voltage reference (REF) reaches its regulation set point of 5 V and the UVLO voltage is

greater than 1.25 V, the soft-start capacitor is released and normal operation begins. The regulator output at

VCC is internally current limited. The value of the VCC capacitor depends on the total system design, and its

start-up characteristics. The recommended range of values for the VCC capacitor is 0.47 μF to 10 µF.

The internal power dissipation of the LM5045 can be reduced by powering VCC from an external supply. The

output voltage of the VCC regulator is initially regulated to 9.5 V. After the synchronous rectifiers are engaged

(which is approximately when the output voltage in within regulation), the VCC voltage is reduced to 7.7 V. In

typical applications, an auxiliary transformer winding is connected through a diode to the VCC pin. This winding

must raise the VCC voltage above 8V to shut off the internal start-up regulator. Powering VCC from an auxiliary

winding improves efficiency while reducing the power dissipation of the controller. The VCC UV circuit will still

function in this mode, requiring that VCC never falls below its UV threshold during the start-up sequence. The

VCC regulator series pass transistor includes a diode between VCC and VIN that should not be forward biased

in normal operation. Therefore, the auxiliary VCC voltage should never exceed the VIN voltage.

An external DC bias voltage can be used instead of the internal regulator by connecting the external bias voltage

to both the VCC and the VIN pins. This implementation is shown in the Application and Implementation section.

The external bias must be greater than 10 V and less than the VCC maximum voltage rating of 14 V.

7.3.2 Line Undervoltage Detector

The LM5045 contains a dual level undervoltage lockout (UVLO) circuit. When the UVLO pin voltage is below 0.4

V, the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.4 V but less

than 1.25 V, the controller is in standby mode. In standby mode the VCC and REF bias regulators are active

while the controller outputs are disabled. When the VCC and REF outputs exceed their respective under-voltage

thresholds and the UVLO pin voltage is greater than 1.25 V, the soft-start capacitor is released and the normal

operation begins. An external set-point voltage divider from VIN to GND can be used to set the minimum

operating voltage of the converter. The divider must be designed such that the voltage at the UVLO pin will be

greater than 1.25 V when VIN enters the desired operating range. UVLO hysteresis is accomplished with an

internal 20 μA current sink that is switched on or off into the impedance of the set-point divider. When the UVLO

threshold is exceeded, the current sink is deactivated to quickly raise the voltage at the UVLO pin. When the

UVLO pin voltage falls below the 1.25 V threshold, the current sink is enabled causing the voltage at the UVLO

pin to quickly fall. The hysteresis of the 0.4 V shutdown comparator is internally fixed at 50 mV.

The UVLO pin can also be used to implement various remote enable / disable functions. Turning off the

converter by forcing the UVLO pin to standby condition (0.4 V < UVLO < 1.25 V) provides a controlled soft-stop.

Refer to the Soft-Stop section for more details.

7.3.3 Overvoltage Protection

An external voltage divider can be used to set either an overvoltage or an overtemperature protection. During an

OVP condition, the SS and SSSR capacitors are discharged and all the outputs are disabled. The divider must

be designed such that the voltage at the OVP pin is greater than 1.25 V when overvoltage/temperature condition

exists. Hysteresis is accomplished with an internal 20 μA current source. When the OVP pin voltage exceeds

1.25 V, the 20 μA current source is activated to quickly raise the voltage at the OVP pin. When the OVP pin

voltage falls below the 1.25 V threshold, the current source is deactivated causing the voltage at the OVP to

quickly fall. Refer to the Application and Implementation section for more details.

7.3.4 Reference

The REF pin is the output of a 5-V linear regulator that can be used to bias an optocoupler transistor and

external housekeeping circuits. The regulator output is internally current limited to 15 mA. The REF pin must be

locally decoupled with a ceramic capacitor, the recommended range of values are from 0.1 μF to 10 μF

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Feature Description (continued)

7.3.5 Oscillator, Sync Input

The LM5045 oscillator frequency is set by a resistor connected between the RT pin and AGND. The RT resistor

should be located very close to the device. To set a desired oscillator frequency (F_OSC), the necessary value of

RT resistor can be calculated from the following equation:

1

R_T=

F_OSCx 1 x 10^-10

(1)

For example, if the desired oscillator frequency is 400 kHz, that is, each phase (LO1 or LO2) at 200 kHz, the

value of R_Twill be 25 kΩ. If the LM5045 is to be synchronized to an external clock, that signal must be coupled

into the RT pin through a 100 pF capacitor. The RT pin voltage is nominally regulated at 2.0 V and the external

pulse amplitude should lift the pin to between 3.5 V and 5.0 V on the low-to-high transition. The synchronization

pulse width should be between 15 and 200 ns. The RT resistor is always required, whether the oscillator is free

running or externally synchronized and the SYNC frequency must be equal to, or greater than the frequency set

by the RT resistor. When syncing to an external clock, it is recommended to add slope compensation by

connecting an appropriate resistor from the VCC pin to the CS pin. Also disable the SLOPE pin by grounding it.

7.3.6 Cycle-by-Cycle Current Limit

The CS pin is to be driven by a signal representative of the primary current of the transformer. If the voltage on

the CS pin exceeds 0.75 V, the current sense comparator immediately terminates the PWM cycle. A small RC

filter connected to the CS pin and located near the controller is recommended to suppress noise. An internal 18-

Ω MOSFET discharges the external current sense filter capacitor at the conclusion of every cycle. The discharge

MOSFET remains on for an additional 40 ns after the start of a new PWM cycle to blank leading edge spikes.

The current sense comparator is very fast and may respond to short duration noise pulses. Layout is critical for

the current sense filter and the sense resistor. The capacitor associated with CS filter must be placed very close

to the device and connected directly to the CS and AGND pins. If a current sense transformer is used, both the

leads of the transformer secondary should be routed to the filter network, which should be located close to the

IC. When designing with a current sense resistor, all of the noise sensitive low power ground connections should

be connected together near the AGND pin, and a single connection should be made to the power ground (sense

resistor ground point).

7.3.7 Hiccup Mode

The LM5045 provides a current limit restart timer to disable the controller outputs and force a delayed restart

(such as Hiccup mode) if a current limit condition is repeatedly sensed. The number of cycle-by-cycle current

limit events required to trigger the restart is programmed by the external capacitor at the RES pin. During each

PWM cycle, the LM5045 either sources or sinks current from the RES capacitor. If current limit is detected, the 5

μA current sink is disabled and a 30μA current source is enabled. If the RES voltage reaches the 1.0 V

threshold, the following restart sequence occurs, as shown in Figure 10:

•

The SS and SSSR capacitors are fully discharged

The 30 μA current source is turned-off and the 10 μA current source is turned-on.

Once the voltage at the RES pin reaches 4.0 V the 10 μA current source is turned-off and a 5μA current sink

is turned-on, ramping the voltage on the RES capacitor down to 2.0 V.

•

Once RES capacitor reaches 2.0 V, threshold, the 10 μA current source is turned-on again. The RES

capacitor voltage is ramped between 4.0 V and 2.0 V eight times.

When the counter reaches eight, the RES pin voltage is pulled low and the soft-start capacitor is released to

begin a soft-start sequence. The SS capacitor voltage slowly increases. When the SS voltage reaches 1.0 V,

the PWM comparator will produce the first narrow pulse.

•

If the overload condition persists after restart, cycle-by-cycle current limiting will begin to increase the voltage

on the RES capacitor again, repeating the hiccup mode sequence.

If the overload condition no longer exists after restart, the RES pin will be held at ground by the 5 μA current

sink and the normal operation resumes.

The hiccup mode function can be completely disabled by connecting the RES pin to the AGND pin. In this

configuration the cycle-by-cycle protection will limit the maximum output current indefinitely, no hiccup restart

sequences will occur.

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Feature Description (continued)

4V

2V

1V

Count to Eight

Restart delay

Soft-Start

1V

Hiccup Mode off-time

Figure 10. Hiccup Mode Delay and Soft-Start Timing Diagram

7.3.8 PWM Comparator

The LM5045 pulse width modulator (PWM) comparator is a three input device, it compares the signal at the

RAMP pin to the loop error signal or the soft-start, whichever is lower, to control the duty cycle. This comparator

is optimized for speed to achieve minimum controllable duty cycles. The loop error signal is received from the

external feedback and isolation circuit in the form of a control current into the COMP pin. The COMP pin current

is internally mirrored by a matching pair of NPN transistors which sink current through a 5-kΩ resistor connected

to the 5-V reference. The resulting control voltage passes through a 1-V offset, followed by a 2:1 resistor divider

before being applied to the PWM comparator.

An optocoupler detector can be connected between the REF pin and the COMP pin. Because the COMP pin is

controlled by a current input, the potential difference across the optocoupler detector is nearly constant. The

bandwidth limiting phase delay which is normally introduced by the significant capacitance of the optocoupler is

thereby greatly reduced. Higher loop bandwidths can be realized because the bandwidth limiting pole associated

with the optocoupler is now at a much higher frequency. The PWM comparator polarity is configured such that

with no current flowing into the COMP pin, the controller produces maximum duty cycle.

7.3.9 Ramp Pin

The voltage at the RAMP pin provides the modulation ramp for the PWM comparator. The PWM comparator

compares the modulation ramp signal at the RAMP pin to the loop error signal to control the duty cycle. The

modulation ramp signal can be implemented either as a ramp proportional to the input voltage, known as feed-

forward voltage mode control, or as a ramp proportional to the primary current, known as current mode control.

The RAMP pin is reset by an internal MOSFET with an R_DS(ON)of 5.5 Ω at the conclusion of each PWM cycle.

The ability to configure the RAMP pin for either voltage mode or current mode allows the controller to be

implemented for the optimum control method depending upon the design constraints. Refer to the Application

and Implementation section for more details on configuring the RAMP pin for feed-forward voltage mode control

and peak current mode control.

7.3.10 Slope Pin

For duty cycles greater than 50% (25% for each phase), peak current mode control is subject to sub-harmonic

oscillation. Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow duty

cycles. This can be eliminated by adding an artificial ramp, known as slope compensation, to the modulating

signal at the RAMP pin. The SLOPE pin provides a current source ramping from 0 to 100μA, at the frequency set

by the RT resistor, for slope compensation. The ramping current source at the SLOPE pin can be used in several

different ways to add slope compensation to the RAMP signal:

•

As shown in Figure 11(a), the SLOPE and RAMP pins can be connected together through an appropriate

resistor to the CS pin. This configuration will inject current sense signal plus slope compensation to the RAMP

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Feature Description (continued)

pin but CS pin will not see any slope compensation. Therefore, in this scheme slope compensation will not

affect the current limit.

•

In a second configuration, as shown in Figure 11(b), the SLOPE, RAMP and CS pins can be tied together. In

this configuration the ramping current source from the SLOPE pin will flow through the filter resistor and filter

capacitor, therefore both the CS pin and the RAMP pin will see the current sense signal plus the slope

compensation ramp. In this scheme, the current limit is compensated by the slope compensation and the

current limit onset point will vary.

If the slope compensation is not required for example, in feed-forward voltage mode control, the SLOPE pin must

be connected to the AGND pin. When the RT pin is synched to an external clock, it is recommended to disable

the SLOPE pin and add slope compensation externally by connecting an appropriate resistor from the VCC pin to

the CS pin. Refer to the Application and Implementation section for more details.

LM5045

100 PA

SLOPE

0

SLOPE

0

RAMP

CS

RAMP

CS

CLK

Current

Sense

CLK

Current

Sense

R

SLOPE

R

FILTER

R

FILTER

CLK + LEB

R

CS

C

FILTER

C

FILTER

(a)

(b)

A. Slope Compensation Configured for PWM Only (No Current Limit Slope)

B. Slope Compensation Configured for PWM and Current Limit

Figure 11. Slope Compensation Configuration

7.3.11 Soft-Start

The soft-start circuit allows the power converter to gradually reach a steady state operating point, thereby

reducing the start-up stresses and current surges. When bias is supplied to the LM5045, the SS capacitor is

discharged by an internal MOSFET. When the UVLO, VCC and REF pins reach their operating thresholds, the

SS capacitor is released and is charged with a 20-µA current source. Once the SS pin voltage crosses the 1-V

offset, SS controls the duty cycle. The PWM comparator is a three input device; it compares the RAMP signal

against the lower of the signals between the soft-start and the loop error signal. In a typical isolated application,

as the secondary bias is established, the error amplifier on the secondary side soft-starts and establishes closed-

loop control, steering the control away from the SS pin.

One method to shutdown the regulator is to ground the SS pin. This forces the internal PWM control signal to

ground, reducing the output duty cycle quickly to zero. Releasing the SS pin begins a soft-start cycle and normal

operation resumes. A second shutdown method is presented in the UVLO and OVP Voltage Divider Selection

section.

7.3.12 Gate Driver Outputs

The LM5045 provides four gate drivers: two floating high-side gate drivers HO1 and HO2 and two ground

referenced low-side gate drivers LO1 and LO2. Each internal driver is capable of source 1.5-A peak and sinking

2-A peak. Initially, the diagonal HO1 and LO2 are turned-on together, followed by an off-time when all the four

gate driver outputs are off. In the subsequent phase the diagonal HO2 and LO1 are turned on together followed

by an off-time. The low-side gate drivers are powered directly by the VCC regulator. The HO1 and HO2 gate

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Feature Description (continued)

drivers are powered from a bootstrap capacitor connected between BST1/BST2 and HS1/HS2, respectively. An

external diode connected between VCC (anode pin) and BST (cathode pin) provides the high-side gate driver

power by charging the bootstrap capacitor from VCC when the corresponding switch node (HS1/HS2 pin) is low.

When the high side MOSFET is turned on, BST1 rises to a peak voltage equal to VCC + V_HS1where V_HS1is the

switch node voltage.

The BST and VCC capacitors should be placed close to the pins of the LM5045 to minimize voltage transients

due to parasitic inductances because the peak current sourced to the MOSFET gates can exceed 1.5 A. The

recommended value of the BST capacitor is 0.1 μF or greater. A low ESR / ESL capacitor, such as a surface

mount ceramic, should be used to prevent voltage droop during the HO transitions.

If the COMP pin is open circuit, the outputs will operate at maximum duty cycle. The maximum duty cycle for

each phase is limited by the dead-time set by the RD1 resistor. If the RD1 resistor is set to zero then the

maximum duty cycle is slightly less than 50% due to the internally fixed dead-time. The internally fixed dead-time

is 30ns which does not vary with the operating frequency. The maximum duty cycle for each output can be

calculated from the following equation:

1

F_OSC

- (T1)

(

)

D_MAX

=

2

F_OSC

(

)

where

•

T1 is the time set by the RD1 resistor

F_OSCis the frequency of the oscillator

(2)

For example, if the oscillator frequency is set at 400 kHz and the T1 time set by the RD1 resistor is 60 ns, the

resulting D_MAXwill be equal to 0.488.

CLK

HO1,LO2

Tonmax

Tosc

HO2,LO1

T1

1

F_OSC

T_OSC

=

T1 DꢀRD1

Figure 12. Timing Diagram Illustrating the Maximum Duty Cycle and Dead-Time Set by RD1

7.3.13 Synchronous Rectifier Control Outputs (SR1 and SR2)

Synchronous rectification (SR) of the transformer secondary provides higher efficiency, especially for low output

voltage converters, compared to the diode rectification. The reduction of rectifier forward voltage drop (0.5 V to

1.5 V) to 10 mV to 200 mV VDS voltage for a MOSFET significantly reduces rectification losses. In a typical

application, the transformer secondary winding is center tapped, with the output power inductor in series with the

center tap. The SR MOSFETs provide the ground path for the energized secondary winding and the inductor

current. From Figure 13 it can be seen that when the HO1/LO2 diagonal is turned ON, power transfer is enabled

from the primary. During this period, the SR1 MOSFET is enabled and the SR2 MOSFET is turned-off. The

secondary winding connected to the SR2 MOSFET drain is twice the voltage of the center tap at this time. At the

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Feature Description (continued)

conclusion of the HO1/LO2 pulse, the inductor current continues to flow through the SR2 MOSFET body diode.

Because the body diode causes more loss than the SR MOSFET, efficiency can be improved by minimizing the

T2 period while maintaining sufficient timing margin over all conditions (component tolerances, etc.) to prevent

the shoot-through current. When HO2/LO1 enables power transfer from the primary, the SR2 MOSFET is

enabled and the SR1 MOSFET is off.

During the freewheeling period, the inductor current is almost equally shared between both the SR1 and SR2

MOSFETs which effectively shorts the transformer secondary. The SR2 MOSFET is disabled before HO1/LO2 is

turned-on. The SR2 MOSFET body diode continues to carry about the half inductor current until the primary

power raises the SR2 MOSFET drain voltage and reverse biases the body diode. Ideally, dead-time T1 would be

set to the minimum time that allows the SR MOSFET to turn off before the SR MOSFET body diode starts

conducting.

The SR drivers are powered by the REF regulator and each SR output is capable of sourcing 0.1 A and sinking

0.4-A peak. The amplitude of the SR drivers is limited to 5 V. The 5-V SR signals enable the LM5045 to transfer

SR control across the isolation barrier either through a solid-state isolator or a pulse transformer. The actual gate

sourcing and sinking currents for the synchronous MOSFETs are provided by the secondary-side bias and gate

drivers.

T1 and T2 can be programmed by connecting a resistor between RD1 and RD2 pins and AGND. It should be

noted that while RD1 effects the maximum duty cycle, RD2 does not. The RD1 and RD2 resistors should be

located very close to the device. The formula for RD1 and RD2 resistors are given below:

T(1,2)

3 pF

; For 20k < (1,2) < 100k

RD(1,2) =

(3)

If the desired dead-time for T1 is 60ns, then the RD1 will be 20 kΩ.

HO1, LO2

SR2

T1

T2

HO2, LO1

SR1

T1

T2

Figure 13. Synchronous Rectifier Timing Diagram

7.3.14 Soft-Start of the Synchronous Rectifiers

In addition to the basic soft-start already described, the LM5045 contains a second soft-start function that

gradually turns on the synchronous rectifiers to their steady-state duty cycle. This function keeps the

synchronous rectifiers off during the basic soft-start allowing a linear start-up of the output voltage even into pre-

biased loads. Then the SR output duty cycle is gradually increased to prevent output voltage disturbances due to

the difference in the voltage drop between the body diode and the channel resistance of the synchronous

MOSFETs. Initially, when bias is supplied to the LM5045, the SSSR capacitor is discharged by an internal

MOSFET. When the SS capacitor reaches a 2-V threshold and once it is established that COMP is in control of

the duty cycle such as I_COMP< 800 µA, the SSSR discharge is released and SSSR capacitor begins charging

with a 20-µA current source. Once the SSSR cap crosses the internal 1-V threshold, the LM5045 begins the soft-

start of the synchronous FETs. The SR soft-start follows a leading edge modulation technique such as the

leading edge of the SR pulse is soft-started as opposed trailing edge modulation of the primary FETs. As shown

in the Figure 14(a), SR1 and SR2 are turned-on simultaneously with a narrow pulse-width during the

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Feature Description (continued)

freewheeling cycle. At the end of the freewheel cycle, that is, at the rising edge of the internal CLK, the SR FET

in-phase with the next power transfer cycle is kept on while the SR FET out of phase with it is turned-off. The in-

phase SR FET is kept on throughout the power transfer cycle and at the end of it, both the primary FETs and the

in-phase SR FETs are turned-off together. The synchronous rectifier outputs can be disabled by grounding the

SSSR pin.

CLK

HO2/LO1

HO1/LO2

SR1

T1

T2

SR2

Power

Transfer Freewheel

T1

T2

Waveforms during soft-start

Waveforms after soft-start

A. Waveforms during Soft-Start

B. Waveforms after Soft-Start

Figure 14. Waveforms

7.3.15 Prebias Startup

A common requirement for power converters is to have a monotonic output voltage start-up into a prebiased load

such as a precharged output capacitor. In a prebiased load condition, if the synchronous rectifiers are engaged

prematurely they will sink current from the precharged output capacitors resulting in an undesired output voltage

dip. This condition is undesirable and could potentially damage the power converter. The LM5045 uses unique

control circuitry to ensure intelligent turnon of the synchronous rectifiers such that the output has a monotonic

start-up. Initially, the SSSR capacitor is held at ground to disable the synchronous MOSFETs allowing the body

diode to conduct. The synchronous rectifier soft-start is initiated once it is established the duty cycle is controlled

by the COMP instead of the soft-start capacitor, that is, I_COMP< 800 µA and the voltage at the SS pin > 2 V. The

SSSR capacitor is then released and is charged by a 20-µA current source. Further, as shown in Figure 15, a 1-

V offset on the SSSR pin is used to provide additional delay. This delay ensures the output voltage is in

regulation avoiding any reverse current when the synchronous MOSFETs are engaged.

7.3.16 Soft-Stop

As shown in Figure 16, if the UVLO pin voltage falls below the 1.25-V standby threshold, but above the 0.4-V

shutdown threshold, the SSSR capacitor is soft-stopped with a 60-µA current source (3 times the charging

current). Once the SSSR pin reaches the 1.0-V threshold, both the SS and SSSR pins are immediately

discharged to GND. Soft-stopping the power converter gradually winds down the energy in the output capacitors

and results in a monotonic decay of the output voltage. During the hiccup mode, the same sequence is executed

except that the SSSR is discharged with a 120-µA current source (6 times the charging current). In case of an

OVP, VCC UV, thermal limit or a VREF UV condition, the power converter hard-stops, whereby all of the control

outputs are driven to a low state immediately.

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Feature Description (continued)

2.0V

SS

1.0V

Primary

Secondary

Bias

COMP

1.0V

SSSR

SR1, SR2

VOUT

Prebiased Load

Figure 15. Prebias Voltage Start-up Waveforms

7.3.17 Soft-Stop Off

The Soft-Start Off (SSOFF) pin gives additional flexibility by allowing the power converter to be configured for

hard-stop during line UVLO and hiccup mode condition. If the SS OFF pin is pulled up to the 5-V REF pin, the

power converter hard-stops in any fault condition. Hard-stop drives each control output to a low state

immediately. Refer to Table 1 for more details.

1.25V

VIN UVLO

0.45V

SS

SSSR

1.0V

Figure 16. Stop-Stop Waveforms During a UVLO Event

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Feature Description (continued)

Table 1. Soft-Stop in Fault Conditions⁽¹⁾

FAULT CONDITION

SSSR

UVLO

Soft-Stop

(UVLO<1.25V)

3x the charging rate

OVP

Hard-Stop

(OVP>1.25V)

Hiccup

Soft-Stop

(CS>0.75 and RES>1V)

6x the charging rate

VCC/VREF UV

Hard-Stop

Internal Thermal Limit

(1) Note: All the above conditions are valid with SSOFF pin tied to GND. If SSOFF=5V, the LM5045 hard-stops in all the conditions. The SS

pin remains high in all the conditions until the SSSR pin reaches 1V.

7.3.18 Thermal Protection

Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum rated

junction temperature is exceeded. When activated, typically at 160°C, the controller is forced into a shutdown

state with the output drivers, the bias regulators (VCC and REF) disabled. This helps to prevent catastrophic

failures from accidental device overheating. During thermal shutdown, the SS and SSSR capacitors are fully

discharged and the controller follows a normal start-up sequence after the junction temperature falls to the

operating level (140°C).

7.4 Device Functional Modes

7.4.1 Control Method Selection

The LM5045 is a versatile PWM control IC that can be configured for either current mode control or voltage

mode control. The choice of the control method usually depends upon the designer preference. The following

must be taken into consideration while selecting the control method. Current mode control can inherently balance

flux in both phases of the full-bridge topology. The full-bridge topology, like other double ended topologies, is

susceptible to the transformer core saturation. Any asymmetry in the volt-second product applied between the

two alternating phases results in flux imbalance that causes a dc buildup in the transformer. This continual dc

buildup may eventually push the transformer into saturation. The volt-second asymmetry can be corrected by

employing current mode control. In current mode control, a signal representative of the primary current is

compared against an error signal to control the duty cycle. In steady-state, this results in each phase being

terminated at the same peak current by adjusting the pulse-width and thus applying equal volt-seconds to both

the phases.

Current mode control can be susceptible to noise and sub-harmonic oscillation, while voltage mode control

employs a larger ramp for PWM and is usually less susceptible. Voltage-mode control with input line feed-

forward also has excellent line transient response. When configuring for voltage mode control, a dc blocking

capacitor can be placed in series with the primary winding of the power transformer to avoid any flux imbalance

that may cause transformer core saturation.

7.4.2 Voltage Mode Control Using the LM5045

To configure the LM5045 for voltage mode control, an external resistor (R_FF) and capacitor (C_FF) connected to

VIN, AGND, and the RAMP pins is required to create a saw-tooth modulation ramp signal shown in Figure 17.

The slope of the signal at RAMP will vary in proportion to the input line voltage. The varying slope provides line

feed-forward information necessary to improve line transient response with voltage mode control. With a constant

error signal, the on-time (T_ON) varies inversely with the input voltage (VIN) to stabilize the Volt- Second product

of the transformer primary. Using a line feed-forward ramp for PWM control requires very little change in the

voltage regulation loop to compensate for changes in input voltage, as compared to a fixed slope oscillator ramp.

Furthermore, voltage mode control is less susceptible to noise and does not require leading edge filtering.

Therefore, it is a good choice for wide input range power converters. Voltage mode control requires a Type-III

compensation network, due to the complex-conjugate poles of the L-C output filter.

22

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Device Functional Modes (continued)

SLOPE

PROPORTIONAL

TO VIN

VIN

5V

5k

COMP

RFF

R

VIN

R

1V

Gate Drive

1:1

RAMP

CLK

CFF

LM5045

Figure 17. Feed-Forward Voltage Mode Configuration

The recommended capacitor value range for C_FFis from 100 pF to 1800 pF. Referring to Figure 17, it can be

seen that C_FFvalue must be small enough to be discharged with in the clock pulse-width which is typically within

50ns. The R_DS(ON)of the internal discharge FET is 5.5 Ω.

The value of R_FFrequired can be calculated from

-1

R_FF

=

V_RAMP

VIN_MIN

F_OSCx C_FFx In

(1-

)

(4)

For example, assuming a V_RAMPof 1.5 V (a good compromise of signal range and noise immunity), at VIN_MINof

36 V (oscillator frequency of 400 kHz and C_FF= 470 pF results in a value for R_FFof 125 kΩ.

7.4.3 Current Mode Control Using the LM5045

The LM5045 can be configured for current mode control by applying a signal proportional to the primary current

to the RAMP pin. One way to achieve this is shown in Figure 18. The primary current can be sensed using a

current transformer or sense resistor, the resulting signal is filtered and applied to the RAMP pin through a

resistor used for slope compensation. It can be seen that the signal applied to the RAMP pin consists of the

primary current information from the CS pin plus an additional ramp for slope compensation, added by the

resistor R_SLOPE

.

The current sense resistor is selected such that during over current condition, the voltage across the current

sense resistor is above the minimum CS threshold of 728 mV.

In general, the amount of slope compensation required to avoid sub-harmonic oscillation is equal to at least one-

half the down-slope of the output inductor current, transformed to the primary. To mitigate sub-harmonic

oscillation after one switching period, the slope compensation must be equal to one times the down slope of the

filter inductor current transposed to primary. This is known as deadbeat control. The slope compensation resistor

required to implement dead-beat control can be calculated as follows:

where

•

N_TRis the turns-ratio with respect to the secondary

(5)

For example, for a 3.3 V output converter with a turns-ratio between primary and secondary of 9:1, an output

filter inductance (L_FILTER) of 800 nH and a current sense resistor (R_SENSE) of 150 mΩ, R_SLOPEof 1.67 kΩ will

suffice.

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Device Functional Modes (continued)

LM5045

100 PA

SLOPE

0

RAMP

CLK

Current

Sense

R

SLOPE

R

CS

FILTER

CLK + LEB

R

CS

C

FILTER

Figure 18. Current Mode Configuration

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM5045 is a highly integrated PWM controller that contains all of the features necessary for implementing

full-bridge topology power converters using either current mode or voltage mode control. The device targets DC-

DC converter applications with input voltages of up to 100 Vdc and output power in the range 100 W to 1 kW.

8.2 Typical Application

The following schematic shows an example of a 100W full-bridge converter controlled by LM5045. The operating

input voltage range is 36 V to 75 V, and the output voltage is 3.3 V. The output current capability is 30 A. The

converter is configured for current mode control with external slope compensation. An auxiliary winding is used to

raise the VCC voltage to reduce the controller power dissipation.

Figure 19. Evaluation Board Schematic

8.2.1 Design Requirements

PARAMETERS

Input operating range

Output voltage

VALUE

36 V to 75 V

3.3 V

Measured efficiency at 48 V

Frequency of operation

Board size

92% at 30A

420 kHz

2.28 x 1.45 x 0.5 inches

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Typical Application (continued)

PARAMETERS

Load Regulation

Line Regulation

Line UVLO

VALUE

0.2%

0.1%

34V/32V on/off

Current Limit

Hiccup Mode

8.2.2 Detailed Design Procedure

8.2.2.1 VIN and V_CC

The voltage applied to the VIN pin, which may be the same as the system voltage applied to the power

transformer’s primary (V_PWR), can vary in the range of the 14 to 100 V. It is recommended that the filter shown in

Figure 20 be used to suppress the transients that may occur at the input supply. This is particularly important

when VIN is operated close to the maximum operating rating of the LM5045. The current into VIN depends

primarily on the operating current of the LM5045, the switching frequency, and any external loads on the VCC

pin, that typically include the gate capacitances of the power MOSFETs. In typical applications, an auxiliary

transformer winding is connected through a diode to the VCC pin. This pin must raise VCC voltage above 8 V to

shut off the internal start-up regulator.

After the outputs are enabled and the external VCC supply voltage has begun supplying power to the IC, the

current into the VIN pin drops below 1mA. VIN should remain at a voltage equal to or above the VCC voltage to

avoid reverse current through the internal body diode of the internal VCC regulator.

8.2.2.2 For Applications With > 100 VIN

For applications where the system input voltage exceeds 100 V, VIN can be powered from an external start-up

regulator as shown in Figure 21. In this configuration, the VIN and VCC pins should be connected together. The

voltage at the VCC and VIN pins must be greater than 10 V (> Max VCC reference voltage) yet not exceed 16 V.

To enable operation the VCC voltage must be raised above 10 V. The voltage at the VCC pin must not exceed

16 V. The voltage source at the right side of Figure 21 is typically derived from the power stage, and becomes

active once the LM5045’s outputs are active.

V

PWR

50

VIN

LM5045

0.1 PF

Figure 20. Input Transient Protection

10V - 16V

(from aux winding)

V

PWR

VIN

VCC

LM5045

11V

Figure 21. Start-Up Regulator For V_PWR> 100 V

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8.2.2.3 UVLO and OVP Voltage Divider Selection

Two dedicated comparators connected to the UVLO and OVP pins are used to detect undervoltage and

overvoltage conditions. The threshold values of both these comparators are set at 1.25 V. The two functions can

be programmed independently with two separate voltage dividers from VIN to AGND as shown in Figure 22 and

Figure 23, or with a three-resistor divider as shown in Figure 24. Independent UVLO and OVP pins provide

greater flexibility for the user to select the operational voltage range of the system. When the UVLO pin voltage is

below 0.4 V, the controller is in a low current shutdown mode. For a UVLO pin voltage greater than 0.4 V but

less than 1.25 V the controller is in standby mode. Once the UVLO pin voltage is greater than 1.25 V, the

controller is fully enabled. Two external resistors can be used to program the minimum operational voltage for the

power converter as shown in Figure 22. When the UVLO pin voltage falls below the 1.25 V threshold, an internal

20 µA current sink is enabled to lower the voltage at the UVLO pin, thus providing threshold hysteresis.

Resistance values for R₁and R₂can be determined from the following equations:

V_HYS

20 PA

R₁=

1.25V x R₁

R₂=

V_PWR-OFF-1.25V - (20 PA x R1)

where

•

V_PWRis the desired turnon voltage

V_HYSis the desired UVLO hysteresis at V_PWR

(6)

For example, if the LM5045 is to be enabled when V_PWRreaches 33 V, and disabled when V_PWRis decreased to

31 V, R₁should be 100 kΩ, and R₂should be 4.2 kΩ. The voltage at the UVLO pin should not exceed 7 V at any

time.

Two external resistors can be used to program the maximum operational voltage for the power converter as

shown in Figure 23. When the OVP pin voltage rises above the 1.25 V threshold, an internal 20-µA current

source is enabled to raise the voltage at the OVP pin, thus providing threshold hysteresis. Resistance values for

R₁and R₂can be determined from the following equations:

V_HYS

20 PA

R₁=

1.25V x R₁

R₂=

V_PWR-1.25V + (20 PA x R1)

(7)

If the LM5045 is to be disabled when V_PWR-OFFreaches 80 V and enabled when it is decreased to 78 V. R₁

should be 100 kΩ, and R₂should be 1.5 kΩ. The voltage at the OVP pin should not exceed 7 V at any time.

V

PWR

LM5045

R1

1.25V

STANDBY

UVLO

20 PA

R2

0.4V

SHUTDOWN

Figure 22. Basic UVLO Configuration

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LM5045

5V

V

PWR

20 PA

R1

OVP

STANDBY

1.25V

R2

Figure 23. Basic OVP Configuration

V

PWR

R1

1.25V

LM5045

UVLO

STANDBY

20 PA

0.4V

R2

SHUTDOWN

5V

20 PA

OVP

STANDBY

1.25V

R3

Figure 24. UVLO/OVP Divider

The UVLO and OVP can also be set together using a 3 resistor divider ladder as shown in Figure 24. R₁is

calculated as explained in the basic UVLO divider selection. Using the same values, as in the above two

examples, for the UVLO and OVP set points, R₁and R₃remain the same at 100 kΩ and 1.5 kΩ. The R₂is 2.7

kΩ obtained by subtracting R₃from 4.2 kΩ.

Remote configuration of the controller’s operational modes can be accomplished with open drain device(s)

connected to the UVLO pin as shown in Figure 25.

Figure 26 shows an application of the OVP comparator for Remote Thermal Protection using a thermistor (or

multiple thermistors) which may be located near the main heat sources of the power converter. The negative

temperature coefficient (NTC) thermistor is nearly logarithmic, and in this example a 100 kΩ thermistor with the β

material constant of 4500 Kelvin changes to approximately 2 kΩ at 130ºC. Setting R₁to one-third of this

resistance (665 Ω) establishes 130ºC as the desired trip point (for VREF = 5 V). In a temperature band from

20ºC below to 20ºC above the OVP threshold, the voltage divider is nearly linear with 25mV per ºC sensitivity.

R₂provides temperature hysteresis by raising the OVP comparator input by R₂x 20µA. For example, if a 22kΩ

resistor is selected for R₂, then the OVP pin voltage will increase by 22 kΩ x 20 µA = 506 mV. The NTC

temperature must therefore fall by 506 mV / 25 mV per ºC = 20ºC before the LM5045 switches from standby

mode to the normal mode.

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V

PWR

LM5045

R1

1.25V

STANDBY

UVLO

20 PA

R2

STANDBY

SHUTDOWN

0.4V

SHUTDOWN

Figure 25. Remote Standby and Disable Control

LM5045

5V

V

PWR

20 PA

NTC

THERMISTOR

T

R1

OVP

STANDBY

1.25V

R2

Figure 26. Remote Thermal Protection

8.2.2.4 Current Sense

The CS pin receives an input signal representative of its transformer’s primary current, either from a current

sense transformer or from a resistor located at the junction of source pin of the primary switches, as shown in

Figure 27 and Figure 28, respectively. In both the cases, the filter components R_Fand C_Fshould be located as

close to the IC as possible, and the ground connection from the current sense transformer, or R_SENSEshould be

a dedicated trace to the appropriate GND pin. Please refer to the Layout section for more layout tips.

The current sense components must provide a signal > 710 mV at the CS pin during an over-load event. Once

the voltage on the CS pin crosses the current limit threshold, the current sense comparator terminates the PWM

pulse and starts to charge the RES pin. Depending on the configuration of the RES pin, the LM5045 will

eventually initiate a hiccup mode restart or be in continuous current limit.

V

PWR

Q3

Q1

VIN

N

R

S1

S2

F

CS

N

P

R

CS

LM5045

C

F

AGND

Q2

Q4

Figure 27. Transformer Current Sense

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Q3

Q1

N

P

Q4

Q2

VIN

CS

R

F

LM5045

R

CS

C

F

AGND

Figure 28. Resistor Current Sense

8.2.2.5 Hiccup Mode Current Limit Restart

The operation of the hiccup mode restart circuit is explained in the section. During a continuous current limit

condition, the RES pin is charged with 30 µA current source. The restart delay time required to reach the 1.0 V

threshold is given by:

C_RESx 1.0V

T_CS

=

30 PA

(8)

=

This establishes the time allowed before the IC initiates a hiccup restart sequence. For example, if the C_RES

0.01 µF, the time TCS as noted in Figure 29 below is 334 µs. Once the RES pin reaches 1.0 V, the 30 µA

current source is turned-off and a 10 µA current source is turned-on during the ramp up to 4 V and a 5 µA is

turned on during the ramp down to 2 V. The hiccup mode off-time is given by:

C_RESx ((2.0Vx8) + 1.0V)

C_RESx (2.0Vx8)

T_HICCUP

=

+

10 µA

5 µA

(9)

With a C_RES= 0.01 µF, the hiccup time is 49 ms. Once the hiccup time is finished, the RES pin is pulled low and

the SS pin is released allowing a soft-start sequence to commence. Once the SS pin reaches 1 V, the PWM

pulses will commence. The hiccup mode provides a cool-down period for the power converter in the event of a

sustained overload condition thereby lowering the average input current and temperature of the power

components during such an event.

4V

2V

1V

Count to Eight

Restart delay

Soft-Start

1V

Hiccup Mode off-time

Figure 29. Hiccup Mode Delay and Soft-Start Timing Diagram

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8.2.2.6 Augmenting the Gate Drive Strength

The LM5045 includes powerful 2-A integrated gate drivers. However, in certain high-power applications (> 500

W), it might be necessary to augment the strength of the internal gate driver to achieve higher efficiency and

better thermal performance. In high power applications, typically, the I²xR loss in the primary MOSFETs is

significantly higher than the switching loss. To minimize the I²xR loss, either the primary MOSFETs are paralleled

or MOSFETs with low R_{DS (on)}are employed. Both these scenarios increase the total gate charge to be driven by

the controller IC. An increase in the gate charge increases the FET transition time and hence increases the

switching losses. Therefore, to keep the total losses within a manageable limit the transition time must be

reduced.

Generally, during the Miller capacitance charge/discharge the total available driver current is lower during the

turnoff process than during the turnon process and often it is enough to speed-up the turnoff time to achieve the

efficiency and thermal goals. This can be achieved simply by employing a PNP device, as shown in Figure 30,

from gate to source of the power FET. During the turnon process, when the LO1 goes high, the current is

sourced through the diode D1 and the BJT Q1 provides the path for the turnoff current. Q1 should be located as

close to the power FET as possible so that the turnoff current has the shortest possible path to the ground and

does not have to pass through the controller.

VIN

LM5045

BST1

D1

HO1

Q1

HS1

VCC

LO1

PGND

Figure 30. Circuit to Speed-Up the Turnoff Process

Depending on the gate charge characteristics of the primary FET, if it is required to speed up both the turnon and

the turnoff time, a bipolar totem pole structure as shown in Figure 31 can be used. When LO1 goes high, the

gate to source current is sourced through the NPN transistor Q1 and similar to the circuit shown in Figure 30

when LO1 goes low, the PNP transistor Q2 expedites the turnoff process.

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VIN

LM5045

BST1

Q1

Q2

HO1

HS1

VCC

LO1

PGND

Figure 31. Bipolar Totem Pole Arrangement

Alternatively, a low-side gate driver such as LM5112 can be used instead of the discrete totem pole. The

LM5112 comes in a small package with a 3A source and a 7A sink capability. While driving the high-side FET,

the HS1 acts as a local ground and the boot capacitor between the BST and HS pins acts as VCC.

VIN

LM5045

BST1

LM5112

HO1

HS1

VCC

LM5112

LO1

PGND

Figure 32. Using a Low-Side Gate Driver to Augment Gate Drive Strength

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8.2.3 Application Curve

Figure 33. Application Board Efficiency

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9 Power Supply Recommendations

The LM5045 can be used to control power levels up to 1 kW. Therefore the current levels can be considerable.

Care should be taken that components with the correct current rating are chosen. This would include magnetic

components, power MOSFETS and diodes, connectors and wire sizes. Input and output capacitors should have

the correct ripple current rating. The use of a multilayer PCB is recommended with a copper area chosen to

ensure the LM5045 is operating below its maximum junction temperature.

Full power loading should never be attempted with providing with providing adequate cooling.

10 Layout

10.1 Layout Guidelines

The LM5045 current sense and PWM comparators are very fast and respond to short duration noise pulses. The

components at the CS, COMP, SLOPE, RAMP, SS, SSSR, RES, UVLO, OVP, RD1, RD2, and RT pins should

be physically close as possible to the IC, thereby minimizing noise pickup on the PC board trace inductance.

Eliminating or minimizing via’s in these critical connections are essential. Layout consideration is critical for the

current sense filter. If a current sense transformer is used, both leads of the transformer secondary should be

routed to the sense filter components and to the IC pins. The ground side of the transformer should be

connected via a dedicated PC board trace to the AGND pin, rather than through the ground plane. If the current

sense circuit employs a sense resistor in the drive transistor source, low inductance resistors should be used. In

this case, all the noise sensitive, low-current ground trace should be connected in common near the IC, and then

a single connection made to the power ground (sense resistor ground point).

The gate drive outputs of the LM5045 should have short, direct paths to the power MOSFETs to minimize

inductance in the PC board. The boot-strap capacitors required for the high side gate drivers should be located

very close to the IC and connected directly to the BST and HS pins. The VCC and REF capacitors should also

be placed close to their respective pins with short trace inductance. Low ESR and ESL ceramic capacitors are

recommended for the boot-strap, VCC and the REF capacitors. The two ground pins (AGND, PGND) must be

connected together directly underneath the IC with a short, direct connection, to avoid jitter due to relative ground

bounce.

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10.2 Layout Example

VIN

UVLO

OVP

HS1

RAMP

HO1

RAMP

CS

To Current Sensing

Network

BST1

R_FILTER

C_FILTER

SR1

LO1

SLOPE

COMP

To Voltage Feedback

Network

REF

RT

PGND

VCC

LO2

AGND

RD1

RD2

SR2

BST2

HO2

HS2

RES

SS

SS OFF

SSSR

RT

RD1

RD2

RES

SS

SSSR

Figure 34. Layout of Components Around RAMP, CS, SLOPE, COMP, RT, RD1, RD2, RES, SS, and SSR

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Layout Example (continued)

INPUT DC VOLTAGE

R1

R2

VIN

UVLO

OVP

HS1

C1

C3

HO1

RAMP

CS

BST1

R3

SR1

LO1

SLOPE

COMP

C4

REF

RT

PGND

C2

VCC

LO2

AGND

RD1

SR2

RD2

BST2

C4

HO2

HS2

RES

SS

SS OFF

SSSR

Figure 35. Layout of Components Around VIN, VCC, AGND, PGND UVLO, OVP, REF, BST1, BST2, HS1,

and HS2

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11 Device and Documentation Support

11.1 Trademarks

PowerPAD is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

12-Aug-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM5045MHX/NOPB

LM5045SQ/NOPB

LM5045SQX/NOPB

HTSSOP PWP

28

2500

1000

4500

330.0

178.0

330.0

16.4

12.4

6.8

5.3

10.2

5.3

1.6

1.3

8.0

16.0

12.0

Q1

WQFN

RSG

5.3

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Aug-2014

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM5045MHX/NOPB

LM5045SQ/NOPB

LM5045SQX/NOPB

HTSSOP

WQFN

PWP

RSG

28

2500

1000

4500

367.0

210.0

367.0

185.0

367.0

35.0

WQFN

Pack Materials-Page 2

PACKAGE OUTLINE

PWP0028A

PowerPAD^TM- 1.1 mm max height

S

C

A

L

E

1

.

8

0

PLASTIC SMALL OUTLINE

C

6.6

6.2

TYP

SEATING PLANE

A

PIN 1 ID

AREA

0.1 C

26X 0.65

28

1

9.8

9.6

NOTE 3

2X

8.45

14

B

15

0.30

0.19

28X

1.1 MAX

4.5

4.3

0.1

C A

B

NOTE 4

0.20

0.09

TYP

SEE DETAIL A

3.15

2.75

0.25

GAGE PLANE

5.65

5.25

0.10

0.02

THERMAL

PAD

0 - 8

0.7

0.5

DETAIL A

(1)

TYPICAL

4214870/A 10/2014

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MO-153, variation AET.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0028A

PowerPAD^TM- 1.1 mm max height

PLASTIC SMALL OUTLINE

(3.4)

NOTE 9

(3)

SOLDER

MASK

OPENING

SOLDER MASK

DEFINED PAD

28X (1.5)

28X (1.3)

28X (0.45)

1

28

26X

(0.65)

SYMM

(5.5)

(9.7)

SOLDER

MASK

OPENING

(1.3) TYP

14

15

(

0.2) TYP

(1.3)

SEE DETAILS

(0.65) TYP

(0.9) TYP

(6.1)

VIA

SYMM

METAL COVERED

BY SOLDER MASK

HV / ISOLATION OPTION

0.9 CLEARANCE CREEPAGE

OTHER DIMENSIONS IDENTICAL TO IPC-7351

(5.8)

IPC-7351 NOMINAL

0.65 CLEARANCE CREEPAGE

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

METAL UNDER

SOLDER MASK

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214870/A 10/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0028A

PowerPAD^TM- 1.1 mm max height

PLASTIC SMALL OUTLINE

(3)

BASED ON

0.127 THICK

STENCIL

METAL COVERED

BY SOLDER MASK

28X (1.5)

28X (1.3)

28X (0.45)

1

28

26X (0.65)

28X (0.45)

(5.5)

SYMM

BASED ON

0.127 THICK

STENCIL

14

15

SEE TABLE FOR

DIFFERENT OPENINGS

SYMM

(6.1)

FOR OTHER STENCIL

THICKNESSES

(5.8)

HV / ISOLATION OPTION

0.9 CLEARANCE CREEPAGE

OTHER DIMENSIONS IDENTICAL TO IPC-7351

IPC-7351 NOMINAL

0.65 CLEARANCE CREEPAGE

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE AREA

SCALE:6X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.55 X 6.37

3.0 X 5.5 (SHOWN)

2.88 X 5.16

0.127

0.152

0.178

2.66 X 4.77

4214870/A 10/2014

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

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型号：	LM5045SQ/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	Full-Bridge PWM Controller With Integrated MOSFET Drivers 开关
文件：	总46页 (文件大小：1543K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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