LM5050-1-Q1 [TI]
汽车类 5V 至 75V、400uA IQ ORing FET 控制器;
| 型号： | LM5050-1-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 5V 至 75V、400uA IQ ORing FET 控制器 控制器 |
| 文件： | 总30页 (文件大小：1100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM5050-1, LM5050-1-Q1
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
LM5050-1、LM5050-1-Q1 高侧 OR-ing FET 控制器
1 特性
3 说明
1
•
提供标准和符合 AEC-Q100 标准版本的
LM5050Q0MK-1（高达 150°C TJ）和
LM5050Q1MK-1（高达 125°C TJ）
LM5050-1/-Q1 高侧 OR-ing FET 控制器与外部
MOSFET 配合工作，当与电源串联时则用作理想的二
极管整流器。此 ORing 控制器可使 MOSFET 替换电
源分配网络中的二极管整流器，从而降低功率损耗和压
降。
•
•
提供功能安全
–
提供文档以帮助创建功能安全系统设计
宽工作输入电压范围 VIN：1V 至 75V（VIN < 5V 时
需要 VBIAS
LM5050-1/-Q1 控制器为外部 N 沟道 MOSFET 和快速
响应比较器提供电荷泵栅极驱动，以在电流反向流动时
关断 FET。LM5050-1/-Q1 可连接 5V 至 75V 的电
源，可承受高达 100V 的瞬态电压。
）
•
•
•
•
•
•
100V 瞬态电压
适用于外部 N 沟道 MOSFET 的电荷泵栅极驱动器
针对电流反向 50ns 快速响应
2A 峰值栅极关断电流
器件信息(1)
超小 VDS 关断电压，可缩短关断时间
封装：SOT-6（薄型 SOT-23-6）
器件型号
LM5050-1
LM5050-1-Q1
封装
封装尺寸（标称值）
SOT (6)
2.90mm × 1.60mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
冗余 (N+1) 电源的有源 OR-ing
完整应用
V
V
OUT
IN
+5.0V to +75V
100W
IN
GATE
LM5050-1
GND
OUT
VS
Low= FET On, High= FET Off
Shutdown
GND
OFF
0.1 mF
GND
典型冗余电源配置
PS1
IN GATE OUT
LM5050-1
VS
GND
C
LOAD
R
LOAD
PS2
IN
GATE
LM5050-1
GND
OUT
VS
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVS629
LM5050-1, LM5050-1-Q1
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Applications ................................................ 16
Power Supply Recommendations...................... 21
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings: LM5050-1 .......................................... 4
6.3 ESD Ratings: LM5050-1-Q1 ..................................... 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics........................................... 5
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
8
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 器件和文档支持 ..................................................... 22
11.1 文档支持................................................................ 22
11.2 相关链接................................................................ 22
11.3 社区资源................................................................ 22
11.4 商标....................................................................... 22
11.5 静电放电警告......................................................... 22
11.6 Glossary................................................................ 22
12 机械、封装和可订购信息....................................... 22
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision E (December 2015) to Revision F
Page
•
向特性 部分添加了提供功能安全的链接.................................................................................................................................. 1
Changes from Revision D (June 2013) to Revision E
Page
•
已添加 添加了 ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部
分、器件和文档支持 部分以及机械、封装和可订购信息 部分 ................................................................................................ 1
2
Copyright © 2011–2019, Texas Instruments Incorporated
LM5050-1, LM5050-1-Q1
www.ti.com.cn
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
5 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
VS 1
GND 2
OFF 3
6 OUT
5 GATE
4 IN
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
The main supply pin for all internal biasing and an auxiliary supply for the internal gate drive
charge pump. Typically connected to either VOUT or VIN; a separate supply can also be used.
VS
I
2
GND
PWR
Ground return for the controller
A logic high state at the OFF pin will pull the GATE pin low and turn off the external MOSFET.
Note that when the MOSFET is off, current will still conduct through the FET's body diode. This
pin should may be left open or connected to GND if unused.
3
OFF
I
4
5
6
IN
I
Voltage sense connection to the external MOSFET Source pin.
Connect to the Gate of the external MOSFET. Controls the MOSFET to emulate a low forward-
voltage diode.
GATE
OUT
O
O
Voltage sense connection to the external MOSFET Drain pin.
Copyright © 2011–2019, Texas Instruments Incorporated
3
LM5050-1, LM5050-1-Q1
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
−65
MAX
100
100
100
7
UNIT
V
IN, OUT Pins to Ground(2)
GATE Pin to Ground(2)
VS Pin to Ground
V
V
OFF Pin to Ground
V
Storage Temperature
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The GATE pin voltage is typically 12 V above the IN pin voltage when the LM5050-1 is enabled (that is, OFF Pin is Open or Low, and
VIN > VOUT). Therefore, the absolute maximum rating for the IN pin voltage applies only when the LM5050-1 is disabled (that is, OFF
Pin is logic high), or for a momentary surge to that voltage because the Absolute Maximum Rating for the GATE pin is also 100 V
6.2 ESD Ratings: LM5050-1
VALUE
±2000
±150
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Machine model (MM)(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) The MM is a 200-pF capacitor discharged through a 0-Ω resistor (that is, directly) into each pin. Applicable test standard is JESD-A115-
A.
6.3 ESD Ratings: LM5050-1-Q1
VALUE
±2000
±150
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Machine model (MM)(2)
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) The MM is a 200-pF capacitor discharged through a 0-Ω resistor (that is, directly) into each pin. Applicable test standard is JESD-A115-
A.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
5
MAX
75
UNIT
V
IN, OUT, VS Pins
OFF Pin
0
5.5
V
Standard Grade
LM5050Q0MK-1
LM5050Q1MK-1
−40
−40
−40
125
150
125
°C
°C
°C
Junction Temperature (TJ)
6.5 Thermal Information
LM5050-1/-Q1
DDC (SOT)
6 PINS
180.7
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
41.3
28.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.7
ψJB
27.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2011–2019, Texas Instruments Incorporated
LM5050-1, LM5050-1-Q1
www.ti.com.cn
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
Thermal Information (continued)
LM5050-1/-Q1
THERMAL METRIC(1)
DDC (SOT)
6 PINS
N/A
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
6.6 Electrical Characteristics
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12 V, VVS = VIN, VOUT = VIN, VOFF = 0 V, CGATE= 47 nF, and TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VS PIN
Operating
VVS
Supply Voltage
TJ = –40°C to 125°C
5
75
V
Range
TJ = 25°C
75
100
130
VVS= 5 V, VIN = 5 V
VOUT = VIN - 100 mV
TJ = –40°C to 125°C
TJ = 25°C
105
147
288
Operating
Supply Current
VVS= 12 V, VIN = 12 V
VOUT = VIN - 100 mV
IVS
μA
TJ = –40°C to 125°C
TJ = 25°C
VVS= 75 V, VIN = 75 V
VOUT = VIN - 100 mV
TJ = –40°C to 125°C
IN PIN
Operating Input
Voltage Range
VIN
TJ = –40°C to 125°C
5
75
V
VIN = 5 V
VVS= VIN
VOUT = VIN - 100 mV
GATE = Open
TJ = 25°C
190
320
TJ = –40°C to 125°C
32
305
IIN
IN Pin current
μA
TJ = 25°C
VIN = 12 V to 75 V
VVS= VIN
VOUT = VIN - 100 mV
GATE = Open
LM5050MK-1,
LM5050Q1MK-1
TJ = –40°C to 125°C
TJ = –40°C to 125°C
233
233
400
475
LM5050Q0MK-1
OUT PIN
Operating
Output Voltage
Range
VOUT
TJ = –40°C to 125°C
VIN = 5 V to 75 V
5
75
8
V
TJ = 25°C
3.2
IOUT
OUT Pin Current VVS= VIN
VOUT = VIN - 100 mV
µA
TJ = –40°C to 125°C
GATE PIN
VIN = 5 V
VVS = VIN
VGATE = VIN
VOUT = VIN - 175 mV
TJ = 25°C
30
32
TJ = –40°C to 125°C
TJ = 25°C
12
20
41
41
Gate Pin Source
Current
IGATE(ON)
µA
VIN = 12 V to 75 V
VVS = VIN
VGATE = VIN
TJ = –40°C to 125°C
VOUT = VIN - 175 mV
VIN = 5 V
TJ = 25°C
7
VVS = VIN
VOUT = VIN - 175 mV
VGATE - VIN in
Forward
TJ = –40°C to 125°C
TJ = 25°C
4
9
9
VGS
V
Operation(1)
VIN = 12 V to 75 V
VVS = VIN
VOUT = VIN - 175 mV
12
TJ = –40°C to 125°C
14
(1) Measurement of VGS voltage (that is. VGATE - VIN) includes 1 MΩ in parallel with CGATE
.
Copyright © 2011–2019, Texas Instruments Incorporated
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LM5050-1, LM5050-1-Q1
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
www.ti.com.cn
Electrical Characteristics (continued)
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12 V, VVS = VIN, VOUT = VIN, VOFF = 0 V, CGATE= 47 nF, and TJ = 25°C.
PARAMETER
TEST CONDITIONS
TJ = 25°C
MIN
TYP
MAX UNIT
Gate
Capacitance
Discharge Time
tGATE(REV) at Forward to
Reverse
25
CGATE = 0(2)
TJ = –40°C to 125°C
TJ = 25°C
85
ns
CGATE = 10 nF(2)
CGATE = 47 nF(2)
60
TJ = 25°C
180
Transition
See Figure 1
TJ = –40°C to 125°C
350
Gate
Capacitance
DischargeTime
tGATE(OFF) at OFF pin Low CGATE = 47 nF(3)
TJ = 25°C
TJ = 25°C
486
2.8
ns
to High
Transition
See Figure 2
VGATE = VIN + 3 V
Gate Pin Sink
Current
LM5050MK-1,
LM5050Q1MK-1
IGATE(OFF)
VOUT > VIN + 100 mV TJ = –40°C to 125°C
t ≤ 10 ms
1.8
1.4
A
TJ = –40°C to 125°C
LM5050Q0MK-1
Reverse VSD
Threshold
VIN < VOUT
TJ = 25°C
–28
VSD(REV)
VIN - VOUT
mV
TJ = –40°C to 125°C
–41
–16
Reverse VSD
Hysteresis
ΔVSD(REV)
TJ = 25°C
TJ = 25°C
10
19
mV
LM5050MK-1,
LM5050Q1MK-1
VIN = 5 V
VVS = VIN
VIN - VOUT
TJ = –40°C to 125°C
1
1
37
Regulated
Forward VSD
Threshold
VIN > VOUT
TJ = –40°C to 125°C
TJ = 25°C
LM5050Q0MK-1
60
VSD(REG)
mV
22
LM5050MK-1,
LM5050Q1MK-1
VIN = 12 V
VVS = VIN
VIN - VOUT
TJ = –40°C to 125°C
TJ = –40°C to 125°C
4.4
4.4
37
60
LM5050Q0MK-1
OFF PIN
OFF Input High
Threshold
Voltage
TJ = 25°C
1.56
1.4
VOUT = VIN-500 mV
VOFF Rising
VOFF(IH)
TJ = –40°C to 125°C
TJ = 25°C
1.75
V
OFF Input Low
Threshold
Voltage
VOUT = VIN - 500 mV
VOFF Falling
VOFF(IL)
TJ = –40°C to 125°C
1.1
OFF Threshold
Voltage
Hysteresis
ΔVOFF
VOFF(IH) - VOFF(IL)
TJ = 25°C
155
5
mV
TJ = 25°C
VOFF = 4.5 V
VOFF = 5 V
OFF Pin Internal
Pulldown
IOFF
TJ = –40°C to 125°C
TJ = 25°C
3
7
µA
8
(2) Time from VIN-VOUT voltage transition from 200 mV to -500 mV until GATE pin voltage falls to VIN + 1 V. See Figure 1.
(3) Time from VOFF voltage transition from 0 V to 5 V until GATE pin voltage falls to VIN + 1 V. See Figure 2
6
Copyright © 2011–2019, Texas Instruments Incorporated
LM5050-1, LM5050-1-Q1
www.ti.com.cn
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
200 mV
V
SD(REG)
V
V
> V
< V
IN
OUT
0 mV
IN
OUT
V
SD(REV)
-500 mV
t
GATE(OFF)
V
GATE
1.0V
0.0V
Figure 1. Gate OFF Timing for Forward to Reverse Transition
5.0V
V
OFF(IH)
V
OFF(IL)
0.0V
t
GATE(OFF)
V
GATE
1.0V
0.0V
Figure 2. Gate OFF Timing for OFF Pin Low to High Transition
Copyright © 2011–2019, Texas Instruments Incorporated
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LM5050-1, LM5050-1-Q1
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
www.ti.com.cn
6.7 Typical Characteristics
Unless otherwise stated: VVS = 12 V, VIN = 12 V, VOFF = 0 V, and TJ = 25°C
Figure 3. IIN vs VIN
Figure 4. IIN vs VIN
Figure 6. IOUT vs VOUT
Figure 8. IVS vs VVS
Figure 5. IOUT vs VOUT
Figure 7. IVS vs VVS
8
Copyright © 2011–2019, Texas Instruments Incorporated
LM5050-1, LM5050-1-Q1
www.ti.com.cn
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
Typical Characteristics (continued)
Unless otherwise stated: VVS = 12 V, VIN = 12 V, VOFF = 0 V, and TJ = 25°C
Figure 9. (VGATE - VIN) vs VIN, VVS = VOUT
Figure 10. (VGATE - VIN) vs VIN, VVS = VOUT
26
26
Vin
Vout
Vgate
Vin
Vout
Vgate
24
24
22
20
18
16
14
12
10
22
20
18
16
14
12
10
-5
0
5
10
15
20
25
30
-50
0
50
100 150 200 250
TIME (5ms / DIV)
TIME (50ns / DIV)
Figure 11. Forward CGATE Charge Time, CGATE = 47 nF
Figure 12. Reverse CGATE Discharge, CGATE = 47 nF
Figure 13. VGATE - VIN vs Temperature
Figure 14. tGATE(REV) vs Temperature
Copyright © 2011–2019, Texas Instruments Incorporated
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LM5050-1, LM5050-1-Q1
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
www.ti.com.cn
Typical Characteristics (continued)
Unless otherwise stated: VVS = 12 V, VIN = 12 V, VOFF = 0 V, and TJ = 25°C
Figure 15. OFF Pin Thresholds vs Temperature
Figure 16. OFF Pin Pulldown vs Temperature
Figure 17. CGATE Charge and Discharge vs OFF Pin
Figure 18. OFF Pin, ON to OFF Transition
Figure 20. GATE Pin vs (RDS(ON) × IDS
)
Figure 19. OFF Pin, OFF to ON Transition
10
Copyright © 2011–2019, Texas Instruments Incorporated
LM5050-1, LM5050-1-Q1
www.ti.com.cn
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
7 Detailed Description
7.1 Overview
Blocking diodes are commonly placed in series with supply inputs for the purpose of ORing redundant power
sources and protecting against supply reversal. The LM5050 replaces diodes in these applications with an N-
MOSFET to reduce both the voltage drop and power loss associated with a passive solution. At low input
voltages, the improvement in forward voltage loss is readily appreciated where headroom is tight, as shown in
Figure 2. The LM5050 operates from 5 V to 75 V and it can withstand an absolute maximum of 100 V without
damage. A 12-V or 15-A ideal diode application is shown in Figure 24. Several external components are included
in addition to the MOSFET, Q1. Ideal diodes, like their non-ideal counterparts, exhibit a behavior known as
reverse recovery. In combination with parasitic or intentionally introduced inductances, reverse recovery spikes
may be generated by an ideal diode during an reverse current shutdown. D1, D2 and R1 protect against these
spikes which might otherwise exceed the LM5050 100-V survival rating. COUT also plays a role in absorbing
reverse recovery energy. Spikes and protection schemes are discussed in detail in the Short Circuit Failure of an
Input Supply section.
NOTE
The OFF pin may be used to active the GATE pull down circuit and turn off the pass
MOSFET, but it does not disconnect the load from the input because Q1’s body diode is
still present.
If Vs is powered while IN is floating or grounded, then about 0.5mA will leak from the Vs
pin into the IC and about 3mA will leak from the OUT pin into the IC. From this leakage,
about 50 uA will flow out of the IN pin and the rest will flow to ground. This does not affect
long term reliability of the IC, but may influence circuit design. See Reverse Input Voltage
Protection With IQ Reduction for details on how to avoid this leakage current.
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7.2 Functional Block Diagram
INPUT
LOAD
IN
GATE
OUT
14V
30 µA
+12V Charge
Pump
30 mV
+
-
2A
MOSFET Off
35 µA
30 mV
Reverse
Comparator
-
+
Bias
Circuitry
VS
OFF
5 µA
1.5V
GND
LM5050- 1
7.3 Feature Description
7.3.1 IN, GATE, and OUT Pins
When power is initially applied, the load current will flow from source to drain through the body diode of the
MOSFET. Once the voltage across the body diode exceeds VSD(REG) then the LM5050-1 begins charging the
MOSFET gate through a 32 µA (typical) charge pump current source . In forward operation, the gate of the
MOSFET is charged until it reaches the clamping voltage of the 12-V GATE to IN pin Zener diode internal to the
LM5050-1.
The LM5050-1 is designed to regulate the MOSFET gate-to-source voltage. If the MOSFET current decreases to
the point that the voltage across the MOSFET falls below the VSD(REG) voltage regulation point of 22 mV (typical),
the GATE pin voltage will be decreased until the voltage across the MOSFET is regulated at 22 mV. If the
source-to-drain voltage is greater than the VSD(REG) voltage, the gate-to-source voltage will increase and
eventually reach the 12-V GATE to IN pin Zener clamp level.
12
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LM5050-1, LM5050-1-Q1
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ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
Feature Description (continued)
If the MOSFET current reverses, possibly due to failure of the input supply, such that the voltage across the
LM5050-1 IN and OUT pins is more negative than the VSD(REV) voltage of -28 mV (typical), the LM5050-1 will
quickly discharge the MOSFET gate through a strong GATE to IN pin discharge transistor.
If the input supply fails abruptly, as would occur if the supply was shorted directly to ground, a reverse current
will temporarily flow through the MOSFET until the gate can be fully discharged. This reverse current is sourced
from the load capacitance and from the parallel connected supplies. The LM5050-1 responds to a voltage
reversal condition typically within 25 ns. The actual time required to turn off the MOSFET will depend on the
charge held by the gate capacitance of the MOSFET being used. A MOSFET with 47 nF of effective gate
capacitance can be turned off in typically 180 ns. This fast turnoff time minimizes voltage disturbances at the
output, as well as the current transients from the redundant supplies.
7.3.2 VS Pin
The LM5050-1 VS pin is the main supply pin for all internal biasing and an auxiliary supply for the internal gate
drive charge pump.
For typical LM5050-1 applications, where the input voltage is above 5 V, the VS pin can be connected directly to
the OUT pin. In situations where the input voltage is close to, but not less than, the 5 V minimum, it may be
helpful to connect the VS pin to the OUT pin through an RC Low-Pass filter to reduce the possibility of erratic
behavior due to spurious voltage spikes that may appear on the OUT and IN pins. The series resistor value
should be low enough to keep the VS voltage drop at a minimum. A typical series resistor value is 100 Ω. The
capacitor value should be the lowest value that produces acceptable filtering of the voltage noise.
If Vs is powered while IN is floating or grounded, then about 0.5 mA will leak from the Vs pin into the IC and
about 3mA will leak from the OUT pin into the IC. From this leakage, about 50 uA will flow out of the IN pin and
the rest will flow to ground. This does not affect long term reliability of the IC, but may influence circuit design.
See Reverse Input Voltage Protection With IQ Reduction for details on how to avoid this leakage current.
Alternately, it is possible to operate the LM5050-1 with VIN value as low as 1 V if the VS pin is powered from a
separate supply. This separate VS supply must be from 5 V and 75 V. See Figure 27.
7.3.3 OFF Pin
The OFF pin is a logic level input pin that is used to control the gate drive to the external MOSFET. The
maximum operating voltage on this pin is 5.5 V.
When the OFF pin is high, the MOSFET is turned off (independent of the sensed IN and OUT voltages). In this
mode, load current will flow through the body diode of the MOSFET. The voltage difference between the IN pin
and OUT pins will be approximately 700 mV if the MOSFET is operating normally through the body diode.
The OFF pin has an internal pulldown of 5 µA (typical). If the OFF function is not required the pin may be left
open or connected to ground.
7.4 Device Functional Modes
7.4.1 ON/OFF Control Mode
The MOSFET can be turned off by asserting the OFF pin high. This mode only disables the MOSFET, but VOUT
is still available through the body diode of the MOSFET.
7.4.2 External Power Supply Mode
The Vs pin of the LM5050 can be operated from 5 V to 75 V as the bias input supply. In this mode VIN voltage
can be as low as 1 V, as shown in Figure 27.
Copyright © 2011–2019, Texas Instruments Incorporated
13
LM5050-1, LM5050-1-Q1
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Systems that require high availability often use multiple, parallel-connected redundant power supplies to improve
reliability. Schottky OR-ing diodes are typically used to connect these redundant power supplies to a common
point at the load. The disadvantage of using OR-ing diodes is the forward voltage drop, which reduces the
available voltage and the associated power losses as load currents increase. Using an N-channel MOSFET to
replace the OR-ing diode requires a small increase in the level of complexity, but reduces, or eliminates, the
need for diode heat sinks or large thermal copper area in circuit board layouts for high power applications.
PS1
C
LOAD
R
LOAD
PS2
Figure 21. OR-ing with Diodes
The LM5050-1/-Q1 is a positive voltage (that is, high-side) OR-ing controller that will drive an external N-channel
MOSFET to replace an OR-ing diode. The voltage across the MOSFET source and drain pins is monitored by
the LM5050-1 at the IN and OUT pins, while the GATE pin drives the MOSFET to control its operation based on
the monitored source-drain voltage. The resulting behavior is that of an ideal rectifier with source and drain pins
of the MOSFET acting as the anode and cathode pins of a diode respectively.
PS1
IN
GATE OUT
LM5050-1
VS
GND
C
LOAD
R
LOAD
PS2
IN
GATE
LM5050-1
GND
OUT
VS
Figure 22. OR-ing With MOSFETs
14
Copyright © 2011–2019, Texas Instruments Incorporated
LM5050-1, LM5050-1-Q1
www.ti.com.cn
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
Application Information (continued)
8.1.1 MOSFET Selection
The important MOSFET electrical parameters are the maximum continuous Drain current ID, the maximum
Source current (that is, body diode) IS, the maximum drain-to-source voltage VDS(MAX), the gate-to-source
threshold voltage VGS(TH), the drain-to-source reverse breakdown voltage V(BR)DSS, and the drain-to-source On
resistance RDS(ON)
.
The maximum continuous drain current, ID, rating must exceed the maximum continuous load current. The rating
for the maximum current through the body diode, IS, is typically rated the same as, or slightly higher than the
drain current, but body diode current only flows while the MOSFET gate is being charged to VGS(TH)
.
Gate Charge Time = Qg / IGATE(ON)
1. The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential
voltage seen in the application. This would include any anticipated fault conditions.
2. The drain-to-source reverse breakdown voltage, V(BR)DSS, may provide some transient protection to the OUT
pin in low voltage applications by allowing conduction back to the IN pin during positive transients at the OUT
pin.
3. The gate-to-source threshold voltage, VGS(TH), should be compatible with the LM5050-1 gate drive
capabilities. Logic level MOSFETs, with RDS(ON) rated at VGS(TH) at 5 V, are recommended, but sub-Logic
level MOSFETs having RDS(ON) rated at VGS(TH) at 2.5 V, can also be used.
4. The dominate MOSFET loss for the LM5050-1 active OR-ing controller is conduction loss due to source-to-
drain current to the output load, and the RDS(ON) of the MOSFET. This conduction loss could be reduced by
using a MOSFET with the lowest possible RDS(ON). However, contrary to popular belief, arbitrarily selecting a
MOSFET based solely on having low RDS(ON) may not always give desirable results for several reasons:
1. Reverse transition detection. Higher RDS(ON) will provide increased voltage information to the LM5050-1
Reverse Comparator at a lower reverse current level. This will give an earlier MOSFET turnoff condition
should the input voltage become shorted to ground. This will minimize any disturbance of the redundant
bus.
2. Reverse current leakage. In cases where multiple input supplies are closely matched it may be possible
for some small current to flow continuously through the MOSFET drain to source (that is, reverse)
without activating the LM5050-1 Reverse Comparator. Higher RDS(ON) will reduce this reverse current
level.
3. Cost. Generally, as the RDS(ON) rating goes lower, the cost of the MOSFET goes higher.
5. The dominate MOSFET loss for the LM5050-1 active OR-ing controller is conduction loss due to source-to-
drain current to the output load, and the RDS(ON) of the MOSFET. This conduction loss could be reduced by
using a MOSFET with the lowest possible RDS(ON). However, contrary to popular belief, arbitrarily selecting a
MOSFET based solely on having low RDS(ON) may not always give desirable results for several reasons:
a. Selecting a MOSFET with an RDS(ON) that is too large will result in excessive power dissipation.
Additionally, the MOSFET gate will be charged to the full value that the LM5050-1 can provide as it
attempts to drive the Drain to Source voltage down to the VSD(REG) of 22 mV typical. This increased Gate
charge will require some finite amount of additional discharge time when the MOSFET needs to be
turned off.
b. As a guideline, it is suggest that RDS(ON) be selected to provide at least 22 mV, and no more than 100
mV, at the nominal load current.
c. (22 mV / ID) ≤ RDS(ON) ≤ (100 mV / ID)
d. The thermal resistance of the MOSFET package should also be considered against the anticipated
dissipation in the MOSFET to ensure that the junction temperature (TJ) is reasonably well controlled,
because the RDS(ON) of the MOSFET increases as the junction temperature increases.
6. PDISS = ID2 × (RDS(ON)
)
7. Operating with a maximum ambient temperature (TA(MAX)) of 35°C, a load current of 10 A, and an RDS(ON) of
10 mΩ, and desiring to keep the junction temperature under 100°C, the maximum junction-to-ambient
thermal resistance rating (θJA) must be:
a. RθJA ≤ (TJ(MAX) - TA(MAX))/(ID2 × RDS(ON)
)
b. RθJA ≤ (100°C - 35°C)/(10 A × 10 A × 0.01 Ω)
Copyright © 2011–2019, Texas Instruments Incorporated
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LM5050-1, LM5050-1-Q1
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www.ti.com.cn
Application Information (continued)
c. RθJA ≤ 65°C/W
8.1.2 Short Circuit Failure of an Input Supply
An abrupt 0-Ω short circuit across the input supply will cause the highest possible reverse current to flow while
the internal LM5050-1 control circuitry discharges the gate of the MOSFET. During this time, the reverse current
is limited only by the RDS(ON) of the MOSFET, along with parasitic wiring resistances and inductances. Worst
case instantaneous reverse current would be limited to:
ID(REV) = (VOUT - VIN) / RDS(ON)
(1)
The internal Reverse Comparator will react, and will start the process of discharging the Gate, when the reverse
current reaches:
ID(REV) = VSD(REV) / RDS(ON)
(2)
When the MOSFET is finally switched off, the energy stored in the parasitic wiring inductances will be transferred
to the rest of the circuit. As a result, the LM5050-1 IN pin will see a negative voltage spike while the OUT pin will
see a positive voltage spike. The IN pin can be protected by diode clamping the pin to GND in the negative
direction. The OUT pin can be protected with a TVS protection diode, a local bypass capacitor, or both. In low
voltage applications, the MOSFET drainto- source breakdown voltage rating may be adequate to protect the
OUT pin (that is, VIN + V(BR)DSS(MAX) < 75 V ), but most MOSFET data sheets do not ensure the maximum
breakdown rating, so this method should be used with caution.
Parasitic
Inductance
Parasitic
Inductance
Reverse Recovery Current
C
OUT
C
LOAD
IN
GATE OUT
LM5050-1
Shorted
Input
VS
GND
Figure 23. Reverse Recovery Current Generates Inductive Spikes at VIN and VOUT pins.
8.2 Typical Applications
8.2.1 Typical Application With Input and Output Transient Protection
Q1
SUM40N10-30
V
IN
V
OUT
48V
S
D
D1
G
C
SS16T3
IN
R1
1 mF
75V
C
OUT
100W
+
OUT
VS
IN
GATE
D2
SMBJ60A
22 mF
63V
LM5050-1
C1
0.1 mF
100V
OFF
OFF/ON
GND
GND
GND
Figure 24. Typical Application With Input and Output Transient Protection Schematic
16
Copyright © 2011–2019, Texas Instruments Incorporated
LM5050-1, LM5050-1-Q1
www.ti.com.cn
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
Typical Applications (continued)
8.2.1.1 Design Requirements
Table 1 shows the parameters for Figure 24
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Minimum Input Voltage, VINMIN
Maximum Input Voltage, VINMax
Output Current Range, IOUT
Ambient Temperature Range, TA
6 V
50 V
0 to 15 A
0°C to 50°C
8.2.1.2 Detailed Design Procedure
The following design procedure can be used to select component values for the LM5050-1.
8.2.1.2.1 Power Supply Components (R1 C1,) Selection
The LM5050-1 VS pin is the main supply pin for all internal biasing and an auxiliary supply for the internal gate
drive charge pump. The series resistor (R1) value should be low enough to keep the VS voltage drop at a
minimum. A typical series resistor value is 100 Ω. The capacitor value (0.1 uF typical) should be the lowest value
that produces acceptable filtering of the voltage noise.
8.2.1.2.2 MOSFET (Q1) Selection
The MOSFET (Q1) selection procedure is explained in detail in MOSFET Selection. The MOSFET used in the
design example is SUM40N10-30-E3.
8.2.1.2.3 D1 and D2 Selection for Inductive Kick-Back Protection
Diode D1 and capacitor C1 and diode D2 and capacitor C2 in the Figure 27 serve as inductive kick-back
protection to limit negative transient voltage spikes generated on the input when the input supply voltage is
abruptly shorted to zero volts. As a result, the LM5050-1 IN pin will see a negative voltage spike while the OUT
pin will see a positive voltage spike. The IN pin can be protected by schottky diode (D1) clamping the pin to GND
in the negative direction, similarly the OUT pin should be protected with a TVS protection diode (D1), or with a
local bypass capacitor, or both. D1 is selected as 1-A, 60-V Schottky Barrier Rectifier (SS16T3G) and D2 is the
60 V, TVS (SMBJ60A-13-F).
8.2.1.3 Application Curves
Figure 25. Forward voltage (VIN-VOUT) Drop Reduces
When Gate is Enabled (VIN = 12 V)
Figure 26. Forward Voltage (VIN-VOUT) Drop Increases
When Gate is Disabled (VIN = 12 V)
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LM5050-1, LM5050-1-Q1
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
www.ti.com.cn
8.2.2 Using a Separate VS Supply for Low Vin Operation
In some applications, it is desired to operate LM5050-1 from low supply voltage. The LM5050-1 can operate with
a 1-V rail voltage, provided its VS pin is biased from 5 V to 75 V. The detail of such application is depicted in
Figure 27.
V
BIAS
5.0V to 75V
GND
Q1
V
IN
V
OUT
1V to 75V
C1
R1
D1
1.0 mF
100V
100
+
OUT
VS
IN
GATE
C2
D2
22 mF
100V
TVS
82V
LM5050-1
C3
0.1 mF
100V
Off/On
GND
OFF
GND
GND
Figure 27. Using a Separate vs Supply for Low Vin Operation Schematic
8.2.3 ORing of Two Power Sources
C
LOAD
R
LOAD
PS1
IN
GATE OUT
LM5050-1
GND
VS
C
OUT
PS2
IN
GATE OUT
LM5050-1
GND
VS
Figure 28. ORing of Two Power Sources
18
Copyright © 2011–2019, Texas Instruments Incorporated
LM5050-1, LM5050-1-Q1
www.ti.com.cn
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
8.2.4 Reverse Input Voltage Protection With IQ Reduction
If Vs is powered while IN is floating or grounded, then about 0.5 mA will leak from the Vs pin into the IC and
about 3 mA will leak from the OUT pin into the IC. From this leakage, about 50 uA will flow out of the IN pin and
the rest will flow to ground. This does not affect long term reliability of the IC, but may influence circuit design.
In battery powered applications, whenever LM5050-1 functionality is not needed, the supply to the LM5050-1 can
be disconnected by turning “OFF” Q2, as shown in Figure 29. This disconnects the ground path of the LM5050-1
and eliminates the current leakage from the battery.
The quiescent current of LM5050-1 can be also reduced by disconnecting the supply to VS pin, whenever
LM5050-1 function is not need.
Q1
SUM40N10-30
VIN
48V
VOUT
R1
100»
IN
GATE
OUT
VS
D1
LM5050-1
GND
SS16T3
D4
SMBJ60A
CIN
Cout
22uF
63V
1uF
75V
D2
BAS40-7-F
D3
SS16T3
C1
0.1µF
100V
Q2
NTR5198NLT3G
ON/OFF
Control
GND
GND
Figure 29. Reverse Input Voltage Protection With IQ Reduction Schematic
8.2.5 Basic Application With Input Transient Protection
Q1
SUM40N10-30
V
IN
V
OUT
S
D
5.0V to 75V
D1
G
C
B180-13-F
IN
1 mF
100V
OUT
VS
IN
GATE
LM5050-1
OFF
OFF/ON
GND
GND
GND
Figure 30. Basic Application With Input Transient Protection Schematic
Copyright © 2011–2019, Texas Instruments Incorporated
19
LM5050-1, LM5050-1-Q1
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
www.ti.com.cn
8.2.6 48-V Application With Reverse Input Voltage (VIN = –48 V) Protection
Q1
SUM40N10-30
V
IN
V
OUT
48V
S
D
D1
G
C
SS16T3
IN
R1
1 mF
75V
C
OUT
100W
+
OUT
VS
IN
GATE
D2
SMBJ60A
22 mF
63V
LM5050-1
C1
0.1 mF
100V
OFF
GND
D3
SS16T3
GND
GND
Figure 31. 48-V Application With Reverse Input Voltage (VIN = –48 V) Protection Schematic
8.2.6.1 Application Curves
Figure 32. Operation With Positive Polarity Input With
(VIN = 25 V)
Figure 33. Operation With Negative polarity Input With
(VIN = –25 V)
20
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LM5050-1, LM5050-1-Q1
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ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
9 Power Supply Recommendations
When the LM5050-1/-Q1 shuts off the external MOSFET, transient voltages will appear on the input and output
due to reverse recovery, as discussed in Short Circuit Failure of an Input Supply.To prevent LM5050-1 and
surrounding components from damage under the conditions of a direct input short circuit, it is necessary to clamp
the negative transient at IN, and OUT pins with TVS.
10 Layout
10.1 Layout Guidelines
The typical PCB layout for LM5050-1/-Q1 is shown in Figure 34. TI recommends connecting the IN, Gate and
OUT pins close to the source and drain pins of the MOSFET. Keep the traces of the MOSFET drain wide and
short to minimize resistive losses. Place surge suppressors (D1 and D4) components as shown in the example
layout of LM5050-1 in Layout Example.
10.2 Layout Example
R1
VS
OUT
Gate
GND
VOUT
OFF
IN
LM5050-1
D1
CIN
VIN
D4
GND
Figure 34. Typical Layout Example With D2PAK N-MOSFET
版权 © 2011–2019, Texas Instruments Incorporated
21
LM5050-1, LM5050-1-Q1
ZHCSKM9F –MAY 2011–REVISED DECEMBER 2019
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
《使用具有低电流和高噪声输入电源的 LM5050-1 实现稳定 VGS》，SLVA684
11.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 2. 相关链接
器件
产品文件夹
单击此处
单击此处
样片与购买
单击此处
单击此处
技术文档
单击此处
单击此处
工具与软件
单击此处
单击此处
支持和社区
单击此处
单击此处
LM5050-1
LM5050-1-Q1
11.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
22
版权 © 2011–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5050MK-1/NOPB
LM5050MKX-1/NOPB
LM5050Q0MK-1/NOPB
LM5050Q0MKX-1/NOPB
LM5050Q1MK-1/NOPB
LM5050Q1MKX-1/NOPB
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
DDC
DDC
DDC
DDC
6
6
6
6
6
6
1000 RoHS & Green
3000 RoHS & Green
1000 RoHS & Green
3000 RoHS & Green
1000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 150
-40 to 150
-40 to 125
-40 to 125
SZHB
SZHB
SL5B
SL5B
SP3B
SP3B
SN
SN
SN
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5050MK-1/NOPB
SOT-23-
THIN
DDC
DDC
DDC
DDC
DDC
DDC
6
6
6
6
6
6
1000
3000
1000
3000
1000
3000
178.0
178.0
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
LM5050MKX-1/NOPB SOT-23-
THIN
LM5050Q0MK-1/NOPB SOT-23-
THIN
LM5050Q0MKX-1/NOPB SOT-23-
THIN
LM5050Q1MK-1/NOPB SOT-23-
THIN
LM5050Q1MKX-1/NOPB SOT-23-
THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5050MK-1/NOPB
LM5050MKX-1/NOPB
LM5050Q0MK-1/NOPB
LM5050Q0MKX-1/NOPB
LM5050Q1MK-1/NOPB
LM5050Q1MKX-1/NOPB
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
DDC
DDC
DDC
DDC
DDC
DDC
6
6
6
6
6
6
1000
3000
1000
3000
1000
3000
208.0
208.0
208.0
208.0
208.0
208.0
191.0
191.0
191.0
191.0
191.0
191.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
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EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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