LM5100CMA [TI]
1A HALF BRDG BASED MOSFET DRIVER, PDSO8, MS-012AA, SOIC-8;
| 型号： | LM5100CMA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1A HALF BRDG BASED MOSFET DRIVER, PDSO8, MS-012AA, SOIC-8 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总36页 (文件大小：1826K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
LM5100A/B/C, LM5101A/B/C 3-A, 2-A, and 1-A High-Voltage, High-Side
and Low-Side Gate Drivers
An integrated high-voltage diode is provided to
charge the high-side gate drive bootstrap capacitor. A
robust level shifter operates at high speed while
consuming low power and providing clean level
transitions from the control logic to the high-side gate
driver. Undervoltage lockout is provided on both the
low-side and the high-side power rails. These devices
are available in the standard SOIC-8 pin, SO
PowerPAD-8 pin, and the WSON-10 pin packages.
The LM5100C and LM5101C are also available in
MSOP-PowerPAD-8 package. The LM5101A is also
available in WSON-8 pin package.
1 Features
1
•
Drives Both a High-Side and Low-Side N-Channel
MOSFETs
•
•
•
•
Independent High- and Low-Driver Logic Inputs
Bootstrap Supply Voltage up to 118 V DC
Fast Propagation Times (25-ns Typical)
Drives 1000-pF Load With 8-ns Rise and Fall
Times
•
Excellent Propagation Delay Matching (3-ns
Typical)
•
•
•
Supply Rail Undervoltage Lockout
Low Power Consumption
Device Information(1)
PEAK OUTPUT
PART NUMBER INPUT THRESHOLD
CURRENT
Pin Compatible With HIP2100/HIP2101
LM5100A
LM5101A
LM5100B
LM5101B
LM5100C
LM5101C
CMOS
TTL
3 A
3 A
2 A
2 A
1 A
1 A
2 Applications
CMOS
TTL
•
•
•
•
•
Current-Fed Push-Pull Converters
Half and Full Bridge Power Converters
Synchronous Buck Converters
CMOS
TTL
Two Switch Forward Power Converters
Forward with Active Clamp Converters
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
The LM5100A/B/C and LM5101A/B/C high-voltage
gate drivers are designed to drive both the high-side
and the low-side N-Channel MOSFETs in
a
synchronous buck or a half-bridge configuration. The
floating high-side driver is capable of operating with
supply voltages up to 100 V. The A versions provide
a full 3-A of gate drive, while the B and C versions
provide 2 A and 1 A, respectively. The outputs are
independently controlled with CMOS input thresholds
(LM5100A/B/C) or TTL input thresholds
(LM5101A/B/C).
Simplified Block Diagram
HB
UVLO
HO
HS
DRIVER
LEVEL
SHIFT
HI
LI
VDD
UVLO
LO
DRIVER
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
Table of Contents
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ..................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics ......................................... 6
7.6 Switching Characteristics......................................... 8
7.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
9
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 22
12.1 Documentation Support ....................................... 22
12.2 Related Links ........................................................ 22
12.3 Community Resources.......................................... 22
12.4 Trademarks........................................................... 22
12.5 Electrostatic Discharge Caution............................ 22
12.6 Glossary................................................................ 22
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (March 2013) to Revision Q
Page
•
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
Changes from Revision O (March 2013) to Revision P
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 19
2
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
5 Device Comparison Table
PART NUMBER
PACKAGE
BODY SIZE (NOM)
4.00 mm × 4.00 mm
3.90 mm × 4.89 mm
3.91 mm × 4.90 mm
4.00 mm × 4.00 mm
3.91 mm × 4.90 mm
4.00 mm × 4.00 mm
4 .00mm × 4.00 mm
3.90 mm × 4.89 mm
3.91 mm × 4.90 mm
3.00 mm × 3.00 mm
4.00 mm × 4.00 mm
3.91 mm × 4.90 mm
WSON (10)
LM5100A, LM5100C
LM5100B, LM5101B
SO PowerPAD™ (8)
SOIC (8)
WSON (10)
SOIC (8)
WSON (8)
WSON (10)
LM5101A
LM5101C
SO PowerPAD (8)
SOIC (8)
MSOP PowerPAD (8)
WSON (10)
SOIC (8)
6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
DPR Package
10-Pin WSON With Exposed Thermal Pad
Top View
VDD
HB
LO
1
2
3
4
8
7
6
5
LO
VSS
LI
VDD
HB
1
2
3
4
5
10
9
VSS
SOIC-8
HO
HS
8
7
6
WSON-10
HO
HS
LI
HI
HI
NC
NC
NGT Package
8-Pin WSON With Exposed Thermal Pad
Top View
DDA Package
8-Pin SO PowerPAD
Top View
VDD
HB
1
2
3
4
8
7
6
5
LO
VSS
LI
LO
1
2
3
4
8
VDD
WSON-8
7
VSS
HB
HO
HS
HO
HS
SO
PowerPad-8
HI
LI
6
5
HI
Exposed Pad
Connect to VSS
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
DGN Package
8-Pin MSOP-PowerPAD
Top View
VDD
HB
1
LO
8
7
6
5
VSS
2
3
4
MSOP-
PowerPad-8
HO
HS
LI
HI
Pin Functions
PIN
I/O
DESCRIPTION
NAME
8 PINS
10 PINS(1)
High-side gate driver bootstrap supply. Connect the positive terminal of the bootstrap
capacitor to HB and the negative terminal to HS. The bootstrap capacitor should be
placed as close to the IC as possible.
HB
2
2
I
I
High-side driver control input. The LM5100A/B/C inputs have CMOS type thresholds.
The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to
ground and not left open.
HI
5
7
High-side gate driver output. Connect to the gate of high-side MOSFET with a short,
low inductance path.
HO
HS
3
4
3
4
O
High-side MOSFET source connection. Connect to the bootstrap capacitor negative
terminal and the source of the high-side MOSFET.
—
Low-side driver control input. The LM5100A/B/C inputs have CMOS type thresholds.
The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to
ground and not left open.
LI
6
8
8
I
Low-side gate driver output. Connect to the gate of the low-side MOSFET with a
short, low inductance path.
LO
10
O
Positive gate drive supply . Locally decouple to VSS using low ESR/ESL capacitor
located as close to the IC as possible.
VDD
VSS
1
7
1
9
I
—
Ground return. All signals are referenced to this ground.
TI recommends that the exposed pad on the bottom of the package is soldered to
ground plane on the PC board, and that ground plane should extend out from
beneath the IC to help dissipate heat.
EP(2)
—
(1) For WSON-10 package, pins 5 and 6 have no connection.
(2) Exposed pad is not available on the 8-pin SOIC package.
4
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
(1)(2)
See
MIN
−0.3
−0.3
−0.3
−0.3
HS − 0.3
−5
MAX
18
UNIT
V
VDD to VSS
HB to HS
18
V
LI or HI input
LO output
VDD + 0.3
VDD + 0.3
VHB + 0.3
100
V
V
HO output
V
V
(3)
HS to VSS
V
HB to VSS
118
V
Junction temperature
Storage temperature
150
°C
°C
−55
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military or Aerospace specified devices are required, contact the Texas Instruments Sales Office or Distributors for availability and
specifications.
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not
exceed –1 V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage
transiently. If negative transients occur, the HS voltage must never be more negative than VDD – 15 V. For example if VDD = 10 V, the
negative transients at HS must not exceed –5 V.
7.2 ESD Ratings
VALUE
±2000
50
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Option A
Option B and C
Electrostatic
discharge
V(ESD)
V
(2)
Machine Model (MM)
100
(1) The Human Body Model (HBM) is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. 2 kV for all pins except Pin 2,
Pin 3 and Pin 4 which are rated at 1000 V for HBM.
(2) Machine Model (MM) ratings are: 100 V(MM) for Options B and C; 50 V(MM) for Option A.
7.3 Recommended Operating Conditions
MIN
9
NOM
MAX
14
UNIT
V
VDD
HS
–1
100
V
HB
VHS + 8
VHS + 14
< 50
V
HS slew rate
Junction temperature
V/ns
°C
−40
125
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
7.4 Thermal Information
LM5100A,
LM5100C,
LM5101A
LM5100x,
LM5101x
LM5101C
LM5101A
WSON(2)
THERMAL METRIC(1)
UNIT
MSOP-
SO PowerPAD
WSON(2)
SOIC
PowerPAD(2)
8 PINS
40
8 PINS
80
8 PINS
37.8
36.7
14.9
0.3
10 PINS
8 PINS
170
—
RθJA
Junction-to-ambient thermal resistance(3)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
40
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
—
—
—
—
—
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
—
—
—
ψJB
—
—
15.2
4.4
—
RθJC(bot)
—
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) 4-layer board with Cu finished thickness 1.5, 1, 1, 1.5 oz. Maximum die size used. 5× body length of Cu trace on PCB top.
50-mm × 50-mm ground and power planes embedded in PCB. See Application Note AN-1187 (SNOA401).
(3) The RθJA is not a given constant for the package and depends on the printed circuit board design and the operating environment.
7.5 Electrical Characteristics
unless otherwise specified, limits are for TJ = 25°C, VDD = VHB = 12 V, VSS = VHS = 0 V, no load on LO or HO
(1)
.
PARAMETER
SUPPLY CURRENTS
TEST CONDITIONS
MIN
TYP
0.1
0.25
2
MAX UNIT
TJ = 25°C
VDD quiescent current,
LM5100A/B/C
LI = HI = 0 V
LI = HI = 0 V
f = 500 kHz
LI = HI = 0 V
f = 500 kHz
mA
0.2
TJ = –40°C to 125°C
IDD
TJ = 25°C
VDD quiescent current,
LM5101A/B/C
mA
0.4
TJ = –40°C to 125°C
TJ = 25°C
IDDO
VDD operating current
mA
3
TJ = –40°C to 125°C
TJ = 25°C
0.06
1.6
0.1
0.4
5.4
1.8
IHB
Total HB quiescent current
Total HB operating current
mA
0.2
TJ = –40°C to 125°C
TJ = 25°C
IHBO
mA
3
TJ = –40°C to 125°C
TJ = 25°C
IHBS
HB to VSS current, quiescent
HB to VSS current, operating
HS = HB = 100 V
f = 500 kHz
µA
10
TJ = –40°C to 125°C
IHBSO
mA
INPUT PINS
TJ = 25°C
Input voltage threshold
LM5100A/B/C
VIL
VIL
Rising Edge
Rising Edge
V
TJ = –40°C to 125°C
TJ = 25°C
4.5
1.3
6.3
Input voltage threshold
LM5101A/B/C
V
TJ = –40°C to 125°C
2.3
Input voltage hysteresis
LM5100A/B/C
VIHYS
VIHYS
500
mV
mV
Input voltage hysteresis
LM5101A/B/C
50
TJ = 25°C
200
RI
Input pulldown resistance
kΩ
TJ = –40°C to 125°C
100
400
(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
6
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
Electrical Characteristics (continued)
unless otherwise specified, limits are for TJ = 25°C, VDD = VHB = 12 V, VSS = VHS = 0 V, no load on LO or HO (1)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
UNDER VOLTAGE PROTECTION
TJ = 25°C
6.9
VDDR
VDDH
VHBR
VHBH
VDD rising threshold
VDD threshold hysteresis
HB rising threshold
V
TJ = –40°C to 125°C
6
7.4
0.5
6.6
V
TJ = 25°C
V
TJ = –40°C to 125°C
5.7
7.1
HB threshold hysteresis
0.4
0.52
0.8
V
BOOT STRAP DIODE
TJ = 25°C
VDL
VDH
RD
Low-current forward voltage
IVDD-HB = 100 µA
IVDD-HB = 100 mA
IVDD-HB = 100 mA
V
TJ = –40°C to 125°C
TJ = 25°C
0.85
High-current forward voltage
V
1
TJ = –40°C to 125°C
TJ = 25°C
1.0
Dynamic resistance
LM5100A/B/C, LM5101A/B/C
Ω
TJ = –40°C to 125°C
1.65
LO AND HO GATE DRIVER
Low-level output voltage
TJ = 25°C
0.12
0.16
0.28
0.24
0.28
0.6
V
LM5100A/LM5101A
TJ = –40°C to 125°C
TJ = 25°C
0.25
Low-level output voltage
LM5100B/LM5101B
VOL
IHO = ILO = 100 mA
V
TJ = –40°C to 125°C
TJ = 25°C
0.4
Low-level output voltage
LM5100C/LM5101C
V
TJ = –40°C to 125°C
TJ = 25°C
0.65
High-level output voltage
LM5100A/LM5101A
V
TJ = –40°C to 125°C
TJ = 25°C
0.45
IHO = ILO = 100 mA
VOH = VDD– LO or
VOH = HB - HO
High-level output voltage
LM5100B/LM5101B
VOH
V
TJ = –40°C to 125°C
TJ = 25°C
0.60
High-level output voltage
LM5100C/LM5101C
V
TJ = –40°C to 125°C
1.10
Peak pullup current
LM5100A/LM5101A
3
2
1
3
2
1
A
A
A
A
A
A
Peak pullup current
LM5100B/LM5101B
IOHL
HO, LO = 0 V
TJ = 25°C
Peak pullup current
LM5100C/LM5101C
Peak pulldown current
LM5100A/LM5101A
Peak pulldown current
LM5100B/LM5101B
IOLL
HO, LO = 12 V
TJ = 25°C
Peak pulldown current
LM5100C/LM5101C
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
7.6 Switching Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of –40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD
=
(1)
VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO
.
PARAMETER
TEST CONDITIONS
MIN
TYP
20
MAX
45
UNIT
ns
LO turnoff propagation delay LM5100A/B/C
tLPHL
LI Falling to LO Falling
LI Rising to LO Rising
LO turnoff propagation delay LM5101A/B/C
22
56
ns
LO turnon propagation delay LM5100A/B/C
tLPLH
20
45
ns
LO turnon propagation delay LM5101A/B/C
26
56
ns
HO turnoff propagation delay
LM5100A/B/C
20
22
45
56
ns
ns
tHPHL
HI Falling to HO Falling
HI Rising to HO Rising
HO turnoff propagation delay
LM5101A/B/C
LO turnon propagation delay LM5100A/B/C
tHPLH
20
26
45
56
ns
ns
LO turnon propagation delay LM5101A/B/C
Delay matching: LO on and HO off
LM5100A/B/C
1
4
1
10
10
10
10
ns
ns
ns
tMON
Delay matching: LO on and HO off
LM5101A/B/C
Delay matching: LO off and HO on
LM5100A/B/C
tMOFF
Delay matching: LO on and HO off
LM5101A/B/C
4
8
ns
ns
ns
tRC, tFC
Either output rise and fall time
CL = 1000 pF
CL = 0.1 µF
Output rise time (3 V to 9 V)
LM5100A/LM5101A
430
Output rise time (3 V to 9 V)
LM5100B/LM5101B
tR
570
990
260
430
715
50
ns
ns
ns
ns
ns
ns
ns
Output rise time (3 V to 9 V)
LM5100C/LM5101C
Output fall time (3 V to 9 V)
LM5100A/LM5101A
Output fall time (3 V to 9 V)
LM5100B/LM5101B
tF
CL = 0.1 µF
Output fall time (3 V to 9 V)
LM5100C/LM5101C
Minimum input pulse width that changes
the output
tPW
tBS
IF = 100 mA,
IR = 100 mA
Bootstrap diode reverse recovery time
37
(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
8
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
LI
LI
HI
HI
t
HPLH
t
LPLH
t
HPHL
t
LPHL
LO
LO
HO
HO
t
t
MOFF
MON
Figure 1. Timing Diagram
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
7.7 Typical Characteristics
5.0
4.5
4.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
LM5100A/LM5101A
3.5
LM5100A/LM5101A
3.0
2.5
2.0
LM5100B/LM5101B
LM5100B/LM5101B
1.5
1.0
LM5100C/LM5101C
LM5100C/LM5101C
0.5
0.5
0.0
0.0
7
8
9
10 11 12 13 14 15
VDD (V)
7
8
9
10 11 12 13 14 15
VDD (V)
Figure 3. Peak Sinking Current vs VDD
Figure 2. Peak Sourcing Current vs VDD
3.5
3.0
2.5
2.0
1.5
1.0
3.5
3.0
2.5
2.0
1.5
1.0
V
= 12 V
DD
V
= 12 V
DD
LM5100A/LM5101A
LM5100A/LM5101A
LM5100B/LM5101B
LM5100B/LM5101B
LM5100C/LM5101C
LM5100C/LM5101C
0.5
0.0
0.5
0.0
0
2
4
8
10
12
6
0
2
4
8
10
12
6
OUTPUT VOLTAGE (V)
Figure 4. Sink Current vs Output Voltage
OUTPUT VOLTAGE (V)
Figure 5. Source Current vs Output Voltage
100000
10000
1000
100
100000
10000
1000
V
= 12 V
DD
V
DD
= 12 V
C
= 4400 pF
L
C
= 4400 pF
L
C
= 1000 pF
L
C
= 1000 pF
L
C
= 0 pF
L
C
L
= 0 pF
100
10
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 7. LM5101A/B/C IDD vs Frequency
Figure 6. LM5100A/B/C IDD vs Frequency
10
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
Typical Characteristics (continued)
100000
2.3
HB = 12 V,
HS = 0 V
2.1
I
(LM5101A/B/C)
DDO
C
= 4400 pF
L
10000
1000
100
1.9
1.7
1.5
1.3
1.1
0.9
0.7
I
(LM5100A/B/C)
DDO
C
= 1000 pF
L
I
HBO
C
= 0 pF
L
10
-50 -25
0
25 50 75 100 125 150
TEMPERATURE (oC)
Figure 8. Operating Current vs Temperature
400
0.1
1
10
FREQUENCY (kHz)
Figure 9. IHB vs Frequency
100
1000
350
300
250
200
150
100
50
350
300
250
200
150
100
50
I
(LM5101A/B/C)
DD
I
(LM5101A/B/C)
DD
I
(LM5100A/B/C)
DD
I
(LM5100A/B/C)
DD
I
HB
I
HB
0
0
8
9
10 11 12 13 14 15 16
, V (V)
-50 -25
0
25 50 75 100 125 150
V
TEMPERATURE (°C)
DD HB
Figure 10. Quiescent Current vs Supply Voltage
Figure 11. Quiescent Current vs Temperature
0.60
7.30
7.20
7.10
7.00
0.55
V
DDH
0.50
0.45
0.40
0.35
0.30
V
DDR
6.90
6.80
6.70
6.60
6.50
6.40
6.30
V
HBH
V
HBR
-50
0
25
-50 -25
0
25 50 75 100 125 150
TEMPERATURE (oC)
TEMPERATURE (°C)
Figure 13. Undervoltage Threshold Hysteresis vs
Temperature
Figure 12. Undervoltage Rising Thresholds vs Temperature
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
Typical Characteristics (continued)
1.00E-01
50
49
48
47
46
45
44
43
42
41
40
T = 150°C
1.00E-02
Rising
1.00E-03
T = 25°C
1.00E-04
Falling
T = -40°C
1.00E-05
1.00E-06
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
-50 -25
0
25 50 75 100 125 150
TEMPERATURE (°C)
V
(V)
D
Figure 15. LM5100A/B/C Input Threshold vs Temperature
Figure 14. Bootstrap Diode Forward Voltage
1.92
1.91
50
49
1.90
Rising
1.89
48
Rising
47
46
45
44
1.88
1.87
1.86
Falling
1.85
1.84
1.83
1.82
1.81
1.80
43
Falling
42
41
40
-50 -25
0
25 50 75 100 125 150
8
9
10 11 12 13 14 15 16
VDD (V)
TEMPERATURE (°C)
Figure 16. LM5101A/B/C Input Threshold vs Temperature
Figure 17. LM5100A/B/C Input Threshold vs VDD
35
1.92
1.91
1.90
Rising
1.89
30
1.88
1.87
1.86
25
1.85
T_PLH
Falling
1.84
20
T_PHL
1.83
1.82
1.81
1.80
15
-50 -25
0
25 50 75 100 125 150
8
9
10 11 12 13 14 15 16
VDD (V)
TEMPERATURE (°C)
Figure 18. LM5101A/B/C Input Threshold vs VDD
Figure 19. LM5100A/B/C Propagation Delay vs Temperature
12
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
Typical Characteristics (continued)
1.0
40
V
DD
= 12 V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
35
LM5100C/LM5101C
30
T_PLH
LM5100B/LM5101B
25
T_PHL
20
15
LM5100A/LM5101A
0.0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. LO and HO Gate Drive - High Level Output
Voltage vs Temperature
Figure 20. LM5101A/B/C Propagation Delay vs Temperature
0.50
0.8
V
= 12 V
DD
I
= -100 mA
OUT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.7
0.6
0.5
0.4
0.3
0.2
0.1
LM5100C/LM5101C
LM5100C/LM5101C
LM5100B/LM5101B
LM5100B/LM5101B
LM5100A/LM5101A
LM5100A/LM5101A
0.00
-50 -25
0
25 50 75 100 125 150
7
8
9
10 11 12 13 14 15
VDD (V)
TEMPERATURE (°C)
Figure 22. LO and HO Gate Drive - Low Level Output
Voltage vs Temperature
Figure 23. LO and HO Gate Drive - Output High Voltage vs
VDD
0.35
0.30
0.25
0.20
0.15
0.10
I
= 100 mA
OUT
LM5100C/LM5101C
LM5100B/LM5101B
LM5100A/LM5101A
7
8
9
10 11 12 13 14 15
VDD (V)
Figure 24. LO and HO Gate Drive - Output Low Voltage vs VDD
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
8 Detailed Description
8.1 Overview
The LM5100A/B/C and LM5101A/B/C are designed to drive both the high-side and the low-side N-channel FETs
in a synchronous buck or a half-bridge configuration. The outputs are independently controlled with CMOS input
thresholds(LM5101A/B/C) or TTL input thresholds(LM5101A/B/C). The floating high-side driver is capable of
working with supply voltages up to 100 V. An integrated high voltage diode is provided to charge high side gate
drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing
clean level transitions from the control logic to the high side gate driver. Under-voltage lockout is provided on
both the low side and the high side power rails.
8.2 Functional Block Diagram
HB
UVLO
HO
HS
DRIVER
LEVEL
SHIFT
HI
LI
VDD
UVLO
LO
DRIVER
GND
8.3 Feature Description
8.3.1 Start-up and UVLO
Both high and low-side drivers include under voltage lockout (UVLO) protection circuitry which monitors the
supply voltage (VDD) and bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each
driver until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO
hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to the VDD
pin of the LM5100A/B/C and LM5101A/B/C, the outputs of the low-side and high-side are held low until VDD
exceeds the UVLO threshold, typically about 6.6 V. Any UVLO condition on the bootstrap capacitor will disable
only the high-side output (HO).
8.3.2 Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides
excellent delay matching with the low-side driver.
14
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
Feature Description (continued)
8.3.3 Bootstrap Diode
The bootstrap diode necessary to generate the high-side bias is included in the LM5100/1 family. The diode
anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS
pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode
provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliable
operation.
8.3.4 Output Stages
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance,
and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The
low-side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS
.
8.4 Device Functional Modes
The device operates in normal mode and UVLO mode. See Start-up and UVLO for more information on UVLO
operation mode. In normal mode, the output stage is dependent on the states of the HI and LI pins.
Table 1. Input/Output Logic Table
HI
L
LI
L
HO(1)
LO(2)
L
L
L
H
L
L
H
L
H
H
H
L
H
x(3)
H
x
H
L
(1) HO is measured with respect to the HS.
(2) LO is measured with the respect to the VSS.
(3) x is floating condition
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
To affect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate
drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching
devices. With the advent of digital power, this situation will be often encountered because the PWM signal from
the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting
circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses from the controller into the driver.
The LM5100A/B/C and LM5101A/B/C are the high voltage gate drivers that are designed to drive both the high-
side and low-side N-Channel MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck circuit.
The floating high side driver is capable of operating with supply voltages up to 100 V. This allows for N-Channel
MOSFET control in half-bridge, full-bridge, push-pull, two switch forward and active clamp topologies. The
outputs are independently controlled. Each channel is controlled by its respective input pins (HI and LI), allowing
full and independent flexibility to control on and off state of the output.
9.2 Typical Application
Optional external
fast recovery diode
VIN
VCC
RBOOT DBOOT
HB
LM5101A
VSS
RGATE
HO
VDD
OUT1
OUT2
VDD
HI
CBOOT
0.1 µF
HS
LO
PWM
Controller
T1
LI
RGATE
1.0 µF
Figure 25. LM5101A Driving MOSFETs in Half-Bridge Configuration
16
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
Typical Application (continued)
9.2.1 Design Requirements
See Table 2 for the parameter and values.
Table 2. Operating Parameters
PARAMETER
Gate Driver
MOSFET
VDD
VALUE
LM5101A
CSD18531Q5A
10 V
Qgmax
Fsw
43 nC
100 kHz
95%
Dmax
IHBS
10 µA
VDH
1.0 V
VHBR
7.1 V
VHBH
0.4 V
9.2.2 Detailed Design Procedure
9.2.2.1 Select Bootstrap and VDD capacitor
The bootstrap capacitor must maintain the HB pin voltage above the UVLO voltage for the HB circuit in any
circumstances during normal operation. Calculate the maximum allowable drop across the bootstrap capacitor
with Equation 1.
ΔVHB = VDD – VDH – VHBL= 10 V – 1.0 V – 6.7 V = 2.3 V
where
•
•
•
VDD = Supply voltage of the gate drive IC
VDH = Bootstrap diode forward voltage drop
VHBL = VHBR – VHBH = 6.7 V, HB falling threshold
(1)
The quiescent current of the bootstrap circuit is 10 µA, which is negligible compared to the Qgs of the MOSFET
(see Equation 2 and Equation 3).
DMAX
0.95
QTOTAL = Qgmax +IHBS
= 43 nC +10 µA
= 43.01nC
FSW
100 kHz
(2)
QTOTAL
43.01nC
2.3 V
CBOOT
=
=
=18.7 nF
DVHB
(3)
In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where
the power stage may skip pulse due to load transients. It is recommended to place the bootstrap capacitor as
close to the HB and HS pins as possible.
CBOOT = 100 nF
(4)
As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT.
CVDD = 10 × CBOOT = 1 µF
(5)
The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be
twice that of the maximum VDD to allow for loss of capacitance once the devices have a DC bias voltage across
them and to ensure long-term reliability of the devices.
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
9.2.2.2 Select External Bootstrap Diode and Resistor
The bootstrap capacitor is charged by the VDD through the internal bootstrap diode every cycle when low side
MOSFET turns on. The charging of the capacitor involves high peak currents, and therefore transient power
dissipation in the internal bootstrap diode may be significant and dependent on its forward voltage drop. Both the
diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver and need to
be considered in the gate driver IC power dissipation.
For high frequency and high capacitive loads, it may be necessary to consider using an external bootstrap diode
placed in parallel with internal bootstrap diode to reduce power dissipation of the driver. For the selection of
external bootstrap diodes for LM510x device, please refer to the application note SNVA083.
Bootstrap resistor RBOOT is selected to reduce the inrush current in DBOOT and limit the ramp up slew rate of
voltage of HB-HS. It is recommended that RBOOT is between 2 Ω and 10 Ω. For this design, a current limiting
resistor of 2.2 Ω is selected to limit inrush current of bootstrap diode.
V
DD - VDBOOT
10 V - 0.6 V
IDBOOT pk
( )
=
=
=4.27 A
RBOOT
2.2 W
(6)
9.2.2.3 Select Gate driver Resistor
Resistor RGATE is sized to reduce ringing caused by parasitic inductances and capacitances and also to limit the
current coming out of the gate driver. For this design 4.7-Ω resistors were selected for this design. Maximum HO
and LO drive current are calculated by Equation 7 through Equation 10.
V
DD - VDH - VOH
10 V -1.0 V - 0.45 V
IHOH
ILOH
IHOL
ILOL
=
=
=
=
= 1.819 A
RGATE
4.7 W
(7)
(8)
(9)
VDD - VOH
10 V - 0.45 V
4.7 W
=
= 2.032 A
RGATE
VDD - VDH - VOL
10 V -1.0 V - 0.25 V
4.7 W
=
= 1.862 A
RGATE
VDD - VOH
10 V - 0.25 V
4.7 W
=
=
= 2.074 A
RGATE
where
•
•
•
•
•
•
IHOH = Maximum HO source current
ILOH = Maximum LO source current
IHOL = Maximum HO sink current
ILOH = Maximum HO sink current
VOH = High-Level output voltage drop across HB to HO or VDD to LO
VOL = Low-Level output voltage drop across HO to HS or LO to GND
(10)
9.2.2.4 Estimate the Driver Power Losses
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (fsw), output load capacitance on LO and HO (CL), and supply
voltage (VDD). The gate charge losses can be calculated by Equation 11.
PDGATES = 2´ VD2D ´CL ´ fsw
(11)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with Equation 11. Figure 26 can be used to approximate
the power losses due to the gate drivers.
18
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
1.000
0.100
0.010
0.001
C
= 4400 pF
L
C
= 1000 pF
L
C
= 0 pF
L
0.1
1.0
10.0
100.0
1000.0
SWITCHING FREQUENCY (kHz)
Figure 26. Gate Driver Power Dissipation (LO + HO)
VDD = 12 V, Neglecting Diode Losses
The internal bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these
events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads
require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to
the half bridge result in higher reverse recovery losses. The following plot was generated based on calculation
and lab measurements of the diode recovery time and current under several operating conditions. This can be
useful for approximating the internal diode power dissipation. If the diode losses can be significant, an external
diode placed in parallel with the internal bootstrap diode can be helpful to reduce power dissipation within the IC.
0.100
C
= 4400 pF
L
C
= 0 pF
L
0.010
0.001
1
10
100
1000
SWITCHING FREQUENCY (kHz)
Figure 27. Diode Power Dissipation VIN = 50 V
The total IC power dissipation can be estimated from the plots shown in Figure 26 and Figure 27 by summing the
gate drive losses with the internal bootstrap diode losses for the intended application. For a given ambient
temperature, the maximum allowable power loss of the IC can be defined as equation Equation 12.
TJ - TA
P
=
loss
RqJA
where
•
•
•
•
Ploss = The total power dissipation of the driver
TJ = Junction temperature
TA = Ambient temperature
RθJA = Junction-to-ambient thermal resistance
(12)
19
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
The thermal metrics for the driver package is summarized in the Thermal Information table. For detailed
information regarding the thermal information table, refer to the Application Note from Texas Instruments entitled
Semiconductor and IC Package Thermal Metrics SPRA953.
9.2.3 Application Curves
Figure 28. HI/LI to HO/LO Turnon Propagation Delay
Figure 29. HI/LI to HO/LO Turnoff Propagation Delay
10 Power Supply Recommendations
The bias supply voltage range for which the device is rated to operate is from 9 V to 14 V. The lower end of this
range is governed by the internal under voltage-lockout (UVLO) protection feature on the VDD pin supply circuit
blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the VDDR supply start
threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is
driven by the 18-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating).
Keeping a 4-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin
is 14 V.
The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage
has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device
continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDDH.
Therefore, ensuring that, while operating at or near the 9-V range, the voltage ripple on the auxiliary power
supply output is smaller than the hysteresis specification of the device is important to avoid triggering device
shutdown.
During system shutdown, the device operation continues until the VDD pin voltage has dropped below the
threshold (VDDR – VDDH), which must be accounted for while evaluating system shutdown timing design
requirements. Likewise, at system start up, the device does not begin operation until the VDD pin voltage has
exceeded above the VDDR threshold. The quiescent current consumed by the internal circuit blocks of the device
is supplied through the VDD pin. Keep in mind that the charge for source current pulses delivered by the LO pin
is also supplied through the same VDD pin. As a result, every time a current is sourced out of the LO pin a
corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that a local bypass
capacitor is provided between the VDD and GND pins and located as close as possible to the device for the
purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is necessary. TI recommends
using two capacitors between VDD and GND: a 100-nF ceramic surface-mount capacitor that can be nudged
very close to the pins of the device and another surface-mount capacitor in the range 0.22 µF to 10 µF added in
parallel. In a similar manner, the current pulses delivered by the HO pin are sourced from the HB pin. Therefore,
a 0.022-µF to 1-µF local decoupling capacitor is recommended between the HB and HS pins.
20
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
11 Layout
11.1 Layout Guidelines
The optimum performance of high and low-side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. Low-ESR/ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the
HB and HS pins to support the high peak currents being drawn from VDD during turnon of the external
MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS pin), the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding Considerations:
–
The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gate into a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
–
The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on
a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
A recommended layout pattern for the driver is shown in Figure 30. If possible a single layer placement is
preferred.
11.2 Layout Example
Recommended Layout for Driver IC and
Passives
VDD
HB
LO
VSS
LI
SO
PowerPAD-8
HO
HS
HI
Single Layer
Option
Multi Layer
Option
To Hi-Side FET
To Low-Side FET
Figure 30. PCB Layout Recommendation
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
•
•
AN-1187 Leadless Leadframe Package (LLP) (SNOA401)
AN-1317 Selection of External Bootstrap Diode for LM510X Devices (SNVA083)
Semiconductor and IC Package Thermal Metrics (SPRA953)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
LM5100A
LM5100B
LM5100C
LM5101A
LM5101B
LM5101C
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
PACKAGE OPTION ADDENDUM
www.ti.com
1-Oct-2016
PACKAGING INFORMATION
Orderable Device
LM5100AM/NOPB
LM5100AMR/NOPB
LM5100AMRX/NOPB
LM5100AMX/NOPB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
D
8
8
8
8
95
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
-40 to 125
L5100
AM
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
D
95
Green (RoHS
& no Sb/Br)
L5100
AMR
2500
2500
Green (RoHS
& no Sb/Br)
L5100
AMR
ACTIVE
SOIC
Green (RoHS
& no Sb/Br)
-40 to 125
L5100
AM
LM5100ASD
NRND
WSON
WSON
DPR
DPR
10
10
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
5100ASD
5100ASD
LM5100ASD/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM5100BMA/NOPB
LM5100BMAX/NOPB
LM5100BSD/NOPB
LM5100CMA/NOPB
LM5100CMAX/NOPB
LM5100CMY/NOPB
LM5100CMYE/NOPB
LM5100CMYX/NOPB
ACTIVE
ACTIVE
SOIC
SOIC
WSON
SOIC
SOIC
D
D
8
8
95
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Call TI
CU SN
Call TI
Call TI
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
L5100
BMA
2500
1000
Green (RoHS
& no Sb/Br)
L5100
BMA
ACTIVE
DPR
D
10
8
Green (RoHS
& no Sb/Br)
5100BSD
OBSOLETE
ACTIVE
TBD
L5100
CMA
D
8
2500
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Call TI
L5100
CMA
OBSOLETE
OBSOLETE
OBSOLETE
MSOP-
PowerPAD
DGN
DGN
DGN
8
TBD
TBD
TBD
TBD
SXCB
MSOP-
PowerPAD
8
Call TI
SXCB
MSOP-
PowerPAD
8
Call TI
SXCB
LM5100CSD/NOPB
LM5101AM/NOPB
OBSOLETE
ACTIVE
WSON
SOIC
DPR
D
10
8
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
5100CSD
95
95
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
L5101
AM
LM5101AMR/NOPB
LM5101AMRX/NOPB
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
8
8
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
L5101
AMR
2500
Green (RoHS
& no Sb/Br)
L5101
AMR
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Oct-2016
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
LM5101AMX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
L5101
AM
LM5101ASD
NRND
WSON
WSON
DPR
NGT
10
8
1000
1000
TBD
Call TI
Call TI
-40 to 125
5101ASD
5101A-1
LM5101ASD-1/NOPB
ACTIVE
Green (RoHS CU NIPDAU | CU SN
& no Sb/Br)
Level-1-260C-UNLIM
LM5101ASD/NOPB
ACTIVE
WSON
DPR
10
1000
Green (RoHS CU NIPDAU | CU SN
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 125
-40 to 125
5101ASD
LM5101ASDX
NRND
WSON
WSON
DPR
NGT
10
8
4500
4500
TBD
Call TI
CU SN
Call TI
5101ASD
5101A-1
LM5101ASDX-1/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM5101ASDX/NOPB
LM5101BMA/NOPB
LM5101BMAX/NOPB
LM5101BSD/NOPB
LM5101BSDX/NOPB
LM5101CMA/NOPB
LM5101CMAX/NOPB
LM5101CMY/NOPB
LM5101CMYE/NOPB
LM5101CMYX/NOPB
LM5101CSD/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
SOIC
DPR
D
10
8
4500
95
Green (RoHS CU NIPDAU | CU SN
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
5101ASD
Green (RoHS
& no Sb/Br)
CU SN
L5101
BMA
SOIC
D
8
2500
1000
4500
95
Green (RoHS
& no Sb/Br)
CU SN
L5101
BMA
WSON
WSON
SOIC
DPR
DPR
D
10
10
8
Green (RoHS CU NIPDAU | CU SN
& no Sb/Br)
(5101ASD ~
5101BSD)
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
5101BSD
Green (RoHS
& no Sb/Br)
L5101
CMA
SOIC
D
8
2500
1000
250
Green (RoHS
& no Sb/Br)
L5101
CMA
MSOP-
PowerPAD
DGN
DGN
DGN
DPR
8
Green (RoHS
& no Sb/Br)
SXDB
MSOP-
PowerPAD
8
Green (RoHS
& no Sb/Br)
SXDB
MSOP-
PowerPAD
8
3500
1000
Green (RoHS
& no Sb/Br)
SXDB
WSON
10
Green (RoHS CU NIPDAU | CU SN
& no Sb/Br)
-40 to 125
5101CSD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
1-Oct-2016
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5100AMRX/NOPB
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM5100AMX/NOPB
LM5100ASD
SOIC
WSON
WSON
SOIC
D
8
10
10
8
2500
1000
1000
2500
1000
2500
2500
330.0
178.0
178.0
330.0
178.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
6.5
4.3
4.3
6.5
4.3
6.5
6.5
5.4
4.3
4.3
5.4
4.3
5.4
5.4
2.0
1.3
1.3
2.0
1.3
2.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
DPR
DPR
D
LM5100ASD/NOPB
LM5100BMAX/NOPB
LM5100BSD/NOPB
LM5100CMAX/NOPB
LM5101AMRX/NOPB
WSON
SOIC
DPR
D
10
8
SO
Power
PAD
DDA
8
LM5101AMX/NOPB
LM5101ASD
SOIC
D
8
10
8
2500
1000
1000
1000
4500
4500
4500
330.0
178.0
180.0
180.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
6.5
4.3
4.3
4.3
4.3
4.3
4.3
5.4
4.3
4.3
4.3
4.3
4.3
4.3
2.0
1.3
1.1
1.1
1.3
1.3
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
WSON
WSON
WSON
WSON
WSON
WSON
DPR
NGT
DPR
DPR
NGT
DPR
LM5101ASD-1/NOPB
LM5101ASD/NOPB
LM5101ASDX
10
10
8
LM5101ASDX-1/NOPB
LM5101ASDX/NOPB
10
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2016
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5101BMAX/NOPB
LM5101BSD/NOPB
LM5101BSDX/NOPB
LM5101CMAX/NOPB
LM5101CMY/NOPB
SOIC
WSON
WSON
SOIC
D
8
10
10
8
2500
1000
4500
2500
1000
330.0
180.0
330.0
330.0
178.0
12.4
12.4
12.4
12.4
12.4
6.5
4.3
4.3
6.5
5.3
5.4
4.3
4.3
5.4
3.4
2.0
1.1
1.3
2.0
1.4
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
DPR
DPR
D
MSOP-
Power
PAD
DGN
8
LM5101CMYE/NOPB
LM5101CMYX/NOPB
LM5101CSD/NOPB
MSOP-
Power
PAD
DGN
DGN
DPR
8
8
250
3500
1000
178.0
330.0
180.0
12.4
12.4
12.4
5.3
5.3
4.3
3.4
3.4
4.3
1.4
1.4
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
MSOP-
Power
PAD
WSON
10
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5100AMRX/NOPB
LM5100AMX/NOPB
LM5100ASD
SO PowerPAD
SOIC
DDA
D
8
8
2500
2500
1000
1000
2500
367.0
367.0
210.0
210.0
367.0
367.0
367.0
185.0
185.0
367.0
35.0
35.0
35.0
35.0
35.0
WSON
DPR
DPR
D
10
10
8
LM5100ASD/NOPB
LM5100BMAX/NOPB
WSON
SOIC
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2016
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5100BSD/NOPB
LM5100CMAX/NOPB
LM5101AMRX/NOPB
LM5101AMX/NOPB
LM5101ASD
WSON
SOIC
DPR
D
10
8
1000
2500
2500
2500
1000
1000
1000
4500
4500
4500
2500
1000
4500
2500
1000
250
210.0
367.0
367.0
367.0
210.0
203.0
203.0
367.0
367.0
346.0
367.0
203.0
367.0
367.0
210.0
210.0
367.0
203.0
185.0
367.0
367.0
367.0
185.0
203.0
203.0
367.0
367.0
346.0
367.0
203.0
367.0
367.0
185.0
185.0
367.0
203.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
SO PowerPAD
SOIC
DDA
D
8
8
WSON
DPR
NGT
DPR
DPR
NGT
DPR
D
10
8
LM5101ASD-1/NOPB
LM5101ASD/NOPB
LM5101ASDX
WSON
WSON
10
10
8
WSON
LM5101ASDX-1/NOPB
LM5101ASDX/NOPB
LM5101BMAX/NOPB
LM5101BSD/NOPB
LM5101BSDX/NOPB
LM5101CMAX/NOPB
LM5101CMY/NOPB
LM5101CMYE/NOPB
LM5101CMYX/NOPB
LM5101CSD/NOPB
WSON
WSON
10
8
SOIC
WSON
DPR
DPR
D
10
10
8
WSON
SOIC
MSOP-PowerPAD
MSOP-PowerPAD
MSOP-PowerPAD
WSON
DGN
DGN
DGN
DPR
8
8
8
3500
1000
10
Pack Materials-Page 3
MECHANICAL DATA
DGN0008A
MUY08A (Rev A)
BOTTOM VIEW
www.ti.com
MECHANICAL DATA
DDA0008B
MRA08B (Rev B)
www.ti.com
MECHANICAL DATA
NGT0008A
SDC08A (Rev A)
www.ti.com
MECHANICAL DATA
DPR0010A
SDC10A (Rev A)
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明