LM5108DRCT [TI]
具有使能和互锁功能的 2.6A、110V 半桥栅极驱动器 | DRC | 10 | -40 to 125;
| 型号： | LM5108DRCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能和互锁功能的 2.6A、110V 半桥栅极驱动器 | DRC | 10 | -40 to 125 栅极驱动 驱动器 |
| 文件： | 总33页 (文件大小：1806K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM5108
ZHCSJQ0 –MAY 2019
LM5108 稳健、紧凑型 100V 半桥栅极驱动器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
可驱动两个采用高侧/低侧配置的 N 沟道 MOSFET
LM5108 是一款高频半桥栅极驱动器，最大开关节点
(HS) 额定电压为 100V。借助此器件，可在基于半桥配
置的拓扑（例如同步降压、全桥、有源钳位正激式、
LLC 和同步升压）中控制两个 N 沟道 MOSFET。
采用 3mm × 3mm 封装
互锁或跨导保护
启用/禁用功能
HS 引脚上的绝对最大负电压处理能力 (-5V)
5V 典型欠压锁定
此器件具有互锁功能，可以在两个输入都处于高电平时
防止两个输出同时处于高电平。此互锁功能可改进电机
驱动和电动工具应用中的系统 稳健性。使用启用和禁
用功能，可以灵活、快速地控制功率级。电池供电的工
具也可以使用 LM5108 的功能来减小待机电流和响应
系统故障。输入与电源电压无关，并且可以具有独立的
脉宽。这样即可实现极高的控制灵活性。输入和启用功
能都具有足够的迟滞，可以在易产生噪声的 应用（例
如电机驱动器）中改善系统稳健性 。
20ns 典型传播延迟
1000pF 负载时的上升时间为 11ns，下降时间典型
值为 8ns
•
•
•
•
•
1ns 典型延迟匹配
2.6A 灌电流，1.6A 拉电流输出
绝对最大启动电压为 110V
禁用时消耗的电流很低 (7µA)
集成式自举二极管
低侧和高侧输出在彼此的接通和关断之间实现了低至
1ns 的匹配。这样即可优化死区时间，进而提高效率。
5V UVLO 允许驱动器使用更低的偏置电源运行，进而
允许功率级以更高的开关频率运行且不会增加开关损
耗。VDD 和 HB UVLO 阈值规格设计为使高侧和低侧
驱动器通常在 5V 电压时接通。如果 VDD 和 HB
UVLO 阈值相同，则设计器需要高于 VDD UVLO 阈值
的偏置电源才能同时接通高侧和低侧驱动器。
2 应用
•
•
•
电机驱动器和电动工具
开关模式电源
辅助逆变器
简化应用示意图
7V
75V
板载自举二极管无需使用外部分立式二极管，因此提高
了布板空间利用率。小型封装支持紧凑型电源设计，例
如电动工具。
VDD
EN
HO
NC
HB
器件信息(1)
HI
LI
To Load
器件型号
封装（大小）
HS
LO
LM5108
SON10 (3mm x 3mm)
VSS
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDP6
LM5108
ZHCSJQ0 –MAY 2019
www.ti.com.cn
目录
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 17
Power Supply Recommendations...................... 24
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
8
9
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 器件和文档支持 ..................................................... 26
11.1 接收文档更新通知 ................................................. 26
11.2 社区资源................................................................ 26
11.3 商标....................................................................... 26
11.4 静电放电警告......................................................... 26
11.5 Glossary................................................................ 26
12 机械、封装和可订购信息....................................... 26
7
4 修订历史记录
日期
修订版本
说明
2019 年 5 月
*
初始发行版。
2
Copyright © 2019, Texas Instruments Incorporated
LM5108
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ZHCSJQ0 –MAY 2019
5 Pin Configuration and Functions
DRC Package
10-Pin VSON With Exposed Thermal Pad
Top View
VDD
NC
HB
1
2
3
4
5
10
9
LO
VSS
LI
Thermal
Pad
8
HO
HS
7
HI
6
EN
Not to scale
Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
DRC
Enable input. When this pin is pulled high, it will enable the driver. If left floating or
pulled low, it will disable the driver. 1 nF filter capacitor is recommended for high-
noise systems.
EN
HB
6
I
High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap
capacitor is required. Connect positive side of the bootstrap capacitor to this pin.
Typical recommended value of HB bypass capacitor is 0.1 μF, This value primarily
depends on the gate charge of the high-side MOSFET. When using external boot
diode, connect cathode of the diode to this pin.
3
P
HI
7
4
I
High-side input.
High-side output. Connect to the gate of the high-side power MOSFET or one end of
external gate resistor, when used.
HO
O
High-side source connection. Connect to source of high-side power MOSFET.
Connect negative side of bootstrap capacitor to this pin.
HS
LI
5
8
P
I
Low-side input
Low-side output. Connect to the gate of the low-side power MOSFET or one end of
external gate resistor, when used.
LO
NC
10
2
O
—
Not connected internally.
Positive supply to the low-side gate driver. Decouple this pin to VSS. Typical
decoupling capacitor value is 1 μF. When using an external boot diode, connect the
anode to this pin.
VDD
VSS
1
9
P
G
Negative supply terminal for the device which is generally the system ground.
Connect to a large thermal mass trace (generally IC ground plane) to improve
thermal performance. This can only be electrically connected to VSS.
Thermal pad
—
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output
Copyright © 2019, Texas Instruments Incorporated
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ZHCSJQ0 –MAY 2019
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6 Specifications
6.1 Absolute Maximum Ratings
(1)(2)
All voltages are with respect to Vss
MIN
–0.3
MAX
20
UNIT
V
VDD
Supply voltage
VEN, VHI, VLI
VLO
Input voltages on EN, HI and LI
Output voltage on LO
–0.3
20
V
–0.3
VDD + 0.3
VHB + 0.3
105
V
VHO
Output voltage on HO
VHS – 0.3
–5
V
VHS
Voltage on HS
V
VHB
Voltage on HB
–0.3
110
V
VHB-HS
TJ
Voltage on HB with respect to HS
Operating junction temperature
Lead temperature (soldering, 10 sec.)
Storage temperature
–0.3
20
V
–40
150
°C
°C
°C
300
Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to Vss. Currents are positive into, negative out of the specified terminal.
6.2 ESD Ratings
VALUE
±2000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2)
Charged-device model (CDM), per JEDEC specification JESD22-C101(3)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Pins HS, HB and HO are rated at 500V HBM
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Supply voltage
5.5
12
16
VDD
VDD
VHB
V
V
VEN, VHI, VLI Input Voltage
0
0
VLO
VHO
VHS
VHB
Vsr
Low side output voltage
V
High side output voltage
Voltage on HS(1)
VHS
V
–1
100
V
Voltage on HB
VHS + 5.5
VHS+16
50
V
Voltage slew rate on HS
Operating junction temperature
V/ns
°C
TJ
–40
125
(1) VHB-HS < 16V (Voltage on HB with respect to HS must be less than 16V)
4
Copyright © 2019, Texas Instruments Incorporated
LM5108
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ZHCSJQ0 –MAY 2019
6.4 Thermal Information
LM5108
THERMAL METRIC(1)
DRC
10 PINS
47.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
50.3
Junction-to-board thermal resistance
21.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.0
ψJB
21.2
RθJC(bot)
4.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VDD = VHB = VEN =12 V, VHS = VSS = 0 V, No load on LO or HO, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SUPPLY CURRENTS
IDD
VDD quiescent current
VDD operating current
HB quiescent current
HB operating current
Leakage current
VLI = VHI = 0
f = 500 kHz
0.28
2.3
0.29 mA
2.4 mA
0.14 mA
IDDO
IHB
VLI = VHI = 0 V
f = 500 kHz
0.13
2.5
IHBO
2.8
mA
μA
μA
ILK
VHS = VHB = 110 V
VEN = 0
2.0
IDD_DIS
INPUT
VHIT
IDD when driver is disabled
7.0
Input rising threshold
Input falling threshold
Input voltage Hysteresis
Input pulldown resistance
2.3
V
V
VLIT
1.0
1.0
VIHYS
RIN
0.7
V
250
kΩ
ENABLE
VEN
Voltage threshold on EN pin to enable the driver
Voltage threshold on EN pin to disable the driver
Enable pin hysteresis
1.65
V
V
VDIS
VENHYS
REN
0.12
250
V
EN pin internal pull-down resistor
kΩ
UNDERVOLTAGE LOCKOUT PROTECTION (UVLO)
VDDR
VDD rising threshold
4.8
4.3
5.0
4.5
0.5
3.7
3.4
0.3
5.2
4.8
V
V
V
V
V
V
VDDF
VDD falling threshold
VDDHYS
VHBR
VDD threshold hysteresis
HB rising threshold with respect to HS pin
HB falling threshold with respect to HS pin
HB threshold hysteresis
3.4
3.1
4.1
3.8
VHBF
VHBHYS
BOOTSTRAP DIODE
VF
Low-current forward voltage
IVDD-HB = 100 μA
0.55
0.9
V
V
Ω
VFI
RD
High-current forward voltage
IVDD-HB = 80 mA
Dynamic resistance, ΔVF/ΔI
IVDD-HB = 100 mA and 80 mA
2.0
Copyright © 2019, Texas Instruments Incorporated
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Electrical Characteristics (continued)
VDD = VHB = VEN =12 V, VHS = VSS = 0 V, No load on LO or HO, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
LO GATE DRIVER
VLOL
VLOH
Low level output voltage
High level output voltage
Peak pullup current
ILO = 100 mA
0.13
0.4
V
V
A
A
ILO = -100 mA, VLOH = VDD – VLO
VLO = 0 V
1.6
Peak pulldown current
VLO = 12 V
2.6
HO GATE DRIVER
VHOL
VHOH
Low level output voltage
IHO = 100 mA
0.13
0.4
V
High level output voltage
Peak pullup current
IHO = –100 mA, VHOH = VHB- VHO
VHO = 0 V
1.6
A
A
Peak pulldown current
VHO = 12 V
2.6
6.6 Switching Characteristics
VDD = VHB = VEN = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = 25°C, (unless otherwise noted)
PARAMETER
PROPAGATION DELAYS
TEST CONDITIONS
MIN
TYP
MAX UNIT
tDLFF
tDHFF
tDLRR
tDHRR
VLI falling to VLO falling
VHI falling to VHO falling
VLI rising to VLO rising
VHI rising to VHO rising
See 图 1
See 图 1
See 图 1
See 图 1
20
20
20
20
ns
ns
ns
ns
DELAY MATCHING
tMON
From LO being ON to HO being OFF
From LO being OFF to HO being ON
See 图 1
See 图 1
1
1
5
5
ns
ns
tMOFF
OUTPUT RISE AND FALL TIME
tR
tF
LO, HO rise time
LO, HO fall time
CLOAD = 1000 pF
CLOAD = 1000 pF
11
8
ns
ns
MISCELLANEOUS
TPW,min Minimum input pulse width that changes the output
Bootstrap diode turnoff time
40
ns
ns
IF = 20 mA, IREV = 0.5 A
20
6
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LM5108
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ZHCSJQ0 –MAY 2019
LI
HI
Input
(HI, LI)
LO
TDLRR, TDHRR
Output
(HO, LO)
HO
TDLFF
,
TDHFF
Time (s)
Time (s)
TMOFF
TMON
图 1. Timing Diagram
6.7 Typical Characteristics
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
0.3
0.28
0.26
0.24
0.22
0.2
0.22
0.18
0.14
0.1
0.18
0.16
0.14
0.12
0.1
0.06
5.5V
12V
16V
5.5V
12V
16V
0.02
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
IDDQ
IHBQ
VHI = VLI = 0 V
VHI = VLI = 0 V
图 2. VDD Quiescent Current
图 3. HB Quiescent Current
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Typical Characteristics (接下页)
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
6
5
4
3
2
1
0
4.5
-40°C
25°°C
125°°C
-40°C
25°C
125°C
4
3.5
3
2.5
2
1.5
1
0.5
0
1
2
3 4 5 67 10
20 30 50 70100 200
Frequency (kHz)
500 1000
1
2
3 4 567 10
20 30 50 70100 200
Frequency (kHz)
500 1000
IDDO
IHBO
CL = 0 F
VDD =VHB= 12V
CL = 0 F
VDD =VHB= 12V
图 4. VDD Operating Current
图 5. HB Operating Current
14
12
10
8
2.22
2.21
2.2
5.5V
12V
16V
2.19
2.18
2.17
2.16
6
4
5.5V
12V
16V
2
0
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
IDD_
IN_R
CL = 0 F
VEN = 0 V
图 6. VDD Current When Disabled
图 7. Input Rising Threshold
1.145
1.14
280
270
260
250
240
230
1.135
1.13
1.125
1.12
1.115
1.11
5.5V
12V
16V
1.105
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
IN_F
R_IN
图 8. Input Falling Threshold
图 9. Input Pull-down Resistor
8
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ZHCSJQ0 –MAY 2019
Typical Characteristics (接下页)
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.35
5.5V
12V
16V
5.5V
12V
16V
1.3
1.25
1.2
1.15
1.1
1.05
1
0.95
0.9
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
EN_T
Dis_
图 10. Enable Threshold
图 11. Disable Threshold
4
3.8
3.6
3.4
3.2
3
5.2
5
4.8
4.6
4.4
4.2
Rise
Fall
Rise
Fall
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
VDDU
HBUV
图 12. VDD UVLO Threshold
图 13. HB UVLO Threshold
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1
0.8
0.6
0.4
0.2
100uA
80mA
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
R_Dy
Vf
图 14. Boot Diode Forward Voltage Drop
图 15. Boot Diode Dynamic Resistance
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Typical Characteristics (接下页)
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
15
14
13
12
11
10
9
10.5
10
9.5
9
5.5V
12V
16V
5.5V
12V
16V
8.5
8
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
LO_R
LO_F
CL=1000pF
CL=1000pF
图 16. LO Rise Time
图 17. LO Fall Time
9
8.7
8.4
8.1
7.8
7.5
7.2
18
15
12
9
5.5V
12V
16V
5.5V
12V
16V
6
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
HO_R
HO_F
CL=1000pF
CL=1000pF
图 18. HO Rise Time
图 19. HO Fall Time
20
19
18
17
16
15
14
21
20
19
18
17
16
15
14
5.5V
12V
16V
5.5V
12V
16V
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
TDHR
TDHF
CL=No Load
CL= No Load
图 21. HO Falling Propagation Delay (TDHFF)
图 20. HO Rising Propagation Delay (TDHRR)
10
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ZHCSJQ0 –MAY 2019
Typical Characteristics (接下页)
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
20
19.5
19
19
18.5
18
18.5
18
17.5
17
17.5
17
16.5
16
16.5
16
15.5
15
5.5V
12V
16V
5.5V
12V
16V
15.5
15
14.5
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
TDLR
TDLF
CL= No Load
图 22. LO Rising Propagation Delay (TDLRR)
CL= No Load
图 23. LO Falling Propagation Delay (TDLFF)
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7 Detailed Description
7.1 Overview
The LM5108 is a high-voltage gate driver designed to drive both the high-side and the low-side N-channel FETs
in a synchronous buck or a half-bridge configurations. The two outputs are independently controlled with two
TTL-compatible input signals. The device can also work with CMOS type control signals at its inputs as long as
signals meet turn-on and turn-off threshold specifications of the LM5108. The floating high-side driver is capable
of working with HS voltage up to 100 V with respect to VSS. A 100 V bootstrap diode is integrated in the LM5108
device to charge high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while
consuming low power and provides clean level transitions from the control logic to the high-side gate driver.
Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails. EN pin is provided
(in DRC packaged parts) to enable or disable the driver. The driver also has input interlock functionality, which
shuts off both the outputs when the two inputs overlap.
7.2 Functional Block Diagram
HB
UVLO
DRIVER
STAGE
HO
LEVEL
SHIFT
HS
HI
VDD
UVLO
EN
DRIVER
LO
STAGE
Interlock Logic
VSS
LI
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7.3 Feature Description
7.3.1 Enable
The device in DRC package has an enable (EN) pin. The outputs will be active only if the EN pin voltage is
above the threshold voltage. Outputs will be held low if EN pin is left floating or pulled-down to ground. An
internal 250 kΩ resistor connects EN pin to VSS pin. Thus, leaving the EN pin floating disables the device.
Externally pulling EN pin to ground shall also disable the device. If the EN pin is not used, then it is
recommended to connect it to VDD pin. If a pull-up resistor needs to be used then a strong pull-up resistor is
recommended. For 12V supply voltage, a 10kΩ pull-up is suggested. In noise prone application, a small filter
capacitor, 1nF, should be connected from the EN pin to VSS pin as close to the device as possible. An analog or
a digital controller output pin could be connected to EN pin to enable or disable the device. Built-in hysteresis
helps prevent any nuisance tripping or chattering of the outputs.
7.3.2 Start-up and UVLO
Both the high-side and the low-side driver stages include UVLO protection circuitry which monitors the supply
voltage (VDD) and the bootstrap capacitor voltage (VHB–HS). The UVLO circuit inhibits each output until sufficient
supply voltage is available to turn on the external MOSFETs. The built-in UVLO hysteresis prevents chattering
during supply voltage variations. When the supply voltage is applied to the VDD pin of the device, both the
outputs are held low until VDD exceeds the UVLO threshold, typically 5 V. Any UVLO condition on the bootstrap
capacitor (VHB–HS) disables only the high- side output (HO).
表 1. VDD UVLO Logic Operation
Condition (VHB-HS > VHBR and VEN > Enable Threshold)
HI
H
L
LI
L
HO
L
LO
L
H
H
L
L
L
VDD-VSS < VDDR during device start-up
H
L
L
L
L
L
H
L
L
L
L
H
H
L
L
L
VDD-VSS < VDDR – VDDH after device start-up
H
L
L
L
L
L
表 2. HB UVLO Logic Operation
Condition (VDD > VDDR and VEN > Enable Threshold)
HI
H
L
LI
L
HO
L
LO
L
H
H
L
L
H
L
VHB-HS < VHBR during device start-up
H
L
L
L
L
H
L
L
L
L
H
H
L
L
H
L
VHB-HS < VHBR – VHBH after device start-up
H
L
L
L
L
7.3.3 Input Stages and Interlock Protection
The two inputs operate independently, with an exception that both outputs will be pulled low when both inputs
are high or overlap. The independence allows for full control of two outputs compared to the gate drivers that
have a single input. The device has input interlock or cross-conduction protection. Whenever both the inputs are
high, the internal logic turns both the outputs off. Once the device is in shoot-through mode, when one of the
inputs goes low, the outputs follow the input logic. There is no other fixed time de-glitch filter implemented in the
device and therefore propagation delay and delay matching are not sacrificed. In other words, there is no built-in
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dead-time due to the interlock feature. Any noise on the input that could cause the output to shoot-through will be
filtered by this feature and the system stays protected. Because the inputs are independent of supply voltage,
they can be connected to outputs of either digital controller or analog controller. Small filter at the inputs of the
driver further improves system robustness in noise prone applications. The inputs have internal pull down
resistors with typical value of 250 kΩ. Thus, when the inputs are floating, the outputs are held low.
HI
LI
LO
Interlock
HO
Time
图 24. Interlock or Input Shoot-through Protection
7.3.4 Level Shifter
The level shift circuit is the interface from the high-side input, which is a VSS referenced signal, to the high-side
driver stage which is referenced to the switch node (HS pin). The level shift allows control of the HO output which
is referenced to the HS pin. The delay introduced by the level shifter is kept as low as possible and therefore the
device provides excellent propagation delay characteristic and delay matching with the low-side driver output.
Low delay matching allows power stages to operate with less dead time. The reduction in dead-time is very
important in applications where high efficiency is required.
7.3.5 Output Stage
The output stages are the interface from level shifter output to the power MOSFETs in the power train. High slew
rate, low resistance, and moderate peak current capability of both outputs allow for efficient switching of the
power MOSFETs. The low-side output stage is referenced to VSS and the high-side is referenced to HS. The
device output stages are robust to handle harsh environment. The device output stages feature a pull-up
structure which delivers the peak current when it is most needed, during the Miller plateau region of the power
switch turn on transition. The output pull-up and pull-down structure of the device is totem pole NMOS-PMOS
structure.
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7.3.6 Negative Voltage Transients
In most applications, the body diode of the external low-side power MOSFET clamps the HS node to ground. In
some situations, board capacitances and inductances can cause the HS node to transiently swing several volts
below ground, before the body diode of the external low-side MOSFET clamps this swing. When used in
conjunction with the LM5108, the HS node can swing below ground as long as specifications are not violated and
conditions mentioned in this section are followed.
HS must always be at a lower potential than HO. Pulling HO more negative than specified conditions can
activate parasitic transistors which may result in excessive current flow from the HB supply. This may result in
damage to the device. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be
placed externally between HO and HS or LO and VSS to protect the device from this type of transient. The diode
must be placed as close to the device pins as possible in order to be effective.
Ensure that the HB to HS operating voltage is 16 V or less. Hence, if the HS pin transient voltage is –5 V, then
VDD (and thus HB) is ideally limited to 11 V to keep the HB to HS voltage below 16 V. Generally when HS
swings negative, HB follows HS instantaneously and therefore the HB to HS voltage does not significantly
overshoot.
Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation of the gate
driver device. The capacitor should be located at the leads of the device to minimize series inductance. The peak
currents from LO and HO can be quite large. Any series inductances with the bypass capacitor causes voltage
ringing at the leads of the device which must be avoided for reliable operation.
7.4 Device Functional Modes
When the device is enabled, the device operates in normal mode and UVLO mode. See Start-up and UVLO for
more information on UVLO operation mode. In normal mode when the VDD and VHB–HS are above UVLO
threshold, the output stage is dependent on the states of the EN, HI and LI pins. The output HO and LO will be
low if input state is floating.
表 3. Input/Output Logic in Normal Mode of Operation
(1)
(2)
EN
HI
LI
HO
LO
H
H
L
L
L
H
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
H
L
L
L
H
L
L
L
L
H
L
L
L
H
H
L
H
H
H
L
L
L
Floating
Floating
L
L
H
H
Floating
Floating
Floating
H
Floating
Floating
(1) HO is measured with respect to HS
(2) LO is measured with respect to VSS
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Most electronic devices and applications are becoming more and more power hungry. These applications are
also reducing in overall size. One way to achieve both high power and low size is to improve the efficiency and
distribute the power loss optimally. Most of these applications employ power MOSFETs and they are being
switched at higher and higher frequencies. To operate power MOSFETs at high switching frequencies and to
reduce associated switching losses, a powerful gate driver is employed between the PWM output of controller
and the gates of the power semiconductor devices, such as power MOSFETs, IGBTs, SiC FETs, and GaN FETs.
Many of these applications require proper UVLO protection so that power semiconductor devices are turned ON
and OFF optimally. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly
drive the gates of the switching devices. With the advent of digital power, this situation is often encountered
because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a
power switch. A level-shift circuit is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V or 5
V) in order to fully turn-on the power device, minimize conduction losses, and minimize the switching losses.
Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove
inadequate with digital power because they lack level-shifting capability and under voltage lockout protection.
Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also solve other
problems such as minimizing the effect of high-frequency switching noise (by placing the high-current driver
device physically close to the power switch), driving gate-drive transformers and controlling floating power device
gates. This helps reduce power dissipation and thermal stress in controllers by moving gate charge power losses
from the controller IC to the gate driver.
LM5108 gate drivers offer high voltage (100 V), small delays (20 ns), and good driving capability (1.6 A/2.6 A) in
a single device. The floating high-side driver is capable of operating with switch node voltages up to 100 V. This
allows for N-channel MOSFETs control in half-bridge, full-bridge, synchronous buck, synchronous boost, and
active clamp topologies. LM5108 gate driver IC also has built-in bootstrap diode to help power supply designers
optimize PWB area and to help reduce bill of material cost in most applications. The driver has an enable/disable
functionality to be used in applications where driver needs to be enabled or disabled based on fault condition in
other parts of the circuit. Interlock functionality of the device is very useful in applications where overall reliability
of the system is of utmost criteria and redundant protection is desired. Each channel is controlled by its
respective input pins (HI and LI), allowing flexibility to control ON and OFF state of the output. Both the outputs
are forced OFF when the two inputs overlap.
Switching power devices such as MOSFETs have two main loss components; switching losses and conduction
losses. Conduction loss is dominated by current through the device and ON resistance of the device. Switching
losses are dominated by gate charge of the switching device, gate voltage of the switching device, and switching
frequency. Applications where operating switching frequency is very high, the switching losses start to
significantly impact overall system efficiency. In such applications, to reduce the switching losses it becomes
essential to reduce the gate voltage. The gate voltage is determined by the supply voltage the gate driver ICs,
therefore, the gate driver IC needs to operate at lower supply voltage in such applications. LM5108 gate driver
has typical UVLO level of 5V and therefore, they are perfectly suitable for such applications. There is enough
UVLO hysteresis provided to avoid any chattering or nuisance tripping which improves system robustness.
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8.2 Typical Application
7 V
75 V
EN
VDD
SECONDARY
SIDE
CIRCUIT
HB
HO
HI
LI
DRIVE
HI
HS
LO
PWM
CONTROLLER
DRIVE
LO
LM5108
ISOLATION
AND
FEEDBACK
Copyright © 2018, Texas Instruments Incorporated
图 25. Typical Application
8.2.1 Design Requirements
Table below lists the system parameters. LM5108 needs to operate satisfactorily in conjunction with them.
表 4. Design Requirements
Parameter
MOSFET
Value
CSD19535KTT
75V
Maximum Bus/Input Voltage, Vin
Operating Bias Votage, VDD
Switching Frequency, Fsw
Total Gate Charge of FET at given VDD, QG
7V
300kHz
52nC
MOSFET Internal Gate Resistance,
RGFET_Int
1.4
Maximum Duty Cycle, DMax
Gate Driver
0.5
LM5108
8.2.2 Detailed Design Procedure
8.2.2.1 Select Bootstrap and VDD Capacitor
The bootstrap capacitor must maintain the VHB-HS voltage above the UVLO threshold for normal operation.
Calculate the maximum allowable drop across the bootstrap capacitor, ΔVHB, with 公式 1.
¿VHB = VDD F VDH F VHBL
:
;
= 7 V ꢀ 1 V ꢀ (3.7 V ꢀ 0.3 V) = 2.6 V
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where
•
•
•
VDD is the supply voltage of gate driver device
VDH is the bootstrap diode forward voltage drop
VHBL is the HB falling threshold ( VHBR(max) – VHBH
)
(1)
In this example the allowed voltage drop across bootstrap capacitor is 2.6 V.
It is generally recommended that ripple voltage on both the bootstrap capacitor and VDD capacitor should be
minimized as much as possible. Many of commercial, industrial, and automotive applications use ripple value of
0.5 V.
Use 公式 2 to estimate the total charge needed per switching cycle from bootstrap capacitor.
DMAX
fSW
IHB
fSW
QTOTAL = QG + ILK × l
p + l
p
= 52 nC + 0.003 nC + 0.43 nC = 52.43 nC
where
•
•
•
•
QG is the total MOSFET gate charge
ILK is the HB to VSS leakage current from datasheet
DMax is the converter maximum duty cycle
IHB is the HB quiescent current from the datasheet
(2)
The caculated total charge is 52.43 nC.
Next, use 公式 3 to estimate the minimum bootstrap capacitor value.
QTOTAL
52.43 nC
2.6 V
CBOOT min
=
;
=
= 20.16 nF
:
¿VHB
(3)
The calculated value of minimum bootstrap capacitor is 20.16 nF. It should be noted that, this value of
capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than
calculated value to allow for situations where the power stage may skip pulse due to various transient conditions.
It is recommended to use a 100-nF bootstrap capacitor in this example. It is also recommenced to include
enough margin and place the bootstrap capacitor as close to the HB and HS pins as possible. Also place a small
size, 0402, low value, 1000 pF, capacitor to filter high frequency noise, in parallel with main bypass capacitor.
For this application, choose a CBOOT capacitor that has the following specifications: 0.1 µF, 25 V, X7R
As a general rule the local VDD bypass capacitor must be greater than the value of bootstrap capacitor value
(generally 10 times the bootstrap capacitor value). For this application choose a CVDD capacitor with the following
specifications: 1 µF , 25 V, X7R
CVDD capacitor is placed across VDD and VSS pin of the gate driver. Similar to bootstrap capacitors, place a
small size and low value capacitor in parallel with the main bypass capacitor. For this application, choose 0402,
1000 pF, capacitance in parallel with main bypass capacitor to filter high frequency noise.
The bootstrap and bias capacitors must be ceramic types with X7R dielectric or better. Choose a capacitor with a
voltage rating at least twice the maximum voltage that it will be exposed to. Choose this value because most
ceramic capacitors lose significant capacitance when biased. This value also improves the long term reliability of
the system.
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8.2.2.2 Estimate Driver Power Losses
The total power loss in gate driver device such as the LM5108 is the summation of the power loss in different
functional blocks of the gate driver device. These power loss components are explained in this section.
1. 公式 4 describes how quiescent currents (IDD and IHB) affect the static power losses, PQC
.
:
;
:
;
PQC = VDD × IDD + VDD F VDH × IHB
= 7 V × 0.28 mA + 6 V × 0.13 mA = 2.74 mW
(4)
it is not shown here, but for better approximation, no load operating current, IDDO and IHBO can be added in
above equation.
2. 公式 5 shows how high-side to low-side leakage current (ILK) affects level-shifter losses (PILK).
P
ILK
= VHB × ILK × D = 82 V × 2 µA × 0.5 = 0.082 mW
where
•
•
D is the high-side MOSFET duty cycle
VHB is the sum of input voltage and voltage across bootstrap capacitor.
(5)
3. 公式 6 shows how MOSFETs gate charge (QG) affects the dynamic losses, PQG
.
RGD _R
PQG = 2 × VDD × QG × fSW
×
RGD _R+ RGATE + RGFET int
:
;
= 2 × 7 V × 52 nC × 300 kHz × 0.74 = 0.16 W
where
•
•
•
•
•
QG is the total MOSFET gate charge
fSW is the switching frequency
RGD_R is the average value of pullup and pulldown resistor
RGATE is the external gate drive resistor
RGFET(int) is the power MOSFETs internal gate resistor
(6)
Assume there is no external gate resistor in this example. For simplicity, the resistance of the pull-up
MOSFET of the driver output section is considered here, which is typically 4 Ω. Substitute the application
values to calculate the dynamic loss due to gate charge, which is 160 mW here.
4. 公式 7 shows how parasitic level-shifter charge (QP) on each switching cycle affects dynamic losses, (PLS)
during high-side switching.
P = VHB × QP × fSW
LS
(7)
For this example and simplicity, it is assumed that value of parasitic charge QP is 1 nC. Substituting values
results in 24.6 mW as level shifter dynamic loss. This estimate is very high for level shifter dynamic losses.
The sum of all the losses is 187.42 mW as a total gate driver loss. As shown in this example, in most
applications the dynamic loss due to gate charge dominates the total power loss in gate driver device. For gate
drivers that include bootstrap diode, one should also estimate losses in bootstrap diode. Diode forward
conduction loss is computed as product of average forward voltage drop and average forward current.
公式 8 estimates the maximum allowable power loss of the device for a given ambient temperature.
kT F TAo
J
PMAX
=
REJA
where
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•
•
•
•
PMAX is the maximum allowed power dissipation in the gate driver device
TJ is the recommended maximum operating junction temperature
TA is hte ambient temperature of the gate driver device
RθJA is the junction-to-ambient thermal resistance
(8)
To better estimate the junction temperature of the gate driver device in the application, it is recommended to first
accurately measure the case temperature and then determine the power dissipation in a given application. Then
use ψJT to calculate junction temperature. After estimating junction temperature and measuring ambient
temperature in the application, calculate θJA(effective). Then, if design parameters (such as the value of an external
gate resistor or power MOSFET) change during the development of the project, use θJA(effective) to estimate how
these changes affect junction temperature of the gate driver device.
The Thermal Information table summarizes the thermal metrics for the driver package. For detailed information
regarding the thermal information table, please refer to the Semiconductor and Device Package Thermal Metrics
application report.
8.2.2.3 Selecting External Gate Resistor
In high-frequency switching power supply applications where high-current gate drivers such as the LM5108 are
used, parasitic inductances, parasitic capacitances and high-current loops can cause noise and ringing on the
gate of power MOSFETs. Often external gate resistors are used to damp this ringing and noise. In some
applications the gate charge, which is load on gate driver device, is significantly larger than gate driver peak
output current capability. In such applications external gate resistors can limit the peak output current of the gate
driver. it is recommended that there should be provision of external gate resistor whenever the layout or
application permits.
Use 公式 9 to calculate the driver high-side pull-up current.
VDD F VDH
RHOH + RGATE+ RGFET int
IOHH
=
:
;
where
•
•
•
IOHH is the high-side, peak pull-up current
VDH is the bootstrap diode forward voltage drop
RHOH is the gate driver internal high-side pull-up resistor. Value either directly provided in datasheet or can be
calculated from test conditions (RHOH = VHOH/IHO
)
•
•
RGATE is the external gate resistance connected between driver output and power MOSFET gate
RGFET(int) is the MOSFET internal gate resistance provided by MOSFET datasheet
(9)
(10)
(11)
Use 公式 10 to calculate the driver high-side sink current.
VDD F VDH
IOLH
=
RHOL + RGATE+ RGFET int
:
;
where
•
RHOL is the gate driver internal high-side pull-down resistance
Use 公式 11 to calculate the driver low-side source current.
VDD
IOHL
=
RLOH + RGATE+ RGFET int
:
;
where
•
RLOH is the gate driver internal low-side pull-up resistance
Use 公式 12 to calculate the driver low-side sink current.
VDD
IOLL
=
RLOL + RGATE+ RGFET int
:
;
where
•
RLOL is the gate driver internal low-side pull-down resistance
(12)
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Typical peak pull up and pull down current of the device is 1.6 A and 2.6 A respectively. These equations help
reduce the peak current if needed. To establish different rise time value compared to fall time value, external
gate resistor can be anti-paralleled with diode-resistor combination as shown in 图 25. Generally selecting an
optimal value or configuration of external gate resistor is an iterative process. For additional information on
selecting external gate resistor please refer to External Gate Resistor Design Guide for Gate Drivers
8.2.2.4 Delays and Pulse Width
The total delay encountered in the PWM, driver and power stage need to be considered for a number of reasons,
primarily delay in current limit response. Also to be considered are differences in delays between the drivers
which can lead to various concerns depending on the topology. The synchronous buck topology switching
requires careful selection of dead-time between the high-side and low-side switches to avoid cross conduction as
well as excessive body diode conduction.
Bridge topologies can be affected by a volt-second imbalance on the transformer if there is imbalance in the
high-side and low-side pulse widths in any operating condition. The LM5108 device has typical propagation delay
of 20 ns and typical delay matching of 1 ns.
Narrow input pulse width performance is an important consideration in gate driver devices, because output may
not follow input signals satisfactorily when input pulse widths are very narrow. Although there may be relatively
wide steady state PWM output signals from controller, very narrow pulses may be encountered under following
operating conditions.
•
•
•
soft-start period
large load transients
short circuit conditions
These narrow pulses appear as an input signal to the gate driver device and the gate driver device need to
respond properly to these narrow signals.
The LM5108 device produces reliable output pulse even when the input pulses are very narrow and bias
voltages are very low. The propagation delay and delay matching do not get affected when the input pulse width
is very narrow.
8.2.2.5 External Bootstrap Diode
The LM5108 incorporates the bootstrap diode necessary to generate the high-side bias for HO to work
satisfactorily. The characteristics of this diode are important to achieve efficient, reliable operation. The
characteristics to consider are forward voltage drop and dynamic resistance. Generally, low forward voltage drop
diodes are preferred for low power loss during charging of the bootstrap capacitor. The device has a boot diode
forward voltage drop rated at 0.9 V and dynamic resistance of 2 Ω for reliable charge transfer to the bootstrap
capacitor. The dynamic characteristics to consider are diode recovery time and stored charge. Diode recovery
times that are specified without operating conditions, can be misleading. Diode recovery times at no forward
current (IF) can be noticeably less than with forward current applied. The LM5108 boot diode recovery is
specified as 20 ns at IF = 20 mA, IREV = 0.5 A. Dynamic impedance of LM5108 bootstrap diode helps limit the
peak forward current.
In applications where switching frequencies are very high, for example in excess of 1 MHz, and the low-side
minimum pulse widths are very small, the diode peak forward current could be very high and peak reverse
current could also be very high, specifically if high bootstrap capacitor value has been chosen. In such
applications it might be advisable to use external Schottky diode as bootstrap diode. It is safe to at least make a
provision for such diode on the board if possible.
8.2.2.6 VDD and Input Filter
Some switching power supply applications are extremely noisy. Noise may come from ground bouncing and
ringing at the inputs, (which are the HI and LI pins of the gate driver device). To mitigate such situations, the
LM5108 offers wide input threshold hysteresis. If these features are not enough, then the application might need
an input filter. Small filter such as 10-Ω resistor and 47-pF capacitor might be sufficient to filter noise at the inputs
of the gate driver device. This RC filter would introduce delay and therefore need to be considered carefully. High
frequency noise on bias supply can cause problems in performance of the gate driver device. To filter this noise
it is recommended to use 1-Ω resistor in series with VDD pin as shown in 图 25. This resistor also acts as a
current limiting element. In the event of short circuit on the bias rail, this resistor opens up and prevents further
damage. This resistor can also be helpful in debugging the design during development phase.
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8.2.2.7 Transient Protection
As mentioned in previous sections, high power high switching frequency power supplies are inherently noisy.
High dV/dt and dI/dt in the circuit can cause negative voltage on different pins such as HO, LO, and HS. The
device tolerates negative voltage on HS pin as mentioned in specification tables. If parasitic elements of the
circuit cause very large negative swings, circuit might require additional protection. In such cases fast acting and
low leakage type Schottky diode should be used. This diode must be placed as close to the gate driver device
pin as possible for it to be effective in clamping excessive negative voltage on the gate driver device pin.
Sometimes a small resistor, (for example 2 Ω, in series with HS pin) is also effective in improving performance
reliability. To avoid the possibility of driver device damage due to over-voltage on its output pins or supply pins,
low leakage Zener diode can be used. A 15-V Zener diode is often sufficient to clamp the voltage below the
maximum recommended value of 16 V.
8.2.3 Application Curves
To minimize the switching losses in power supplies, turn-ON and turn-OFF of the power MOSFETs need to be
as fast as possible. Higher the drive current capability of the driver, faster the switching. Therefore, the LM5108
is designed with high drive current capability and low resistance of the output stages. One of the common way to
test the drive capability of the gate driver device , is to test it under heavy load. Rise time and fall time of the
outputs would provide idea of drive capability of the gate driver device. There must not be any resistance in this
test circuit. 图 26 and 图 27 shows rise time and fall time of HO respectively of LM5108. 图 28 and 图 29 shows
rise time and fall time of LO respectively of LM5108. For accuracy purpose, the VDD and HB pin of the gate
driver device were connected together. HS and VSS pins are also connected together for this test.
Peak current capability can be estimated using the fastest dV/dt along the rise and fall curve of the plot. This
method is also useful in comparing performance of two or more gate driver devices.
As explained in Delays and Pulse Width, propagation delay plays an important role in reliable operation of many
applications. 图 30 and 图 31 shows propagation delays of LM5108. In many switching power supply applications
input signals to the gate driver have large amplitude high frequency noise. If there is no filter employed at the
input, then there is a possibility of false signal passing through the gate driver and causing shoot-through on the
output. LM5108 prevents such shoot-through. If two inputs are high at the same time, LM5108 shuts both the
outputs off. 图 32 shows interlock feature of LM5108.
VDD=VHB=12 V,
HS=VSS
CLOAD=68 nF
Ch1=HI, Ch3=HO
CLOAD=68
nF
Ch1=HI, Ch3=HO
VDD=VHB=12 V, HS=VSS
图 26. HO Rise Time
图 27. HO Fall Time
22
版权 © 2019, Texas Instruments Incorporated
LM5108
www.ti.com.cn
ZHCSJQ0 –MAY 2019
VDD=VHB=12 V, HS=VSS
CLOAD=68 nF
Ch2=LI,
Ch4=LO
VDD=VHB=12 V, HS=VSS
CLOAD=68 nF
Ch2=LI,
Ch4=LO
图 28. LO Rise Time
图 29. LO Fall Time
VDD=VHB
12 V,
=
CLOAD=No
load
Ch1=HI Ch2=LI Ch3=HO Ch4=LO
VDD=VHB
=12 V,
CLOAD=No
load
Ch1=HI Ch2=LI Ch3=HO Ch4=LO
HS=VSS
HS=VSS
图 30. Propagation Delay
图 31. Propagation Delay
HI (2V/div)
LI (2V/div)
HO (5V/div)
LO (5V/div)
VDD=VHB=12 V, HS=VSS
图 32. Shoot-through Protection or Interlock
CLOAD=0 nF
版权 © 2019, Texas Instruments Incorporated
23
LM5108
ZHCSJQ0 –MAY 2019
www.ti.com.cn
9 Power Supply Recommendations
The recommended bias supply voltage range for LM5108 is from 5.5 V to 16 V. The lower end of this range is
governed by the internal under voltage-lockout (UVLO) protection feature, 5 V typical, of the VDD supply circuit
block. The upper end of this range is driven by the 16-V recomended maximum voltage rating of the VDD. It is
recommended that voltage on VDD pin should be lower than maximum recommended voltage.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage
drop do not exceeds the hysteresis specification, VDDHYS. If the voltage drop is more than hysteresis
specification, the device shuts down. Therefore, while operating at or near the 5.5-V range, the voltage ripple on
the auxiliary power supply output should be smaller than the hysteresis specification of LM5108 to avoid
triggering device shutdown.
A local bypass capacitor should be placed between the VDD and GND pins. This capacitor should be located as
close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is
recommended to use two capacitors across VDD and GND: a low capacitance ceramic surface-mount capacitor
for high frequency filtering placed very close to VDD and GND pin, and another high capacitance value surface-
mount capacitor for device bias requirements. In a similar manner, the current pulses delivered by the HO pin are
sourced from the HB pin. Therefore, two capacitors across the HB to HS are recommended. One low value small
size capacitor for high frequency filtering and another one high capacitance value capacitor to deliver HO pulses.
LM5108 has enable/disable functionality through EN pin. Therefore, signal at the EN pin should be as clean as
possible. If EN pin is not used, then it is recommended to connect the pin to VDD pin. If EN pin is pulled up
through a resistor, then the pull-up resistor needs to be strong. In noise prone applications, it is recommended to
filter the EN pin with small capacitor, such as X7R 0402 1nF.
In power supplies where noise is very dominant and there is space on the PWB (Printed Wiring Board), it is
recommended to place a small RC filter at the inputs. This allows for improving the overall performance of the
design. In such applications. it is also recommended to have a place holder for power MOSFET external gate
resistor. This resistor allows the control of not only the drive capability but also the slew rate on HS, which
impacts the performance of the high-side circuit. If diode is used across the external gate resistor, it is
recommended to use a resistor in series with the diode, which provides further control of fall time.
In power supply applications such as motor drives, there exist a lot of transients through-out the system. This
sometime causes over voltage and under voltage spikes on almost all pins of the gate driver device. To increase
the robustness of the design, it is recommended that the clamp diode should be used on the those pins. If user
does not wish to use power MOSFET parasitic diode, external clamp diode on HS pin is recommended, which
needs to be high voltage high current type (same rating as MOSFET) and very fast acting. The leakage of these
diodes across the temperature needs to be minimal.
In power supply applications where it is almost certain that there is excessive negative HS voltage, it is
recommended to place a small resistor between the HS pin and the switch node. This resistance helps limit
current into the driver device up to some extent. This resistor will impact the high side drive capability and
therefore needs to be considered carefully.
24
版权 © 2019, Texas Instruments Incorporated
LM5108
www.ti.com.cn
ZHCSJQ0 –MAY 2019
10 Layout
10.1 Layout Guidelines
To achieve optimum performance of high-side and low-side gate drivers, one must consider following printed
wiring board (PWB) layout guidelines.
•
Low ESR/ESL capacitors must be connected close to the device between VDD and VSS pins and between
HB and HS pins to support high peak currents drawn from VDD and HB pins during the turn-on of the
external MOSFETs.
•
•
To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the high side MOSFET drain and ground (VSS).
In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the
source of the high-side MOSFET and the drain of the low-side MOSFET (synchronous rectifier) must be
minimized.
•
•
Overlapping of HS plane and ground (VSS) plane should be minimized as much as possible so that coupling
of switching noise into the ground plane is minimized.
Thermal pad should be connected to large heavy copper plane to improve the thermal performance of the
device. Generally it is connected to the ground plane which is the same as VSS of the device. It is
recommended to connect this pad to the VSS pin only.
•
Grounding considerations:
–
The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area. This confinement decreases the loop inductance
and minimize noise issues on the gate terminals of the MOSFETs. Place the gate driver as close to the
MOSFETs as possible.
–
The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap
diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The
bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground
referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.
10.2 Layout Example
VSS Plane
(Top and Bottom Layer)
Input Filters
(Top Layer)
Input PWMs
VDD Capacitors
(Top Layer)
To Low Side
MOSFET
图 33. Layout Example
版权 © 2019, Texas Instruments Incorporated
25
LM5108
ZHCSJQ0 –MAY 2019
www.ti.com.cn
11 器件和文档支持
11.1 接收文档更新通知
如需接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收
产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
26
版权 © 2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5108DRCR
LM5108DRCT
ACTIVE
ACTIVE
VSON
VSON
DRC
DRC
10
10
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
LM5108
LM5108
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Addendum-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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相关型号：
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IC 1 A HALF BRDG BASED MOSFET DRIVER, PDSO8, LEAD FREE, MS-012AA, SOIC-8, MOSFET Driver
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