LM5123QRGRRQ1 [TI]
2.2MHz 宽输入电压、低 IQ 同步升压控制器 | RGR | 20 | -40 to 150;
| 型号： | LM5123QRGRRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.2MHz 宽输入电压、低 IQ 同步升压控制器 | RGR | 20 | -40 to 150 控制器 |
| 文件： | 总43页 (文件大小：1599K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5123-Q1
ZHCSMW2B –DECEMBER 2021 –REVISED DECEMBER 2022
LM5123-Q1 2.2MHz 宽VIN 低IQ 同步升压控制器，具有VOUT 跟踪功能
• 降低EMI
1 特性
– 可选可编程扩展频谱
• 符合面向汽车应用的AEC-Q100 标准
– 无引线封装
• 可编程性和灵活性
– 动态VOUT 跟踪
– 动态开关频率编程
– 可编程线路UVLO
– 可调软启动
– 自适应死区时间
– PGOOD 指示器
• 集成型保护特性
– 逐周期峰值电流限制
– 过压保护
– 温度等级1：–40°C 至+125°C，TA
• 提供功能安全
– 可帮助进行功能安全系统设计的文档
• 适用于宽工作电压范围的汽车类电池供电应用
– 3.8V 至42V 输入电压工作范围
– 5V 至20V 或15V 至57V 的动态可编程VOUT
– BIAS 电压大于等于3.8V 时最小升压输入为
0.8V
– VSUPPLY > VLOAD 时进行旁路操作
• 最小电池消耗
– HB-SW 短路保护
– 热关断
– 关断电流≤3μA
– 自动模式转换
– 睡眠模式下的电池消耗≤11μA（旁路操作，
电荷泵关闭）
– 睡眠模式下的电池消耗≤38μA（旁路操作，
电荷泵打开）
– 睡眠模式下的偏置电流IQ ≤13μA（跳跃模
式）
2 应用
• 具有跟踪功能的汽车音频电源
• 汽车LED 偏置电源
• 汽车HVAC 控制器电源
• 汽车电机电源
3 说明
– 强大的5V MOSFET 驱动器
• 解决方案尺寸小、成本低
– 最大开关频率：2.2MHz
LM5123-Q1 器件是一款采用峰值电流模式控制的宽输
入范围同步升压控制器。
– 内部自举二极管
器件信息
封装(1)
– 在VIN 范围内峰值电流限制保持恒定
– 支持DCR 电感器电流感应
– 具有可湿性侧面的QFN-20 封装
• 避免AM 频带干扰和串扰
封装尺寸（标称值）
器件型号
LM5123-Q1
QFN (20)
3.5mm x 3.5mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 可选的时钟同步
– 开关频率范围为100kHz 至2.2MHz
– 可选开关模式（FPWM、二极管仿真和跳跃模
式）
VLOAD
VSUPPLY
VOUT
HB
BIAS
VCC
RT
HO
SS
VSUPPLY
SW
COMP
LO
MODE
AGND
VDD(MCU)
PGND
Power Good
Indicator to MCU
CSN
PGOOD
VREF
TRK
VSUPPLY
CSP
UVLO
SYNC/DITHER
Envelope
tracking input
from MCU
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFF1
LM5123-Q1
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ZHCSMW2B –DECEMBER 2021 –REVISED DECEMBER 2022
Table of Contents
9 Application and Implementation..................................33
9.1 Application Information............................................. 33
9.2 Typical Application.................................................... 33
9.3 System Example.......................................................35
10 Power Supply Recommendations..............................36
11 Layout...........................................................................37
11.1 Layout Guidelines................................................... 37
11.2 Layout Example...................................................... 38
12 Device and Documentation Support..........................39
12.1 Device Support....................................................... 39
12.2 接收文档更新通知................................................... 39
12.3 支持资源..................................................................39
12.4 Trademarks.............................................................39
12.5 Electrostatic Discharge Caution..............................39
12.6 术语表..................................................................... 39
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................7
7.6 Typical Characteristics..............................................12
8 Detailed Description......................................................15
8.1 Overview...................................................................15
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................29
Information.................................................................... 39
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2021) to Revision B (January 2022)
Page
• Updated Bias current and battery drain in deep sleep........................................................................................7
• Updated overvoltage (OVP) and undervoltage threshold (PGOOD).................................................................. 7
• Updated dead time............................................................................................................................................. 7
• Updated HB diode resistance.............................................................................................................................7
• Updated VOUT regulation target voltages..........................................................................................................7
Changes from Revision * (December 2020) to Revision A (December 2021)
Page
• 将文档状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 说明（续）
该器件采用低关断IQ 和低IQ 睡眠模式，可尽可能减少无负载和轻负载条件下的电池消耗。该器件还支持旁路模式
的超低 IQ 深度睡眠模式，当电源电压大于升压输出调节目标时，无需外部旁路开关。可使用跟踪功能对此输出电
压进行动态编程。
该器件的宽输入范围支持汽车冷启动和负载突降。当BIAS 等于或大于3.8V 时，最小输入电压可低至0.8V。用户
可通过外部电阻器对开关频率进行动态编程，编程范围为 100kHz 至 2.2MHz。2.2MHz 的开关频率可更大限度地
降低 AM 频带干扰，并支持实现小解决方案尺寸和快速瞬态响应。与转换器架构相比，控制器架构简化了严苛环
境温度条件下的热管理性能。
该器件具有内置的保护功能，例如在 VIN 范围内保持恒定的峰值电流限制、过压保护和热关断功能。外部时钟同
步、可编程展频调制以及具有超低寄生效应的无引线封装有助于降低 EMI 并避免串扰问题。附加功能包括线路
UVLO、FPWM、二极管仿真、DCR 电感器电流检测、可编程的软启动和电源正常状态指示器。
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ZHCSMW2B –DECEMBER 2021 –REVISED DECEMBER 2022
6 Pin Configuration and Functions
20 19
18 17 16
CSP
CSN
1
2
3
4
5
15
14 SYNC/DITHER/VH/CP
13
RT
EP
VOUT/SENSE
PGOOD
HO
UVLO/EN
12 MODE
11 LO
6
7
8
9
10
20-Pin QFN with Wettable Flanks RGR Package (Top View)
表6-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
CSP
NO.
1
I
I
Current sense amplifier input. The pin operates as the positive input pin.
Current sense amplifier input. The pin operates as the negative input pin.
CSN
2
Output voltage sensing pin. An internal feedback resistor voltage divider is connected
from the pin to AGND. Connect a 0.1-μF local VOUT capacitor from the pin to ground.
VOUT/SENSE
3
I
High-side MOSFET drain voltage sensing pin. Connect the pin to the drain of the high-
side MOSFET through a short, low inductance path.
Power-good indicator with open-drain output stage. The pin is grounded when the output
voltage is less than the undervoltage threshold. The pin can be left floating if not used.
PGOOD
HO
4
5
O
O
High-side gate driver output. Connect directly to the gate of the high-side N-channel
MOSFET through a short, low inductance path.
Switching node connection and the high-side MOSFET source voltage sensing pin.
Connect directly to the source of the high-side N-channel MOSFET and the drain of the
low-side N-channel MOSFET through a short, low inductance path. Connect to PGND
for non-synchronous boost configuration.
SW
HB
6
7
P
P
High-side driver supply for bootstrap gate drive. Boot diode is internally connected from
VCC to the pin. Connect a 0.1-μF capacitor between the pin and SW. Connect to VCC
for non-synchronous boost configuration.
Supply voltage input to the VCC regulator. Connect a 1-μF local BIAS capacitor from
the pin to ground.
BIAS
VCC
PGND
LO
8
9
P
P
Output of the internal VCC regulator and supply voltage input of the internal MOSFET
drivers. Connect a 4.7-μF capacitor between the pin and PGND.
Power ground pin. Connect directly to the source of the low-side N-channel MOSFET
and the power ground plane through a short, low inductance path.
10
11
G
O
Low-side gate driver output. Connect directly to the gate of the low-side N-channel
MOSFET through a short, low inductance path.
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表6-1. Pin Functions (continued)
PIN
I/O(1)
DESCRIPTION
NAME
NO.
Device switching mode (FPWM, diode emulation, or skip) selection pin. The device is
configured to skip mode if the pin is open or if a resistor that is greater than 500 kΩis
connected from the pin to AGND during initial power-on. The device is configured to
FPWM mode by connecting the pin to VCC or if the pin voltage is greater than 2.0 V
during power-on. The device is configured to diode emulation mode by connecting the
pin to ground or the pin voltage is less than 0.4 V during initial power-on. The switching
mode can be dynamically programmed between the FPWM and the DE mode during
operation.
MODE
12
I
Enable pin. The pin enables/disables the device. If the pin is less than 0.35 V, the device
shuts down. The pin must be raised above 0.65 V to enable the device.
Undervoltage lockout programming pin. The converter start-up and shutdown levels can
be programmed by connecting the pin to the supply voltage through a resistor voltage
divider. The low-side UVLO resistor must be connected to AGND. Connect to BIAS if not
used.
UVLO/EN
13
I
Synchronization clock input. The internal oscillator can be synchronized to an external
clock during operation. Connect to AGND if not used.
Clock dithering/spread spectrum modulation frequency programming pin. If a capacitor
is connected between the pin and AGND, the clock dithering/spread spectrum function
is activated. During the dithering operation, the capacitor is charged and discharged with
an internal 20-μA current source/sink. As the voltage on the pin ramps up and down,
the oscillator frequency is modulated between –6% and +5% of the nominal frequency
set by the RT resistor. The clock dithering/spread spectrum can be deactivated during
operation by pulling down the pin to ground.
SYNC/DITHER/VH/CP
14
I/O
VCC hold pin. If the pin is greater than 2.0 V, the device holds the VCC pin voltage when
the EN pin is grounded, which helps to restart fast without reconfiguration.
Charge pump enable pin. If the pin is greater than 2.0 V, the internal charge pump
maintains the HB pin voltage above its HB UVLO threshold for bypass operation, which
allows the high-side switch to turn on 100% during bypass operation.
Switching frequency setting pin. If no external clock is applied to the SYNC pin, the
switching frequency is programmed by a single resistor between the pin and AGND.
Switching frequency is dynamically programmable during operation.
RT
15
16
I
1.0-V internal reference voltage output. Connect a 470-pF capacitor from the pin to
AGND. The VOUT regulation target can be programmed by connecting a resistor voltage
divider from the pin to TRK. The resistance from the pin to AGND must be always
greater than 20 kΩif used. Connect the low-side resistor of the divider to AGND.
VOUT range selection pin. Lower VOUT range (5 V to 20 V) is selected if the resistance
from the pin to AGND is in the range of 75 kΩand 100 kΩduring initial power-on.
Upper VOUT range (15 V to 57 V) is selected if the resistance from the pin to AGND is
in the range of 20 kΩand 35 kΩduring initial power-on. Boost converter output voltage
can be dynamically programmed within the pre-programmed range. The accuracy of the
output voltage regulation is specified within the selected range.
VREF/RANGE
I/O
Soft-start time programming pin. An external capacitor and an internal current source set
the ramp rate of the internal error amplifier reference during soft start. The device forces
diode emulation during soft-start time.
SS
17
18
I/O
I
Output regulation target programming pin. The VOUT regulation target can be
programmed by connecting the pin to VREF through a resistor voltage divider or by
controlling the pin voltage directly from a D/A. The recommended operating range of the
pin is from 0.25 V to 1.0 V.
TRK
AGND
COMP
19
20
G
O
Analog ground pin. Connect to the analog ground plane through a wide and short path.
Output of the internal transconductance error amplifier. Connect the loop compensation
components between the pin and AGND.
Exposed pad of the package. The EP must be soldered to a large analog ground plane
to reduce thermal resistance.
EP
—
(1) G = Ground, I = Input, O = Output, P = Power
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range (unless otherwise specified)(1)
MIN
MAX
UNIT
BIAS to AGND
UVLO to AGND
CSP to AGND
50
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
-0.3
BIAS + 0.3
50
0.3
CSP to CSN
VOUT to AGND
HB to AGND
65
65
Input(2)
V
HB to SW
5.8(3)
60
SW to AGND
SW to AGND (50ns)
MODE, SYNC, TRK to AGND
PGOOD to AGND
RT to AGND
–1
5.5
VOUT + 0.3
2.5
–0.3
–0.3
–0.3
–0.3
–0.3
–1
PGND to AGND
VCC to AGND
0.3
5.8(3)
HO to SW (50 ns)
LO to PGND (50 ns)
Output(2)
V
–1
VREF, SS, COMP to AGND(4)
5.5
150
150
–0.3
–40
–55
(5)
Operating junction temperature, TJ
Storage temperature, TSTG
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) It is not allowed to apply an external voltage directly to VREF, COMP, SS, RT, LO, and HO pins.
(3) Operating lifetime is de-rated when the pin voltage is greater than 5.5 V.
(4) Maximum VREF pin sourcing current is 50 μA.
(5) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±2000
Electrostatic
discharge
V(ESD)
V
All pins
±500
±750
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
Corner pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range (unless otherwise specified)(1)
MIN
NOM
MAX
42
UNIT
VSUPPLY(BOOST)
VLOAD(BOOST)
VBIAS
0.8
5
Boost converter input (when BIAS ≥3.8 V)
Boost converter output
BIAS input
57
3.8
0
42
VUVLO
UVLO input
42
V
VCSP, VCSN
VVOUT
Current sense input
0.8
5
42
Boost output sense
57
VTRK
TRK input
0.25
0
1(3)
5.25
2200
2200
150
VSYNC
Synchronization pulse input
Typical switching frequency
Synchronization pulse frequency
Operating junction temperature(2)
fSW
100
200
–40
kHz
°C
fSYNC
TJ
(1) Operating Ratings are conditions under the device is intended to be functional. For specifications and test conditions, see Electrical
Characteristics.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
(3) The maximum TRK pin voltage is limited to 0.95 V when the upper VOUT range is selected.
7.4 Thermal Information
RGR (QFN)
THERMAL METRIC(1)
UNIT
20 PINS
43.3
39.9
17.8
0.8
RqJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RqJC(top)
RqJB
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
yJB
17.8
5.3
RqJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C. Unless otherwise
stated, VBIAS = 12 V, VVOUT = 12 V, RT = 9.09 kΩ, RVREF = 65 kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
2.5
10
MAX
UNIT
SUPPLY CURRENT(BIAS, VCC, VOUT)
IBIAS-SD
BIAS current in shutdown
VUVLO = 0 V, VOUT = 11.3 V
5
µA
BIAS current in deep sleep (skip
or diode emulation mode, charge VUVLO = 2.5 V, VTRK = 0.25 V, VSYNC
pump off, VCC is supplied by
BIAS)
=
=
=
=
IBIAS-DS1
16
µA
0 V, VOUT = 12 V
BIAS current in deep sleep
(FPWM mode, charge pump off,
VCC is supplied by BIAS)
VUVLO = 2.5 V, VTRK = 0.25 V, VSYNC
0 V, VOUT = 12 V
IBIAS-DS2
IBIAS-DS3
IBIAS-DS4
40
32
69
60
µA
µA
µA
BIAS current in deep sleep (skip
or diode emulation mode, charge VUVLO = 2.5 V, VTRK = 0.25 V, VSYNC
pump on, VCC is supplied by
BIAS)
2.5 V, VOUT = 12 V
BIAS current in deep sleep
(FPWM mode, charge pump on,
VCC is supplied by BIAS)
VUVLO = 2.5 V, VTRK = 0.25 V, VSYNC
2.5 V, VOUT = 12 V
114
154
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7.5 Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C. Unless otherwise
stated, VBIAS = 12 V, VVOUT = 12 V, RT = 9.09 kΩ, RVREF = 65 kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BIAS current in sleep (skip
mode, VCC is supplied by BIAS) OPEN, VOUT = 5 V
VUVLO = 2.5 V, VTRK = 0.25 V, MODE =
IBIAS-SLEEP
13
17.5
µA
BIAS current in active (non-
switching, VCC is supplied by
BIAS)
VUVLO = 2.5 V, VTRK = 0.6 V, MODE =
VCC
IBIAS-ACTIVE
IVOUT-SD
IVOUT-DS
IVOUT-ACTIVE
IBATTERY-SD
1.2
1.2
1.5
mA
VOUT current in shutdown
VUVLO = 0 V, VOUT = 11.3 V
1
µA
µA
VOUT current in deep sleep
(diode emulation mode)
VUVLO = 2.5 V, VTRK = 0.25 V, VOUT
12 V
=
1.5
VOUT current in active (non-
switching)
VUVLO = 2.5 V, VTRK = 0.6 V, MODE =
VCC
42
55
5
µA
µA
Battery drain in shutdown
VUVLO = 0 V, VOUT = 11.3 V
2.5
Battery drain in deep sleep (skip
or diode emulation mode, charge
pump off)
VUVLO = 2.5 V, VTRK = 0.25 V, VSYNC
0 V
=
IBATTERY-DS1
IBATTERY-DS2
IBATTERY-DS3
IBATTERY-DS4
11
41
17
70
µA
µA
µA
µA
Battery drain in deep
sleep (FPWM mode, charge
pump off)
VUVLO = 2.5 V, VTRK = 0.25 V, VSYNC
0 V
=
=
=
Battery drain in deep sleep (skip
or diode emulation mode, charge
pump on)
VUVLO = 2.5 V, VTRK = 0.25 V, VSYNC
2.5 V
33
62
Battery drain in deep
sleep (FPWM mode, charge
pump on)
VUVLO = 2.5 V, VTRK = 0.25 V, VSYNC
2.5 V
115
155
ENABLE, UVLO
VEN-RISING
Enable threshold
Enable threshold
Enable hysteresis
EN rising
EN falling
EN falling
0.45
0.35
55
0.55
0.45
90
0.65
0.55
130
V
V
VEN-FALLING
VEN-HYS
mV
UVLO pulldown hysteresis
current
IUVLO-HYS
VUVLO = 0.7 V
8
10
12
µA
VUVLO-RISING
VUVLO-FALLING
VUVLO-HYS
UVLO threshold
UVLO threshold
UVLO hysteresis
UVLO rising
UVLO falling
UVLO falling
1.05
1.1
1.075
25
1.15
V
V
1.025
1.125
mV
SYNC/DITHER/VH/CP
SYNC threshold/SYNC detection
VSYNC-RISING
SYNC rising
SYNC falling
2
V
V
threshold
VSYNC-FALLING
SYNC threshold
0.4
16
Minimum SYNC pull up pulse
width
100
26
ns
µA
IDITHER
Dither source/sink current
fSW modulation (upper limit)
fSW modulation (lower limit)
Dither disable threshold
21
5%
ΔfSW1
ΔfSW2
–6%
VDITHER-FALLING
VCC
0.65
0.75
0.85
V
VVCC-REG1
VVCC-REG2
VVCC-REG3
VVCC-UVLO-RISING
VCC regulation
IVCC = 100 mA
No load
4.75
4.75
3.45
3.55
3.2
5
5
5.25
5.25
V
V
V
V
V
VCC regulation
VCC regulation during dropout
VCC UVLO threshold
VBIAS = 3.8 V, IVCC = 100 mA
VCC rising
3.65
3.3
3.75
3.4
VVCC-UVLO-FALLING VCC UVLO threshold
VCC falling
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7.5 Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C. Unless otherwise
stated, VBIAS = 12 V, VVOUT = 12 V, RT = 9.09 kΩ, RVREF = 65 kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVCC-CL
VCC sourcing current limit
VVCC = 4 V
100
mA
CONFIGURATION (MODE)
VMODE-RISING
VMODE-FALLING
RT
FPWM mode threshold
MODE rising
2.0
V
V
Diode emulation mode threshold MODE falling
0.4
VRT
RT regulation
0.5
V
VREF, TRK, VOUT
VREF
VREF regulation target
0.99
1
5
1.005
5.085
V
V
VOUT regulation target1 with
resistor divider (lower VOUT
range)
VREF resistor divider to make VTRK
0.25 V, RVREF = 65 kΩ
=
=
=
=
=
=
VOUT-REG
VOUT-REG
VOUT-REG
VOUT-REG
VOUT-REG
VOUT-REG
4.915
VOUT regulation target2 with
resistor divider (lower VOUT
range)
VREF resistor divider to make VTRK
0.5 V, RVREF = 65 kΩ
9.9
19.8
10
20
15
30
57
10.1
20.2
V
V
V
V
V
VOUT regulation target3 with
resistor divider (lower VOUT
range)
VREF resistor divider to make VTRK
1.0 V, RVREF = 65 kΩ
VOUT regulation target4 with
resistor divider (upper VOUT
range)
VREF resistor divider to make VTRK
0.25 V, RVREF = 35 kΩ
14.74
29.7
15.24
30.3
VOUT regulation target5 with
resistor divider (upper VOUT
range)
VREF resistor divider to make VTRK
0.5 V, RVREF = 35 kΩ
VOUT regulation target6 with
resistor divider (upper VOUT
range)
VREF resistor divider to make VTRK
0.95 V, RVREF = 35 kΩ
56.43
57.57
VOUT regulation target1 using
TRK (lower VOUT range)
VOUT-REG
VOUT-REG
VOUT-REG
VOUT-REG
VOUT-REG
4.91
9.88
5
10
20
15
30
57
5.09
10.11
20.2
V
V
V
V
V
VTRK = 0.25 V, RVREF = 65 kΩ
VTRK = 0.5 V, RVREF = 65 kΩ
VTRK = 1.0 V, RVREF = 65 kΩ
VTRK = 0.25 V, RVREF = 35 kΩ
VTRK = 0.5 V, RVREF = 35 kΩ
VTRK = 0.95 V, RVREF = 35 kΩ
VOUT regulation target2 using
TRK (lower VOUT range)
VOUT regulation target3 using
TRK (lower VOUT range)
19.8
VOUT regulation target4 using
TRK (upper VOUT range)
14.71
29.6
15.25
30.3
VOUT regulation target5 using
TRK (upper VOUT range)
VOUT regulation target6 using
TRK (upper VOUT range)
VOUT-REG
ITRK
56.45
57.5
1
V
TRK bias current
uA
SOFT START, DE to FPWM TRANSITION
ISS
Soft-start current
17
20
1.5
30
50
55
23
1.7
70
75
75
µA
V
VSS-DONE
RSS
VSS-DIS
VSS-FB
MODE transition start
SS rising
VFB = 0 V
1.3
SS pulldown switch RDSON
SS discharge detection threshold
Internal SS to FB clamp
Ω
30
mV
mV
CURRENT SENSE (CSP, CSN, SW, SENSE)
Peak slope compensation
amplitude
VSLOPE
Referenced to CS input
CSP = 3.0 V
45
10
mV
V/V
ACS
Current sense amplifier gain
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7.5 Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C. Unless otherwise
stated, VBIAS = 12 V, VVOUT = 12 V, RT = 9.09 kΩ, RVREF = 65 kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Current sense amplifier gain
CSP = 1.5 V
10
V/V
Positive peak current limit
threshold (CSP-CSN)
VCLTH
CSP = 3.0 V, MODE = GND
54
51
60
66
72
mV
mV
Positive peak current limit
threshold (CSP-CSN)
CSP = 1.5 V, MODE = GND
MODE = GND
60
4
VZCD-DE
ICSN
ZCD threshold (SW-SENSE)
CSN bias current
mV
µA
µA
1
ICSP
CSP bias current
110
BOOT FAULT PROTECTION (HB)
Maximum replenish pulse cycles
4
cycles
cycles
Replenish off cycles
12
Number of sets to enter hiccup
mode protection
4
sets
Off-cycle during hiccup mode off
512
cycles
ERROR AMPLIFIER (COMP)
Gm
Transconductance
1
mA/V
µA
Maximum COMP sourcing
current
ISOURCE-MAX
VCOMP = 0 V
95
ISINK-MAX
Maximum COMP sinking current VCOMP = 1.8 V
COMP maximum clamp voltage COMP rising
COMP minimum clamp voltage,
90
µA
V
VCLAMP-MAX
1.8
2.2
2.55
VCLAMP-MIN
active in sleep and deep sleep
mode
COMP falling
0.25
V
PULSE WIDTH MODULATION (PWM)
fSW1
Switching frequency
85
1980
14
100
2200
20
115
2420
50
kHz
kHz
ns
RT = 220 kΩ
RT = 9.09 kΩ
RT = 9.09 kΩ
RT = 9.09 kΩ
RT = 220 kΩ
RT = 9.09 kΩ
fSW2
Switching frequency
tON-MIN
tOFF-MIN
DMAX1
DMAX2
Minimum controllable on-time
Minimum forced off-time
Maximum duty cycle limit
Maximum duty cycle limit
70
95
115
ns
90%
75%
94%
80%
98%
83%
LOW IQ SLEEP MODE
VWAKE
Internal wakeup threshold
VOUT falling (referenced to VOUT-REG
)
98.5%
5
Sleep to wake-up delay
RT = 9.09 kΩ
μs
PGOOD, OVP
Overvoltage threshold (OVP
threshold)
VOVTH-RISING
VOUT rising (reference to VOUT-REG
)
104.5%
100.5%
91.5%
89.5%
108%
105%
94%
111%
109%
98%
Overvoltage threshold (OVP
threshold)
VOVTH-FALLING
VUVTH-RISING
VUVTH-FALLING
VOUT falling (reference to VOUT-REG
)
Undervoltage threshold (PGOOD
threshold)
VOUT rising (reference to VOUT-REG
)
Undervoltage threshold (PGOOD
threshold)
VOUT falling (reference to VOUT-REG
)
92%
95.5%
UV comparator deglich filter
UV comparator deglich filter
PGOOD pulldown switch RDSON
Minimum BIAS for valid PGOOD
Rising edge
Falling edge
26
21
90
µs
µs
RPGOOD
180
2.5
Ω
V
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7.5 Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C. Unless otherwise
stated, VBIAS = 12 V, VVOUT = 12 V, RT = 9.09 kΩ, RVREF = 65 kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOSFET DRIVER
High-state voltage drop (HO
driver)
100-mA sinking
0.08
0.04
0.08
0.04
0.15
0.1
V
V
V
V
Low-state voltage drop (HO
driver)
100-mA sourcing
100-mA sinking
100-mA sourcing
High-state voltage drop (LO
driver)
0.17
0.1
Low-state voltage drop (LO
driver)
VHB-UVLO
IHB-SLEEP
tDHL
HB-SW UVLO threshold
HB quiescent current in sleep
HO off to LO on deadtime
LO off to HO on deadtime
HB diode resistance
HB-SW falling
HB-SW = 5V
2.2
2.5
3.5
20
3.0
7
V
µA
ns
ns
Ω
tDLH
22
1.2
THERMAL SHUTDOWN
TTSD-RISING Thermal shutdown threshold
TTSD-HYS Thermal shutdown hysteresis
Temperature rising
175
15
°C
°C
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7.6 Typical Characteristics
2400
2200
2000
1800
1600
1400
1200
1000
800
2.42
2.38
2.34
2.3
2.26
2.22
2.18
2.14
2.1
600
2.06
2.02
1.98
400
200
0
5
6 7 8 10
20
30 40 50 70 100
RT Resistor (k)
200 300
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (°C)
图7-1. Frequency vs RT Resistance
图7-2. Frequency vs Temperature
(RT = 9.09 kΩ, 2.2 MHz)
115
112
109
106
103
100
97
1240
1220
1200
1180
1160
1140
1120
1100
94
91
88
85
0
5
10
15
20
VBIAS (V)
25
30
35
40
45
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (°C)
图7-4. VBIAS vs IBIAS (Active Mode)
图7-3. Frequency vs Temperature
(RT = 220 kΩ, 100 kHz)
36
35
34
33
32
31
30
29
28
27
26
12
11.5
11
10.5
10
9.5
9
0
5
10
15
20
VBIAS (V)
25
30
35
40
45
0
5
10
15
20
VBIAS (V)
25
30
35
40
45
图7-6. VBIAS vs IBIAS (Bypass Mode, Charge Pump Off)
图7-5. VBIAS vs IBIAS (Bypass Mode, Charge Pump On)
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7.6 Typical Characteristics (continued)
4
5.5
5
4.5
4
3.5
3
3.5
3
2.5
2
1.5
1
2.5
2
0.5
0
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
VBIAS (V)
VBIAS (V)
图7-7. VBIAS vs IBIAS (Shutdown Mode)
图7-8. VBIAS vs VVCC
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
20
40
60
80
100 120 140 160 180
IVCC (mA)
图7-9. VVCC vs IVCC
图7-10. VVCC vs Peak Driver Current
66
64
62
60
58
56
54
66
65
64
63
62
61
60
59
58
57
56
55
54
-40 -20
0
20
40
60
80 100 120 140 160
0
5
10
15
20
VCSP (V)
25
30
35
40
Temperature (°C)
图7-12. Peak Current Limit Threshold VCLTH vs Temperature
图7-11. Peak Current Limit Threshold vs VCSP
(CSP = 3 V)
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7.6 Typical Characteristics (continued)
120
119
118
117
116
115
114
113
112
111
110
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-40 -20
0
20
40
60
80 100 120 140 160
0
5
10
15
20
VOUT (V)
25
30
35
40
Temperature (°C)
图7-13. ICSP vs Temperature (Active Mode)
图7-14. VOUT Sink Current vs VOUT (Deep Sleep)
1.5
1.46
1.42
1.38
1.34
1.3
1.01
1.008
1.006
1.004
1.002
1
0.998
0.996
0.994
0.992
0.99
1.26
1.22
1.18
1.14
1.1
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (°C)
Temperature (°C)
图7-16. VREF vs Temperature
图7-15. VOUT Sink Current vs Temperature (Deep Sleep)
94
92
90
88
86
84
82
80
78
0
250 500 750 1000 1250 1500 1750 2000 2250
Frequency (kHz)
DMAX
图7-17. DMAX vs Frequency
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8 Detailed Description
8.1 Overview
The LM5123-Q1 device is a wide input range synchronous boost controller that employs peak current mode
control. The device features a low shutdown IQ and a low IQ sleep mode, which minimizes battery drain at no/
light load condition. The device also supports an ultra-low IQ deep sleep mode with bypass operation, which
eliminates the need for an external bypass switch when the supply voltage is greater than the boost output
regulation target. The output voltage can be dynamically programmed by using the tracking function.
The wide input range of the device supports automotive cold-crank and load dump. The minimum input voltage
can be as low as 0.8 V when BIAS is equal to or greater than 3.8 V. The switching frequency is dynamically
programmed with an external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes AM band
interference and allows for a small solution size and fast transient response. Controller architecture simplifies
thermal management at harsh ambient temperature conditions when compared to converter architectures.
The device has built-in protection features such as peak current limit, which is constant over VIN, overvoltage
protection, and thermal shutdown. External clock synchronization, programmable spread spectrum modulation,
and a lead-less package with minimal parasitic, help reduce EMI and avoid cross talk. Additional features include
the following:
• Line UVLO
• FPWM
• Diode emulation
• DCR inductor current sensing
• Programmable soft start
• Power-good indicator
8.2 Functional Block Diagram
VLOAD
VOUT/SENSE
VREF / RANGE
1V
VCC_EN
Min. Peak C/L
Comparator
CP
COUT
RLOAD
VZCDTH
VCC
BIAS
VCS
SKIP
+
VOUT
ZCD
Comparator
CVREF
HB
RANGE
œ
+
10mV
RVREFT
RVREFB
TRK
HO
SW
Q
Q
S
QH
DE/SKIP
+
Reference
generator
œ
Peak
450mV
PWM
Comparator
SW
œ
R
œ
FB
+
VSUPPLY
AGND
+
VCS
Bypass
Mode
VCC
LO
LM
CIN
RS
œ
Q
S
R
QL
ISS
0.3V
Peak C/L
Comparator
VCS
PGND
Q
+
SS
VCLTH
CLK
Css
CSN
CSP
œ
œ
COMP
ACS
VCS
+
VSUPPLY
25us
Delay
BIAS
RCOMP
VUVTH
VCC
Regulator
PGOOD
+
UV
VCC
VCC_EN2
œ
œ
+
œ
CCOMP
VCC
UVLO
VEN
FB
4-cycle
Delay
CLK,
DMAX
+
VCC_EN1
CP Enable
RUVLOT
VCC_OK
VOVTH
OV
Bypass Mode
(Only LM5152)
œ
Ready
EN/UVLO
IUVLO-HYS
VUVLO
SYNC /
DITHER
Selector
RUVLOB
Clock
Generator
+
MODE
FPWM
DE
SKIP
Switching Mode
Selector
TSD
SYNC/DITHER/VH/CP
RT
RT
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8.3 Feature Description
备注
Read through 节 8.4 before reading the feature description of the device. It is recommended to
understand which device functional modes and what type of light load switching modes are supported
by the device.
The parameters or thresholds values mentioned in this section are reference values unless otherwise
specified. Refer to the Electrical Characteristics to find the minimum, maximum, and typical values.
8.3.1 Device Enable/Disable (EN, VH Pin)
The device shuts down when EN is less than the EN threshold (VEN) and VH is less than the SYNC threshold
(VSYNC). The device is enabled when EN is greater than VEN or VH is greater than VSYNC. The VH pin provides a
40-μs internal delay before the device shuts down.
During shutdown a 33-kΩ internal pulldown resistor on the EN pin is connected to GND to prevent a false turn-
on when the pin is floating. Once EN goes above the EN threshold (VEN), the 33-kΩresistor is disconnected and
the IUVLO-HYS current source is enabled to provide the UVLO functionality. The IUVLO-HYS current is designed to
avoid chatter around the EN threshold voltage.
VSUPPLY
≥
VCC VVCC-UVLO
RUVLOT
RUVLOS
EN/UVLO
œ
Ready
to start
VUVLO
IUVLO-HYS
RUVLOB
+
CUVLO
TSD
PD
Configuration
+
Enable
VCC
VEN
œ
33 kꢀ
PD
≥
VH
VSYNC
Configuration
图8-1. EN/UVLO Circuit
8.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
The device features a high voltage 5-V VCC regulator, which is sourced from the BIAS pin. The internal VCC
regulator turns on 50 μs after the device is enabled, and 120-μs device configuration starts when VCC is
above VCC UVLO threshold (VVCC-UVLO). The device configuration is reset when the device shuts down or VCC
falls down below 2.2 V. The preferred way to reconfigure the device is to shut down the device. During
configuration time, the light load switching mode and VOUT range are selected.
The high voltage VCC regulator allows the connection of the BIAS pin directly to supply voltages from 3.8 V to
42 V. When BIAS is less than the 5-V VCC regulation target (VVCC-REG), the VCC output tracks the BIAS pin
voltage with a small dropout voltage which is caused by 1.7-Ωresistance of the VCC regulator.
The recommended VCC capacitor value is 4.7 μF. The VCC capacitor should be populated between VCC and
PGND as close to the device. The recommended BIAS capacitor value is 1.0 μF. The BIAS capacitor must be
populated between BIAS and PGND close to the device.
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BIAS
VCC
1.0 …F
4.7 …F
5-V VCC
Regulator
图8-2. High Voltage VCC Regulator
The VCC regulator features a VCC current limit function that prevents device damage when the VCC pin is
shorted to ground accidentally. The minimum sourcing capability of the VCC regulator is 100 mA (IVCC-CL) during
either the device configuration time or active mode operation. The minimum sourcing capability of the VCC
regulator is reduced to 1 mA during sleep mode or deep sleep mode, or when EN is less than VEN and VH is
greater than VSYNC. The VCC regulator supplies the internal drivers and other internal circuits. The external
MOSFETs must be carefully selected to make the driver current consumption less than IVCC-CL. The driver
current consumption can be calculated in 方程式1.
IG = 2 × QG@5V × fSW
(1)
where
• QG@5V is the N-channel MOSFET gate charge at 5 V gate-source voltage.
If VIN operation below 3.8 V is required, the BIAS pin must be connected to the output of the boost converter
(VLOAD). By connecting the BIAS pin to VLOAD, the boost converter input voltage (VSUPPLY) can drop down to 0.8
V if BIAS is greater than 3.8 V. See 节8.3.17 for more detailed information about the minimum VSUPPLY
.
8.3.3 Light Load Switching Mode Selection (MODE Pin)
The light load switching mode is selected during the device configuration. The device is configured to skip mode
when the MODE pin is floating or a resistor that is greater than 500 kΩis connected between MODE and AGND
during the device configuration. Once the device is configured to skip mode, the light load switching mode
cannot be changed until reconfiguring the device.
If the MODE pin voltage is less than 0.4 V (VMODE-FALLING) or grounded during the device configuration, the
device is configured to diode emulation (DE) mode. If the MODE pin voltage is greater than 2.0 V (VMODE-RISING
)
or connected to VCC during the device configuration, the device is configured to forced PWM (FPWM) mode. If
the device is configured to DE or FPWM mode, the light load switching mode can be dynamically changed
between DE and FPWM modes during operation without reconfiguration.
Closed during
configuration
MODE
FPWM or DE
SKIP
MODE
Selector
Closed during
configuration
图8-3. MODE Selection Circuit
8.3.4 VOUT Range Selection (RANGE Pin)
The programmable VOUT range is selected during the device configuration and it cannot be changed until the
user reconfigures the device. Lower VOUT range (5 V to 20 V) is selected if the resistance from VREF to AGND
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(RVREFT + RVREFB) is in the range of 75 kΩ to 100 kΩ during the device configuration. Upper VOUT range (15 V
to 57 V) is selected if the resistance from VREF to AGND is in the range of 20 kΩ to 35 kΩ during the device
configuration. The accuracy of the VOUT regulation is specified within the selected range.
8.3.5 Line Undervoltage Lockout (UVLO Pin)
When UVLO is greater than the UVLO threshold (VUVLO), the device enters active mode if the device
configuration is finished. UVLO hysteresis is accomplished with an internal 25-mV voltage hysteresis (VUVLO-HYS
)
at the UVLO pin, and an additional 10-μA current sink (IUVLO-HYS) that is switched on or off. When the UVLO pin
voltage exceeds VUVLO, the current sink is disabled to quickly raise the voltage at the UVLO pin. When the
UVLO pin voltage falls below VUVLO or during the device configuration time, the current sink is enabled, causing
the voltage at the UVLO pin to fall quickly.
The external UVLO resistor voltage divider (RUVLOT, RUVLOB) must be designed so that the voltage at the UVLO
pin is greater than VUVLO when VSUPPLY is in the desired operating range. The values of RUVLOT and RUVLOB can
be calculated as follows.
V
UVLO_RISING
V
−
× V
SUPPLY_OFF
SUPPLY_ON
V
UVLO_FALLING
R
R
=
=
(2)
(3)
UVLOT
I
UVLO_HYS
V
× R
UVLO_FALLING
UVLOT
UVLOB
V
− V
SUPPLY_OFF
UVLO_FALLING
A UVLO capacitor (CUVLO) is required in case VSUPPLY drops below VSUPPLY-OFF momentarily during the start-up
or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an additional
series UVLO resistor (RUVLOS) can be used to quickly raise the voltage at the UVLO pin when IUVLO-HYS is
disabled.
The UVLO pin can be connected to the BIAS pin if not used. Drive the UVLO pin through a minimum of a 5-kΩ
resistor if the BIAS pin voltage is less than the UVLO pin voltage in any conditions.
8.3.6 Fast Restart using VCC HOLD (VH Pin)
The device is prepared for a fast start or restart when VH is greater than VSYNC. The device configuration is done
and the VCC regulator is active. The device stops switching, but keeps the VCC regulator active when EN is less
than VEN and VH is greater than VSYNC (see 图8-5).
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3.8 V
BIAS
VUVLO
VEN
UVLO/
EN
VVCC-UVLO
120-µs (Typ.)
configuration
time
120-µs (Typ.)
configuration
time
VCC
SS
VTRK
50-µs (Typ.)
internal start-up delay
LO
x VTRK
VLOAD
SS =
VLOAD(TARGET)
VLOAD
图8-4. Boost Start-Up Waveforms Case 1: Start-Up by EN/UVLO, Restart when VH < VSYNC
3.8 V
BIAS
VUVLO
VEN
UVLO/
EN
VVCC-UVLO
120-µs (Typ.)
configuration
time
VCC
SS
VTRK
50-µs (Typ.)
internal start-up delay
LO
VLOAD x VTRK
SS =
VLOAD(TARGET)
VLOAD
图8-5. Boost Start-Up Waveforms Case 2: Start-Up by EN/UVLO, Restart when VH > VSYNC
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8.3.7 Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
The VOUT regulation target (VOUT-REG) is adjustable by programming the TRK pin voltage, which is the reference
of the internal error amplifier. The accuracy of VOUT-REG is given when the TRK voltage is between 0.25 V and
1.0 V. The high impedance TRK pin allows users to program the pin voltage directly by a D/A converter or by
connecting to a resistor voltage divider (RVREFT, RVREFB) between VREF and AGND.
The device provides a 1-V voltage reference (VREF), which can be used to program the TRK pin voltage through
a resistor voltage divider. It is not recommended to use VREF as a reference voltage of an external circuit
because the device periodically disables VREF in sleep or deep sleep mode. For stability reasons, the VREF
capacitor (CVREF) should be between 330 pF and 1 nF. 470 pF is recommended.
When RVREFT and RVREFB are used to program the TRK pin voltage, VOUT-REG can be calculated as follows.
Lower VOUT Range
20 × R
VREFB
V
=
(4)
OUT_REG
R
+ R
VREFT
VREFB
Upper VOUT Range
60 × R
VREFB
V
=
(5)
OUT_REG
R
+ R
VREFB
VREFT
The TRK pin voltage can be dynamically programmed in active mode, which makes an envelope tracking power
supply design easy. When designing a tracking power supply, it is required to adjust the TRK pin voltage slow
enough so that the VOUT pin voltage can track the command and the internal overvoltage or undervoltage
comparator is not triggered during the transient operation. An RC filter must be used at the TRK pin to slow
down the slew rate of the command signal at the TRK pin, especially when a step input is applied. When a
trapezoidal or sinusoidal input is applied, the slew rate or the frequency of the command signal must be limited.
VREF
VREF
CVREF
CVREF
RVREF
RVREFT
RVREFB
TRK
RFTRK
TRK
AGND
AGND
CFTRK
(b)
(a)
图8-6. TRK Control (a) using VREF (b) by External Step Input
In FPWM operation, VOUT-REG tracks the TRK pin voltage immediately as well during deep sleep mode. While in
skip or diode mode operation, VOUT-REG tracks the TRK pin voltage pin voltage with a maximum of a 20 ms delay
during deep sleep mode to save power. Take extra care when programming TRK if VSUPPLY is greater than
VOUT-REG in any conditions. The device enters active mode with a 5-μs delay if VLOAD falls down below
VOUT-REG in deep sleep mode, but the device enters active mode with maximum of a 20 ms delay if VOUT-REG is
increased by TRK above VLOAD in deep sleep mode.
8.3.8 Overvoltage Protection (VOUT Pin)
The device provides an overvoltage protection (OVP) for boost converter output. The OVP comparator monitors
the VOUT pin through an internal resistor voltage resistors. If the VOUT pin voltage rises above the overvoltage
threshold (VOVTH), OVP is activated. When OVP is triggered, the device turns off the low-side driver and turns on
the high-side driver until zero current is detected in diode emulation or skip mode. In FPWM mode, the low-side
driver is not turned off when the OVP is triggered.
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After at least 40 μs in OVP status, the device enters deep sleep mode and turns on the high-side driver 100%.
The recommended VOUT capacitor (CVOUT) is 0.1 μF.
8.3.9 Power Good Indicator (PGOOD Pin)
The device provides a power-good indicator (PGOOD) to simplify sequencing and supervision. PGOOD is an
open-drain output and a pullup resistor between 5 kΩ and 100 kΩ can be externally connected. The PGOOD
switch opens when the VOUT pin voltage is greater than the undervoltage threshold (VUVTH). The PGOOD pin is
pulled down to ground when the VOUT pin voltage is less than VUVTH, UVLO is less than VUVLO, VCC is less
than VVCC-UVLO, or during thermal shutdown. A 26-μs rising and 21-μs falling deglitch filter prevents any false
pulldown of the PGOOD due to transients. The PGOOD pin voltage cannot be greater than VVOUT + 0.3 V.
26 us Delay
21 us Delay
VUVTH
PGOOD
+
–
+
–
UV
FB
4-cycle
Delay
VOVTH
OV
图8-7. PGOOD Indicator
8.3.10 Dynamically Programmable Switching Frequency (RT)
The switching frequency of the device is set by a single RT resistor connected between RT and AGND if no
external synchronization clock is applied to the SYNC pin. The resistor value to set the RT switching frequency
(RT) is calculated as follows.
10
2 . 21 × 10
R =
− 955
(6)
T
f
RT typical
The RT pin is regulated to 0.5 V by an internal RT regulator when the device is in active mode or during the
device configuration. The switching frequency can be dynamically programmed during operation as shown in 图
8-8.
RT
Higher FSW
图8-8. Frequency Hopping Example
8.3.11 External Clock Synchronization (SYNC Pin)
The switching frequency of the device can be synchronized to an external clock by directly applying an external
pulse signal to the SYNC pin. The internal clock is synchronized at the rising edge of the external
synchronization pulse using an internal PLL. Connect the SYNC pin to ground if not used.
The external synchronization pulse must be greater than VSYNC in the high logic state and must be less than
VSYNC in the low logic state. The duty cycle of the external synchronization pulse is not limited, but the minimum
on-pulse and the minimum off-pulse widths must be greater than 100 ns. The frequency of the external
synchronization pulse must satisfy the following two inequalities.
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(7)
0.75ì fRT(typical) Ç fSYNC Ç 1.5ì fRT(typical)
(8)
For example, an RT resistor is required for typical 350-kHz switching to cover from 263-kHz to 525-kHz clock
synchronization without changing the RT resistor.
RSYNC
SYNC
SYNC rising threshold
SYNC falling threshold
SYNC
2 cycles
SYNC exit delay
7 cycles
PLL enable delay
~150us
PLL lock time
Clock
Synchronized
RT programmed
switching
RT programmed
switching
图8-9. External Clock Synchronization
Drive the SYNC pin through a minimum 1-kΩ resistor if the BIAS pin voltage is less than the SYNC pin voltage
in any conditions.
8.3.12 Programmable Spread Spectrum (DITHER Pin)
The device provides an optional programmable spread spectrum (clock dithering) function that is activated by
connecting a capacitor between DITHER and AGND. A triangular waveform centered at 1.0 V is generated
across the dither capacitor. This triangular waveform modulates the oscillator frequency by –6% to +5% of the
frequency set by the RT resistor. The dither capacitance value sets the rate of the low frequency modulation.
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DITHER
CDITHER
IDITHER = -20uA
1.0V +7.0%
1.0V -7.0%
IDITHER = 20uA
Dither disable threshold
TMOD = 1 / fMOD
DITHER
RT programmed
switching
Clock dithering
RT programmed
switching
图8-10. Switching Frequency Dithering
For the dithering circuit to effectively reduce peak EMI, the modulation frequency must be much less than the RT
switching frequency. The dither capacitance which is required for a given modulation frequency (fMOD), can be
calculated from 方程式9. Setting the fMOD to 9 kHz or 10 kHz is a good starting point.
20μA
C
=
(9)
DITHER
f
× 0 . 29
MOD
Connecting DITHER to AGND deactivates clock dithering, and the internal oscillator operates at a fixed
frequency set by the RT resistor. Clock dithering is also disabled when an external synchronization pulse is
applied.
DITHER
No Dither
图8-11. Dynamic Dither On/Off Example
8.3.13 Programmable Soft Start (SS Pin)
The soft-start feature helps the converter gradually reach the steady state operating point. To reduce start-up
stresses and surges, the device regulates the error amplifier reference to the SS pin voltage or the TRK pin
voltage (VTRK), whichever is lower.
The internal 20 μA soft-start (ISS) current turns on 120 μs after the VCC pin crosses VVCC-UVLO. ISS gradually
increases the voltage on an external soft-start capacitor (CSS). This results in a gradual rise of the output
voltage.
In FPWM mode, the device forces diode emulation while the SS pin voltage is less than 1.5 V. When the SS pin
voltage is greater than 1.5 V, the device changes the zero current detection (ZCD) threshold gradually from 4 mV
to –145 mV to achieve a smooth transition from diode emulation to FPWM mode.
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VCC
UVLO
ISS=20uA
VCC
1.5V
VTRK
SS
Transient period
120us
delay
Forced Diode
Emulation
图8-12. Soft Start and Smooth Transition to FPWM
In boost topology, the soft-start time (tSS) varies with the input supply voltage because the boost output voltage is
equal to the boost input voltage at the beginning of the soft-start switching. tSS in boost topology is calculated in
方程式10.
C
V
SUPPLY
SS
t
= V
×
× 1 −
(10)
SS
TRK
20μA
V
LOAD
In general, it is recommended to choose a soft-start time long enough so that the converter can start up without
going into an overcurrent state. If the device is used for a pre-boost in automotive application, it is recommended
to use 100-pF CSS to reach steady state as soon as possible.
The device also features an internal SS-to-FB clamp (VSS-FB), which clamps SS 55 mV above FB and is
activated if 256 consecutive switching cycles occur with current limit. The SS-to-FB clamp is deactivated if 32
consecutive switching cycles occur without exceeding the current limit threshold. This clamp helps to minimize
surges after output shorts or over load situations. The device can enter deep sleep mode when SS is greater
than 1.5 V. It is not recommended to pulldown SS to stop switching.
8.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
The device includes an internal feedback resistor voltage divider. The internal feedback resistor voltage divider is
connected to the negative input of the internal transconductance error amplifier, and the TRK pin voltage
programs the positive input of the internal transconductance error amplifier after the soft start is finished. The
internal transconductance error amplifier features high output resistance (RO = 10 MΩ) and wide bandwidth (BW
= 3 MHz) and sinks (or sources) current which is proportional to the difference between the negative and the
positive inputs of the error amplifier.
The output of the error amplifier is connected to the COMP pin, allowing the use of a Type-2 loop compensation
network. RCOMP, CCOMP, and an optional CHF loop compensation components configure the error amplifier gain
and phase characteristics to achieve a stable loop response. This compensation network creates a pole at very
low frequency, a mid-band zero, and a high frequency pole.
The PWM comparator in 图 8-13 compares the sum of the amplified sensed inductor current and the slope
compensation ramp with the sum of the COMP pin voltage and a –0.3-V internal offset, and terminates the
present cycle if the sum of the amplified sensed inductor current and the slope compensation ramp is greater
than the sum of the COMP pin voltage and the –0.3-V internal offset.
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VSUPPLY
RS
CSN
CSP
VSLOPE
œ
+
VCC_EN
VREF
1V
Gain=10
VOUT
CVREF
RVREFT
TRK
+
+
Reference
generator
œ
RVREFB
PWM
Comparator
œ
FB
0.3V
DC offset
AGND
Bypass
Mode
ISS
SS
COMP
Css
RCOMP
CHF
(optional)
CCOMP
图8-13. Error Amplifier, Current Sense Amplifier, and PWM
8.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)
The device features a current sense amplifier with an effective gain of 10 (ACS), and provides an internal slope
compensation ramp to the PWM comparator to prevent a subharmonic oscillation at high duty cycle. The device
generates the 45-mV peak slope compensation ramp (VSLOPE) at the input of the current sense amplifier, which
is a 0.45-V peak (at 100% duty cycle) slope compensation ramp at the PWM comparator input.
According to peak current mode control theory, the slope of the slope compensation ramp must be greater than
at least half of the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle.
Therefore, the minimum amount of the slope compensation must satisfy 方程式11.
0.5 × (VLOAD - VSUPPLY) / LM × RS × Margin < VSLOPE × fSW (in Boost)
(11)
where
• 1.5-1.7 is recommended as the margin to cover non-ideal factors.
V
VCOMP
0.3V offset
Internal Slope
Compensation
0.45V x D
Sensed Inductor
Current (10 x Rs x ILM
)
图8-14. PWM Comparator Input
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8.3.16 Constant Peak Current Limit (CSP, CSN Pin)
When the CSP-CSN voltage exceeds the 60-mV cycle-by-cycle current limit threshold (VCLTH), the current limit
comparator immediately terminates the LO output. The device provides an constant peak current limit whose
peak inductor current limit is constant over the input and output voltage. For the case where the inductor current
can overshoot, such as inductor saturation, the current limit comparator skips pulses until the current has
decayed below the current limit threshold.
VSUPPLY
RS
CSN
CSP
Gain=10
CS Amplifier
+
œ
0.6V
Current Limit
Comparator
图8-15. Current Limit Comparator
Cycle-by-cycle peak current limit is calculated as follows:
0.06
RS
IPEAK-CL
=
(12)
V
Current Limit = 0.6V
Sensed Inductor
Current (10 x Rs x ILM
)
图8-16. Current Limit Comparator Input
Boost converters have a natural pass-through path from the supply to the load through the high-side MOSFET
body diode. Due to this path, boost converters cannot provide the peak current limit protection when the output
voltage is close to or less than the input supply voltage, especially the peak current limit protection that does not
work during the minimum on-time (tON-MIN).
8.3.17 Maximum Duty Cycle and Minimum Controllable On-Time Limits
The device provides the maximum duty cycle limit (DMAX) / minimum off time to cover the non-ideal factors
caused by resistive elements. DMAX decides the minimum input supply voltage (VSUPPLY(MIN)), which can achieve
the target output voltage (VLOAD) during CCM operation, but VSUPPLY(MIN) , which can achieve the target output
voltage during DCM operation, is not limited by DMAX. VSUPPLY(MIN), which can achieve the target output voltage
during CCM operation, can be estimated as follows. See also 图7-17.
V
SUPPLY(MIN) ≈VLOAD × (1 - DMAX) + ISUPPLY(MAX) × (RDCR + RS + RDS(ON)
)
(13)
where
• ISUPPLY(MAX) is the maximum input current at VSUPPLY(MIN)
• RDCR is the DC resistance of the inductor.
.
• RDS(ON) is the turn-on resistance of the MOSFET.
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At very light load condition or when VSUPPLY is close to VOUT-REG, the device skips the low-side driver pulses if
the required on-time is less than tON-MIN. This pulse skipping appears as a random behavior. If VSUPPLY is further
increased to the voltage higher than VOUT-REG, the required on time becomes zero and eventually the device can
start bypass operation, which turns on the high-side driver 100% when the VOUT pin voltage is greater than
VOVTH
.
8.3.18 Deep Sleep Mode and Bypass Operation (HO, CP Pin)
When SS is greater than 1.5 V, the device enters deep sleep mode after at least 40 μs in OVP status. The
device re-enters active mode if VOUT falls down below VOVP. During bypass operation, the loss, which is caused
by the body diode of the high-side MOSFET, is minimized. See 节8.4.1.5 for more information.
Boost
Output
Bypass Operation
Boost
Input
Pulse
Skipping
Pulse
Skipping
HO-SW
Pulse
Skipping
Pulse
Skipping
LO-PGND
图8-17. PWM to Bypass Transition in CCM Operation
Boost
Output
Boost
Input
Bypass Operation
Diode Emulation
Diode Emulation
Pulse
Skipping
Pulse
Skipping
HO-SW
Pulse
Skipping
Pulse
Skipping
LO-PGND
图8-18. PWM to Bypass Transition in DCM Operation
8.3.19 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
The device provides N-channel logic MOSFET drivers, which can source a peak current of 2.2 A and sink a peak
current of 3.3 A. The LO driver is powered by VCC, and is enabled when EN is greater than VEN and VCC is
greater than VVCC-UVLO. The HO driver is powered by HB, and is enabled when EN is greater than VEN and HB-
SW voltage is greater than HB UVLO threshold (VHB-UVLO).
When the SW pin voltage is approximately 0 V by turning on the low-side MOSFET, the CHB is charged from
VCC through the internal boot diode. The recommended value of the CHB is 0.1 μF.
The LO and HO outputs are controlled with an adaptive dead-time methodology which ensures that both outputs
are not turned on at the same time. When the device commands LO to be turned on, the adaptive dead-time
logic first turns off HO and waits for HO-SW voltage to drop. LO is then turned on after a small delay (tDHL).
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Similarly, the HO driver turn-on is delayed until the LO-PGND voltage has discharged. HO is then turned on after
a small delay (tDLH).
If the BIAS pin voltage is below the 5-V VCC regulation target, take extra care when selecting the MOSFETs.
The gate plateau voltage of the MOSFET switch must be less than the BIAS pin voltage to completely enhance
the MOSFET, especially during start-up at low BIAS pin voltage. If the driver output voltage is lower than the
MOSFET gate plateau voltage during start-up, the converter may not start up properly and it can stick at the
maximum duty cycle in a high-power dissipation state. This condition can be avoided by selecting a lower
threshold MOSFET or by turning on the device when the BIAS pin voltage is sufficient. Care should be taken
when the converter operates in bypass at any conditions. During the bypass operation, the minimum HO-SW
voltage is 3.75 V.
VCC
DHB
Qpump
HB
ZCD
Delay
HO
SW
Level
Shifter
Adaptive
Deadtime
VCC
PWM
Delay
LO
PGND
图8-19. Driver Structure with Internal Boot Diode
The hiccup mode fault protection is triggered by the HB UVLO. If the HB-SW voltage is less than the HB UVLO
threshold (VHB-UVLO), the LO turns on by force for 75 ns to replenish the boost capacitor. The device allows up to
four consecutive replenish switching. After the maximum four consecutive boot replenish switching, the device
skips switching for 12 cycles. If the device fails to replenish the boost capacitor after the four sets of the four
consecutive replenish switching, the device stops switching and enters 512 cycles of hiccup mode off time.
During the hiccup mode off time, PGOOD and SS are grounded.
If required, the slew rate of the switching node voltage can be adjusted by adding a gate resistor in parallel with
a pulldown PNP transistor. Extra care should be taken when adding the gate resistor since it can decrease the
effective dead-time.
RGL
LO
QGL
PGND
图8-20. Slew Rate Control
8.3.20 Thermal Shutdown Protection
An internal thermal shutdown (TSD) is provided to protect the device if the junction temperature (TJ) exceeds
175°C. When TSD is activated, the device is forced into a low-power thermal shutdown state with the MOSFET
drivers and the VCC regulator disabled. After the TJ is reduced (typical hysteresis is 15⁰C), the device restarts.
The TSD is disabled during sleep or deep sleep mode.
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8.4 Device Functional Modes
8.4.1 Device Status
8.4.1.1 Shutdown Mode
When EN is less than VEN and VH is less than VSYNC, the device shuts down, consuming 3 μA from BIAS. In
shutdown mode, COMP, SS, and PGOOD are grounded. The device is enabled when EN is greater than VEN or
VH is greater than VSYNC
.
8.4.1.2 Configuration Mode
When the device is enabled initially, the 120-μs device configuration starts if VCC is greater than VVCC-UVLO
.
During device configuration, the light load switching mode and VOUT range are selected. The device
configuration is reset when the device shuts down or VCC falls down below 2.2 V. The preferred way to
reconfigure the device is to shut down the device. During the configuration time, a 33-kΩ internal EN pulldown
resistor is connected, the minimum sourcing capability of the VCC regulator is 100 mA and the RT pin is
regulated to 0.5 V by the internal RT regulator.
8.4.1.3 Active Mode
After the 120-μs initial device configuration is finished, the device enters active mode with all functions enabled
if UVLO is greater than VUVLO. In active mode, a soft-start sequence starts and the error amplifier is enabled.
8.4.1.4 Sleep Mode
When skip mode is selected as the light load switching mode and SS is greater than 1.5 V, the device enters
sleep mode if the low-side driver skips switching for 16 consecutive cycles. Once the device enters sleep mode,
the device cannot re-enter active mode during 8 μs minimum sleep time. During sleep mode, the device stops
internal oscillator to reduce the operating current, disables UVLO comparator, disables the error amplifier, and
parks the COMP pin at 0.25 V. The device re-enters active mode if the VOUT pin voltage falls down below the
wake up threshold (VWAKE) which is 1.1% lower than the VOUT-REG
.
8.4.1.5 Deep Sleep Mode
When SS is greater than 1.5 V, the device enters deep sleep mode after four cycles in OVP status. During deep
sleep mode, the device stops the internal oscillator to reduce the operating current, disables UVLO comparator,
disables the error amplifier, and parks the COMP pin at 0.25 V.
In FPWM or DE mode, the device re-enters active mode if VOUT falls down below VOVTH. In skip mode, the
device re-enters active mode if VOUT falls down below VOVTH, then immediately enters sleep mode after 16
consecutive cycles of pulse skipping.
8.4.2 Light Load Switching Mode
The device provides three light load switching modes. Inductor current waveforms in each mode are different at
the light/no load condition.
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Inductor
Inductor current coducts continuously.
Current
Negative current flow is allowed.
0A
(a)
Inductor
Current
Random pulse skip
when the required tON
is less than tON-MIN
Random pulse skip
when the required tON
is less than tON-MIN
0A
(b)
Inductor
Current
Minimum peak inductor
current is limited
The channel enters sleep mode after 16
consecutive pulse skipping
IPEAK-MIN=10mV / RS
0A
(c)
图8-21. Inductor Current Waveform at Light Load (a) FPWM (b) Diode Emulation (c) Skip Mode
8.4.2.1 Forced PWM (FPWM) Mode
In FPWM mode, the inductor current conducts continuously at light or no load conditions, allowing a continuous
conduction mode (CCM) operation. The benefits of the FPWM mode are a fast light load to heavy load transient
response, and constant switching frequency at light or no load conditions. The maximum reverse current is
limited to 145 mV/RDS(ON) in FPWM mode.
8.4.2.2 Diode Emulation (DE) Mode
In diode emulation (DE) mode, inductor current flow is allowed only in one direction – from the input source to
the output load. The device monitors the SENSE-SW voltage during the high-side switch on time and turns off
the high-side switch for the remainder of the PWM cycle when the SENSE-SW voltage falls down below the 5-
mV zero current detection (ZCD) threshold (VZCD). The benefit of the diode emulation is a higher efficiency than
FPWM mode efficiency at light load condition.
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SENSE + 5mV
SW
ZCD
ZCD
HO-SW
LO1
Dead-time
图8-22. Zero Current Detection
8.4.2.3 Forced Diode Emulation Operation in FPWM Mode
During soft start, the device forces diode emulation while the SS pin voltage is less than 1.5 V. When the SS pin
is greater than 1.5 V, the device reduces the zero current detection (ZCD) threshold down to –145 mV. The
peak-to-peak inductor current must satisfy 方程式14 for a proper FPWM operation at no load.
I
× R
DS on
2
PP
< 145mV
(14)
8.4.2.4 Skip Mode
When skip mode is selected as the light load switching mode, the device enters sleep mode when the pulse skip
counter detects 16 consecutive cycles of pulse skipping in the active mode, and re-enters the active mode if
VOUT falls down below VWAKE
.
The light load efficiency can be increased by entering sleep mode more frequently and staying in sleep mode
longer. In skip mode and when SS is greater than 1.5 V, the device works in the diode emulation, but the
minimum peak current is limited to 10 mV/RS once the low-side driver turns on. By limiting the minimum peak
current, the boost converter is able to supply more current than what is required when switching, and enters
sleep mode more frequently and stays longer in the sleep mode.
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VWAKE
+
Active Mode
Sleep Mode
S
R
Q
Q
VOUT
œ
16-cycle
Pulse Skip
Counter
Pulse Skip
VOUT-REG
VOUT
VWAKE
COMP
0.25V
LO
5us wake-up delay
16 consecutive
pulse skipping
Active Mode
Active Mode
Sleep Mode
(8 us minimum sleep time)
图8-23. Skip Mode Operation
When skip mode is selected as the light load switching mode, LM should be selected for the peak inductor to
reach the 10m-V minimum peak current limit before LO turns off by DMAX at the minimum VSUPPLY
.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The device integrates several optional features to meet system design requirements, including input UVLO,
programmable soft start, clock synchronization, spread spectrum, and selectable light load switching mode.
Each application incorporates these features as needed for a more comprehensive design. Refer to the
LM5123EVM-BST User's Guide for more information.
9.2 Typical Application
图9-1 shows all optional components to design a boost converter.
VSUPPLY
CBIAS
CVOUT
VLOAD
CVCC
VOUT
BIAS
VCC
RT
+
CHB
RGH
SW
RLOAD
HB
œ
COUT2
COUT1
QH
RT
HO
SW
SS
VSUPPLY
CCOMP
CSS
QGH
+
LM
COMP
RS
QL
RCOMP
RGL
œ
CIN2
CIN1
LO
MODE
AGND
QGL
PGND
CSN
CSP
UVLO
RFCS
RPU
VSUPPLY
PGOOD
VREF
TRK
CVREF
CFCS
RUVLOT
RUVLOS
SYNC/DITHER
RVREFT
RVREFB
RUVLOB
CUVLO
CDITHER
图9-1. Typical Synchronous Boost Converter with Optional Components
9.2.1 Design Requirements
表9-1 shows the intended input, output, and performance parameters for this application example.
表9-1. Design Example Parameters
DESIGN PARAMETER
VALUE
9 V
Minimum input supply voltage (VSUPPLY(MIN)
)
Target output voltage (VLOAD
Maximum load current (ILOAD
Typical switching frequency (fSW
)
24 V
)
4 A ( 96 Watt)
440 kHz
)
9.2.2 Detailed Design Procedure
Use the Quick Start Calculator to expedite the process of designing of a regulator for a given application.
Refer to the LM5123EVM-BST EVM user guide for recommended components and typical application curves.
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9.2.2.1 Application Ideas
For applications requiring the lowest cost with minimum conduction loss, inductor DC resistance (DCR) can be
used to sense the inductor current rather than using a sense resistor. RDCRC and CDCRC must meet 方程式 15 to
match a time constant.
LM
RDCR
VSUPPLY
CDCRC
RDCRC
CSN
CSP
图9-2. DCR Current Sensing
L
M
= R
× C
(15)
DCRC
DCRC
R
DCR
If required, an additional PGOOD delay can be programmed using an external circuit.
VDD_MCU
PGOOD : Internal 25us pull-down and pull-up delay
PGOOD
VDD_MCU
/RESET (with additional delay)
CDELAY
图9-3. Additional PGOOD Delay
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9.2.3 Application Curves
100
95
90
85
80
75
70
65
60
55
50
100
80
60
40
20
0
18V_EFF
14V_EFF
12V_EFF
10V_EFF
8V_EFF
SKIP MODE
FPWM MODE
0
0.8 1.6 2.4 3.2
4
4.8 5.6 6.4 7.2
8
0.001
0.021
0.041
0.061
0.081
0.1
IOUT (A)
IOUT (A)
图9-4. Efficiency vs. IOUT, VOUT = 24 V (FPWM)
图9-5. Efficiency vs. IOUT, VOUT = 24 V Light Load
24.4
24.3
24.2
24.1
24
VIN = 18V
VIN = 14V
VIN = 12V
VIN = 10V
VIN = 8V
23.9
23.8
23.7
23.6
0
1
2
3
4
5
6
7
8
IOUT (A)
图9-6. 24 V Load Regulation
9.3 System Example
Use LM5123 in LED application. The TRK pin can be used to control head-room.
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TPS92515 Buck
LED Driver
VLOAD
TPS92515 Buck
LED Driver
BIAS VCC
VOUT/SENSE
MCU VDD
High-side MOSFET can turn
on 100% when car battery
voltage is in normal range
HB
SYNC/DITHER/VH/QP
PGOOD
HO
SW
Car Battery
VSUPPLY
RT
SS
Power Good
indicator to
MCU
LO
PGND
COMP
CSN
VCC
MODE
CSP
REF/ RANGE
Enable from MCU
RVREF
TRK
UVLO/EN AGND
RFTRK
Dynamic
Headroom
Control
CFTRK
图9-7. LM5123 in LED Application
To configure non-synchronous boost converter, please connect SW to PGND, and connect HB to VCC.
VLOAD
VOUT
VCC
HB
HO
VSUPPLY
SW
LO
PGND
CSN
CSP
图9-8. Non-synchronous Boost Configuration
10 Power Supply Recommendations
The device is designed to operate from a power supply or a battery that has a voltage range is from 0.8 V to 42
V. The input power supply must be able to supply the maximum boost supply voltage and handle the maximum
input current at 0.8 V. The impedance of the power supply and battery including cables must be low enough that
an input current transient does not cause an excessive drop. Additional input ceramic capacitors can be required
at the supply input of the converter.
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11 Layout
11.1 Layout Guidelines
The performance of switching converters heavily depends on the quality of the PCB layout. The following
guidelines will help users design a PCB with the best power conversion performance, thermal performance, and
minimize generation of unwanted EMI.
• Place CVCC, CBIAS, CHB, and CVOUT as close to the device. Make direct connections to the pins.
• Place QH, QL, and COUT. Make the switching loop (COUT to QH to QL to COUT) as small as possible. A small
size ceramic capacitor helps to minimize the loop length. Leave a copper area near the drain connection of
QH for a thermal dissipation.
• Place LM, RS, and CIN. Make the loop (CIN to RS to LM to CIN) as small as possible. A small size ceramic
capacitor helps to minimize the loop length.
• Connect RS to CSP-CSN. The CSP-CSN traces must be routed in parallel and surrounded by ground.
• Connect VOUT, HO, and SW. These traces must be routed in parallel using a short, low inductance path.
VOUT must be directly connected the drain connection of QH. SW must be directly connected to the source
connection of QH
• Connect LO and PGND. The LO-PGND traces must be routed in parallel using a short, low inductance path.
PGND must be directly connected the source connection of QL
• Place RCOMP, CCOMP, CSS, CVREF, RVREFT, RVREFB, RT, and RUVLOB as close to the device, and connect to a
common analog ground plane.
• Connect power ground plane (the source connection of the QL) to EP through PGND. Connect the common
analog ground plane to EP through AGND. PGND and AGND must be connected underneath the device.
• Add several vias under EP to help conduct heat away from the device. Connect the vias to a large analog
ground plane on the bottom layer.
• Do not connect COUT and CIN grounds underneath the device and through the large analog ground plane
which is connected to EP.
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11.2 Layout Example
Analog Ground Plane
(Connect to EP via AGND pin)
CCOMP
RVREFB
CVREF
CSS
RCOMP
RVREFT
To RS
To RS
RT
CSP
RT
CSN
SYNC
Top Layer
VOUT
UVLO
CVOUT
EP
RUVLOB
Bottom Layer
PGOOD
HO
MODE
LO
Inner Layer
To MCU
To RUVLOT
CVCC
CHB
VLOAD
To
VSUPPLY
CBIAS
GND
GND
COUT
COUT
COUT
QH
QL
RS
CIN
CIN
CIN
/}u‰}vꢀvš •]Ìꢀ• ꢁ}v[š
match with actual
LM
To
CSP
To
CSN
VSUPPLY
图11-1. PCB Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5123QRGRRQ1
ACTIVE
VQFN
RGR
20
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
LM5123
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5123QRGRRQ1
VQFN
RGR
20
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGR 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LM5123QRGRRQ1
3000
Pack Materials-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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